3 * ARM backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
11 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
17 #include <mono/metadata/abi-details.h>
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/utils/mono-mmap.h>
22 #include <mono/utils/mono-hwcap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/utils/mono-threads-coop.h>
25 #include <mono/utils/unlocked.h>
31 #include "debugger-agent.h"
33 #include "mono/arch/arm/arm-vfp-codegen.h"
35 /* Sanity check: This makes no sense */
36 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
37 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
41 * IS_SOFT_FLOAT: Is full software floating point used?
42 * IS_HARD_FLOAT: Is full hardware floating point used?
43 * IS_VFP: Is hardware floating point with software ABI used?
45 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
46 * IS_VFP may delegate to mono_arch_is_soft_float ().
49 #if defined(ARM_FPU_VFP_HARD)
50 #define IS_SOFT_FLOAT (FALSE)
51 #define IS_HARD_FLOAT (TRUE)
53 #elif defined(ARM_FPU_NONE)
54 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
55 #define IS_HARD_FLOAT (FALSE)
56 #define IS_VFP (!mono_arch_is_soft_float ())
58 #define IS_SOFT_FLOAT (FALSE)
59 #define IS_HARD_FLOAT (FALSE)
63 #define THUNK_SIZE (3 * 4)
65 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
68 void sys_icache_invalidate (void *start, size_t len);
71 /* This mutex protects architecture specific caches */
72 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
73 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
74 static mono_mutex_t mini_arch_mutex;
76 static gboolean v5_supported = FALSE;
77 static gboolean v6_supported = FALSE;
78 static gboolean v7_supported = FALSE;
79 static gboolean v7s_supported = FALSE;
80 static gboolean v7k_supported = FALSE;
81 static gboolean thumb_supported = FALSE;
82 static gboolean thumb2_supported = FALSE;
84 * Whenever to use the ARM EABI
86 static gboolean eabi_supported = FALSE;
89 * Whenever to use the iphone ABI extensions:
90 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
91 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
92 * This is required for debugging/profiling tools to work, but it has some overhead so it should
93 * only be turned on in debug builds.
95 static gboolean iphone_abi = FALSE;
98 * The FPU we are generating code for. This is NOT runtime configurable right now,
99 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
101 static MonoArmFPU arm_fpu;
103 #if defined(ARM_FPU_VFP_HARD)
105 * On armhf, d0-d7 are used for argument passing and d8-d15
106 * must be preserved across calls, which leaves us no room
107 * for scratch registers. So we use d14-d15 but back up their
108 * previous contents to a stack slot before using them - see
109 * mono_arm_emit_vfp_scratch_save/_restore ().
111 static int vfp_scratch1 = ARM_VFP_D14;
112 static int vfp_scratch2 = ARM_VFP_D15;
115 * On armel, d0-d7 do not need to be preserved, so we can
116 * freely make use of them as scratch registers.
118 static int vfp_scratch1 = ARM_VFP_D0;
119 static int vfp_scratch2 = ARM_VFP_D1;
124 static gpointer single_step_tramp, breakpoint_tramp;
127 * The code generated for sequence points reads from this location, which is
128 * made read-only when single stepping is enabled.
130 static gpointer ss_trigger_page;
132 /* Enabled breakpoints read from this trigger page */
133 static gpointer bp_trigger_page;
137 * floating point support: on ARM it is a mess, there are at least 3
138 * different setups, each of which binary incompat with the other.
139 * 1) FPA: old and ugly, but unfortunately what current distros use
140 * the double binary format has the two words swapped. 8 double registers.
141 * Implemented usually by kernel emulation.
142 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
143 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
144 * 3) VFP: the new and actually sensible and useful FP support. Implemented
145 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
147 * We do not care about FPA. We will support soft float and VFP.
149 int mono_exc_esp_offset = 0;
151 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
152 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
153 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
155 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
156 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
157 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
159 //#define DEBUG_IMT 0
162 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
166 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
169 mono_arch_regname (int reg)
171 static const char * rnames[] = {
172 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
173 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
174 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
177 if (reg >= 0 && reg < 16)
183 mono_arch_fregname (int reg)
185 static const char * rnames[] = {
186 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
187 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
188 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
189 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
190 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
191 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
194 if (reg >= 0 && reg < 32)
202 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
204 int imm8, rot_amount;
205 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
206 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
210 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
211 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
213 code = mono_arm_emit_load_imm (code, dreg, imm);
214 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
220 emit_ldr_imm (guint8 *code, int dreg, int sreg, int imm)
222 if (!arm_is_imm12 (imm)) {
223 g_assert (dreg != sreg);
224 code = emit_big_add (code, dreg, sreg, imm);
225 ARM_LDR_IMM (code, dreg, dreg, 0);
227 ARM_LDR_IMM (code, dreg, sreg, imm);
232 /* If dreg == sreg, this clobbers IP */
234 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
236 int imm8, rot_amount;
237 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
238 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
242 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
243 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
245 code = mono_arm_emit_load_imm (code, dreg, imm);
246 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
252 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
254 /* we can use r0-r3, since this is called only for incoming args on the stack */
255 if (size > sizeof (gpointer) * 4) {
257 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
258 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
259 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
260 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
261 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
262 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
263 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
264 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
265 ARM_B_COND (code, ARMCOND_NE, 0);
266 arm_patch (code - 4, start_loop);
269 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
270 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
272 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
273 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
279 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
280 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
281 doffset = soffset = 0;
283 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
284 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
290 g_assert (size == 0);
295 emit_call_reg (guint8 *code, int reg)
298 ARM_BLX_REG (code, reg);
300 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
304 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
310 emit_call_seq (MonoCompile *cfg, guint8 *code)
312 if (cfg->method->dynamic) {
313 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
315 *(gpointer*)code = NULL;
317 code = emit_call_reg (code, ARMREG_IP);
321 cfg->thunk_area += THUNK_SIZE;
326 mono_arm_patchable_b (guint8 *code, int cond)
328 ARM_B_COND (code, cond, 0);
333 mono_arm_patchable_bl (guint8 *code, int cond)
335 ARM_BL_COND (code, cond, 0);
339 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(HOST_ANDROID) && !defined(MONO_CROSS_COMPILE)
340 #define HAVE_AEABI_READ_TP 1
343 #ifdef HAVE_AEABI_READ_TP
344 gpointer __aeabi_read_tp (void);
348 mono_arch_have_fast_tls (void)
350 #ifdef HAVE_AEABI_READ_TP
351 static gboolean have_fast_tls = FALSE;
352 static gboolean inited = FALSE;
354 if (mini_get_debug_options ()->use_fallback_tls)
358 return have_fast_tls;
363 tp1 = __aeabi_read_tp ();
364 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
366 have_fast_tls = tp1 && tp1 == tp2;
369 return have_fast_tls;
376 emit_tls_get (guint8 *code, int dreg, int tls_offset)
378 g_assert (v7_supported);
379 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
380 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
385 emit_tls_set (guint8 *code, int sreg, int tls_offset)
387 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
388 g_assert (v7_supported);
389 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
390 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
397 * Emit code to push an LMF structure on the LMF stack.
398 * On arm, this is intermixed with the initialization of other fields of the structure.
401 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
405 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
406 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
408 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
409 (gpointer)"mono_tls_get_lmf_addr");
410 code = emit_call_seq (cfg, code);
412 /* we build the MonoLMF structure on the stack - see mini-arm.h */
413 /* lmf_offset is the offset from the previous stack pointer,
414 * alloc_size is the total stack space allocated, so the offset
415 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
416 * The pointer to the struct is put in r1 (new_lmf).
417 * ip is used as scratch
418 * The callee-saved registers are already in the MonoLMF structure
420 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
421 /* r0 is the result from mono_get_lmf_addr () */
422 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
423 /* new_lmf->previous_lmf = *lmf_addr */
424 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
425 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
426 /* *(lmf_addr) = r1 */
427 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
428 /* Skip method (only needed for trampoline LMF frames) */
429 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
430 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
431 /* save the current IP */
432 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
433 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
435 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
436 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
447 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
451 for (list = inst->float_args; list; list = list->next) {
452 FloatArgData *fad = list->data;
453 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
454 gboolean imm = arm_is_fpimm8 (var->inst_offset);
456 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
462 if (*offset + *max_len > cfg->code_size) {
463 cfg->code_size += *max_len;
464 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
466 code = cfg->native_code + *offset;
470 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
471 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
473 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
475 *offset = code - cfg->native_code;
482 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
486 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
488 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
491 if (!arm_is_fpimm8 (inst->inst_offset)) {
492 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
493 ARM_FSTD (code, reg, ARMREG_LR, 0);
495 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
502 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
506 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
508 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
511 if (!arm_is_fpimm8 (inst->inst_offset)) {
512 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
513 ARM_FLDD (code, reg, ARMREG_LR, 0);
515 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
524 * Emit code to pop an LMF structure from the LMF stack.
527 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
531 if (lmf_offset < 32) {
532 basereg = cfg->frame_reg;
537 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
540 /* ip = previous_lmf */
541 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
543 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
544 /* *(lmf_addr) = previous_lmf */
545 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
550 #endif /* #ifndef DISABLE_JIT */
553 * mono_arch_get_argument_info:
554 * @csig: a method signature
555 * @param_count: the number of parameters to consider
556 * @arg_info: an array to store the result infos
558 * Gathers information on parameters such as size, alignment and
559 * padding. arg_info should be large enought to hold param_count + 1 entries.
561 * Returns the size of the activation frame.
564 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
566 int k, frame_size = 0;
567 guint32 size, align, pad;
571 t = mini_get_underlying_type (csig->ret);
572 if (MONO_TYPE_ISSTRUCT (t)) {
573 frame_size += sizeof (gpointer);
577 arg_info [0].offset = offset;
580 frame_size += sizeof (gpointer);
584 arg_info [0].size = frame_size;
586 for (k = 0; k < param_count; k++) {
587 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
589 /* ignore alignment for now */
592 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
593 arg_info [k].pad = pad;
595 arg_info [k + 1].pad = 0;
596 arg_info [k + 1].size = size;
598 arg_info [k + 1].offset = offset;
602 align = MONO_ARCH_FRAME_ALIGNMENT;
603 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
604 arg_info [k].pad = pad;
609 #define MAX_ARCH_DELEGATE_PARAMS 3
612 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
614 guint8 *code, *start;
615 GSList *unwind_ops = mono_arch_get_cie_program ();
618 start = code = mono_global_codeman_reserve (12);
620 /* Replace the this argument with the target */
621 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
622 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
623 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
625 g_assert ((code - start) <= 12);
627 mono_arch_flush_icache (start, 12);
631 size = 8 + param_count * 4;
632 start = code = mono_global_codeman_reserve (size);
634 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
635 /* slide down the arguments */
636 for (i = 0; i < param_count; ++i) {
637 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
639 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
641 g_assert ((code - start) <= size);
643 mono_arch_flush_icache (start, size);
647 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
649 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
650 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
654 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
660 * mono_arch_get_delegate_invoke_impls:
662 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
666 mono_arch_get_delegate_invoke_impls (void)
672 get_delegate_invoke_impl (&info, TRUE, 0);
673 res = g_slist_prepend (res, info);
675 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
676 get_delegate_invoke_impl (&info, FALSE, i);
677 res = g_slist_prepend (res, info);
684 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
686 guint8 *code, *start;
689 /* FIXME: Support more cases */
690 sig_ret = mini_get_underlying_type (sig->ret);
691 if (MONO_TYPE_ISSTRUCT (sig_ret))
695 static guint8* cached = NULL;
696 mono_mini_arch_lock ();
698 mono_mini_arch_unlock ();
703 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
706 start = get_delegate_invoke_impl (&info, TRUE, 0);
707 mono_tramp_info_register (info, NULL);
710 mono_mini_arch_unlock ();
713 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
716 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
718 for (i = 0; i < sig->param_count; ++i)
719 if (!mono_is_regsize_var (sig->params [i]))
722 mono_mini_arch_lock ();
723 code = cache [sig->param_count];
725 mono_mini_arch_unlock ();
730 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
731 start = mono_aot_get_trampoline (name);
735 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
736 mono_tramp_info_register (info, NULL);
738 cache [sig->param_count] = start;
739 mono_mini_arch_unlock ();
747 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
753 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
755 return (gpointer)regs [ARMREG_R0];
759 * Initialize the cpu to execute managed code.
762 mono_arch_cpu_init (void)
764 i8_align = MONO_ABI_ALIGNOF (gint64);
765 #ifdef MONO_CROSS_COMPILE
766 /* Need to set the alignment of i8 since it can different on the target */
767 #ifdef TARGET_ANDROID
769 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
775 * Initialize architecture specific code.
778 mono_arch_init (void)
782 #ifdef TARGET_WATCHOS
783 mini_get_debug_options ()->soft_breakpoints = TRUE;
786 mono_os_mutex_init_recursive (&mini_arch_mutex);
787 if (mini_get_debug_options ()->soft_breakpoints) {
789 breakpoint_tramp = mini_get_breakpoint_trampoline ();
791 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
792 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
793 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
796 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
797 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
798 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
799 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
800 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
802 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
803 #if defined(__ARM_EABI__)
804 eabi_supported = TRUE;
807 #if defined(ARM_FPU_VFP_HARD)
808 arm_fpu = MONO_ARM_FPU_VFP_HARD;
810 arm_fpu = MONO_ARM_FPU_VFP;
812 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
814 * If we're compiling with a soft float fallback and it
815 * turns out that no VFP unit is available, we need to
816 * switch to soft float. We don't do this for iOS, since
817 * iOS devices always have a VFP unit.
819 if (!mono_hwcap_arm_has_vfp)
820 arm_fpu = MONO_ARM_FPU_NONE;
823 * This environment variable can be useful in testing
824 * environments to make sure the soft float fallback
825 * works. Most ARM devices have VFP units these days, so
826 * normally soft float code would not be exercised much.
828 char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
830 if (soft && !strncmp (soft, "1", 1))
831 arm_fpu = MONO_ARM_FPU_NONE;
836 v5_supported = mono_hwcap_arm_is_v5;
837 v6_supported = mono_hwcap_arm_is_v6;
838 v7_supported = mono_hwcap_arm_is_v7;
841 * On weird devices, the hwcap code may fail to detect
842 * the ARM version. In that case, we can at least safely
843 * assume the version the runtime was compiled for.
855 #if defined(TARGET_IOS)
856 /* iOS is special-cased here because we don't yet
857 have a way to properly detect CPU features on it. */
858 thumb_supported = TRUE;
861 thumb_supported = mono_hwcap_arm_has_thumb;
862 thumb2_supported = mono_hwcap_arm_has_thumb2;
865 /* Format: armv(5|6|7[s])[-thumb[2]] */
866 cpu_arch = g_getenv ("MONO_CPU_ARCH");
868 /* Do this here so it overrides any detection. */
870 if (strncmp (cpu_arch, "armv", 4) == 0) {
871 v5_supported = cpu_arch [4] >= '5';
872 v6_supported = cpu_arch [4] >= '6';
873 v7_supported = cpu_arch [4] >= '7';
874 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
875 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
878 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
879 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
885 * Cleanup architecture specific code.
888 mono_arch_cleanup (void)
893 * This function returns the optimizations supported on this cpu.
896 mono_arch_cpu_optimizations (guint32 *exclude_mask)
898 /* no arm-specific optimizations yet */
904 * This function test for all SIMD functions supported.
906 * Returns a bitmask corresponding to all supported versions.
910 mono_arch_cpu_enumerate_simd_versions (void)
912 /* SIMD is currently unimplemented */
917 mono_arm_is_hard_float (void)
919 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
925 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
927 if (v7s_supported || v7k_supported) {
941 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
943 mono_arch_is_soft_float (void)
945 return arm_fpu == MONO_ARM_FPU_NONE;
950 is_regsize_var (MonoType *t)
954 t = mini_get_underlying_type (t);
961 case MONO_TYPE_FNPTR:
963 case MONO_TYPE_OBJECT:
965 case MONO_TYPE_GENERICINST:
966 if (!mono_type_generic_inst_is_valuetype (t))
969 case MONO_TYPE_VALUETYPE:
976 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
981 for (i = 0; i < cfg->num_varinfo; i++) {
982 MonoInst *ins = cfg->varinfo [i];
983 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
986 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
989 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
992 /* we can only allocate 32 bit values */
993 if (is_regsize_var (ins->inst_vtype)) {
994 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
995 g_assert (i == vmv->idx);
996 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1004 mono_arch_get_global_int_regs (MonoCompile *cfg)
1008 mono_arch_compute_omit_fp (cfg);
1011 * FIXME: Interface calls might go through a static rgctx trampoline which
1012 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1015 if (cfg->flags & MONO_CFG_HAS_CALLS)
1016 cfg->uses_rgctx_reg = TRUE;
1018 if (cfg->arch.omit_fp)
1019 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1020 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1021 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1022 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1024 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1025 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1027 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1028 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1029 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1030 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1031 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1032 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1038 * mono_arch_regalloc_cost:
1040 * Return the cost, in number of memory references, of the action of
1041 * allocating the variable VMV into a register during global register
1045 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1051 #endif /* #ifndef DISABLE_JIT */
1054 mono_arch_flush_icache (guint8 *code, gint size)
1056 #if defined(MONO_CROSS_COMPILE)
1058 sys_icache_invalidate (code, size);
1060 __builtin___clear_cache (code, code + size);
1067 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1070 if (*gr > ARMREG_R3) {
1072 ainfo->offset = *stack_size;
1073 ainfo->reg = ARMREG_SP; /* in the caller */
1074 ainfo->storage = RegTypeBase;
1077 ainfo->storage = RegTypeGeneral;
1084 split = i8_align == 4;
1089 if (*gr == ARMREG_R3 && split) {
1090 /* first word in r3 and the second on the stack */
1091 ainfo->offset = *stack_size;
1092 ainfo->reg = ARMREG_SP; /* in the caller */
1093 ainfo->storage = RegTypeBaseGen;
1095 } else if (*gr >= ARMREG_R3) {
1096 if (eabi_supported) {
1097 /* darwin aligns longs to 4 byte only */
1098 if (i8_align == 8) {
1103 ainfo->offset = *stack_size;
1104 ainfo->reg = ARMREG_SP; /* in the caller */
1105 ainfo->storage = RegTypeBase;
1108 if (eabi_supported) {
1109 if (i8_align == 8 && ((*gr) & 1))
1112 ainfo->storage = RegTypeIRegPair;
1121 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1124 * If we're calling a function like this:
1126 * void foo(float a, double b, float c)
1128 * We pass a in s0 and b in d1. That leaves us
1129 * with s1 being unused. The armhf ABI recognizes
1130 * this and requires register assignment to then
1131 * use that for the next single-precision arg,
1132 * i.e. c in this example. So float_spare either
1133 * tells us which reg to use for the next single-
1134 * precision arg, or it's -1, meaning use *fpr.
1136 * Note that even though most of the JIT speaks
1137 * double-precision, fpr represents single-
1138 * precision registers.
1140 * See parts 5.5 and 6.1.2 of the AAPCS for how
1144 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1145 ainfo->storage = RegTypeFP;
1149 * If we're passing a double-precision value
1150 * and *fpr is odd (e.g. it's s1, s3, ...)
1151 * we need to use the next even register. So
1152 * we mark the current *fpr as a spare that
1153 * can be used for the next single-precision
1157 *float_spare = *fpr;
1162 * At this point, we have an even register
1163 * so we assign that and move along.
1167 } else if (*float_spare >= 0) {
1169 * We're passing a single-precision value
1170 * and it looks like a spare single-
1171 * precision register is available. Let's
1175 ainfo->reg = *float_spare;
1179 * If we hit this branch, we're passing a
1180 * single-precision value and we can simply
1181 * use the next available register.
1189 * We've exhausted available floating point
1190 * regs, so pass the rest on the stack.
1198 ainfo->offset = *stack_size;
1199 ainfo->reg = ARMREG_SP;
1200 ainfo->storage = RegTypeBase;
1207 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1211 MonoClassField *field;
1212 MonoType *ftype, *prev_ftype = NULL;
1215 klass = mono_class_from_mono_type (t);
1217 while ((field = mono_class_get_fields (klass, &iter))) {
1218 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1220 ftype = mono_field_get_type (field);
1221 ftype = mini_get_underlying_type (ftype);
1223 if (MONO_TYPE_ISSTRUCT (ftype)) {
1224 int nested_nfields, nested_esize;
1226 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1228 if (nested_esize == 4)
1229 ftype = &mono_defaults.single_class->byval_arg;
1231 ftype = &mono_defaults.double_class->byval_arg;
1232 if (prev_ftype && prev_ftype->type != ftype->type)
1235 nfields += nested_nfields;
1237 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1239 if (prev_ftype && prev_ftype->type != ftype->type)
1245 if (nfields == 0 || nfields > 4)
1247 *out_nfields = nfields;
1248 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1253 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1255 guint i, gr, fpr, pstart;
1257 int n = sig->hasthis + sig->param_count;
1261 guint32 stack_size = 0;
1263 gboolean is_pinvoke = sig->pinvoke;
1264 gboolean vtype_retaddr = FALSE;
1267 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1269 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1276 t = mini_get_underlying_type (sig->ret);
1287 case MONO_TYPE_FNPTR:
1288 case MONO_TYPE_OBJECT:
1289 cinfo->ret.storage = RegTypeGeneral;
1290 cinfo->ret.reg = ARMREG_R0;
1294 cinfo->ret.storage = RegTypeIRegPair;
1295 cinfo->ret.reg = ARMREG_R0;
1299 cinfo->ret.storage = RegTypeFP;
1301 if (t->type == MONO_TYPE_R4)
1302 cinfo->ret.size = 4;
1304 cinfo->ret.size = 8;
1306 if (IS_HARD_FLOAT) {
1307 cinfo->ret.reg = ARM_VFP_F0;
1309 cinfo->ret.reg = ARMREG_R0;
1312 case MONO_TYPE_GENERICINST:
1313 if (!mono_type_generic_inst_is_valuetype (t)) {
1314 cinfo->ret.storage = RegTypeGeneral;
1315 cinfo->ret.reg = ARMREG_R0;
1318 if (mini_is_gsharedvt_variable_type (t)) {
1319 cinfo->ret.storage = RegTypeStructByAddr;
1323 case MONO_TYPE_VALUETYPE:
1324 case MONO_TYPE_TYPEDBYREF:
1325 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1326 cinfo->ret.storage = RegTypeHFA;
1328 cinfo->ret.nregs = nfields;
1329 cinfo->ret.esize = esize;
1332 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1335 #ifdef TARGET_WATCHOS
1340 if (native_size <= max_size) {
1341 cinfo->ret.storage = RegTypeStructByVal;
1342 cinfo->ret.struct_size = native_size;
1343 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1345 cinfo->ret.storage = RegTypeStructByAddr;
1348 cinfo->ret.storage = RegTypeStructByAddr;
1353 case MONO_TYPE_MVAR:
1354 g_assert (mini_is_gsharedvt_type (t));
1355 cinfo->ret.storage = RegTypeStructByAddr;
1357 case MONO_TYPE_VOID:
1360 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1363 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1368 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1369 * the first argument, allowing 'this' to be always passed in the first arg reg.
1370 * Also do this if the first argument is a reference type, since virtual calls
1371 * are sometimes made using calli without sig->hasthis set, like in the delegate
1374 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1376 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1378 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1382 cinfo->ret.reg = gr;
1384 cinfo->vret_arg_index = 1;
1388 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1391 if (vtype_retaddr) {
1392 cinfo->ret.reg = gr;
1397 DEBUG(g_print("params: %d\n", sig->param_count));
1398 for (i = pstart; i < sig->param_count; ++i) {
1399 ArgInfo *ainfo = &cinfo->args [n];
1401 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1402 /* Prevent implicit arguments and sig_cookie from
1403 being passed in registers */
1406 /* Emit the signature cookie just before the implicit arguments */
1407 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1409 DEBUG(g_print("param %d: ", i));
1410 if (sig->params [i]->byref) {
1411 DEBUG(g_print("byref\n"));
1412 add_general (&gr, &stack_size, ainfo, TRUE);
1416 t = mini_get_underlying_type (sig->params [i]);
1420 cinfo->args [n].size = 1;
1421 add_general (&gr, &stack_size, ainfo, TRUE);
1425 cinfo->args [n].size = 2;
1426 add_general (&gr, &stack_size, ainfo, TRUE);
1430 cinfo->args [n].size = 4;
1431 add_general (&gr, &stack_size, ainfo, TRUE);
1436 case MONO_TYPE_FNPTR:
1437 case MONO_TYPE_OBJECT:
1438 cinfo->args [n].size = sizeof (gpointer);
1439 add_general (&gr, &stack_size, ainfo, TRUE);
1441 case MONO_TYPE_GENERICINST:
1442 if (!mono_type_generic_inst_is_valuetype (t)) {
1443 cinfo->args [n].size = sizeof (gpointer);
1444 add_general (&gr, &stack_size, ainfo, TRUE);
1447 if (mini_is_gsharedvt_variable_type (t)) {
1448 /* gsharedvt arguments are passed by ref */
1449 g_assert (mini_is_gsharedvt_type (t));
1450 add_general (&gr, &stack_size, ainfo, TRUE);
1451 switch (ainfo->storage) {
1452 case RegTypeGeneral:
1453 ainfo->storage = RegTypeGSharedVtInReg;
1456 ainfo->storage = RegTypeGSharedVtOnStack;
1459 g_assert_not_reached ();
1464 case MONO_TYPE_TYPEDBYREF:
1465 case MONO_TYPE_VALUETYPE: {
1468 int nwords, nfields, esize;
1471 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1472 if (fpr + nfields < ARM_VFP_F16) {
1473 ainfo->storage = RegTypeHFA;
1475 ainfo->nregs = nfields;
1476 ainfo->esize = esize;
1487 if (t->type == MONO_TYPE_TYPEDBYREF) {
1488 size = sizeof (MonoTypedRef);
1489 align = sizeof (gpointer);
1491 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1493 size = mono_class_native_size (klass, &align);
1495 size = mini_type_stack_size_full (t, &align, FALSE);
1497 DEBUG(g_print ("load %d bytes struct\n", size));
1499 #ifdef TARGET_WATCHOS
1500 /* Watchos pass large structures by ref */
1501 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1502 if (sig->pinvoke && size > 16) {
1503 add_general (&gr, &stack_size, ainfo, TRUE);
1504 switch (ainfo->storage) {
1505 case RegTypeGeneral:
1506 ainfo->storage = RegTypeStructByAddr;
1509 ainfo->storage = RegTypeStructByAddrOnStack;
1512 g_assert_not_reached ();
1521 align_size += (sizeof (gpointer) - 1);
1522 align_size &= ~(sizeof (gpointer) - 1);
1523 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1524 ainfo->storage = RegTypeStructByVal;
1525 ainfo->struct_size = size;
1526 ainfo->align = align;
1527 /* FIXME: align stack_size if needed */
1528 if (eabi_supported) {
1529 if (align >= 8 && (gr & 1))
1532 if (gr > ARMREG_R3) {
1534 ainfo->vtsize = nwords;
1536 int rest = ARMREG_R3 - gr + 1;
1537 int n_in_regs = rest >= nwords? nwords: rest;
1539 ainfo->size = n_in_regs;
1540 ainfo->vtsize = nwords - n_in_regs;
1543 nwords -= n_in_regs;
1545 if (sig->call_convention == MONO_CALL_VARARG)
1546 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1547 stack_size = ALIGN_TO (stack_size, align);
1548 ainfo->offset = stack_size;
1549 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1550 stack_size += nwords * sizeof (gpointer);
1556 add_general (&gr, &stack_size, ainfo, FALSE);
1562 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1564 add_general (&gr, &stack_size, ainfo, TRUE);
1570 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1572 add_general (&gr, &stack_size, ainfo, FALSE);
1575 case MONO_TYPE_MVAR:
1576 /* gsharedvt arguments are passed by ref */
1577 g_assert (mini_is_gsharedvt_type (t));
1578 add_general (&gr, &stack_size, ainfo, TRUE);
1579 switch (ainfo->storage) {
1580 case RegTypeGeneral:
1581 ainfo->storage = RegTypeGSharedVtInReg;
1584 ainfo->storage = RegTypeGSharedVtOnStack;
1587 g_assert_not_reached ();
1591 g_error ("Can't handle 0x%x", sig->params [i]->type);
1596 /* Handle the case where there are no implicit arguments */
1597 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1598 /* Prevent implicit arguments and sig_cookie from
1599 being passed in registers */
1602 /* Emit the signature cookie just before the implicit arguments */
1603 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1606 /* align stack size to 8 */
1607 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1608 stack_size = (stack_size + 7) & ~7;
1610 cinfo->stack_usage = stack_size;
1616 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1618 MonoType *callee_ret;
1622 c1 = get_call_info (NULL, caller_sig);
1623 c2 = get_call_info (NULL, callee_sig);
1626 * Tail calls with more callee stack usage than the caller cannot be supported, since
1627 * the extra stack space would be left on the stack after the tail call.
1629 res = c1->stack_usage >= c2->stack_usage;
1630 callee_ret = mini_get_underlying_type (callee_sig->ret);
1631 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1632 /* An address on the callee's stack is passed as the first argument */
1635 if (c2->stack_usage > 16 * 4)
1647 debug_omit_fp (void)
1650 return mono_debug_count ();
1657 * mono_arch_compute_omit_fp:
1658 * Determine whether the frame pointer can be eliminated.
1661 mono_arch_compute_omit_fp (MonoCompile *cfg)
1663 MonoMethodSignature *sig;
1664 MonoMethodHeader *header;
1668 if (cfg->arch.omit_fp_computed)
1671 header = cfg->header;
1673 sig = mono_method_signature (cfg->method);
1675 if (!cfg->arch.cinfo)
1676 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1677 cinfo = cfg->arch.cinfo;
1680 * FIXME: Remove some of the restrictions.
1682 cfg->arch.omit_fp = TRUE;
1683 cfg->arch.omit_fp_computed = TRUE;
1685 if (cfg->disable_omit_fp)
1686 cfg->arch.omit_fp = FALSE;
1687 if (!debug_omit_fp ())
1688 cfg->arch.omit_fp = FALSE;
1690 if (cfg->method->save_lmf)
1691 cfg->arch.omit_fp = FALSE;
1693 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1694 cfg->arch.omit_fp = FALSE;
1695 if (header->num_clauses)
1696 cfg->arch.omit_fp = FALSE;
1697 if (cfg->param_area)
1698 cfg->arch.omit_fp = FALSE;
1699 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1700 cfg->arch.omit_fp = FALSE;
1701 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1702 cfg->arch.omit_fp = FALSE;
1703 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1704 ArgInfo *ainfo = &cinfo->args [i];
1706 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1708 * The stack offset can only be determined when the frame
1711 cfg->arch.omit_fp = FALSE;
1716 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1717 MonoInst *ins = cfg->varinfo [i];
1720 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1725 * Set var information according to the calling convention. arm version.
1726 * The locals var stuff should most likely be split in another method.
1729 mono_arch_allocate_vars (MonoCompile *cfg)
1731 MonoMethodSignature *sig;
1732 MonoMethodHeader *header;
1735 int i, offset, size, align, curinst;
1740 sig = mono_method_signature (cfg->method);
1742 if (!cfg->arch.cinfo)
1743 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1744 cinfo = cfg->arch.cinfo;
1745 sig_ret = mini_get_underlying_type (sig->ret);
1747 mono_arch_compute_omit_fp (cfg);
1749 if (cfg->arch.omit_fp)
1750 cfg->frame_reg = ARMREG_SP;
1752 cfg->frame_reg = ARMREG_FP;
1754 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1756 /* allow room for the vararg method args: void* and long/double */
1757 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1758 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1760 header = cfg->header;
1762 /* See mono_arch_get_global_int_regs () */
1763 if (cfg->flags & MONO_CFG_HAS_CALLS)
1764 cfg->uses_rgctx_reg = TRUE;
1766 if (cfg->frame_reg != ARMREG_SP)
1767 cfg->used_int_regs |= 1 << cfg->frame_reg;
1769 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1770 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1771 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1775 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1776 if (sig_ret->type != MONO_TYPE_VOID) {
1777 cfg->ret->opcode = OP_REGVAR;
1778 cfg->ret->inst_c0 = ARMREG_R0;
1781 /* local vars are at a positive offset from the stack pointer */
1783 * also note that if the function uses alloca, we use FP
1784 * to point at the local variables.
1786 offset = 0; /* linkage area */
1787 /* align the offset to 16 bytes: not sure this is needed here */
1789 //offset &= ~(8 - 1);
1791 /* add parameter area size for called functions */
1792 offset += cfg->param_area;
1795 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1798 /* allow room to save the return value */
1799 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1802 switch (cinfo->ret.storage) {
1803 case RegTypeStructByVal:
1805 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1806 offset = ALIGN_TO (offset, 8);
1807 cfg->ret->opcode = OP_REGOFFSET;
1808 cfg->ret->inst_basereg = cfg->frame_reg;
1809 cfg->ret->inst_offset = offset;
1810 if (cinfo->ret.storage == RegTypeStructByVal)
1811 offset += cinfo->ret.nregs * sizeof (gpointer);
1815 case RegTypeStructByAddr:
1816 ins = cfg->vret_addr;
1817 offset += sizeof(gpointer) - 1;
1818 offset &= ~(sizeof(gpointer) - 1);
1819 ins->inst_offset = offset;
1820 ins->opcode = OP_REGOFFSET;
1821 ins->inst_basereg = cfg->frame_reg;
1822 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1823 g_print ("vret_addr =");
1824 mono_print_ins (cfg->vret_addr);
1826 offset += sizeof(gpointer);
1832 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1833 if (cfg->arch.seq_point_info_var) {
1836 ins = cfg->arch.seq_point_info_var;
1840 offset += align - 1;
1841 offset &= ~(align - 1);
1842 ins->opcode = OP_REGOFFSET;
1843 ins->inst_basereg = cfg->frame_reg;
1844 ins->inst_offset = offset;
1847 if (cfg->arch.ss_trigger_page_var) {
1850 ins = cfg->arch.ss_trigger_page_var;
1853 offset += align - 1;
1854 offset &= ~(align - 1);
1855 ins->opcode = OP_REGOFFSET;
1856 ins->inst_basereg = cfg->frame_reg;
1857 ins->inst_offset = offset;
1861 if (cfg->arch.seq_point_ss_method_var) {
1864 ins = cfg->arch.seq_point_ss_method_var;
1867 offset += align - 1;
1868 offset &= ~(align - 1);
1869 ins->opcode = OP_REGOFFSET;
1870 ins->inst_basereg = cfg->frame_reg;
1871 ins->inst_offset = offset;
1874 if (cfg->arch.seq_point_bp_method_var) {
1877 ins = cfg->arch.seq_point_bp_method_var;
1880 offset += align - 1;
1881 offset &= ~(align - 1);
1882 ins->opcode = OP_REGOFFSET;
1883 ins->inst_basereg = cfg->frame_reg;
1884 ins->inst_offset = offset;
1888 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1889 /* Allocate a temporary used by the atomic ops */
1893 /* Allocate a local slot to hold the sig cookie address */
1894 offset += align - 1;
1895 offset &= ~(align - 1);
1896 cfg->arch.atomic_tmp_offset = offset;
1899 cfg->arch.atomic_tmp_offset = -1;
1902 cfg->locals_min_stack_offset = offset;
1904 curinst = cfg->locals_start;
1905 for (i = curinst; i < cfg->num_varinfo; ++i) {
1908 ins = cfg->varinfo [i];
1909 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1912 t = ins->inst_vtype;
1913 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1916 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1917 * pinvoke wrappers when they call functions returning structure */
1918 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1919 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1923 size = mono_type_size (t, &align);
1925 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1926 * since it loads/stores misaligned words, which don't do the right thing.
1928 if (align < 4 && size >= 4)
1930 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1931 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1932 offset += align - 1;
1933 offset &= ~(align - 1);
1934 ins->opcode = OP_REGOFFSET;
1935 ins->inst_offset = offset;
1936 ins->inst_basereg = cfg->frame_reg;
1938 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1941 cfg->locals_max_stack_offset = offset;
1945 ins = cfg->args [curinst];
1946 if (ins->opcode != OP_REGVAR) {
1947 ins->opcode = OP_REGOFFSET;
1948 ins->inst_basereg = cfg->frame_reg;
1949 offset += sizeof (gpointer) - 1;
1950 offset &= ~(sizeof (gpointer) - 1);
1951 ins->inst_offset = offset;
1952 offset += sizeof (gpointer);
1957 if (sig->call_convention == MONO_CALL_VARARG) {
1961 /* Allocate a local slot to hold the sig cookie address */
1962 offset += align - 1;
1963 offset &= ~(align - 1);
1964 cfg->sig_cookie = offset;
1968 for (i = 0; i < sig->param_count; ++i) {
1969 ainfo = cinfo->args + i;
1971 ins = cfg->args [curinst];
1973 switch (ainfo->storage) {
1975 offset = ALIGN_TO (offset, 8);
1976 ins->opcode = OP_REGOFFSET;
1977 ins->inst_basereg = cfg->frame_reg;
1978 /* These arguments are saved to the stack in the prolog */
1979 ins->inst_offset = offset;
1980 if (cfg->verbose_level >= 2)
1981 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1989 if (ins->opcode != OP_REGVAR) {
1990 ins->opcode = OP_REGOFFSET;
1991 ins->inst_basereg = cfg->frame_reg;
1992 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1994 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1995 * since it loads/stores misaligned words, which don't do the right thing.
1997 if (align < 4 && size >= 4)
1999 /* The code in the prolog () stores words when storing vtypes received in a register */
2000 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2002 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2003 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2004 offset += align - 1;
2005 offset &= ~(align - 1);
2006 ins->inst_offset = offset;
2012 /* align the offset to 8 bytes */
2013 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2014 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2019 cfg->stack_offset = offset;
2023 mono_arch_create_vars (MonoCompile *cfg)
2025 MonoMethodSignature *sig;
2029 sig = mono_method_signature (cfg->method);
2031 if (!cfg->arch.cinfo)
2032 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2033 cinfo = cfg->arch.cinfo;
2035 if (IS_HARD_FLOAT) {
2036 for (i = 0; i < 2; i++) {
2037 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2038 inst->flags |= MONO_INST_VOLATILE;
2040 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2044 if (cinfo->ret.storage == RegTypeStructByVal)
2045 cfg->ret_var_is_local = TRUE;
2047 if (cinfo->ret.storage == RegTypeStructByAddr) {
2048 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2049 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2050 g_print ("vret_addr = ");
2051 mono_print_ins (cfg->vret_addr);
2055 if (cfg->gen_sdb_seq_points) {
2056 if (cfg->compile_aot) {
2057 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2058 ins->flags |= MONO_INST_VOLATILE;
2059 cfg->arch.seq_point_info_var = ins;
2061 if (!cfg->soft_breakpoints) {
2062 /* Allocate a separate variable for this to save 1 load per seq point */
2063 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2064 ins->flags |= MONO_INST_VOLATILE;
2065 cfg->arch.ss_trigger_page_var = ins;
2068 if (cfg->soft_breakpoints) {
2071 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2072 ins->flags |= MONO_INST_VOLATILE;
2073 cfg->arch.seq_point_ss_method_var = ins;
2075 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2076 ins->flags |= MONO_INST_VOLATILE;
2077 cfg->arch.seq_point_bp_method_var = ins;
2083 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2085 MonoMethodSignature *tmp_sig;
2088 if (call->tail_call)
2091 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2094 * mono_ArgIterator_Setup assumes the signature cookie is
2095 * passed first and all the arguments which were before it are
2096 * passed on the stack after the signature. So compensate by
2097 * passing a different signature.
2099 tmp_sig = mono_metadata_signature_dup (call->signature);
2100 tmp_sig->param_count -= call->signature->sentinelpos;
2101 tmp_sig->sentinelpos = 0;
2102 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2104 sig_reg = mono_alloc_ireg (cfg);
2105 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2107 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2112 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2117 LLVMCallInfo *linfo;
2119 n = sig->param_count + sig->hasthis;
2121 cinfo = get_call_info (cfg->mempool, sig);
2123 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2126 * LLVM always uses the native ABI while we use our own ABI, the
2127 * only difference is the handling of vtypes:
2128 * - we only pass/receive them in registers in some cases, and only
2129 * in 1 or 2 integer registers.
2131 switch (cinfo->ret.storage) {
2132 case RegTypeGeneral:
2135 case RegTypeIRegPair:
2137 case RegTypeStructByAddr:
2138 /* Vtype returned using a hidden argument */
2139 linfo->ret.storage = LLVMArgVtypeRetAddr;
2140 linfo->vret_arg_index = cinfo->vret_arg_index;
2143 case RegTypeStructByVal:
2144 /* LLVM models this by returning an int array */
2145 linfo->ret.storage = LLVMArgAsIArgs;
2146 linfo->ret.nslots = cinfo->ret.nregs;
2150 linfo->ret.storage = LLVMArgFpStruct;
2151 linfo->ret.nslots = cinfo->ret.nregs;
2152 linfo->ret.esize = cinfo->ret.esize;
2155 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2156 cfg->disable_llvm = TRUE;
2160 for (i = 0; i < n; ++i) {
2161 LLVMArgInfo *lainfo = &linfo->args [i];
2162 ainfo = cinfo->args + i;
2164 lainfo->storage = LLVMArgNone;
2166 switch (ainfo->storage) {
2167 case RegTypeGeneral:
2168 case RegTypeIRegPair:
2170 case RegTypeBaseGen:
2172 lainfo->storage = LLVMArgNormal;
2174 case RegTypeStructByVal:
2175 lainfo->storage = LLVMArgAsIArgs;
2176 if (eabi_supported && ainfo->align == 8) {
2177 /* LLVM models this by passing an int64 array */
2178 lainfo->nslots = ALIGN_TO (ainfo->struct_size, 8) / 8;
2181 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2185 case RegTypeStructByAddr:
2186 case RegTypeStructByAddrOnStack:
2187 lainfo->storage = LLVMArgVtypeByRef;
2192 lainfo->storage = LLVMArgAsFpArgs;
2193 lainfo->nslots = ainfo->nregs;
2194 lainfo->esize = ainfo->esize;
2195 for (j = 0; j < ainfo->nregs; ++j)
2196 lainfo->pair_storage [j] = LLVMArgInFPReg;
2200 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2201 cfg->disable_llvm = TRUE;
2211 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2214 MonoMethodSignature *sig;
2218 sig = call->signature;
2219 n = sig->param_count + sig->hasthis;
2221 cinfo = get_call_info (cfg->mempool, sig);
2223 switch (cinfo->ret.storage) {
2224 case RegTypeStructByVal:
2226 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2227 /* The JIT will transform this into a normal call */
2228 call->vret_in_reg = TRUE;
2231 if (call->inst.opcode == OP_TAILCALL)
2234 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2235 * the location pointed to by it after call in emit_move_return_value ().
2237 if (!cfg->arch.vret_addr_loc) {
2238 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2239 /* Prevent it from being register allocated or optimized away */
2240 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2243 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2245 case RegTypeStructByAddr: {
2247 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2248 vtarg->sreg1 = call->vret_var->dreg;
2249 vtarg->dreg = mono_alloc_preg (cfg);
2250 MONO_ADD_INS (cfg->cbb, vtarg);
2252 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2259 for (i = 0; i < n; ++i) {
2260 ArgInfo *ainfo = cinfo->args + i;
2263 if (i >= sig->hasthis)
2264 t = sig->params [i - sig->hasthis];
2266 t = &mono_defaults.int_class->byval_arg;
2267 t = mini_get_underlying_type (t);
2269 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2270 /* Emit the signature cookie just before the implicit arguments */
2271 emit_sig_cookie (cfg, call, cinfo);
2274 in = call->args [i];
2276 switch (ainfo->storage) {
2277 case RegTypeGeneral:
2278 case RegTypeIRegPair:
2279 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2280 MONO_INST_NEW (cfg, ins, OP_MOVE);
2281 ins->dreg = mono_alloc_ireg (cfg);
2282 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2283 MONO_ADD_INS (cfg->cbb, ins);
2284 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2286 MONO_INST_NEW (cfg, ins, OP_MOVE);
2287 ins->dreg = mono_alloc_ireg (cfg);
2288 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2289 MONO_ADD_INS (cfg->cbb, ins);
2290 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2291 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2292 if (ainfo->size == 4) {
2293 if (IS_SOFT_FLOAT) {
2294 /* mono_emit_call_args () have already done the r8->r4 conversion */
2295 /* The converted value is in an int vreg */
2296 MONO_INST_NEW (cfg, ins, OP_MOVE);
2297 ins->dreg = mono_alloc_ireg (cfg);
2298 ins->sreg1 = in->dreg;
2299 MONO_ADD_INS (cfg->cbb, ins);
2300 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2304 cfg->param_area = MAX (cfg->param_area, 8);
2305 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2306 creg = mono_alloc_ireg (cfg);
2307 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2308 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2311 if (IS_SOFT_FLOAT) {
2312 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2313 ins->dreg = mono_alloc_ireg (cfg);
2314 ins->sreg1 = in->dreg;
2315 MONO_ADD_INS (cfg->cbb, ins);
2316 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2318 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2319 ins->dreg = mono_alloc_ireg (cfg);
2320 ins->sreg1 = in->dreg;
2321 MONO_ADD_INS (cfg->cbb, ins);
2322 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2326 cfg->param_area = MAX (cfg->param_area, 8);
2327 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2328 creg = mono_alloc_ireg (cfg);
2329 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2330 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2331 creg = mono_alloc_ireg (cfg);
2332 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2333 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2336 cfg->flags |= MONO_CFG_HAS_FPOUT;
2338 MONO_INST_NEW (cfg, ins, OP_MOVE);
2339 ins->dreg = mono_alloc_ireg (cfg);
2340 ins->sreg1 = in->dreg;
2341 MONO_ADD_INS (cfg->cbb, ins);
2343 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2346 case RegTypeStructByVal:
2347 case RegTypeGSharedVtInReg:
2348 case RegTypeGSharedVtOnStack:
2350 case RegTypeStructByAddr:
2351 case RegTypeStructByAddrOnStack:
2352 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2353 ins->opcode = OP_OUTARG_VT;
2354 ins->sreg1 = in->dreg;
2355 ins->klass = in->klass;
2356 ins->inst_p0 = call;
2357 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2358 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2359 mono_call_inst_add_outarg_vt (cfg, call, ins);
2360 MONO_ADD_INS (cfg->cbb, ins);
2363 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2365 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2366 if (t->type == MONO_TYPE_R8) {
2367 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2370 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2372 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2375 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2378 case RegTypeBaseGen:
2379 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2380 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2381 MONO_INST_NEW (cfg, ins, OP_MOVE);
2382 ins->dreg = mono_alloc_ireg (cfg);
2383 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2384 MONO_ADD_INS (cfg->cbb, ins);
2385 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2386 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2389 /* This should work for soft-float as well */
2391 cfg->param_area = MAX (cfg->param_area, 8);
2392 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2393 creg = mono_alloc_ireg (cfg);
2394 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2395 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2396 creg = mono_alloc_ireg (cfg);
2397 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2398 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2399 cfg->flags |= MONO_CFG_HAS_FPOUT;
2401 g_assert_not_reached ();
2405 int fdreg = mono_alloc_freg (cfg);
2407 if (ainfo->size == 8) {
2408 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2409 ins->sreg1 = in->dreg;
2411 MONO_ADD_INS (cfg->cbb, ins);
2413 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2418 * Mono's register allocator doesn't speak single-precision registers that
2419 * overlap double-precision registers (i.e. armhf). So we have to work around
2420 * the register allocator and load the value from memory manually.
2422 * So we create a variable for the float argument and an instruction to store
2423 * the argument into the variable. We then store the list of these arguments
2424 * in call->float_args. This list is then used by emit_float_args later to
2425 * pass the arguments in the various call opcodes.
2427 * This is not very nice, and we should really try to fix the allocator.
2430 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2432 /* Make sure the instruction isn't seen as pointless and removed.
2434 float_arg->flags |= MONO_INST_VOLATILE;
2436 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2438 /* We use the dreg to look up the instruction later. The hreg is used to
2439 * emit the instruction that loads the value into the FP reg.
2441 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2442 fad->vreg = float_arg->dreg;
2443 fad->hreg = ainfo->reg;
2445 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2448 call->used_iregs |= 1 << ainfo->reg;
2449 cfg->flags |= MONO_CFG_HAS_FPOUT;
2453 g_assert_not_reached ();
2457 /* Handle the case where there are no implicit arguments */
2458 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2459 emit_sig_cookie (cfg, call, cinfo);
2461 call->call_info = cinfo;
2462 call->stack_usage = cinfo->stack_usage;
2466 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2472 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2473 ins->dreg = mono_alloc_freg (cfg);
2474 ins->sreg1 = arg->dreg;
2475 MONO_ADD_INS (cfg->cbb, ins);
2476 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2479 g_assert_not_reached ();
2485 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2487 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2489 ArgInfo *ainfo = ins->inst_p1;
2490 int ovf_size = ainfo->vtsize;
2491 int doffset = ainfo->offset;
2492 int struct_size = ainfo->struct_size;
2493 int i, soffset, dreg, tmpreg;
2495 switch (ainfo->storage) {
2496 case RegTypeGSharedVtInReg:
2497 case RegTypeStructByAddr:
2499 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2501 case RegTypeGSharedVtOnStack:
2502 case RegTypeStructByAddrOnStack:
2503 /* Pass by addr on stack */
2504 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2507 for (i = 0; i < ainfo->nregs; ++i) {
2508 if (ainfo->esize == 4)
2509 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2511 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2512 load->dreg = mono_alloc_freg (cfg);
2513 load->inst_basereg = src->dreg;
2514 load->inst_offset = i * ainfo->esize;
2515 MONO_ADD_INS (cfg->cbb, load);
2517 if (ainfo->esize == 4) {
2520 /* See RegTypeFP in mono_arch_emit_call () */
2521 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2522 float_arg->flags |= MONO_INST_VOLATILE;
2523 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2525 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2526 fad->vreg = float_arg->dreg;
2527 fad->hreg = ainfo->reg + i;
2529 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2531 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2537 for (i = 0; i < ainfo->size; ++i) {
2538 dreg = mono_alloc_ireg (cfg);
2539 switch (struct_size) {
2541 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2544 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2547 tmpreg = mono_alloc_ireg (cfg);
2548 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2549 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2550 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2551 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2552 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2553 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2554 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2557 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2560 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2561 soffset += sizeof (gpointer);
2562 struct_size -= sizeof (gpointer);
2564 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2566 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2572 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2574 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2577 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2580 if (COMPILE_LLVM (cfg)) {
2581 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2583 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2584 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2585 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2586 MONO_ADD_INS (cfg->cbb, ins);
2591 case MONO_ARM_FPU_NONE:
2592 if (ret->type == MONO_TYPE_R8) {
2595 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2596 ins->dreg = cfg->ret->dreg;
2597 ins->sreg1 = val->dreg;
2598 MONO_ADD_INS (cfg->cbb, ins);
2601 if (ret->type == MONO_TYPE_R4) {
2602 /* Already converted to an int in method_to_ir () */
2603 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2607 case MONO_ARM_FPU_VFP:
2608 case MONO_ARM_FPU_VFP_HARD:
2609 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2612 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2613 ins->dreg = cfg->ret->dreg;
2614 ins->sreg1 = val->dreg;
2615 MONO_ADD_INS (cfg->cbb, ins);
2620 g_assert_not_reached ();
2624 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2627 #endif /* #ifndef DISABLE_JIT */
2630 mono_arch_is_inst_imm (gint64 imm)
2636 MonoMethodSignature *sig;
2639 MonoType **param_types;
2643 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2647 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2650 switch (cinfo->ret.storage) {
2652 case RegTypeGeneral:
2653 case RegTypeIRegPair:
2654 case RegTypeStructByAddr:
2665 for (i = 0; i < cinfo->nargs; ++i) {
2666 ArgInfo *ainfo = &cinfo->args [i];
2669 switch (ainfo->storage) {
2670 case RegTypeGeneral:
2671 case RegTypeIRegPair:
2672 case RegTypeBaseGen:
2676 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2679 case RegTypeStructByVal:
2680 if (ainfo->size == 0)
2681 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2683 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2684 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2692 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2693 for (i = 0; i < sig->param_count; ++i) {
2694 MonoType *t = sig->params [i];
2699 t = mini_get_underlying_type (t);
2722 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2724 ArchDynCallInfo *info;
2728 cinfo = get_call_info (NULL, sig);
2730 if (!dyn_call_supported (cinfo, sig)) {
2735 info = g_new0 (ArchDynCallInfo, 1);
2736 // FIXME: Preprocess the info to speed up start_dyn_call ()
2738 info->cinfo = cinfo;
2739 info->rtype = mini_get_underlying_type (sig->ret);
2740 info->param_types = g_new0 (MonoType*, sig->param_count);
2741 for (i = 0; i < sig->param_count; ++i)
2742 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2744 return (MonoDynCallInfo*)info;
2748 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2750 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2752 g_free (ainfo->cinfo);
2757 mono_arch_dyn_call_get_buf_size (MonoDynCallInfo *info)
2759 return sizeof (DynCallArgs);
2763 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf)
2765 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2766 DynCallArgs *p = (DynCallArgs*)buf;
2767 int arg_index, greg, i, j, pindex;
2768 MonoMethodSignature *sig = dinfo->sig;
2778 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2779 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2784 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2785 p->regs [greg ++] = (mgreg_t)ret;
2787 for (i = pindex; i < sig->param_count; i++) {
2788 MonoType *t = dinfo->param_types [i];
2789 gpointer *arg = args [arg_index ++];
2790 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2793 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2795 } else if (ainfo->storage == RegTypeFP) {
2796 } else if (ainfo->storage == RegTypeBase) {
2797 slot = PARAM_REGS + (ainfo->offset / 4);
2798 } else if (ainfo->storage == RegTypeBaseGen) {
2799 /* slot + 1 is the first stack slot, so the code below will work */
2802 g_assert_not_reached ();
2806 p->regs [slot] = (mgreg_t)*arg;
2811 case MONO_TYPE_OBJECT:
2815 p->regs [slot] = (mgreg_t)*arg;
2818 p->regs [slot] = *(guint8*)arg;
2821 p->regs [slot] = *(gint8*)arg;
2824 p->regs [slot] = *(gint16*)arg;
2827 p->regs [slot] = *(guint16*)arg;
2830 p->regs [slot] = *(gint32*)arg;
2833 p->regs [slot] = *(guint32*)arg;
2837 p->regs [slot ++] = (mgreg_t)arg [0];
2838 p->regs [slot] = (mgreg_t)arg [1];
2841 if (ainfo->storage == RegTypeFP) {
2842 float f = *(float*)arg;
2843 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2846 p->regs [slot] = *(mgreg_t*)arg;
2850 if (ainfo->storage == RegTypeFP) {
2851 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2854 p->regs [slot ++] = (mgreg_t)arg [0];
2855 p->regs [slot] = (mgreg_t)arg [1];
2858 case MONO_TYPE_GENERICINST:
2859 if (MONO_TYPE_IS_REFERENCE (t)) {
2860 p->regs [slot] = (mgreg_t)*arg;
2863 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2864 MonoClass *klass = mono_class_from_mono_type (t);
2865 guint8 *nullable_buf;
2868 size = mono_class_value_size (klass, NULL);
2869 nullable_buf = g_alloca (size);
2870 g_assert (nullable_buf);
2872 /* The argument pointed to by arg is either a boxed vtype or null */
2873 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2875 arg = (gpointer*)nullable_buf;
2881 case MONO_TYPE_VALUETYPE:
2882 g_assert (ainfo->storage == RegTypeStructByVal);
2884 if (ainfo->size == 0)
2885 slot = PARAM_REGS + (ainfo->offset / 4);
2889 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2890 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2893 g_assert_not_reached ();
2899 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2901 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2902 DynCallArgs *p = (DynCallArgs*)buf;
2903 MonoType *ptype = ainfo->rtype;
2904 guint8 *ret = p->ret;
2905 mgreg_t res = p->res;
2906 mgreg_t res2 = p->res2;
2908 switch (ptype->type) {
2909 case MONO_TYPE_VOID:
2910 *(gpointer*)ret = NULL;
2912 case MONO_TYPE_OBJECT:
2916 *(gpointer*)ret = (gpointer)res;
2922 *(guint8*)ret = res;
2925 *(gint16*)ret = res;
2928 *(guint16*)ret = res;
2931 *(gint32*)ret = res;
2934 *(guint32*)ret = res;
2938 /* This handles endianness as well */
2939 ((gint32*)ret) [0] = res;
2940 ((gint32*)ret) [1] = res2;
2942 case MONO_TYPE_GENERICINST:
2943 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2944 *(gpointer*)ret = (gpointer)res;
2949 case MONO_TYPE_VALUETYPE:
2950 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2956 *(float*)ret = *(float*)&p->fpregs [0];
2958 *(float*)ret = *(float*)&res;
2960 case MONO_TYPE_R8: {
2964 if (IS_HARD_FLOAT) {
2965 *(double*)ret = p->fpregs [0];
2970 *(double*)ret = *(double*)®s;
2975 g_assert_not_reached ();
2982 * Allow tracing to work with this interface (with an optional argument)
2986 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2990 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2991 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2992 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2993 code = emit_call_reg (code, ARMREG_R2);
3007 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3010 int save_mode = SAVE_NONE;
3012 MonoMethod *method = cfg->method;
3013 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3014 int rtype = ret_type->type;
3015 int save_offset = cfg->param_area;
3019 offset = code - cfg->native_code;
3020 /* we need about 16 instructions */
3021 if (offset > (cfg->code_size - 16 * 4)) {
3022 cfg->code_size *= 2;
3023 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3024 code = cfg->native_code + offset;
3027 case MONO_TYPE_VOID:
3028 /* special case string .ctor icall */
3029 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3030 save_mode = SAVE_ONE;
3032 save_mode = SAVE_NONE;
3036 save_mode = SAVE_TWO;
3040 save_mode = SAVE_ONE_FP;
3042 save_mode = SAVE_ONE;
3046 save_mode = SAVE_TWO_FP;
3048 save_mode = SAVE_TWO;
3050 case MONO_TYPE_GENERICINST:
3051 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3052 save_mode = SAVE_ONE;
3056 case MONO_TYPE_VALUETYPE:
3057 save_mode = SAVE_STRUCT;
3060 save_mode = SAVE_ONE;
3064 switch (save_mode) {
3066 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3067 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3068 if (enable_arguments) {
3069 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3070 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3074 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3075 if (enable_arguments) {
3076 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3080 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3081 if (enable_arguments) {
3082 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3086 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3087 if (enable_arguments) {
3088 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3092 if (enable_arguments) {
3093 /* FIXME: get the actual address */
3094 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3102 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3103 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3104 code = emit_call_reg (code, ARMREG_IP);
3106 switch (save_mode) {
3108 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3109 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3112 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3115 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3118 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3129 * The immediate field for cond branches is big enough for all reasonable methods
3131 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3132 if (0 && ins->inst_true_bb->native_offset) { \
3133 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3135 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3136 ARM_B_COND (code, (condcode), 0); \
3139 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3141 /* emit an exception if condition is fail
3143 * We assign the extra code used to throw the implicit exceptions
3144 * to cfg->bb_exit as far as the big branch handling is concerned
3146 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3148 mono_add_patch_info (cfg, code - cfg->native_code, \
3149 MONO_PATCH_INFO_EXC, exc_name); \
3150 ARM_BL_COND (code, (condcode), 0); \
3153 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3156 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3161 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3165 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3166 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3168 switch (ins->opcode) {
3171 /* Already done by an arch-independent pass */
3173 case OP_LOAD_MEMBASE:
3174 case OP_LOADI4_MEMBASE:
3176 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3177 * OP_LOAD_MEMBASE offset(basereg), reg
3179 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3180 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3181 ins->inst_basereg == last_ins->inst_destbasereg &&
3182 ins->inst_offset == last_ins->inst_offset) {
3183 if (ins->dreg == last_ins->sreg1) {
3184 MONO_DELETE_INS (bb, ins);
3187 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3188 ins->opcode = OP_MOVE;
3189 ins->sreg1 = last_ins->sreg1;
3193 * Note: reg1 must be different from the basereg in the second load
3194 * OP_LOAD_MEMBASE offset(basereg), reg1
3195 * OP_LOAD_MEMBASE offset(basereg), reg2
3197 * OP_LOAD_MEMBASE offset(basereg), reg1
3198 * OP_MOVE reg1, reg2
3200 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3201 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3202 ins->inst_basereg != last_ins->dreg &&
3203 ins->inst_basereg == last_ins->inst_basereg &&
3204 ins->inst_offset == last_ins->inst_offset) {
3206 if (ins->dreg == last_ins->dreg) {
3207 MONO_DELETE_INS (bb, ins);
3210 ins->opcode = OP_MOVE;
3211 ins->sreg1 = last_ins->dreg;
3214 //g_assert_not_reached ();
3218 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3219 * OP_LOAD_MEMBASE offset(basereg), reg
3221 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3222 * OP_ICONST reg, imm
3224 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3225 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3226 ins->inst_basereg == last_ins->inst_destbasereg &&
3227 ins->inst_offset == last_ins->inst_offset) {
3228 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3229 ins->opcode = OP_ICONST;
3230 ins->inst_c0 = last_ins->inst_imm;
3231 g_assert_not_reached (); // check this rule
3235 case OP_LOADU1_MEMBASE:
3236 case OP_LOADI1_MEMBASE:
3237 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3238 ins->inst_basereg == last_ins->inst_destbasereg &&
3239 ins->inst_offset == last_ins->inst_offset) {
3240 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3241 ins->sreg1 = last_ins->sreg1;
3244 case OP_LOADU2_MEMBASE:
3245 case OP_LOADI2_MEMBASE:
3246 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3247 ins->inst_basereg == last_ins->inst_destbasereg &&
3248 ins->inst_offset == last_ins->inst_offset) {
3249 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3250 ins->sreg1 = last_ins->sreg1;
3254 ins->opcode = OP_MOVE;
3258 if (ins->dreg == ins->sreg1) {
3259 MONO_DELETE_INS (bb, ins);
3263 * OP_MOVE sreg, dreg
3264 * OP_MOVE dreg, sreg
3266 if (last_ins && last_ins->opcode == OP_MOVE &&
3267 ins->sreg1 == last_ins->dreg &&
3268 ins->dreg == last_ins->sreg1) {
3269 MONO_DELETE_INS (bb, ins);
3278 * the branch_cc_table should maintain the order of these
3292 branch_cc_table [] = {
3306 #define ADD_NEW_INS(cfg,dest,op) do { \
3307 MONO_INST_NEW ((cfg), (dest), (op)); \
3308 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3312 map_to_reg_reg_op (int op)
3321 case OP_COMPARE_IMM:
3323 case OP_ICOMPARE_IMM:
3337 case OP_LOAD_MEMBASE:
3338 return OP_LOAD_MEMINDEX;
3339 case OP_LOADI4_MEMBASE:
3340 return OP_LOADI4_MEMINDEX;
3341 case OP_LOADU4_MEMBASE:
3342 return OP_LOADU4_MEMINDEX;
3343 case OP_LOADU1_MEMBASE:
3344 return OP_LOADU1_MEMINDEX;
3345 case OP_LOADI2_MEMBASE:
3346 return OP_LOADI2_MEMINDEX;
3347 case OP_LOADU2_MEMBASE:
3348 return OP_LOADU2_MEMINDEX;
3349 case OP_LOADI1_MEMBASE:
3350 return OP_LOADI1_MEMINDEX;
3351 case OP_STOREI1_MEMBASE_REG:
3352 return OP_STOREI1_MEMINDEX;
3353 case OP_STOREI2_MEMBASE_REG:
3354 return OP_STOREI2_MEMINDEX;
3355 case OP_STOREI4_MEMBASE_REG:
3356 return OP_STOREI4_MEMINDEX;
3357 case OP_STORE_MEMBASE_REG:
3358 return OP_STORE_MEMINDEX;
3359 case OP_STORER4_MEMBASE_REG:
3360 return OP_STORER4_MEMINDEX;
3361 case OP_STORER8_MEMBASE_REG:
3362 return OP_STORER8_MEMINDEX;
3363 case OP_STORE_MEMBASE_IMM:
3364 return OP_STORE_MEMBASE_REG;
3365 case OP_STOREI1_MEMBASE_IMM:
3366 return OP_STOREI1_MEMBASE_REG;
3367 case OP_STOREI2_MEMBASE_IMM:
3368 return OP_STOREI2_MEMBASE_REG;
3369 case OP_STOREI4_MEMBASE_IMM:
3370 return OP_STOREI4_MEMBASE_REG;
3372 g_assert_not_reached ();
3376 * Remove from the instruction list the instructions that can't be
3377 * represented with very simple instructions with no register
3381 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3383 MonoInst *ins, *temp, *last_ins = NULL;
3384 int rot_amount, imm8, low_imm;
3386 MONO_BB_FOR_EACH_INS (bb, ins) {
3388 switch (ins->opcode) {
3392 case OP_COMPARE_IMM:
3393 case OP_ICOMPARE_IMM:
3407 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3408 int opcode2 = mono_op_imm_to_op (ins->opcode);
3409 ADD_NEW_INS (cfg, temp, OP_ICONST);
3410 temp->inst_c0 = ins->inst_imm;
3411 temp->dreg = mono_alloc_ireg (cfg);
3412 ins->sreg2 = temp->dreg;
3414 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3415 ins->opcode = opcode2;
3417 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3423 if (ins->inst_imm == 1) {
3424 ins->opcode = OP_MOVE;
3427 if (ins->inst_imm == 0) {
3428 ins->opcode = OP_ICONST;
3432 imm8 = mono_is_power_of_two (ins->inst_imm);
3434 ins->opcode = OP_SHL_IMM;
3435 ins->inst_imm = imm8;
3438 ADD_NEW_INS (cfg, temp, OP_ICONST);
3439 temp->inst_c0 = ins->inst_imm;
3440 temp->dreg = mono_alloc_ireg (cfg);
3441 ins->sreg2 = temp->dreg;
3442 ins->opcode = OP_IMUL;
3448 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3449 /* ARM sets the C flag to 1 if there was _no_ overflow */
3450 ins->next->opcode = OP_COND_EXC_NC;
3453 case OP_IDIV_UN_IMM:
3455 case OP_IREM_UN_IMM: {
3456 int opcode2 = mono_op_imm_to_op (ins->opcode);
3457 ADD_NEW_INS (cfg, temp, OP_ICONST);
3458 temp->inst_c0 = ins->inst_imm;
3459 temp->dreg = mono_alloc_ireg (cfg);
3460 ins->sreg2 = temp->dreg;
3462 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3463 ins->opcode = opcode2;
3466 case OP_LOCALLOC_IMM:
3467 ADD_NEW_INS (cfg, temp, OP_ICONST);
3468 temp->inst_c0 = ins->inst_imm;
3469 temp->dreg = mono_alloc_ireg (cfg);
3470 ins->sreg1 = temp->dreg;
3471 ins->opcode = OP_LOCALLOC;
3473 case OP_LOAD_MEMBASE:
3474 case OP_LOADI4_MEMBASE:
3475 case OP_LOADU4_MEMBASE:
3476 case OP_LOADU1_MEMBASE:
3477 /* we can do two things: load the immed in a register
3478 * and use an indexed load, or see if the immed can be
3479 * represented as an ad_imm + a load with a smaller offset
3480 * that fits. We just do the first for now, optimize later.
3482 if (arm_is_imm12 (ins->inst_offset))
3484 ADD_NEW_INS (cfg, temp, OP_ICONST);
3485 temp->inst_c0 = ins->inst_offset;
3486 temp->dreg = mono_alloc_ireg (cfg);
3487 ins->sreg2 = temp->dreg;
3488 ins->opcode = map_to_reg_reg_op (ins->opcode);
3490 case OP_LOADI2_MEMBASE:
3491 case OP_LOADU2_MEMBASE:
3492 case OP_LOADI1_MEMBASE:
3493 if (arm_is_imm8 (ins->inst_offset))
3495 ADD_NEW_INS (cfg, temp, OP_ICONST);
3496 temp->inst_c0 = ins->inst_offset;
3497 temp->dreg = mono_alloc_ireg (cfg);
3498 ins->sreg2 = temp->dreg;
3499 ins->opcode = map_to_reg_reg_op (ins->opcode);
3501 case OP_LOADR4_MEMBASE:
3502 case OP_LOADR8_MEMBASE:
3503 if (arm_is_fpimm8 (ins->inst_offset))
3505 low_imm = ins->inst_offset & 0x1ff;
3506 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3507 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3508 temp->inst_imm = ins->inst_offset & ~0x1ff;
3509 temp->sreg1 = ins->inst_basereg;
3510 temp->dreg = mono_alloc_ireg (cfg);
3511 ins->inst_basereg = temp->dreg;
3512 ins->inst_offset = low_imm;
3516 ADD_NEW_INS (cfg, temp, OP_ICONST);
3517 temp->inst_c0 = ins->inst_offset;
3518 temp->dreg = mono_alloc_ireg (cfg);
3520 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3521 add_ins->sreg1 = ins->inst_basereg;
3522 add_ins->sreg2 = temp->dreg;
3523 add_ins->dreg = mono_alloc_ireg (cfg);
3525 ins->inst_basereg = add_ins->dreg;
3526 ins->inst_offset = 0;
3529 case OP_STORE_MEMBASE_REG:
3530 case OP_STOREI4_MEMBASE_REG:
3531 case OP_STOREI1_MEMBASE_REG:
3532 if (arm_is_imm12 (ins->inst_offset))
3534 ADD_NEW_INS (cfg, temp, OP_ICONST);
3535 temp->inst_c0 = ins->inst_offset;
3536 temp->dreg = mono_alloc_ireg (cfg);
3537 ins->sreg2 = temp->dreg;
3538 ins->opcode = map_to_reg_reg_op (ins->opcode);
3540 case OP_STOREI2_MEMBASE_REG:
3541 if (arm_is_imm8 (ins->inst_offset))
3543 ADD_NEW_INS (cfg, temp, OP_ICONST);
3544 temp->inst_c0 = ins->inst_offset;
3545 temp->dreg = mono_alloc_ireg (cfg);
3546 ins->sreg2 = temp->dreg;
3547 ins->opcode = map_to_reg_reg_op (ins->opcode);
3549 case OP_STORER4_MEMBASE_REG:
3550 case OP_STORER8_MEMBASE_REG:
3551 if (arm_is_fpimm8 (ins->inst_offset))
3553 low_imm = ins->inst_offset & 0x1ff;
3554 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3555 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3556 temp->inst_imm = ins->inst_offset & ~0x1ff;
3557 temp->sreg1 = ins->inst_destbasereg;
3558 temp->dreg = mono_alloc_ireg (cfg);
3559 ins->inst_destbasereg = temp->dreg;
3560 ins->inst_offset = low_imm;
3564 ADD_NEW_INS (cfg, temp, OP_ICONST);
3565 temp->inst_c0 = ins->inst_offset;
3566 temp->dreg = mono_alloc_ireg (cfg);
3568 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3569 add_ins->sreg1 = ins->inst_destbasereg;
3570 add_ins->sreg2 = temp->dreg;
3571 add_ins->dreg = mono_alloc_ireg (cfg);
3573 ins->inst_destbasereg = add_ins->dreg;
3574 ins->inst_offset = 0;
3577 case OP_STORE_MEMBASE_IMM:
3578 case OP_STOREI1_MEMBASE_IMM:
3579 case OP_STOREI2_MEMBASE_IMM:
3580 case OP_STOREI4_MEMBASE_IMM:
3581 ADD_NEW_INS (cfg, temp, OP_ICONST);
3582 temp->inst_c0 = ins->inst_imm;
3583 temp->dreg = mono_alloc_ireg (cfg);
3584 ins->sreg1 = temp->dreg;
3585 ins->opcode = map_to_reg_reg_op (ins->opcode);
3587 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3590 gboolean swap = FALSE;
3594 /* Optimized away */
3599 /* Some fp compares require swapped operands */
3600 switch (ins->next->opcode) {
3602 ins->next->opcode = OP_FBLT;
3606 ins->next->opcode = OP_FBLT_UN;
3610 ins->next->opcode = OP_FBGE;
3614 ins->next->opcode = OP_FBGE_UN;
3622 ins->sreg1 = ins->sreg2;
3631 bb->last_ins = last_ins;
3632 bb->max_vreg = cfg->next_vreg;
3636 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3640 if (long_ins->opcode == OP_LNEG) {
3642 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3643 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3649 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3651 /* sreg is a float, dreg is an integer reg */
3653 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3655 ARM_TOSIZD (code, vfp_scratch1, sreg);
3657 ARM_TOUIZD (code, vfp_scratch1, sreg);
3658 ARM_FMRS (code, dreg, vfp_scratch1);
3659 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3663 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3664 else if (size == 2) {
3665 ARM_SHL_IMM (code, dreg, dreg, 16);
3666 ARM_SHR_IMM (code, dreg, dreg, 16);
3670 ARM_SHL_IMM (code, dreg, dreg, 24);
3671 ARM_SAR_IMM (code, dreg, dreg, 24);
3672 } else if (size == 2) {
3673 ARM_SHL_IMM (code, dreg, dreg, 16);
3674 ARM_SAR_IMM (code, dreg, dreg, 16);
3681 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3683 /* sreg is a float, dreg is an integer reg */
3685 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3687 ARM_TOSIZS (code, vfp_scratch1, sreg);
3689 ARM_TOUIZS (code, vfp_scratch1, sreg);
3690 ARM_FMRS (code, dreg, vfp_scratch1);
3691 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3695 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3696 else if (size == 2) {
3697 ARM_SHL_IMM (code, dreg, dreg, 16);
3698 ARM_SHR_IMM (code, dreg, dreg, 16);
3702 ARM_SHL_IMM (code, dreg, dreg, 24);
3703 ARM_SAR_IMM (code, dreg, dreg, 24);
3704 } else if (size == 2) {
3705 ARM_SHL_IMM (code, dreg, dreg, 16);
3706 ARM_SAR_IMM (code, dreg, dreg, 16);
3712 #endif /* #ifndef DISABLE_JIT */
3714 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3717 emit_thunk (guint8 *code, gconstpointer target)
3721 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3722 if (thumb_supported)
3723 ARM_BX (code, ARMREG_IP);
3725 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3726 *(guint32*)code = (guint32)target;
3728 mono_arch_flush_icache (p, code - p);
3732 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3734 MonoJitInfo *ji = NULL;
3735 MonoThunkJitInfo *info;
3738 guint8 *orig_target;
3739 guint8 *target_thunk;
3742 domain = mono_domain_get ();
3746 * This can be called multiple times during JITting,
3747 * save the current position in cfg->arch to avoid
3748 * doing a O(n^2) search.
3750 if (!cfg->arch.thunks) {
3751 cfg->arch.thunks = cfg->thunks;
3752 cfg->arch.thunks_size = cfg->thunk_area;
3754 thunks = cfg->arch.thunks;
3755 thunks_size = cfg->arch.thunks_size;
3757 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3758 g_assert_not_reached ();
3761 g_assert (*(guint32*)thunks == 0);
3762 emit_thunk (thunks, target);
3763 arm_patch (code, thunks);
3765 cfg->arch.thunks += THUNK_SIZE;
3766 cfg->arch.thunks_size -= THUNK_SIZE;
3768 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3770 info = mono_jit_info_get_thunk_info (ji);
3773 thunks = (guint8*)ji->code_start + info->thunks_offset;
3774 thunks_size = info->thunks_size;
3776 orig_target = mono_arch_get_call_target (code + 4);
3778 mono_mini_arch_lock ();
3780 target_thunk = NULL;
3781 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3782 /* The call already points to a thunk, because of trampolines etc. */
3783 target_thunk = orig_target;
3785 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3786 if (((guint32*)p) [0] == 0) {
3790 } else if (((guint32*)p) [2] == (guint32)target) {
3791 /* Thunk already points to target */
3798 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3800 if (!target_thunk) {
3801 mono_mini_arch_unlock ();
3802 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3803 g_assert_not_reached ();
3806 emit_thunk (target_thunk, target);
3807 arm_patch (code, target_thunk);
3808 mono_arch_flush_icache (code, 4);
3810 mono_mini_arch_unlock ();
3815 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3817 guint32 *code32 = (void*)code;
3818 guint32 ins = *code32;
3819 guint32 prim = (ins >> 25) & 7;
3820 guint32 tval = GPOINTER_TO_UINT (target);
3822 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3823 if (prim == 5) { /* 101b */
3824 /* the diff starts 8 bytes from the branch opcode */
3825 gint diff = target - code - 8;
3827 gint tmask = 0xffffffff;
3828 if (tval & 1) { /* entering thumb mode */
3829 diff = target - 1 - code - 8;
3830 g_assert (thumb_supported);
3831 tbits = 0xf << 28; /* bl->blx bit pattern */
3832 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3833 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3837 tmask = ~(1 << 24); /* clear the link bit */
3838 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3843 if (diff <= 33554431) {
3845 ins = (ins & 0xff000000) | diff;
3847 *code32 = ins | tbits;
3851 /* diff between 0 and -33554432 */
3852 if (diff >= -33554432) {
3854 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3856 *code32 = ins | tbits;
3861 handle_thunk (cfg, domain, code, target);
3866 * The alternative call sequences looks like this:
3868 * ldr ip, [pc] // loads the address constant
3869 * b 1f // jumps around the constant
3870 * address constant embedded in the code
3875 * There are two cases for patching:
3876 * a) at the end of method emission: in this case code points to the start
3877 * of the call sequence
3878 * b) during runtime patching of the call site: in this case code points
3879 * to the mov pc, ip instruction
3881 * We have to handle also the thunk jump code sequence:
3885 * address constant // execution never reaches here
3887 if ((ins & 0x0ffffff0) == 0x12fff10) {
3888 /* Branch and exchange: the address is constructed in a reg
3889 * We can patch BX when the code sequence is the following:
3890 * ldr ip, [pc, #0] ; 0x8
3897 guint8 *emit = (guint8*)ccode;
3898 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3900 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3901 ARM_BX (emit, ARMREG_IP);
3903 /*patching from magic trampoline*/
3904 if (ins == ccode [3]) {
3905 g_assert (code32 [-4] == ccode [0]);
3906 g_assert (code32 [-3] == ccode [1]);
3907 g_assert (code32 [-1] == ccode [2]);
3908 code32 [-2] = (guint32)target;
3911 /*patching from JIT*/
3912 if (ins == ccode [0]) {
3913 g_assert (code32 [1] == ccode [1]);
3914 g_assert (code32 [3] == ccode [2]);
3915 g_assert (code32 [4] == ccode [3]);
3916 code32 [2] = (guint32)target;
3919 g_assert_not_reached ();
3920 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3928 guint8 *emit = (guint8*)ccode;
3929 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3931 ARM_BLX_REG (emit, ARMREG_IP);
3933 g_assert (code32 [-3] == ccode [0]);
3934 g_assert (code32 [-2] == ccode [1]);
3935 g_assert (code32 [0] == ccode [2]);
3937 code32 [-1] = (guint32)target;
3940 guint32 *tmp = ccode;
3941 guint8 *emit = (guint8*)tmp;
3942 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3943 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3944 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3945 ARM_BX (emit, ARMREG_IP);
3946 if (ins == ccode [2]) {
3947 g_assert_not_reached (); // should be -2 ...
3948 code32 [-1] = (guint32)target;
3951 if (ins == ccode [0]) {
3952 /* handles both thunk jump code and the far call sequence */
3953 code32 [2] = (guint32)target;
3956 g_assert_not_reached ();
3958 // g_print ("patched with 0x%08x\n", ins);
3962 arm_patch (guchar *code, const guchar *target)
3964 arm_patch_general (NULL, NULL, code, target);
3968 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3969 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3970 * to be used with the emit macros.
3971 * Return -1 otherwise.
3974 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3977 for (i = 0; i < 31; i+= 2) {
3978 res = (val << (32 - i)) | (val >> i);
3981 *rot_amount = i? 32 - i: 0;
3988 * Emits in code a sequence of instructions that load the value 'val'
3989 * into the dreg register. Uses at most 4 instructions.
3992 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3994 int imm8, rot_amount;
3996 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3997 /* skip the constant pool */
4003 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4004 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4005 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4009 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4010 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4011 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4012 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4015 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4017 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4021 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4023 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4025 if (val & 0xFF0000) {
4026 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4028 if (val & 0xFF000000) {
4029 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4031 } else if (val & 0xFF00) {
4032 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4033 if (val & 0xFF0000) {
4034 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4036 if (val & 0xFF000000) {
4037 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4039 } else if (val & 0xFF0000) {
4040 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4041 if (val & 0xFF000000) {
4042 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4045 //g_assert_not_reached ();
4051 mono_arm_thumb_supported (void)
4053 return thumb_supported;
4057 mono_arm_eabi_supported (void)
4059 return eabi_supported;
4063 mono_arm_i8_align (void)
4071 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4076 call = (MonoCallInst*)ins;
4077 cinfo = call->call_info;
4079 switch (cinfo->ret.storage) {
4080 case RegTypeStructByVal:
4082 MonoInst *loc = cfg->arch.vret_addr_loc;
4085 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4086 /* The JIT treats this as a normal call */
4090 /* Load the destination address */
4091 g_assert (loc && loc->opcode == OP_REGOFFSET);
4093 if (arm_is_imm12 (loc->inst_offset)) {
4094 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4096 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4097 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4100 if (cinfo->ret.storage == RegTypeStructByVal) {
4101 int rsize = cinfo->ret.struct_size;
4103 for (i = 0; i < cinfo->ret.nregs; ++i) {
4104 g_assert (rsize >= 0);
4109 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4112 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4115 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4121 for (i = 0; i < cinfo->ret.nregs; ++i) {
4122 if (cinfo->ret.esize == 4)
4123 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4125 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4134 switch (ins->opcode) {
4137 case OP_FCALL_MEMBASE:
4139 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4140 if (sig_ret->type == MONO_TYPE_R4) {
4141 if (IS_HARD_FLOAT) {
4142 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4144 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4145 ARM_CVTS (code, ins->dreg, ins->dreg);
4148 if (IS_HARD_FLOAT) {
4149 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4151 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4158 case OP_RCALL_MEMBASE: {
4163 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4164 g_assert (sig_ret->type == MONO_TYPE_R4);
4165 if (IS_HARD_FLOAT) {
4166 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4168 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4169 ARM_CPYS (code, ins->dreg, ins->dreg);
4181 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4186 guint8 *code = cfg->native_code + cfg->code_len;
4187 MonoInst *last_ins = NULL;
4188 guint last_offset = 0;
4190 int imm8, rot_amount;
4192 /* we don't align basic blocks of loops on arm */
4194 if (cfg->verbose_level > 2)
4195 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4197 cpos = bb->max_offset;
4199 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4200 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4201 (gpointer)"mono_break");
4202 code = emit_call_seq (cfg, code);
4205 MONO_BB_FOR_EACH_INS (bb, ins) {
4206 offset = code - cfg->native_code;
4208 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4210 if (offset > (cfg->code_size - max_len - 16)) {
4211 cfg->code_size *= 2;
4212 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4213 code = cfg->native_code + offset;
4215 // if (ins->cil_code)
4216 // g_print ("cil code\n");
4217 mono_debug_record_line_number (cfg, ins, offset);
4219 switch (ins->opcode) {
4220 case OP_MEMORY_BARRIER:
4222 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4223 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4227 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4230 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4232 case OP_ATOMIC_EXCHANGE_I4:
4233 case OP_ATOMIC_CAS_I4:
4234 case OP_ATOMIC_ADD_I4: {
4238 g_assert (v7_supported);
4241 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4243 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4245 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4249 g_assert (cfg->arch.atomic_tmp_offset != -1);
4250 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4252 switch (ins->opcode) {
4253 case OP_ATOMIC_EXCHANGE_I4:
4255 ARM_DMB (code, ARM_DMB_SY);
4256 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4257 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4258 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4260 ARM_B_COND (code, ARMCOND_NE, 0);
4261 arm_patch (buf [1], buf [0]);
4263 case OP_ATOMIC_CAS_I4:
4264 ARM_DMB (code, ARM_DMB_SY);
4266 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4267 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4269 ARM_B_COND (code, ARMCOND_NE, 0);
4270 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4271 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4273 ARM_B_COND (code, ARMCOND_NE, 0);
4274 arm_patch (buf [2], buf [0]);
4275 arm_patch (buf [1], code);
4277 case OP_ATOMIC_ADD_I4:
4279 ARM_DMB (code, ARM_DMB_SY);
4280 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4281 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4282 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4283 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4285 ARM_B_COND (code, ARMCOND_NE, 0);
4286 arm_patch (buf [1], buf [0]);
4289 g_assert_not_reached ();
4292 ARM_DMB (code, ARM_DMB_SY);
4293 if (tmpreg != ins->dreg)
4294 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4295 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4298 case OP_ATOMIC_LOAD_I1:
4299 case OP_ATOMIC_LOAD_U1:
4300 case OP_ATOMIC_LOAD_I2:
4301 case OP_ATOMIC_LOAD_U2:
4302 case OP_ATOMIC_LOAD_I4:
4303 case OP_ATOMIC_LOAD_U4:
4304 case OP_ATOMIC_LOAD_R4:
4305 case OP_ATOMIC_LOAD_R8: {
4306 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4307 ARM_DMB (code, ARM_DMB_SY);
4309 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4311 switch (ins->opcode) {
4312 case OP_ATOMIC_LOAD_I1:
4313 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4315 case OP_ATOMIC_LOAD_U1:
4316 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4318 case OP_ATOMIC_LOAD_I2:
4319 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4321 case OP_ATOMIC_LOAD_U2:
4322 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4324 case OP_ATOMIC_LOAD_I4:
4325 case OP_ATOMIC_LOAD_U4:
4326 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4328 case OP_ATOMIC_LOAD_R4:
4330 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4331 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4333 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4334 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4335 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4336 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4337 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4340 case OP_ATOMIC_LOAD_R8:
4341 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4342 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4346 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4347 ARM_DMB (code, ARM_DMB_SY);
4350 case OP_ATOMIC_STORE_I1:
4351 case OP_ATOMIC_STORE_U1:
4352 case OP_ATOMIC_STORE_I2:
4353 case OP_ATOMIC_STORE_U2:
4354 case OP_ATOMIC_STORE_I4:
4355 case OP_ATOMIC_STORE_U4:
4356 case OP_ATOMIC_STORE_R4:
4357 case OP_ATOMIC_STORE_R8: {
4358 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4359 ARM_DMB (code, ARM_DMB_SY);
4361 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4363 switch (ins->opcode) {
4364 case OP_ATOMIC_STORE_I1:
4365 case OP_ATOMIC_STORE_U1:
4366 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4368 case OP_ATOMIC_STORE_I2:
4369 case OP_ATOMIC_STORE_U2:
4370 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4372 case OP_ATOMIC_STORE_I4:
4373 case OP_ATOMIC_STORE_U4:
4374 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4376 case OP_ATOMIC_STORE_R4:
4378 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4379 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4381 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4382 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4383 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4384 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4385 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4388 case OP_ATOMIC_STORE_R8:
4389 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4390 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4394 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4395 ARM_DMB (code, ARM_DMB_SY);
4399 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4402 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4404 case OP_STOREI1_MEMBASE_IMM:
4405 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4406 g_assert (arm_is_imm12 (ins->inst_offset));
4407 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4409 case OP_STOREI2_MEMBASE_IMM:
4410 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4411 g_assert (arm_is_imm8 (ins->inst_offset));
4412 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4414 case OP_STORE_MEMBASE_IMM:
4415 case OP_STOREI4_MEMBASE_IMM:
4416 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4417 g_assert (arm_is_imm12 (ins->inst_offset));
4418 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4420 case OP_STOREI1_MEMBASE_REG:
4421 g_assert (arm_is_imm12 (ins->inst_offset));
4422 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4424 case OP_STOREI2_MEMBASE_REG:
4425 g_assert (arm_is_imm8 (ins->inst_offset));
4426 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4428 case OP_STORE_MEMBASE_REG:
4429 case OP_STOREI4_MEMBASE_REG:
4430 /* this case is special, since it happens for spill code after lowering has been called */
4431 if (arm_is_imm12 (ins->inst_offset)) {
4432 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4434 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4435 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4438 case OP_STOREI1_MEMINDEX:
4439 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4441 case OP_STOREI2_MEMINDEX:
4442 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4444 case OP_STORE_MEMINDEX:
4445 case OP_STOREI4_MEMINDEX:
4446 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4449 g_assert_not_reached ();
4451 case OP_LOAD_MEMINDEX:
4452 case OP_LOADI4_MEMINDEX:
4453 case OP_LOADU4_MEMINDEX:
4454 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4456 case OP_LOADI1_MEMINDEX:
4457 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4459 case OP_LOADU1_MEMINDEX:
4460 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4462 case OP_LOADI2_MEMINDEX:
4463 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4465 case OP_LOADU2_MEMINDEX:
4466 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4468 case OP_LOAD_MEMBASE:
4469 case OP_LOADI4_MEMBASE:
4470 case OP_LOADU4_MEMBASE:
4471 /* this case is special, since it happens for spill code after lowering has been called */
4472 if (arm_is_imm12 (ins->inst_offset)) {
4473 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4475 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4476 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4479 case OP_LOADI1_MEMBASE:
4480 g_assert (arm_is_imm8 (ins->inst_offset));
4481 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4483 case OP_LOADU1_MEMBASE:
4484 g_assert (arm_is_imm12 (ins->inst_offset));
4485 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4487 case OP_LOADU2_MEMBASE:
4488 g_assert (arm_is_imm8 (ins->inst_offset));
4489 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4491 case OP_LOADI2_MEMBASE:
4492 g_assert (arm_is_imm8 (ins->inst_offset));
4493 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4495 case OP_ICONV_TO_I1:
4496 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4497 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4499 case OP_ICONV_TO_I2:
4500 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4501 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4503 case OP_ICONV_TO_U1:
4504 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4506 case OP_ICONV_TO_U2:
4507 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4508 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4512 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4514 case OP_COMPARE_IMM:
4515 case OP_ICOMPARE_IMM:
4516 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4517 g_assert (imm8 >= 0);
4518 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4522 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4523 * So instead of emitting a trap, we emit a call a C function and place a
4526 //*(int*)code = 0xef9f0001;
4529 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4530 (gpointer)"mono_break");
4531 code = emit_call_seq (cfg, code);
4533 case OP_RELAXED_NOP:
4538 case OP_DUMMY_STORE:
4539 case OP_DUMMY_ICONST:
4540 case OP_DUMMY_R8CONST:
4541 case OP_NOT_REACHED:
4544 case OP_IL_SEQ_POINT:
4545 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4547 case OP_SEQ_POINT: {
4549 MonoInst *info_var = cfg->arch.seq_point_info_var;
4550 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4551 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4552 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4554 int dreg = ARMREG_LR;
4557 if (cfg->soft_breakpoints) {
4558 g_assert (!cfg->compile_aot);
4563 * For AOT, we use one got slot per method, which will point to a
4564 * SeqPointInfo structure, containing all the information required
4565 * by the code below.
4567 if (cfg->compile_aot) {
4568 g_assert (info_var);
4569 g_assert (info_var->opcode == OP_REGOFFSET);
4572 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4574 * Read from the single stepping trigger page. This will cause a
4575 * SIGSEGV when single stepping is enabled.
4576 * We do this _before_ the breakpoint, so single stepping after
4577 * a breakpoint is hit will step to the next IL offset.
4579 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4582 /* Single step check */
4583 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4584 if (cfg->soft_breakpoints) {
4585 /* Load the address of the sequence point method variable. */
4586 var = ss_method_var;
4588 g_assert (var->opcode == OP_REGOFFSET);
4589 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4590 /* Read the value and check whether it is non-zero. */
4591 ARM_LDR_IMM (code, dreg, dreg, 0);
4592 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4593 /* Call it conditionally. */
4594 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4596 if (cfg->compile_aot) {
4597 /* Load the trigger page addr from the variable initialized in the prolog */
4598 var = ss_trigger_page_var;
4600 g_assert (var->opcode == OP_REGOFFSET);
4601 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4603 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4605 *(int*)code = (int)ss_trigger_page;
4608 ARM_LDR_IMM (code, dreg, dreg, 0);
4612 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4614 /* Breakpoint check */
4615 if (cfg->compile_aot) {
4616 guint32 offset = code - cfg->native_code;
4620 code = emit_ldr_imm (code, dreg, var->inst_basereg, var->inst_offset);
4621 /* Add the offset */
4622 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4623 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4624 if (arm_is_imm12 ((int)val)) {
4625 ARM_LDR_IMM (code, dreg, dreg, val);
4627 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4629 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4631 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4632 g_assert (!(val & 0xFF000000));
4634 ARM_LDR_IMM (code, dreg, dreg, 0);
4636 /* What is faster, a branch or a load ? */
4637 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4638 /* The breakpoint instruction */
4639 if (cfg->soft_breakpoints)
4640 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4642 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4643 } else if (cfg->soft_breakpoints) {
4644 /* Load the address of the breakpoint method into ip. */
4645 var = bp_method_var;
4647 g_assert (var->opcode == OP_REGOFFSET);
4648 g_assert (arm_is_imm12 (var->inst_offset));
4649 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4652 * A placeholder for a possible breakpoint inserted by
4653 * mono_arch_set_breakpoint ().
4658 * A placeholder for a possible breakpoint inserted by
4659 * mono_arch_set_breakpoint ().
4661 for (i = 0; i < 4; ++i)
4666 * Add an additional nop so skipping the bp doesn't cause the ip to point
4667 * to another IL offset.
4675 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4678 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4682 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4685 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4686 g_assert (imm8 >= 0);
4687 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4691 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4692 g_assert (imm8 >= 0);
4693 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4697 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4698 g_assert (imm8 >= 0);
4699 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4702 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4703 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4705 case OP_IADD_OVF_UN:
4706 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4707 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4710 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4711 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4713 case OP_ISUB_OVF_UN:
4714 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4715 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4717 case OP_ADD_OVF_CARRY:
4718 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4719 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4721 case OP_ADD_OVF_UN_CARRY:
4722 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4723 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4725 case OP_SUB_OVF_CARRY:
4726 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4727 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4729 case OP_SUB_OVF_UN_CARRY:
4730 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4731 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4735 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4738 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4739 g_assert (imm8 >= 0);
4740 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4743 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4747 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4751 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4752 g_assert (imm8 >= 0);
4753 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4757 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4758 g_assert (imm8 >= 0);
4759 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4761 case OP_ARM_RSBS_IMM:
4762 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4763 g_assert (imm8 >= 0);
4764 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4766 case OP_ARM_RSC_IMM:
4767 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4768 g_assert (imm8 >= 0);
4769 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4772 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4776 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4777 g_assert (imm8 >= 0);
4778 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4781 g_assert (v7s_supported || v7k_supported);
4782 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4785 g_assert (v7s_supported || v7k_supported);
4786 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4789 g_assert (v7s_supported || v7k_supported);
4790 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4791 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4794 g_assert (v7s_supported || v7k_supported);
4795 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4796 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4800 g_assert_not_reached ();
4802 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4806 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4807 g_assert (imm8 >= 0);
4808 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4811 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4815 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4816 g_assert (imm8 >= 0);
4817 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4820 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4825 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4826 else if (ins->dreg != ins->sreg1)
4827 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4830 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4835 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4836 else if (ins->dreg != ins->sreg1)
4837 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4840 case OP_ISHR_UN_IMM:
4842 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4843 else if (ins->dreg != ins->sreg1)
4844 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4847 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4850 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4853 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4856 if (ins->dreg == ins->sreg2)
4857 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4859 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4862 g_assert_not_reached ();
4865 /* FIXME: handle ovf/ sreg2 != dreg */
4866 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4867 /* FIXME: MUL doesn't set the C/O flags on ARM */
4869 case OP_IMUL_OVF_UN:
4870 /* FIXME: handle ovf/ sreg2 != dreg */
4871 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4872 /* FIXME: MUL doesn't set the C/O flags on ARM */
4875 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4878 /* Load the GOT offset */
4879 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4880 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4882 *(gpointer*)code = NULL;
4884 /* Load the value from the GOT */
4885 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4887 case OP_OBJC_GET_SELECTOR:
4888 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4889 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4891 *(gpointer*)code = NULL;
4893 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4895 case OP_ICONV_TO_I4:
4896 case OP_ICONV_TO_U4:
4898 if (ins->dreg != ins->sreg1)
4899 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4902 int saved = ins->sreg2;
4903 if (ins->sreg2 == ARM_LSW_REG) {
4904 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4907 if (ins->sreg1 != ARM_LSW_REG)
4908 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4909 if (saved != ARM_MSW_REG)
4910 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4914 if (IS_VFP && ins->dreg != ins->sreg1)
4915 ARM_CPYD (code, ins->dreg, ins->sreg1);
4918 if (IS_VFP && ins->dreg != ins->sreg1)
4919 ARM_CPYS (code, ins->dreg, ins->sreg1);
4921 case OP_MOVE_F_TO_I4:
4923 ARM_FMRS (code, ins->dreg, ins->sreg1);
4925 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4926 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4927 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4928 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4931 case OP_MOVE_I4_TO_F:
4933 ARM_FMSR (code, ins->dreg, ins->sreg1);
4935 ARM_FMSR (code, ins->dreg, ins->sreg1);
4936 ARM_CVTS (code, ins->dreg, ins->dreg);
4939 case OP_FCONV_TO_R4:
4942 ARM_CVTD (code, ins->dreg, ins->sreg1);
4944 ARM_CVTD (code, ins->dreg, ins->sreg1);
4945 ARM_CVTS (code, ins->dreg, ins->dreg);
4950 MonoCallInst *call = (MonoCallInst*)ins;
4953 * The stack looks like the following:
4954 * <caller argument area>
4957 * <callee argument area>
4958 * Need to copy the arguments from the callee argument area to
4959 * the caller argument area, and pop the frame.
4961 if (call->stack_usage) {
4962 int i, prev_sp_offset = 0;
4964 /* Compute size of saved registers restored below */
4966 prev_sp_offset = 2 * 4;
4968 prev_sp_offset = 1 * 4;
4969 for (i = 0; i < 16; ++i) {
4970 if (cfg->used_int_regs & (1 << i))
4971 prev_sp_offset += 4;
4974 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4976 /* Copy arguments on the stack to our argument area */
4977 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4978 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4979 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4984 * Keep in sync with mono_arch_emit_epilog
4986 g_assert (!cfg->method->save_lmf);
4988 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4990 if (cfg->used_int_regs)
4991 ARM_POP (code, cfg->used_int_regs);
4992 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4994 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4997 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4998 if (cfg->compile_aot) {
4999 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5001 *(gpointer*)code = NULL;
5003 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5005 code = mono_arm_patchable_b (code, ARMCOND_AL);
5006 cfg->thunk_area += THUNK_SIZE;
5011 /* ensure ins->sreg1 is not NULL */
5012 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5015 g_assert (cfg->sig_cookie < 128);
5016 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5017 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5027 call = (MonoCallInst*)ins;
5030 code = emit_float_args (cfg, call, code, &max_len, &offset);
5032 if (ins->flags & MONO_INST_HAS_METHOD)
5033 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5035 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5036 code = emit_call_seq (cfg, code);
5037 ins->flags |= MONO_INST_GC_CALLSITE;
5038 ins->backend.pc_offset = code - cfg->native_code;
5039 code = emit_move_return_value (cfg, ins, code);
5046 case OP_VOIDCALL_REG:
5049 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5051 code = emit_call_reg (code, ins->sreg1);
5052 ins->flags |= MONO_INST_GC_CALLSITE;
5053 ins->backend.pc_offset = code - cfg->native_code;
5054 code = emit_move_return_value (cfg, ins, code);
5056 case OP_FCALL_MEMBASE:
5057 case OP_RCALL_MEMBASE:
5058 case OP_LCALL_MEMBASE:
5059 case OP_VCALL_MEMBASE:
5060 case OP_VCALL2_MEMBASE:
5061 case OP_VOIDCALL_MEMBASE:
5062 case OP_CALL_MEMBASE: {
5063 g_assert (ins->sreg1 != ARMREG_LR);
5064 call = (MonoCallInst*)ins;
5067 code = emit_float_args (cfg, call, code, &max_len, &offset);
5068 if (!arm_is_imm12 (ins->inst_offset)) {
5069 /* sreg1 might be IP */
5070 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5071 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5072 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5073 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5074 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5076 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5077 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5079 ins->flags |= MONO_INST_GC_CALLSITE;
5080 ins->backend.pc_offset = code - cfg->native_code;
5081 code = emit_move_return_value (cfg, ins, code);
5084 case OP_GENERIC_CLASS_INIT: {
5088 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5090 g_assert (arm_is_imm8 (byte_offset));
5091 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5092 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5094 ARM_B_COND (code, ARMCOND_NE, 0);
5096 /* Uninitialized case */
5097 g_assert (ins->sreg1 == ARMREG_R0);
5099 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5100 (gpointer)"mono_generic_class_init");
5101 code = emit_call_seq (cfg, code);
5103 /* Initialized case */
5104 arm_patch (jump, code);
5108 /* round the size to 8 bytes */
5109 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5110 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5111 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5112 /* memzero the area: dreg holds the size, sp is the pointer */
5113 if (ins->flags & MONO_INST_INIT) {
5114 guint8 *start_loop, *branch_to_cond;
5115 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5116 branch_to_cond = code;
5119 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5120 arm_patch (branch_to_cond, code);
5121 /* decrement by 4 and set flags */
5122 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5123 ARM_B_COND (code, ARMCOND_GE, 0);
5124 arm_patch (code - 4, start_loop);
5126 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5127 if (cfg->param_area)
5128 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5133 MonoInst *var = cfg->dyn_call_var;
5136 g_assert (var->opcode == OP_REGOFFSET);
5137 g_assert (arm_is_imm12 (var->inst_offset));
5139 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5140 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5142 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5144 /* Save args buffer */
5145 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5147 /* Set stack slots using R0 as scratch reg */
5148 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5149 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5150 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5151 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5154 /* Set fp argument registers */
5155 if (IS_HARD_FLOAT) {
5156 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5157 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5159 ARM_B_COND (code, ARMCOND_EQ, 0);
5160 for (i = 0; i < FP_PARAM_REGS; ++i) {
5161 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5162 g_assert (arm_is_fpimm8 (offset));
5163 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5165 arm_patch (buf [0], code);
5168 /* Set argument registers */
5169 for (i = 0; i < PARAM_REGS; ++i)
5170 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5173 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5174 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5177 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5178 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5179 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5181 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5185 if (ins->sreg1 != ARMREG_R0)
5186 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5187 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5188 (gpointer)"mono_arch_throw_exception");
5189 code = emit_call_seq (cfg, code);
5193 if (ins->sreg1 != ARMREG_R0)
5194 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5195 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5196 (gpointer)"mono_arch_rethrow_exception");
5197 code = emit_call_seq (cfg, code);
5200 case OP_START_HANDLER: {
5201 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5202 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5205 /* Reserve a param area, see filter-stack.exe */
5207 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5208 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5210 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5211 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5215 if (arm_is_imm12 (spvar->inst_offset)) {
5216 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5218 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5219 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5223 case OP_ENDFILTER: {
5224 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5225 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5228 /* Free the param area */
5230 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5231 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5233 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5234 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5238 if (ins->sreg1 != ARMREG_R0)
5239 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5240 if (arm_is_imm12 (spvar->inst_offset)) {
5241 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5243 g_assert (ARMREG_IP != spvar->inst_basereg);
5244 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5245 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5247 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5250 case OP_ENDFINALLY: {
5251 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5252 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5255 /* Free the param area */
5257 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5258 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5260 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5261 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5265 if (arm_is_imm12 (spvar->inst_offset)) {
5266 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5268 g_assert (ARMREG_IP != spvar->inst_basereg);
5269 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5270 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5272 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5275 case OP_CALL_HANDLER:
5276 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5277 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5278 cfg->thunk_area += THUNK_SIZE;
5279 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5282 if (ins->dreg != ARMREG_R0)
5283 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5287 ins->inst_c0 = code - cfg->native_code;
5290 /*if (ins->inst_target_bb->native_offset) {
5292 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5294 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5295 code = mono_arm_patchable_b (code, ARMCOND_AL);
5299 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5303 * In the normal case we have:
5304 * ldr pc, [pc, ins->sreg1 << 2]
5307 * ldr lr, [pc, ins->sreg1 << 2]
5309 * After follows the data.
5310 * FIXME: add aot support.
5312 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5313 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5314 if (offset + max_len > (cfg->code_size - 16)) {
5315 cfg->code_size += max_len;
5316 cfg->code_size *= 2;
5317 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5318 code = cfg->native_code + offset;
5320 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5322 code += 4 * GPOINTER_TO_INT (ins->klass);
5326 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5327 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5331 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5332 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5336 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5337 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5341 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5342 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5346 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5347 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5350 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5351 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5354 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5355 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5358 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5359 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5362 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5363 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5366 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5367 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5369 case OP_COND_EXC_EQ:
5370 case OP_COND_EXC_NE_UN:
5371 case OP_COND_EXC_LT:
5372 case OP_COND_EXC_LT_UN:
5373 case OP_COND_EXC_GT:
5374 case OP_COND_EXC_GT_UN:
5375 case OP_COND_EXC_GE:
5376 case OP_COND_EXC_GE_UN:
5377 case OP_COND_EXC_LE:
5378 case OP_COND_EXC_LE_UN:
5379 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5381 case OP_COND_EXC_IEQ:
5382 case OP_COND_EXC_INE_UN:
5383 case OP_COND_EXC_ILT:
5384 case OP_COND_EXC_ILT_UN:
5385 case OP_COND_EXC_IGT:
5386 case OP_COND_EXC_IGT_UN:
5387 case OP_COND_EXC_IGE:
5388 case OP_COND_EXC_IGE_UN:
5389 case OP_COND_EXC_ILE:
5390 case OP_COND_EXC_ILE_UN:
5391 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5394 case OP_COND_EXC_IC:
5395 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5397 case OP_COND_EXC_OV:
5398 case OP_COND_EXC_IOV:
5399 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5401 case OP_COND_EXC_NC:
5402 case OP_COND_EXC_INC:
5403 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5405 case OP_COND_EXC_NO:
5406 case OP_COND_EXC_INO:
5407 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5419 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5422 /* floating point opcodes */
5424 if (cfg->compile_aot) {
5425 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5427 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5429 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5432 /* FIXME: we can optimize the imm load by dealing with part of
5433 * the displacement in LDFD (aligning to 512).
5435 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5436 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5440 if (cfg->compile_aot) {
5441 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5443 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5446 ARM_CVTS (code, ins->dreg, ins->dreg);
5448 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5449 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5451 ARM_CVTS (code, ins->dreg, ins->dreg);
5454 case OP_STORER8_MEMBASE_REG:
5455 /* This is generated by the local regalloc pass which runs after the lowering pass */
5456 if (!arm_is_fpimm8 (ins->inst_offset)) {
5457 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5458 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5459 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5461 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5464 case OP_LOADR8_MEMBASE:
5465 /* This is generated by the local regalloc pass which runs after the lowering pass */
5466 if (!arm_is_fpimm8 (ins->inst_offset)) {
5467 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5468 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5469 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5471 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5474 case OP_STORER4_MEMBASE_REG:
5475 g_assert (arm_is_fpimm8 (ins->inst_offset));
5477 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5479 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5480 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5481 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5482 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5485 case OP_LOADR4_MEMBASE:
5487 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5489 g_assert (arm_is_fpimm8 (ins->inst_offset));
5490 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5491 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5492 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5493 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5496 case OP_ICONV_TO_R_UN: {
5497 g_assert_not_reached ();
5500 case OP_ICONV_TO_R4:
5502 ARM_FMSR (code, ins->dreg, ins->sreg1);
5503 ARM_FSITOS (code, ins->dreg, ins->dreg);
5505 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5506 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5507 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5508 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5509 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5512 case OP_ICONV_TO_R8:
5513 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5514 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5515 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5516 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5520 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5521 if (sig_ret->type == MONO_TYPE_R4) {
5523 if (IS_HARD_FLOAT) {
5524 if (ins->sreg1 != ARM_VFP_D0)
5525 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5527 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5530 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5533 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5537 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5539 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5543 case OP_FCONV_TO_I1:
5544 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5546 case OP_FCONV_TO_U1:
5547 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5549 case OP_FCONV_TO_I2:
5550 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5552 case OP_FCONV_TO_U2:
5553 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5555 case OP_FCONV_TO_I4:
5557 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5559 case OP_FCONV_TO_U4:
5561 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5563 case OP_FCONV_TO_I8:
5564 case OP_FCONV_TO_U8:
5565 g_assert_not_reached ();
5566 /* Implemented as helper calls */
5568 case OP_LCONV_TO_R_UN:
5569 g_assert_not_reached ();
5570 /* Implemented as helper calls */
5572 case OP_LCONV_TO_OVF_I4_2: {
5573 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5575 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5578 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5579 high_bit_not_set = code;
5580 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5582 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5583 valid_negative = code;
5584 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5585 invalid_negative = code;
5586 ARM_B_COND (code, ARMCOND_AL, 0);
5588 arm_patch (high_bit_not_set, code);
5590 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5591 valid_positive = code;
5592 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5594 arm_patch (invalid_negative, code);
5595 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5597 arm_patch (valid_negative, code);
5598 arm_patch (valid_positive, code);
5600 if (ins->dreg != ins->sreg1)
5601 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5605 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5608 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5611 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5614 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5617 ARM_NEGD (code, ins->dreg, ins->sreg1);
5621 g_assert_not_reached ();
5625 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5631 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5636 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5639 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5640 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5644 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5647 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5648 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5652 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5655 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5656 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5657 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5661 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5664 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5665 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5669 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5672 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5673 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5674 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5678 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5681 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5682 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5686 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5689 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5690 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5694 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5697 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5698 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5701 /* ARM FPA flags table:
5702 * N Less than ARMCOND_MI
5703 * Z Equal ARMCOND_EQ
5704 * C Greater Than or Equal ARMCOND_CS
5705 * V Unordered ARMCOND_VS
5708 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5711 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5714 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5717 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5718 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5724 g_assert_not_reached ();
5728 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5730 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5731 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5732 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5736 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5737 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5742 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5743 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5745 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5746 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5748 *(guint32*)code = 0xffffffff;
5750 *(guint32*)code = 0x7fefffff;
5752 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5754 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5755 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5757 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5758 ARM_CPYD (code, ins->dreg, ins->sreg1);
5760 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5761 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5766 case OP_RCONV_TO_I1:
5767 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5769 case OP_RCONV_TO_U1:
5770 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5772 case OP_RCONV_TO_I2:
5773 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5775 case OP_RCONV_TO_U2:
5776 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5778 case OP_RCONV_TO_I4:
5779 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5781 case OP_RCONV_TO_U4:
5782 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5784 case OP_RCONV_TO_R4:
5786 if (ins->dreg != ins->sreg1)
5787 ARM_CPYS (code, ins->dreg, ins->sreg1);
5789 case OP_RCONV_TO_R8:
5791 ARM_CVTS (code, ins->dreg, ins->sreg1);
5794 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5797 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5800 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5803 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5806 ARM_NEGS (code, ins->dreg, ins->sreg1);
5810 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5813 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5814 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5818 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5821 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5822 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5826 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5829 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5830 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5831 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5835 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5838 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5839 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5843 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5846 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5847 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5848 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5852 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5855 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5856 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5860 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5863 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5864 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5868 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5871 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5872 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5875 case OP_GC_LIVENESS_DEF:
5876 case OP_GC_LIVENESS_USE:
5877 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5878 ins->backend.pc_offset = code - cfg->native_code;
5880 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5881 ins->backend.pc_offset = code - cfg->native_code;
5882 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5884 case OP_GC_SAFE_POINT: {
5887 g_assert (mono_threads_is_coop_enabled ());
5889 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5890 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5892 ARM_B_COND (code, ARMCOND_EQ, 0);
5893 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5894 code = emit_call_seq (cfg, code);
5895 arm_patch (buf [0], code);
5898 case OP_FILL_PROF_CALL_CTX:
5899 for (int i = 0; i < ARMREG_MAX; i++)
5900 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) || i == ARMREG_SP || i == ARMREG_FP)
5901 ARM_STR_IMM (code, i, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, regs) + i * sizeof (mgreg_t));
5904 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5905 g_assert_not_reached ();
5908 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5909 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5910 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5911 g_assert_not_reached ();
5917 last_offset = offset;
5920 cfg->code_len = code - cfg->native_code;
5923 #endif /* DISABLE_JIT */
5926 mono_arch_register_lowlevel_calls (void)
5928 /* The signature doesn't matter */
5929 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5930 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5931 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5934 #define patch_lis_ori(ip,val) do {\
5935 guint16 *__lis_ori = (guint16*)(ip); \
5936 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5937 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5941 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5943 unsigned char *ip = ji->ip.i + code;
5945 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5949 case MONO_PATCH_INFO_SWITCH: {
5950 gpointer *jt = (gpointer*)(ip + 8);
5952 /* jt is the inlined jump table, 2 instructions after ip
5953 * In the normal case we store the absolute addresses,
5954 * otherwise the displacements.
5956 for (i = 0; i < ji->data.table->table_size; i++)
5957 jt [i] = code + (int)ji->data.table->table [i];
5960 case MONO_PATCH_INFO_IP:
5961 g_assert_not_reached ();
5962 patch_lis_ori (ip, ip);
5964 case MONO_PATCH_INFO_METHOD_REL:
5965 g_assert_not_reached ();
5966 *((gpointer *)(ip)) = target;
5968 case MONO_PATCH_INFO_METHODCONST:
5969 case MONO_PATCH_INFO_CLASS:
5970 case MONO_PATCH_INFO_IMAGE:
5971 case MONO_PATCH_INFO_FIELD:
5972 case MONO_PATCH_INFO_VTABLE:
5973 case MONO_PATCH_INFO_IID:
5974 case MONO_PATCH_INFO_SFLDA:
5975 case MONO_PATCH_INFO_LDSTR:
5976 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5977 case MONO_PATCH_INFO_LDTOKEN:
5978 g_assert_not_reached ();
5979 /* from OP_AOTCONST : lis + ori */
5980 patch_lis_ori (ip, target);
5982 case MONO_PATCH_INFO_R4:
5983 case MONO_PATCH_INFO_R8:
5984 g_assert_not_reached ();
5985 *((gconstpointer *)(ip + 2)) = target;
5987 case MONO_PATCH_INFO_EXC_NAME:
5988 g_assert_not_reached ();
5989 *((gconstpointer *)(ip + 1)) = target;
5991 case MONO_PATCH_INFO_NONE:
5992 case MONO_PATCH_INFO_BB_OVF:
5993 case MONO_PATCH_INFO_EXC_OVF:
5994 /* everything is dealt with at epilog output time */
5997 arm_patch_general (cfg, domain, ip, target);
6003 mono_arm_unaligned_stack (MonoMethod *method)
6005 g_assert_not_reached ();
6011 * Stack frame layout:
6013 * ------------------- fp
6014 * MonoLMF structure or saved registers
6015 * -------------------
6017 * -------------------
6019 * -------------------
6020 * optional 8 bytes for tracing
6021 * -------------------
6022 * param area size is cfg->param_area
6023 * ------------------- sp
6026 mono_arch_emit_prolog (MonoCompile *cfg)
6028 MonoMethod *method = cfg->method;
6030 MonoMethodSignature *sig;
6032 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6037 int prev_sp_offset, reg_offset;
6039 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6042 sig = mono_method_signature (method);
6043 cfg->code_size = 256 + sig->param_count * 64;
6044 code = cfg->native_code = g_malloc (cfg->code_size);
6046 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6048 alloc_size = cfg->stack_offset;
6054 * The iphone uses R7 as the frame pointer, and it points at the saved
6059 * We can't use r7 as a frame pointer since it points into the middle of
6060 * the frame, so we keep using our own frame pointer.
6061 * FIXME: Optimize this.
6063 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6064 prev_sp_offset += 8; /* r7 and lr */
6065 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6066 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6067 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6070 if (!method->save_lmf) {
6072 /* No need to push LR again */
6073 if (cfg->used_int_regs)
6074 ARM_PUSH (code, cfg->used_int_regs);
6076 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6077 prev_sp_offset += 4;
6079 for (i = 0; i < 16; ++i) {
6080 if (cfg->used_int_regs & (1 << i))
6081 prev_sp_offset += 4;
6083 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6085 for (i = 0; i < 16; ++i) {
6086 if ((cfg->used_int_regs & (1 << i))) {
6087 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6088 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6092 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6093 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6095 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6096 ARM_PUSH (code, 0x5ff0);
6097 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6098 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6100 for (i = 0; i < 16; ++i) {
6101 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6102 /* The original r7 is saved at the start */
6103 if (!(iphone_abi && i == ARMREG_R7))
6104 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6108 g_assert (reg_offset == 4 * 10);
6109 pos += sizeof (MonoLMF) - (4 * 10);
6113 orig_alloc_size = alloc_size;
6114 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6115 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6116 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6117 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6120 /* the stack used in the pushed regs */
6121 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6122 cfg->stack_usage = alloc_size;
6124 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6125 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6127 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6128 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6130 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6132 if (cfg->frame_reg != ARMREG_SP) {
6133 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6134 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6136 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6137 prev_sp_offset += alloc_size;
6139 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6140 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6142 /* compute max_offset in order to use short forward jumps
6143 * we could skip do it on arm because the immediate displacement
6144 * for jumps is large enough, it may be useful later for constant pools
6147 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6148 MonoInst *ins = bb->code;
6149 bb->max_offset = max_offset;
6151 MONO_BB_FOR_EACH_INS (bb, ins)
6152 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6155 /* stack alignment check */
6159 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6160 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6161 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6162 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6164 ARM_B_COND (code, ARMCOND_EQ, 0);
6165 if (cfg->compile_aot)
6166 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6168 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6169 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6170 code = emit_call_seq (cfg, code);
6171 arm_patch (buf [0], code);
6175 /* store runtime generic context */
6176 if (cfg->rgctx_var) {
6177 MonoInst *ins = cfg->rgctx_var;
6179 g_assert (ins->opcode == OP_REGOFFSET);
6181 if (arm_is_imm12 (ins->inst_offset)) {
6182 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6184 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6185 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6189 /* load arguments allocated to register from the stack */
6192 cinfo = get_call_info (NULL, sig);
6194 if (cinfo->ret.storage == RegTypeStructByAddr) {
6195 ArgInfo *ainfo = &cinfo->ret;
6196 inst = cfg->vret_addr;
6197 g_assert (arm_is_imm12 (inst->inst_offset));
6198 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6201 if (sig->call_convention == MONO_CALL_VARARG) {
6202 ArgInfo *cookie = &cinfo->sig_cookie;
6204 /* Save the sig cookie address */
6205 g_assert (cookie->storage == RegTypeBase);
6207 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6208 g_assert (arm_is_imm12 (cfg->sig_cookie));
6209 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6210 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6213 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6214 ArgInfo *ainfo = cinfo->args + i;
6215 inst = cfg->args [pos];
6217 if (cfg->verbose_level > 2)
6218 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6220 if (inst->opcode == OP_REGVAR) {
6221 if (ainfo->storage == RegTypeGeneral)
6222 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6223 else if (ainfo->storage == RegTypeFP) {
6224 g_assert_not_reached ();
6225 } else if (ainfo->storage == RegTypeBase) {
6226 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6227 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6229 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6230 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6233 g_assert_not_reached ();
6235 if (cfg->verbose_level > 2)
6236 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6238 switch (ainfo->storage) {
6240 for (part = 0; part < ainfo->nregs; part ++) {
6241 if (ainfo->esize == 4)
6242 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6244 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6247 case RegTypeGeneral:
6248 case RegTypeIRegPair:
6249 case RegTypeGSharedVtInReg:
6250 case RegTypeStructByAddr:
6251 switch (ainfo->size) {
6253 if (arm_is_imm12 (inst->inst_offset))
6254 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6256 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6257 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6261 if (arm_is_imm8 (inst->inst_offset)) {
6262 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6264 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6265 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6269 if (arm_is_imm12 (inst->inst_offset)) {
6270 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6272 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6273 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6275 if (arm_is_imm12 (inst->inst_offset + 4)) {
6276 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6278 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6279 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6283 if (arm_is_imm12 (inst->inst_offset)) {
6284 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6286 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6287 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6292 case RegTypeBaseGen:
6293 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6294 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6296 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6297 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6299 if (arm_is_imm12 (inst->inst_offset + 4)) {
6300 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6301 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6303 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6304 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6305 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6306 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6310 case RegTypeGSharedVtOnStack:
6311 case RegTypeStructByAddrOnStack:
6312 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6313 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6315 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6316 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6319 switch (ainfo->size) {
6321 if (arm_is_imm8 (inst->inst_offset)) {
6322 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6324 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6325 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6329 if (arm_is_imm8 (inst->inst_offset)) {
6330 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6332 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6333 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6337 if (arm_is_imm12 (inst->inst_offset)) {
6338 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6340 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6341 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6343 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6344 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6346 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6347 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6349 if (arm_is_imm12 (inst->inst_offset + 4)) {
6350 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6352 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6353 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6357 if (arm_is_imm12 (inst->inst_offset)) {
6358 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6360 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6361 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6367 int imm8, rot_amount;
6369 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6370 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6371 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6373 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6375 if (ainfo->size == 8)
6376 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6378 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6381 case RegTypeStructByVal: {
6382 int doffset = inst->inst_offset;
6386 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6387 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6388 if (arm_is_imm12 (doffset)) {
6389 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6391 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6392 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6394 soffset += sizeof (gpointer);
6395 doffset += sizeof (gpointer);
6397 if (ainfo->vtsize) {
6398 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6399 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6400 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6405 g_assert_not_reached ();
6412 if (method->save_lmf)
6413 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6416 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6418 if (cfg->arch.seq_point_info_var) {
6419 MonoInst *ins = cfg->arch.seq_point_info_var;
6421 /* Initialize the variable from a GOT slot */
6422 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6423 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6425 *(gpointer*)code = NULL;
6427 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6429 g_assert (ins->opcode == OP_REGOFFSET);
6431 if (arm_is_imm12 (ins->inst_offset)) {
6432 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6434 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6435 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6439 /* Initialize ss_trigger_page_var */
6440 if (!cfg->soft_breakpoints) {
6441 MonoInst *info_var = cfg->arch.seq_point_info_var;
6442 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6443 int dreg = ARMREG_LR;
6446 g_assert (info_var->opcode == OP_REGOFFSET);
6448 code = emit_ldr_imm (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6449 /* Load the trigger page addr */
6450 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6451 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6455 if (cfg->arch.seq_point_ss_method_var) {
6456 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6457 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6459 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6460 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6462 if (cfg->compile_aot) {
6463 MonoInst *info_var = cfg->arch.seq_point_info_var;
6464 int dreg = ARMREG_LR;
6466 g_assert (info_var->opcode == OP_REGOFFSET);
6467 g_assert (arm_is_imm12 (info_var->inst_offset));
6469 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6470 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6471 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6473 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6474 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6476 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6478 *(gpointer*)code = &single_step_tramp;
6480 *(gpointer*)code = breakpoint_tramp;
6483 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6484 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6485 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6486 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6490 cfg->code_len = code - cfg->native_code;
6491 g_assert (cfg->code_len < cfg->code_size);
6498 mono_arch_emit_epilog (MonoCompile *cfg)
6500 MonoMethod *method = cfg->method;
6501 int pos, i, rot_amount;
6502 int max_epilog_size = 16 + 20*4;
6506 if (cfg->method->save_lmf)
6507 max_epilog_size += 128;
6509 if (mono_jit_trace_calls != NULL)
6510 max_epilog_size += 50;
6512 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6513 cfg->code_size *= 2;
6514 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6515 cfg->stat_code_reallocs++;
6519 * Keep in sync with OP_JMP
6521 code = cfg->native_code + cfg->code_len;
6523 /* Save the uwind state which is needed by the out-of-line code */
6524 mono_emit_unwind_op_remember_state (cfg, code);
6526 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6527 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6531 /* Load returned vtypes into registers if needed */
6532 cinfo = cfg->arch.cinfo;
6533 switch (cinfo->ret.storage) {
6534 case RegTypeStructByVal: {
6535 MonoInst *ins = cfg->ret;
6537 if (cinfo->ret.nregs == 1) {
6538 if (arm_is_imm12 (ins->inst_offset)) {
6539 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6541 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6542 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6545 for (i = 0; i < cinfo->ret.nregs; ++i) {
6546 int offset = ins->inst_offset + (i * 4);
6547 if (arm_is_imm12 (offset)) {
6548 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6550 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6551 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6558 MonoInst *ins = cfg->ret;
6560 for (i = 0; i < cinfo->ret.nregs; ++i) {
6561 if (cinfo->ret.esize == 4)
6562 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6564 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6572 if (method->save_lmf) {
6573 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6574 /* all but r0-r3, sp and pc */
6575 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6578 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6580 /* This points to r4 inside MonoLMF->iregs */
6581 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6583 regmask = 0x9ff0; /* restore lr to pc */
6584 /* Skip caller saved registers not used by the method */
6585 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6586 regmask &= ~(1 << reg);
6591 /* Restored later */
6592 regmask &= ~(1 << ARMREG_PC);
6593 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6594 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6595 for (i = 0; i < 16; i++) {
6596 if (regmask & (1 << i))
6599 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6601 ARM_POP (code, regmask);
6603 for (i = 0; i < 16; i++) {
6604 if (regmask & (1 << i))
6605 mono_emit_unwind_op_same_value (cfg, code, i);
6607 /* Restore saved r7, restore LR to PC */
6608 /* Skip lr from the lmf */
6609 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6610 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6611 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6612 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6615 int i, nused_int_regs = 0;
6617 for (i = 0; i < 16; i++) {
6618 if (cfg->used_int_regs & (1 << i))
6622 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6623 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6625 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6626 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6629 if (cfg->frame_reg != ARMREG_SP) {
6630 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6634 /* Restore saved gregs */
6635 if (cfg->used_int_regs) {
6636 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6637 ARM_POP (code, cfg->used_int_regs);
6638 for (i = 0; i < 16; i++) {
6639 if (cfg->used_int_regs & (1 << i))
6640 mono_emit_unwind_op_same_value (cfg, code, i);
6643 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6644 /* Restore saved r7, restore LR to PC */
6645 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6647 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6648 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6652 /* Restore the unwind state to be the same as before the epilog */
6653 mono_emit_unwind_op_restore_state (cfg, code);
6655 cfg->code_len = code - cfg->native_code;
6657 g_assert (cfg->code_len < cfg->code_size);
6662 mono_arch_emit_exceptions (MonoCompile *cfg)
6664 MonoJumpInfo *patch_info;
6667 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6668 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6669 int max_epilog_size = 50;
6671 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6672 exc_throw_pos [i] = NULL;
6673 exc_throw_found [i] = 0;
6676 /* count the number of exception infos */
6679 * make sure we have enough space for exceptions
6681 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6682 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6683 i = mini_exception_id_by_name (patch_info->data.target);
6684 if (!exc_throw_found [i]) {
6685 max_epilog_size += 32;
6686 exc_throw_found [i] = TRUE;
6691 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6692 cfg->code_size *= 2;
6693 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6694 cfg->stat_code_reallocs++;
6697 code = cfg->native_code + cfg->code_len;
6699 /* add code to raise exceptions */
6700 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6701 switch (patch_info->type) {
6702 case MONO_PATCH_INFO_EXC: {
6703 MonoClass *exc_class;
6704 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6706 i = mini_exception_id_by_name (patch_info->data.target);
6707 if (exc_throw_pos [i]) {
6708 arm_patch (ip, exc_throw_pos [i]);
6709 patch_info->type = MONO_PATCH_INFO_NONE;
6712 exc_throw_pos [i] = code;
6714 arm_patch (ip, code);
6716 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6718 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6719 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6720 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6721 patch_info->data.name = "mono_arch_throw_corlib_exception";
6722 patch_info->ip.i = code - cfg->native_code;
6724 cfg->thunk_area += THUNK_SIZE;
6725 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6735 cfg->code_len = code - cfg->native_code;
6737 g_assert (cfg->code_len < cfg->code_size);
6741 #endif /* #ifndef DISABLE_JIT */
6744 mono_arch_finish_init (void)
6749 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6754 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6765 mono_arch_get_patch_offset (guint8 *code)
6772 mono_arch_flush_register_windows (void)
6777 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6779 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6783 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6785 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6789 mono_arch_get_cie_program (void)
6793 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6798 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6799 #define BASE_SIZE (6 * 4)
6800 #define BSEARCH_ENTRY_SIZE (4 * 4)
6801 #define CMP_SIZE (3 * 4)
6802 #define BRANCH_SIZE (1 * 4)
6803 #define CALL_SIZE (2 * 4)
6804 #define WMC_SIZE (8 * 4)
6805 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6808 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6810 guint32 delta = DISTANCE (target, code);
6812 g_assert (delta >= 0 && delta <= 0xFFF);
6813 *target = *target | delta;
6818 #ifdef ENABLE_WRONG_METHOD_CHECK
6820 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6822 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6828 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6829 gpointer fail_tramp)
6832 arminstr_t *code, *start;
6833 gboolean large_offsets = FALSE;
6834 guint32 **constant_pool_starts;
6835 arminstr_t *vtable_target = NULL;
6836 int extra_space = 0;
6837 #ifdef ENABLE_WRONG_METHOD_CHECK
6843 constant_pool_starts = g_new0 (guint32*, count);
6845 for (i = 0; i < count; ++i) {
6846 MonoIMTCheckItem *item = imt_entries [i];
6847 if (item->is_equals) {
6848 gboolean fail_case = !item->check_target_idx && fail_tramp;
6850 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6851 item->chunk_size += 32;
6852 large_offsets = TRUE;
6855 if (item->check_target_idx || fail_case) {
6856 if (!item->compare_done || fail_case)
6857 item->chunk_size += CMP_SIZE;
6858 item->chunk_size += BRANCH_SIZE;
6860 #ifdef ENABLE_WRONG_METHOD_CHECK
6861 item->chunk_size += WMC_SIZE;
6865 item->chunk_size += 16;
6866 large_offsets = TRUE;
6868 item->chunk_size += CALL_SIZE;
6870 item->chunk_size += BSEARCH_ENTRY_SIZE;
6871 imt_entries [item->check_target_idx]->compare_done = TRUE;
6873 size += item->chunk_size;
6877 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6880 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6882 code = mono_domain_code_reserve (domain, size);
6885 unwind_ops = mono_arch_get_cie_program ();
6888 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6889 for (i = 0; i < count; ++i) {
6890 MonoIMTCheckItem *item = imt_entries [i];
6891 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6895 if (large_offsets) {
6896 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6897 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6899 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6900 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6902 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6903 vtable_target = code;
6904 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6905 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6907 for (i = 0; i < count; ++i) {
6908 MonoIMTCheckItem *item = imt_entries [i];
6909 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6910 gint32 vtable_offset;
6912 item->code_target = (guint8*)code;
6914 if (item->is_equals) {
6915 gboolean fail_case = !item->check_target_idx && fail_tramp;
6917 if (item->check_target_idx || fail_case) {
6918 if (!item->compare_done || fail_case) {
6920 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6921 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6923 item->jmp_code = (guint8*)code;
6924 ARM_B_COND (code, ARMCOND_NE, 0);
6926 /*Enable the commented code to assert on wrong method*/
6927 #ifdef ENABLE_WRONG_METHOD_CHECK
6929 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6930 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6932 ARM_B_COND (code, ARMCOND_EQ, 0);
6934 /* Define this if your system is so bad that gdb is failing. */
6935 #ifdef BROKEN_DEV_ENV
6936 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6938 arm_patch (code - 1, mini_dump_bad_imt);
6942 arm_patch (cond, code);
6946 if (item->has_target_code) {
6947 /* Load target address */
6948 target_code_ins = code;
6949 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6950 /* Save it to the fourth slot */
6951 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6952 /* Restore registers and branch */
6953 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6955 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6957 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6958 if (!arm_is_imm12 (vtable_offset)) {
6960 * We need to branch to a computed address but we don't have
6961 * a free register to store it, since IP must contain the
6962 * vtable address. So we push the two values to the stack, and
6963 * load them both using LDM.
6965 /* Compute target address */
6966 vtable_offset_ins = code;
6967 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6968 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6969 /* Save it to the fourth slot */
6970 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6971 /* Restore registers and branch */
6972 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6974 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6976 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6977 if (large_offsets) {
6978 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6979 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6981 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6982 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6987 arm_patch (item->jmp_code, (guchar*)code);
6989 target_code_ins = code;
6990 /* Load target address */
6991 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6992 /* Save it to the fourth slot */
6993 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6994 /* Restore registers and branch */
6995 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6997 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6998 item->jmp_code = NULL;
7002 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7004 /*must emit after unconditional branch*/
7005 if (vtable_target) {
7006 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7007 item->chunk_size += 4;
7008 vtable_target = NULL;
7011 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7012 constant_pool_starts [i] = code;
7014 code += extra_space;
7018 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7019 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7021 item->jmp_code = (guint8*)code;
7022 ARM_B_COND (code, ARMCOND_HS, 0);
7027 for (i = 0; i < count; ++i) {
7028 MonoIMTCheckItem *item = imt_entries [i];
7029 if (item->jmp_code) {
7030 if (item->check_target_idx)
7031 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7033 if (i > 0 && item->is_equals) {
7035 arminstr_t *space_start = constant_pool_starts [i];
7036 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7037 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7044 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7045 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7050 g_free (constant_pool_starts);
7052 mono_arch_flush_icache ((guint8*)start, size);
7053 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
7054 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
7056 g_assert (DISTANCE (start, code) <= size);
7058 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7064 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7066 return ctx->regs [reg];
7070 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7072 ctx->regs [reg] = val;
7076 * mono_arch_get_trampolines:
7078 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7082 mono_arch_get_trampolines (gboolean aot)
7084 return mono_arm_get_exception_trampolines (aot);
7087 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7089 * mono_arch_set_breakpoint:
7091 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7092 * The location should contain code emitted by OP_SEQ_POINT.
7095 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7098 guint32 native_offset = ip - (guint8*)ji->code_start;
7099 MonoDebugOptions *opt = mini_get_debug_options ();
7102 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7104 if (!breakpoint_tramp)
7105 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7107 g_assert (native_offset % 4 == 0);
7108 g_assert (info->bp_addrs [native_offset / 4] == 0);
7109 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7110 } else if (opt->soft_breakpoints) {
7112 ARM_BLX_REG (code, ARMREG_LR);
7113 mono_arch_flush_icache (code - 4, 4);
7115 int dreg = ARMREG_LR;
7117 /* Read from another trigger page */
7118 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7120 *(int*)code = (int)bp_trigger_page;
7122 ARM_LDR_IMM (code, dreg, dreg, 0);
7124 mono_arch_flush_icache (code - 16, 16);
7127 /* This is currently implemented by emitting an SWI instruction, which
7128 * qemu/linux seems to convert to a SIGILL.
7130 *(int*)code = (0xef << 24) | 8;
7132 mono_arch_flush_icache (code - 4, 4);
7138 * mono_arch_clear_breakpoint:
7140 * Clear the breakpoint at IP.
7143 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7145 MonoDebugOptions *opt = mini_get_debug_options ();
7150 guint32 native_offset = ip - (guint8*)ji->code_start;
7151 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7153 if (!breakpoint_tramp)
7154 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7156 g_assert (native_offset % 4 == 0);
7157 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7158 info->bp_addrs [native_offset / 4] = 0;
7159 } else if (opt->soft_breakpoints) {
7162 mono_arch_flush_icache (code - 4, 4);
7164 for (i = 0; i < 4; ++i)
7167 mono_arch_flush_icache (ip, code - ip);
7172 * mono_arch_start_single_stepping:
7174 * Start single stepping.
7177 mono_arch_start_single_stepping (void)
7179 if (ss_trigger_page)
7180 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7182 single_step_tramp = mini_get_single_step_trampoline ();
7186 * mono_arch_stop_single_stepping:
7188 * Stop single stepping.
7191 mono_arch_stop_single_stepping (void)
7193 if (ss_trigger_page)
7194 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7196 single_step_tramp = NULL;
7200 #define DBG_SIGNAL SIGBUS
7202 #define DBG_SIGNAL SIGSEGV
7206 * mono_arch_is_single_step_event:
7208 * Return whenever the machine state in SIGCTX corresponds to a single
7212 mono_arch_is_single_step_event (void *info, void *sigctx)
7214 siginfo_t *sinfo = info;
7216 if (!ss_trigger_page)
7219 /* Sometimes the address is off by 4 */
7220 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7227 * mono_arch_is_breakpoint_event:
7229 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7232 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7234 siginfo_t *sinfo = info;
7236 if (!ss_trigger_page)
7239 if (sinfo->si_signo == DBG_SIGNAL) {
7240 /* Sometimes the address is off by 4 */
7241 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7251 * mono_arch_skip_breakpoint:
7253 * See mini-amd64.c for docs.
7256 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7258 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7262 * mono_arch_skip_single_step:
7264 * See mini-amd64.c for docs.
7267 mono_arch_skip_single_step (MonoContext *ctx)
7269 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7272 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7275 * mono_arch_get_seq_point_info:
7277 * See mini-amd64.c for docs.
7280 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7285 // FIXME: Add a free function
7287 mono_domain_lock (domain);
7288 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7290 mono_domain_unlock (domain);
7293 ji = mono_jit_info_table_find (domain, (char*)code);
7296 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7298 info->ss_trigger_page = ss_trigger_page;
7299 info->bp_trigger_page = bp_trigger_page;
7300 info->ss_tramp_addr = &single_step_tramp;
7302 mono_domain_lock (domain);
7303 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7305 mono_domain_unlock (domain);
7312 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7314 ext->lmf.previous_lmf = prev_lmf;
7315 /* Mark that this is a MonoLMFExt */
7316 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7317 ext->lmf.sp = (gssize)ext;
7321 * mono_arch_set_target:
7323 * Set the target architecture the JIT backend should generate code for, in the form
7324 * of a GNU target triplet. Only used in AOT mode.
7327 mono_arch_set_target (char *mtriple)
7329 /* The GNU target triple format is not very well documented */
7330 if (strstr (mtriple, "armv7")) {
7331 v5_supported = TRUE;
7332 v6_supported = TRUE;
7333 v7_supported = TRUE;
7335 if (strstr (mtriple, "armv6")) {
7336 v5_supported = TRUE;
7337 v6_supported = TRUE;
7339 if (strstr (mtriple, "armv7s")) {
7340 v7s_supported = TRUE;
7342 if (strstr (mtriple, "armv7k")) {
7343 v7k_supported = TRUE;
7345 if (strstr (mtriple, "thumbv7s")) {
7346 v5_supported = TRUE;
7347 v6_supported = TRUE;
7348 v7_supported = TRUE;
7349 v7s_supported = TRUE;
7350 thumb_supported = TRUE;
7351 thumb2_supported = TRUE;
7353 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7354 v5_supported = TRUE;
7355 v6_supported = TRUE;
7356 thumb_supported = TRUE;
7359 if (strstr (mtriple, "gnueabi"))
7360 eabi_supported = TRUE;
7364 mono_arch_opcode_supported (int opcode)
7367 case OP_ATOMIC_ADD_I4:
7368 case OP_ATOMIC_EXCHANGE_I4:
7369 case OP_ATOMIC_CAS_I4:
7370 case OP_ATOMIC_LOAD_I1:
7371 case OP_ATOMIC_LOAD_I2:
7372 case OP_ATOMIC_LOAD_I4:
7373 case OP_ATOMIC_LOAD_U1:
7374 case OP_ATOMIC_LOAD_U2:
7375 case OP_ATOMIC_LOAD_U4:
7376 case OP_ATOMIC_STORE_I1:
7377 case OP_ATOMIC_STORE_I2:
7378 case OP_ATOMIC_STORE_I4:
7379 case OP_ATOMIC_STORE_U1:
7380 case OP_ATOMIC_STORE_U2:
7381 case OP_ATOMIC_STORE_U4:
7382 return v7_supported;
7383 case OP_ATOMIC_LOAD_R4:
7384 case OP_ATOMIC_LOAD_R8:
7385 case OP_ATOMIC_STORE_R4:
7386 case OP_ATOMIC_STORE_R8:
7387 return v7_supported && IS_VFP;
7394 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7396 return get_call_info (mp, sig);
7400 mono_arch_get_get_tls_tramp (void)
7406 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7409 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7410 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7412 *(gpointer*)code = NULL;
7414 /* Load the value from the GOT */
7415 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7420 mono_arm_emit_aotconst (gpointer ji_list, guint8 *code, guint8 *buf, int dreg, int patch_type, gconstpointer data)
7422 MonoJumpInfo **ji = (MonoJumpInfo**)ji_list;
7424 *ji = mono_patch_info_list_prepend (*ji, code - buf, patch_type, data);
7425 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7427 *(gpointer*)code = NULL;
7429 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);