2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
33 || defined(TARGET_ANDROID) \
34 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean v7k_supported = FALSE;
107 static gboolean thumb_supported = FALSE;
108 static gboolean thumb2_supported = FALSE;
110 * Whenever to use the ARM EABI
112 static gboolean eabi_supported = FALSE;
115 * Whenever to use the iphone ABI extensions:
116 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
117 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
118 * This is required for debugging/profiling tools to work, but it has some overhead so it should
119 * only be turned on in debug builds.
121 static gboolean iphone_abi = FALSE;
124 * The FPU we are generating code for. This is NOT runtime configurable right now,
125 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
127 static MonoArmFPU arm_fpu;
129 #if defined(ARM_FPU_VFP_HARD)
131 * On armhf, d0-d7 are used for argument passing and d8-d15
132 * must be preserved across calls, which leaves us no room
133 * for scratch registers. So we use d14-d15 but back up their
134 * previous contents to a stack slot before using them - see
135 * mono_arm_emit_vfp_scratch_save/_restore ().
137 static int vfp_scratch1 = ARM_VFP_D14;
138 static int vfp_scratch2 = ARM_VFP_D15;
141 * On armel, d0-d7 do not need to be preserved, so we can
142 * freely make use of them as scratch registers.
144 static int vfp_scratch1 = ARM_VFP_D0;
145 static int vfp_scratch2 = ARM_VFP_D1;
150 static gpointer single_step_tramp, breakpoint_tramp;
153 * The code generated for sequence points reads from this location, which is
154 * made read-only when single stepping is enabled.
156 static gpointer ss_trigger_page;
158 /* Enabled breakpoints read from this trigger page */
159 static gpointer bp_trigger_page;
163 * floating point support: on ARM it is a mess, there are at least 3
164 * different setups, each of which binary incompat with the other.
165 * 1) FPA: old and ugly, but unfortunately what current distros use
166 * the double binary format has the two words swapped. 8 double registers.
167 * Implemented usually by kernel emulation.
168 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
169 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
170 * 3) VFP: the new and actually sensible and useful FP support. Implemented
171 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
173 * We do not care about FPA. We will support soft float and VFP.
175 int mono_exc_esp_offset = 0;
177 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
178 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
179 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
181 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
182 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
183 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
185 //#define DEBUG_IMT 0
188 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
192 mono_arch_regname (int reg)
194 static const char * rnames[] = {
195 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
196 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
197 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
200 if (reg >= 0 && reg < 16)
206 mono_arch_fregname (int reg)
208 static const char * rnames[] = {
209 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
210 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
211 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
212 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
213 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
214 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
217 if (reg >= 0 && reg < 32)
225 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
227 int imm8, rot_amount;
228 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
229 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
233 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
234 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
236 code = mono_arm_emit_load_imm (code, dreg, imm);
237 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
242 /* If dreg == sreg, this clobbers IP */
244 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
246 int imm8, rot_amount;
247 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
248 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
252 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
253 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
255 code = mono_arm_emit_load_imm (code, dreg, imm);
256 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
262 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
264 /* we can use r0-r3, since this is called only for incoming args on the stack */
265 if (size > sizeof (gpointer) * 4) {
267 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
268 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
269 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
270 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
271 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
272 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
274 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
275 ARM_B_COND (code, ARMCOND_NE, 0);
276 arm_patch (code - 4, start_loop);
279 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
280 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
282 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
283 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
289 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
290 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
291 doffset = soffset = 0;
293 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
294 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
300 g_assert (size == 0);
305 emit_call_reg (guint8 *code, int reg)
308 ARM_BLX_REG (code, reg);
310 #ifdef USE_JUMP_TABLES
311 g_assert_not_reached ();
313 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
317 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
323 emit_call_seq (MonoCompile *cfg, guint8 *code)
325 #ifdef USE_JUMP_TABLES
326 code = mono_arm_patchable_bl (code, ARMCOND_AL);
328 if (cfg->method->dynamic) {
329 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
331 *(gpointer*)code = NULL;
333 code = emit_call_reg (code, ARMREG_IP);
337 cfg->thunk_area += THUNK_SIZE;
343 mono_arm_patchable_b (guint8 *code, int cond)
345 #ifdef USE_JUMP_TABLES
348 jte = mono_jumptable_add_entry ();
349 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
350 ARM_BX_COND (code, cond, ARMREG_IP);
352 ARM_B_COND (code, cond, 0);
358 mono_arm_patchable_bl (guint8 *code, int cond)
360 #ifdef USE_JUMP_TABLES
363 jte = mono_jumptable_add_entry ();
364 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
365 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
367 ARM_BL_COND (code, cond, 0);
372 #ifdef USE_JUMP_TABLES
374 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
376 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
377 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
382 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
384 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
385 ARM_LDR_IMM (code, reg, reg, 0);
391 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
394 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
395 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
397 code = emit_call_seq (cfg, code);
398 if (dreg != ARMREG_R0)
399 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
401 g_assert_not_reached ();
407 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
410 if (tls_offset_reg != ARMREG_R0)
411 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
412 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
414 code = emit_call_seq (cfg, code);
415 if (dreg != ARMREG_R0)
416 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
418 g_assert_not_reached ();
424 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
427 if (sreg != ARMREG_R1)
428 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
429 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
430 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
432 code = emit_call_seq (cfg, code);
434 g_assert_not_reached ();
440 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
443 /* Get sreg in R1 and tls_offset_reg in R0 */
444 if (tls_offset_reg == ARMREG_R1) {
445 if (sreg == ARMREG_R0) {
446 /* swap sreg and tls_offset_reg */
447 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
448 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
451 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
452 if (sreg != ARMREG_R1)
453 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
456 if (sreg != ARMREG_R1)
457 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
458 if (tls_offset_reg != ARMREG_R0)
459 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
461 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
463 code = emit_call_seq (cfg, code);
465 g_assert_not_reached ();
473 * Emit code to push an LMF structure on the LMF stack.
474 * On arm, this is intermixed with the initialization of other fields of the structure.
477 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
479 gboolean get_lmf_fast = FALSE;
482 if (mono_arm_have_tls_get ()) {
484 if (cfg->compile_aot) {
486 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
487 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
489 *(gpointer*)code = NULL;
491 /* Load the value from the GOT */
492 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
493 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
495 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
496 g_assert (lmf_addr_tls_offset != -1);
497 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
502 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
503 (gpointer)"mono_get_lmf_addr");
504 code = emit_call_seq (cfg, code);
506 /* we build the MonoLMF structure on the stack - see mini-arm.h */
507 /* lmf_offset is the offset from the previous stack pointer,
508 * alloc_size is the total stack space allocated, so the offset
509 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
510 * The pointer to the struct is put in r1 (new_lmf).
511 * ip is used as scratch
512 * The callee-saved registers are already in the MonoLMF structure
514 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
515 /* r0 is the result from mono_get_lmf_addr () */
516 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
517 /* new_lmf->previous_lmf = *lmf_addr */
518 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
519 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 /* *(lmf_addr) = r1 */
521 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
522 /* Skip method (only needed for trampoline LMF frames) */
523 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
524 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
525 /* save the current IP */
526 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
529 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
530 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
541 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
545 g_assert (!cfg->r4fp);
547 for (list = inst->float_args; list; list = list->next) {
548 FloatArgData *fad = list->data;
549 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
550 gboolean imm = arm_is_fpimm8 (var->inst_offset);
552 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
558 if (*offset + *max_len > cfg->code_size) {
559 cfg->code_size += *max_len;
560 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
562 code = cfg->native_code + *offset;
566 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
567 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
569 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
571 *offset = code - cfg->native_code;
578 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
582 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
584 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
587 if (!arm_is_fpimm8 (inst->inst_offset)) {
588 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
589 ARM_FSTD (code, reg, ARMREG_LR, 0);
591 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
598 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
602 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
604 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
607 if (!arm_is_fpimm8 (inst->inst_offset)) {
608 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
609 ARM_FLDD (code, reg, ARMREG_LR, 0);
611 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
620 * Emit code to pop an LMF structure from the LMF stack.
623 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
627 if (lmf_offset < 32) {
628 basereg = cfg->frame_reg;
633 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
636 /* ip = previous_lmf */
637 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
639 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
640 /* *(lmf_addr) = previous_lmf */
641 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
646 #endif /* #ifndef DISABLE_JIT */
649 * mono_arm_have_tls_get:
651 * Returns whether we have tls access implemented on the current
655 mono_arm_have_tls_get (void)
665 * mono_arch_get_argument_info:
666 * @csig: a method signature
667 * @param_count: the number of parameters to consider
668 * @arg_info: an array to store the result infos
670 * Gathers information on parameters such as size, alignment and
671 * padding. arg_info should be large enought to hold param_count + 1 entries.
673 * Returns the size of the activation frame.
676 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
678 int k, frame_size = 0;
679 guint32 size, align, pad;
683 t = mini_get_underlying_type (csig->ret);
684 if (MONO_TYPE_ISSTRUCT (t)) {
685 frame_size += sizeof (gpointer);
689 arg_info [0].offset = offset;
692 frame_size += sizeof (gpointer);
696 arg_info [0].size = frame_size;
698 for (k = 0; k < param_count; k++) {
699 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
701 /* ignore alignment for now */
704 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
705 arg_info [k].pad = pad;
707 arg_info [k + 1].pad = 0;
708 arg_info [k + 1].size = size;
710 arg_info [k + 1].offset = offset;
714 align = MONO_ARCH_FRAME_ALIGNMENT;
715 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
716 arg_info [k].pad = pad;
721 #define MAX_ARCH_DELEGATE_PARAMS 3
724 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
726 guint8 *code, *start;
727 GSList *unwind_ops = mono_arch_get_cie_program ();
730 start = code = mono_global_codeman_reserve (12);
732 /* Replace the this argument with the target */
733 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
734 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
735 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
737 g_assert ((code - start) <= 12);
739 mono_arch_flush_icache (start, 12);
743 size = 8 + param_count * 4;
744 start = code = mono_global_codeman_reserve (size);
746 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
747 /* slide down the arguments */
748 for (i = 0; i < param_count; ++i) {
749 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
751 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
753 g_assert ((code - start) <= size);
755 mono_arch_flush_icache (start, size);
759 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
761 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
762 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
766 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
772 * mono_arch_get_delegate_invoke_impls:
774 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
778 mono_arch_get_delegate_invoke_impls (void)
784 get_delegate_invoke_impl (&info, TRUE, 0);
785 res = g_slist_prepend (res, info);
787 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
788 get_delegate_invoke_impl (&info, FALSE, i);
789 res = g_slist_prepend (res, info);
796 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
798 guint8 *code, *start;
801 /* FIXME: Support more cases */
802 sig_ret = mini_get_underlying_type (sig->ret);
803 if (MONO_TYPE_ISSTRUCT (sig_ret))
807 static guint8* cached = NULL;
808 mono_mini_arch_lock ();
810 mono_mini_arch_unlock ();
815 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
818 start = get_delegate_invoke_impl (&info, TRUE, 0);
819 mono_tramp_info_register (info, NULL);
822 mono_mini_arch_unlock ();
825 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
828 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
830 for (i = 0; i < sig->param_count; ++i)
831 if (!mono_is_regsize_var (sig->params [i]))
834 mono_mini_arch_lock ();
835 code = cache [sig->param_count];
837 mono_mini_arch_unlock ();
842 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
843 start = mono_aot_get_trampoline (name);
847 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
848 mono_tramp_info_register (info, NULL);
850 cache [sig->param_count] = start;
851 mono_mini_arch_unlock ();
859 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
865 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
867 return (gpointer)regs [ARMREG_R0];
871 * Initialize the cpu to execute managed code.
874 mono_arch_cpu_init (void)
876 i8_align = MONO_ABI_ALIGNOF (gint64);
877 #ifdef MONO_CROSS_COMPILE
878 /* Need to set the alignment of i8 since it can different on the target */
879 #ifdef TARGET_ANDROID
881 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
887 * Initialize architecture specific code.
890 mono_arch_init (void)
892 const char *cpu_arch;
894 mono_os_mutex_init_recursive (&mini_arch_mutex);
895 if (mini_get_debug_options ()->soft_breakpoints) {
896 breakpoint_tramp = mini_get_breakpoint_trampoline ();
898 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
899 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
900 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
903 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
904 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
905 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
906 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
907 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
909 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
911 #if defined(__ARM_EABI__)
912 eabi_supported = TRUE;
915 #if defined(ARM_FPU_VFP_HARD)
916 arm_fpu = MONO_ARM_FPU_VFP_HARD;
918 arm_fpu = MONO_ARM_FPU_VFP;
920 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
922 * If we're compiling with a soft float fallback and it
923 * turns out that no VFP unit is available, we need to
924 * switch to soft float. We don't do this for iOS, since
925 * iOS devices always have a VFP unit.
927 if (!mono_hwcap_arm_has_vfp)
928 arm_fpu = MONO_ARM_FPU_NONE;
931 * This environment variable can be useful in testing
932 * environments to make sure the soft float fallback
933 * works. Most ARM devices have VFP units these days, so
934 * normally soft float code would not be exercised much.
936 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
938 if (soft && !strncmp (soft, "1", 1))
939 arm_fpu = MONO_ARM_FPU_NONE;
943 v5_supported = mono_hwcap_arm_is_v5;
944 v6_supported = mono_hwcap_arm_is_v6;
945 v7_supported = mono_hwcap_arm_is_v7;
947 #if defined(__APPLE__)
948 /* iOS is special-cased here because we don't yet
949 have a way to properly detect CPU features on it. */
950 thumb_supported = TRUE;
953 thumb_supported = mono_hwcap_arm_has_thumb;
954 thumb2_supported = mono_hwcap_arm_has_thumb2;
957 /* Format: armv(5|6|7[s])[-thumb[2]] */
958 cpu_arch = g_getenv ("MONO_CPU_ARCH");
960 /* Do this here so it overrides any detection. */
962 if (strncmp (cpu_arch, "armv", 4) == 0) {
963 v5_supported = cpu_arch [4] >= '5';
964 v6_supported = cpu_arch [4] >= '6';
965 v7_supported = cpu_arch [4] >= '7';
966 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
967 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
970 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
971 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
976 * Cleanup architecture specific code.
979 mono_arch_cleanup (void)
984 * This function returns the optimizations supported on this cpu.
987 mono_arch_cpu_optimizations (guint32 *exclude_mask)
989 /* no arm-specific optimizations yet */
995 * This function test for all SIMD functions supported.
997 * Returns a bitmask corresponding to all supported versions.
1001 mono_arch_cpu_enumerate_simd_versions (void)
1003 /* SIMD is currently unimplemented */
1011 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1013 if (v7s_supported || v7k_supported) {
1027 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1029 mono_arch_is_soft_float (void)
1031 return arm_fpu == MONO_ARM_FPU_NONE;
1036 mono_arm_is_hard_float (void)
1038 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1042 is_regsize_var (MonoType *t)
1046 t = mini_get_underlying_type (t);
1053 case MONO_TYPE_FNPTR:
1055 case MONO_TYPE_OBJECT:
1056 case MONO_TYPE_STRING:
1057 case MONO_TYPE_CLASS:
1058 case MONO_TYPE_SZARRAY:
1059 case MONO_TYPE_ARRAY:
1061 case MONO_TYPE_GENERICINST:
1062 if (!mono_type_generic_inst_is_valuetype (t))
1065 case MONO_TYPE_VALUETYPE:
1072 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1077 for (i = 0; i < cfg->num_varinfo; i++) {
1078 MonoInst *ins = cfg->varinfo [i];
1079 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1082 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1085 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1088 /* we can only allocate 32 bit values */
1089 if (is_regsize_var (ins->inst_vtype)) {
1090 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1091 g_assert (i == vmv->idx);
1092 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1100 mono_arch_get_global_int_regs (MonoCompile *cfg)
1104 mono_arch_compute_omit_fp (cfg);
1107 * FIXME: Interface calls might go through a static rgctx trampoline which
1108 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1111 if (cfg->flags & MONO_CFG_HAS_CALLS)
1112 cfg->uses_rgctx_reg = TRUE;
1114 if (cfg->arch.omit_fp)
1115 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1116 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1117 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1118 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1120 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1121 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1123 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1124 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1125 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1126 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1127 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1128 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1134 * mono_arch_regalloc_cost:
1136 * Return the cost, in number of memory references, of the action of
1137 * allocating the variable VMV into a register during global register
1141 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1147 #endif /* #ifndef DISABLE_JIT */
1150 mono_arch_flush_icache (guint8 *code, gint size)
1152 #if defined(MONO_CROSS_COMPILE) || defined(__native_client__)
1153 // For Native Client we don't have to flush i-cache here,
1154 // as it's being done by dyncode interface.
1156 sys_icache_invalidate (code, size);
1158 __builtin___clear_cache (code, code + size);
1165 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1168 if (*gr > ARMREG_R3) {
1170 ainfo->offset = *stack_size;
1171 ainfo->reg = ARMREG_SP; /* in the caller */
1172 ainfo->storage = RegTypeBase;
1175 ainfo->storage = RegTypeGeneral;
1182 split = i8_align == 4;
1187 if (*gr == ARMREG_R3 && split) {
1188 /* first word in r3 and the second on the stack */
1189 ainfo->offset = *stack_size;
1190 ainfo->reg = ARMREG_SP; /* in the caller */
1191 ainfo->storage = RegTypeBaseGen;
1193 } else if (*gr >= ARMREG_R3) {
1194 if (eabi_supported) {
1195 /* darwin aligns longs to 4 byte only */
1196 if (i8_align == 8) {
1201 ainfo->offset = *stack_size;
1202 ainfo->reg = ARMREG_SP; /* in the caller */
1203 ainfo->storage = RegTypeBase;
1206 if (eabi_supported) {
1207 if (i8_align == 8 && ((*gr) & 1))
1210 ainfo->storage = RegTypeIRegPair;
1219 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1222 * If we're calling a function like this:
1224 * void foo(float a, double b, float c)
1226 * We pass a in s0 and b in d1. That leaves us
1227 * with s1 being unused. The armhf ABI recognizes
1228 * this and requires register assignment to then
1229 * use that for the next single-precision arg,
1230 * i.e. c in this example. So float_spare either
1231 * tells us which reg to use for the next single-
1232 * precision arg, or it's -1, meaning use *fpr.
1234 * Note that even though most of the JIT speaks
1235 * double-precision, fpr represents single-
1236 * precision registers.
1238 * See parts 5.5 and 6.1.2 of the AAPCS for how
1242 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1243 ainfo->storage = RegTypeFP;
1247 * If we're passing a double-precision value
1248 * and *fpr is odd (e.g. it's s1, s3, ...)
1249 * we need to use the next even register. So
1250 * we mark the current *fpr as a spare that
1251 * can be used for the next single-precision
1255 *float_spare = *fpr;
1260 * At this point, we have an even register
1261 * so we assign that and move along.
1265 } else if (*float_spare >= 0) {
1267 * We're passing a single-precision value
1268 * and it looks like a spare single-
1269 * precision register is available. Let's
1273 ainfo->reg = *float_spare;
1277 * If we hit this branch, we're passing a
1278 * single-precision value and we can simply
1279 * use the next available register.
1287 * We've exhausted available floating point
1288 * regs, so pass the rest on the stack.
1296 ainfo->offset = *stack_size;
1297 ainfo->reg = ARMREG_SP;
1298 ainfo->storage = RegTypeBase;
1305 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1309 MonoClassField *field;
1310 MonoType *ftype, *prev_ftype = NULL;
1313 klass = mono_class_from_mono_type (t);
1315 while ((field = mono_class_get_fields (klass, &iter))) {
1316 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1318 ftype = mono_field_get_type (field);
1319 ftype = mini_get_underlying_type (ftype);
1321 if (MONO_TYPE_ISSTRUCT (ftype)) {
1322 int nested_nfields, nested_esize;
1324 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1326 if (nested_esize == 4)
1327 ftype = &mono_defaults.single_class->byval_arg;
1329 ftype = &mono_defaults.double_class->byval_arg;
1330 if (prev_ftype && prev_ftype->type != ftype->type)
1333 nfields += nested_nfields;
1335 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1337 if (prev_ftype && prev_ftype->type != ftype->type)
1343 if (nfields == 0 || nfields > 4)
1345 *out_nfields = nfields;
1346 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1351 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1353 guint i, gr, fpr, pstart;
1355 int n = sig->hasthis + sig->param_count;
1359 guint32 stack_size = 0;
1361 gboolean is_pinvoke = sig->pinvoke;
1362 gboolean vtype_retaddr = FALSE;
1365 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1367 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1374 t = mini_get_underlying_type (sig->ret);
1385 case MONO_TYPE_FNPTR:
1386 case MONO_TYPE_CLASS:
1387 case MONO_TYPE_OBJECT:
1388 case MONO_TYPE_SZARRAY:
1389 case MONO_TYPE_ARRAY:
1390 case MONO_TYPE_STRING:
1391 cinfo->ret.storage = RegTypeGeneral;
1392 cinfo->ret.reg = ARMREG_R0;
1396 cinfo->ret.storage = RegTypeIRegPair;
1397 cinfo->ret.reg = ARMREG_R0;
1401 cinfo->ret.storage = RegTypeFP;
1403 if (t->type == MONO_TYPE_R4)
1404 cinfo->ret.size = 4;
1406 cinfo->ret.size = 8;
1408 if (IS_HARD_FLOAT) {
1409 cinfo->ret.reg = ARM_VFP_F0;
1411 cinfo->ret.reg = ARMREG_R0;
1414 case MONO_TYPE_GENERICINST:
1415 if (!mono_type_generic_inst_is_valuetype (t)) {
1416 cinfo->ret.storage = RegTypeGeneral;
1417 cinfo->ret.reg = ARMREG_R0;
1420 if (mini_is_gsharedvt_variable_type (t)) {
1421 cinfo->ret.storage = RegTypeStructByAddr;
1425 case MONO_TYPE_VALUETYPE:
1426 case MONO_TYPE_TYPEDBYREF:
1427 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1428 cinfo->ret.storage = RegTypeHFA;
1430 cinfo->ret.nregs = nfields;
1431 cinfo->ret.esize = esize;
1433 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1434 cinfo->ret.storage = RegTypeStructByVal;
1436 cinfo->ret.storage = RegTypeStructByAddr;
1440 case MONO_TYPE_MVAR:
1441 g_assert (mini_is_gsharedvt_type (t));
1442 cinfo->ret.storage = RegTypeStructByAddr;
1444 case MONO_TYPE_VOID:
1447 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1450 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1455 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1456 * the first argument, allowing 'this' to be always passed in the first arg reg.
1457 * Also do this if the first argument is a reference type, since virtual calls
1458 * are sometimes made using calli without sig->hasthis set, like in the delegate
1461 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1463 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1465 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1469 cinfo->ret.reg = gr;
1471 cinfo->vret_arg_index = 1;
1475 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1478 if (vtype_retaddr) {
1479 cinfo->ret.reg = gr;
1484 DEBUG(g_print("params: %d\n", sig->param_count));
1485 for (i = pstart; i < sig->param_count; ++i) {
1486 ArgInfo *ainfo = &cinfo->args [n];
1488 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1489 /* Prevent implicit arguments and sig_cookie from
1490 being passed in registers */
1493 /* Emit the signature cookie just before the implicit arguments */
1494 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1496 DEBUG(g_print("param %d: ", i));
1497 if (sig->params [i]->byref) {
1498 DEBUG(g_print("byref\n"));
1499 add_general (&gr, &stack_size, ainfo, TRUE);
1503 t = mini_get_underlying_type (sig->params [i]);
1507 cinfo->args [n].size = 1;
1508 add_general (&gr, &stack_size, ainfo, TRUE);
1512 cinfo->args [n].size = 2;
1513 add_general (&gr, &stack_size, ainfo, TRUE);
1517 cinfo->args [n].size = 4;
1518 add_general (&gr, &stack_size, ainfo, TRUE);
1523 case MONO_TYPE_FNPTR:
1524 case MONO_TYPE_CLASS:
1525 case MONO_TYPE_OBJECT:
1526 case MONO_TYPE_STRING:
1527 case MONO_TYPE_SZARRAY:
1528 case MONO_TYPE_ARRAY:
1529 cinfo->args [n].size = sizeof (gpointer);
1530 add_general (&gr, &stack_size, ainfo, TRUE);
1532 case MONO_TYPE_GENERICINST:
1533 if (!mono_type_generic_inst_is_valuetype (t)) {
1534 cinfo->args [n].size = sizeof (gpointer);
1535 add_general (&gr, &stack_size, ainfo, TRUE);
1538 if (mini_is_gsharedvt_variable_type (t)) {
1539 /* gsharedvt arguments are passed by ref */
1540 g_assert (mini_is_gsharedvt_type (t));
1541 add_general (&gr, &stack_size, ainfo, TRUE);
1542 switch (ainfo->storage) {
1543 case RegTypeGeneral:
1544 ainfo->storage = RegTypeGSharedVtInReg;
1547 ainfo->storage = RegTypeGSharedVtOnStack;
1550 g_assert_not_reached ();
1555 case MONO_TYPE_TYPEDBYREF:
1556 case MONO_TYPE_VALUETYPE: {
1559 int nwords, nfields, esize;
1562 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1563 if (fpr + nfields < ARM_VFP_F16) {
1564 ainfo->storage = RegTypeHFA;
1566 ainfo->nregs = nfields;
1567 ainfo->esize = esize;
1578 if (t->type == MONO_TYPE_TYPEDBYREF) {
1579 size = sizeof (MonoTypedRef);
1580 align = sizeof (gpointer);
1582 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1584 size = mono_class_native_size (klass, &align);
1586 size = mini_type_stack_size_full (t, &align, FALSE);
1588 DEBUG(g_print ("load %d bytes struct\n", size));
1591 align_size += (sizeof (gpointer) - 1);
1592 align_size &= ~(sizeof (gpointer) - 1);
1593 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1594 ainfo->storage = RegTypeStructByVal;
1595 ainfo->struct_size = size;
1596 /* FIXME: align stack_size if needed */
1597 if (eabi_supported) {
1598 if (align >= 8 && (gr & 1))
1601 if (gr > ARMREG_R3) {
1603 ainfo->vtsize = nwords;
1605 int rest = ARMREG_R3 - gr + 1;
1606 int n_in_regs = rest >= nwords? nwords: rest;
1608 ainfo->size = n_in_regs;
1609 ainfo->vtsize = nwords - n_in_regs;
1612 nwords -= n_in_regs;
1614 if (sig->call_convention == MONO_CALL_VARARG)
1615 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1616 stack_size = ALIGN_TO (stack_size, align);
1617 ainfo->offset = stack_size;
1618 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1619 stack_size += nwords * sizeof (gpointer);
1625 add_general (&gr, &stack_size, ainfo, FALSE);
1631 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1633 add_general (&gr, &stack_size, ainfo, TRUE);
1639 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1641 add_general (&gr, &stack_size, ainfo, FALSE);
1644 case MONO_TYPE_MVAR:
1645 /* gsharedvt arguments are passed by ref */
1646 g_assert (mini_is_gsharedvt_type (t));
1647 add_general (&gr, &stack_size, ainfo, TRUE);
1648 switch (ainfo->storage) {
1649 case RegTypeGeneral:
1650 ainfo->storage = RegTypeGSharedVtInReg;
1653 ainfo->storage = RegTypeGSharedVtOnStack;
1656 g_assert_not_reached ();
1660 g_error ("Can't handle 0x%x", sig->params [i]->type);
1665 /* Handle the case where there are no implicit arguments */
1666 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1667 /* Prevent implicit arguments and sig_cookie from
1668 being passed in registers */
1671 /* Emit the signature cookie just before the implicit arguments */
1672 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1675 /* align stack size to 8 */
1676 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1677 stack_size = (stack_size + 7) & ~7;
1679 cinfo->stack_usage = stack_size;
1685 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1687 MonoType *callee_ret;
1691 c1 = get_call_info (NULL, caller_sig);
1692 c2 = get_call_info (NULL, callee_sig);
1695 * Tail calls with more callee stack usage than the caller cannot be supported, since
1696 * the extra stack space would be left on the stack after the tail call.
1698 res = c1->stack_usage >= c2->stack_usage;
1699 callee_ret = mini_get_underlying_type (callee_sig->ret);
1700 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1701 /* An address on the callee's stack is passed as the first argument */
1704 if (c2->stack_usage > 16 * 4)
1716 debug_omit_fp (void)
1719 return mono_debug_count ();
1726 * mono_arch_compute_omit_fp:
1728 * Determine whenever the frame pointer can be eliminated.
1731 mono_arch_compute_omit_fp (MonoCompile *cfg)
1733 MonoMethodSignature *sig;
1734 MonoMethodHeader *header;
1738 if (cfg->arch.omit_fp_computed)
1741 header = cfg->header;
1743 sig = mono_method_signature (cfg->method);
1745 if (!cfg->arch.cinfo)
1746 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1747 cinfo = cfg->arch.cinfo;
1750 * FIXME: Remove some of the restrictions.
1752 cfg->arch.omit_fp = TRUE;
1753 cfg->arch.omit_fp_computed = TRUE;
1755 if (cfg->disable_omit_fp)
1756 cfg->arch.omit_fp = FALSE;
1757 if (!debug_omit_fp ())
1758 cfg->arch.omit_fp = FALSE;
1760 if (cfg->method->save_lmf)
1761 cfg->arch.omit_fp = FALSE;
1763 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1764 cfg->arch.omit_fp = FALSE;
1765 if (header->num_clauses)
1766 cfg->arch.omit_fp = FALSE;
1767 if (cfg->param_area)
1768 cfg->arch.omit_fp = FALSE;
1769 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1770 cfg->arch.omit_fp = FALSE;
1771 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1772 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1773 cfg->arch.omit_fp = FALSE;
1774 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1775 ArgInfo *ainfo = &cinfo->args [i];
1777 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1779 * The stack offset can only be determined when the frame
1782 cfg->arch.omit_fp = FALSE;
1787 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1788 MonoInst *ins = cfg->varinfo [i];
1791 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1796 * Set var information according to the calling convention. arm version.
1797 * The locals var stuff should most likely be split in another method.
1800 mono_arch_allocate_vars (MonoCompile *cfg)
1802 MonoMethodSignature *sig;
1803 MonoMethodHeader *header;
1806 int i, offset, size, align, curinst;
1811 sig = mono_method_signature (cfg->method);
1813 if (!cfg->arch.cinfo)
1814 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1815 cinfo = cfg->arch.cinfo;
1816 sig_ret = mini_get_underlying_type (sig->ret);
1818 mono_arch_compute_omit_fp (cfg);
1820 if (cfg->arch.omit_fp)
1821 cfg->frame_reg = ARMREG_SP;
1823 cfg->frame_reg = ARMREG_FP;
1825 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1827 /* allow room for the vararg method args: void* and long/double */
1828 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1829 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1831 header = cfg->header;
1833 /* See mono_arch_get_global_int_regs () */
1834 if (cfg->flags & MONO_CFG_HAS_CALLS)
1835 cfg->uses_rgctx_reg = TRUE;
1837 if (cfg->frame_reg != ARMREG_SP)
1838 cfg->used_int_regs |= 1 << cfg->frame_reg;
1840 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1841 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1842 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1846 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1847 if (sig_ret->type != MONO_TYPE_VOID) {
1848 cfg->ret->opcode = OP_REGVAR;
1849 cfg->ret->inst_c0 = ARMREG_R0;
1852 /* local vars are at a positive offset from the stack pointer */
1854 * also note that if the function uses alloca, we use FP
1855 * to point at the local variables.
1857 offset = 0; /* linkage area */
1858 /* align the offset to 16 bytes: not sure this is needed here */
1860 //offset &= ~(8 - 1);
1862 /* add parameter area size for called functions */
1863 offset += cfg->param_area;
1866 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1869 /* allow room to save the return value */
1870 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1873 switch (cinfo->ret.storage) {
1874 case RegTypeStructByVal:
1875 cfg->ret->opcode = OP_REGOFFSET;
1876 cfg->ret->inst_basereg = cfg->frame_reg;
1877 offset += sizeof (gpointer) - 1;
1878 offset &= ~(sizeof (gpointer) - 1);
1879 cfg->ret->inst_offset = - offset;
1880 offset += sizeof(gpointer);
1883 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1884 offset = ALIGN_TO (offset, 8);
1885 cfg->ret->opcode = OP_REGOFFSET;
1886 cfg->ret->inst_basereg = cfg->frame_reg;
1887 cfg->ret->inst_offset = offset;
1891 case RegTypeStructByAddr:
1892 ins = cfg->vret_addr;
1893 offset += sizeof(gpointer) - 1;
1894 offset &= ~(sizeof(gpointer) - 1);
1895 ins->inst_offset = offset;
1896 ins->opcode = OP_REGOFFSET;
1897 ins->inst_basereg = cfg->frame_reg;
1898 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1899 g_print ("vret_addr =");
1900 mono_print_ins (cfg->vret_addr);
1902 offset += sizeof(gpointer);
1908 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1909 if (cfg->arch.seq_point_info_var) {
1912 ins = cfg->arch.seq_point_info_var;
1916 offset += align - 1;
1917 offset &= ~(align - 1);
1918 ins->opcode = OP_REGOFFSET;
1919 ins->inst_basereg = cfg->frame_reg;
1920 ins->inst_offset = offset;
1923 ins = cfg->arch.ss_trigger_page_var;
1926 offset += align - 1;
1927 offset &= ~(align - 1);
1928 ins->opcode = OP_REGOFFSET;
1929 ins->inst_basereg = cfg->frame_reg;
1930 ins->inst_offset = offset;
1934 if (cfg->arch.seq_point_ss_method_var) {
1937 ins = cfg->arch.seq_point_ss_method_var;
1940 offset += align - 1;
1941 offset &= ~(align - 1);
1942 ins->opcode = OP_REGOFFSET;
1943 ins->inst_basereg = cfg->frame_reg;
1944 ins->inst_offset = offset;
1947 ins = cfg->arch.seq_point_bp_method_var;
1950 offset += align - 1;
1951 offset &= ~(align - 1);
1952 ins->opcode = OP_REGOFFSET;
1953 ins->inst_basereg = cfg->frame_reg;
1954 ins->inst_offset = offset;
1958 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1959 /* Allocate a temporary used by the atomic ops */
1963 /* Allocate a local slot to hold the sig cookie address */
1964 offset += align - 1;
1965 offset &= ~(align - 1);
1966 cfg->arch.atomic_tmp_offset = offset;
1969 cfg->arch.atomic_tmp_offset = -1;
1972 cfg->locals_min_stack_offset = offset;
1974 curinst = cfg->locals_start;
1975 for (i = curinst; i < cfg->num_varinfo; ++i) {
1978 ins = cfg->varinfo [i];
1979 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1982 t = ins->inst_vtype;
1983 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1986 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1987 * pinvoke wrappers when they call functions returning structure */
1988 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1989 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1993 size = mono_type_size (t, &align);
1995 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1996 * since it loads/stores misaligned words, which don't do the right thing.
1998 if (align < 4 && size >= 4)
2000 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2001 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2002 offset += align - 1;
2003 offset &= ~(align - 1);
2004 ins->opcode = OP_REGOFFSET;
2005 ins->inst_offset = offset;
2006 ins->inst_basereg = cfg->frame_reg;
2008 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2011 cfg->locals_max_stack_offset = offset;
2015 ins = cfg->args [curinst];
2016 if (ins->opcode != OP_REGVAR) {
2017 ins->opcode = OP_REGOFFSET;
2018 ins->inst_basereg = cfg->frame_reg;
2019 offset += sizeof (gpointer) - 1;
2020 offset &= ~(sizeof (gpointer) - 1);
2021 ins->inst_offset = offset;
2022 offset += sizeof (gpointer);
2027 if (sig->call_convention == MONO_CALL_VARARG) {
2031 /* Allocate a local slot to hold the sig cookie address */
2032 offset += align - 1;
2033 offset &= ~(align - 1);
2034 cfg->sig_cookie = offset;
2038 for (i = 0; i < sig->param_count; ++i) {
2039 ainfo = cinfo->args + i;
2041 ins = cfg->args [curinst];
2043 switch (ainfo->storage) {
2045 offset = ALIGN_TO (offset, 8);
2046 ins->opcode = OP_REGOFFSET;
2047 ins->inst_basereg = cfg->frame_reg;
2048 /* These arguments are saved to the stack in the prolog */
2049 ins->inst_offset = offset;
2050 if (cfg->verbose_level >= 2)
2051 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2059 if (ins->opcode != OP_REGVAR) {
2060 ins->opcode = OP_REGOFFSET;
2061 ins->inst_basereg = cfg->frame_reg;
2062 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2064 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2065 * since it loads/stores misaligned words, which don't do the right thing.
2067 if (align < 4 && size >= 4)
2069 /* The code in the prolog () stores words when storing vtypes received in a register */
2070 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2072 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2073 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2074 offset += align - 1;
2075 offset &= ~(align - 1);
2076 ins->inst_offset = offset;
2082 /* align the offset to 8 bytes */
2083 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2084 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2089 cfg->stack_offset = offset;
2093 mono_arch_create_vars (MonoCompile *cfg)
2095 MonoMethodSignature *sig;
2099 sig = mono_method_signature (cfg->method);
2101 if (!cfg->arch.cinfo)
2102 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2103 cinfo = cfg->arch.cinfo;
2105 if (IS_HARD_FLOAT) {
2106 for (i = 0; i < 2; i++) {
2107 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2108 inst->flags |= MONO_INST_VOLATILE;
2110 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2114 if (cinfo->ret.storage == RegTypeStructByVal)
2115 cfg->ret_var_is_local = TRUE;
2117 if (cinfo->ret.storage == RegTypeStructByAddr) {
2118 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2119 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2120 g_print ("vret_addr = ");
2121 mono_print_ins (cfg->vret_addr);
2125 if (cfg->gen_sdb_seq_points) {
2126 if (cfg->soft_breakpoints) {
2129 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2130 ins->flags |= MONO_INST_VOLATILE;
2131 cfg->arch.seq_point_ss_method_var = ins;
2133 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2134 ins->flags |= MONO_INST_VOLATILE;
2135 cfg->arch.seq_point_bp_method_var = ins;
2137 g_assert (!cfg->compile_aot);
2138 } else if (cfg->compile_aot) {
2139 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2140 ins->flags |= MONO_INST_VOLATILE;
2141 cfg->arch.seq_point_info_var = ins;
2143 /* Allocate a separate variable for this to save 1 load per seq point */
2144 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2145 ins->flags |= MONO_INST_VOLATILE;
2146 cfg->arch.ss_trigger_page_var = ins;
2152 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2154 MonoMethodSignature *tmp_sig;
2157 if (call->tail_call)
2160 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2163 * mono_ArgIterator_Setup assumes the signature cookie is
2164 * passed first and all the arguments which were before it are
2165 * passed on the stack after the signature. So compensate by
2166 * passing a different signature.
2168 tmp_sig = mono_metadata_signature_dup (call->signature);
2169 tmp_sig->param_count -= call->signature->sentinelpos;
2170 tmp_sig->sentinelpos = 0;
2171 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2173 sig_reg = mono_alloc_ireg (cfg);
2174 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2176 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2181 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2186 LLVMCallInfo *linfo;
2188 n = sig->param_count + sig->hasthis;
2190 cinfo = get_call_info (cfg->mempool, sig);
2192 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2195 * LLVM always uses the native ABI while we use our own ABI, the
2196 * only difference is the handling of vtypes:
2197 * - we only pass/receive them in registers in some cases, and only
2198 * in 1 or 2 integer registers.
2200 switch (cinfo->ret.storage) {
2201 case RegTypeGeneral:
2204 case RegTypeIRegPair:
2206 case RegTypeStructByAddr:
2207 /* Vtype returned using a hidden argument */
2208 linfo->ret.storage = LLVMArgVtypeRetAddr;
2209 linfo->vret_arg_index = cinfo->vret_arg_index;
2212 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2213 cfg->disable_llvm = TRUE;
2217 for (i = 0; i < n; ++i) {
2218 ainfo = cinfo->args + i;
2220 linfo->args [i].storage = LLVMArgNone;
2222 switch (ainfo->storage) {
2223 case RegTypeGeneral:
2224 case RegTypeIRegPair:
2226 case RegTypeBaseGen:
2227 linfo->args [i].storage = LLVMArgNormal;
2229 case RegTypeStructByVal:
2230 linfo->args [i].storage = LLVMArgAsIArgs;
2231 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2234 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2235 cfg->disable_llvm = TRUE;
2245 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2248 MonoMethodSignature *sig;
2252 sig = call->signature;
2253 n = sig->param_count + sig->hasthis;
2255 cinfo = get_call_info (cfg->mempool, sig);
2257 switch (cinfo->ret.storage) {
2258 case RegTypeStructByVal:
2259 /* The JIT will transform this into a normal call */
2260 call->vret_in_reg = TRUE;
2264 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2265 * the location pointed to by it after call in emit_move_return_value ().
2267 if (!cfg->arch.vret_addr_loc) {
2268 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2269 /* Prevent it from being register allocated or optimized away */
2270 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2273 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2275 case RegTypeStructByAddr: {
2277 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2278 vtarg->sreg1 = call->vret_var->dreg;
2279 vtarg->dreg = mono_alloc_preg (cfg);
2280 MONO_ADD_INS (cfg->cbb, vtarg);
2282 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2289 for (i = 0; i < n; ++i) {
2290 ArgInfo *ainfo = cinfo->args + i;
2293 if (i >= sig->hasthis)
2294 t = sig->params [i - sig->hasthis];
2296 t = &mono_defaults.int_class->byval_arg;
2297 t = mini_get_underlying_type (t);
2299 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2300 /* Emit the signature cookie just before the implicit arguments */
2301 emit_sig_cookie (cfg, call, cinfo);
2304 in = call->args [i];
2306 switch (ainfo->storage) {
2307 case RegTypeGeneral:
2308 case RegTypeIRegPair:
2309 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2310 MONO_INST_NEW (cfg, ins, OP_MOVE);
2311 ins->dreg = mono_alloc_ireg (cfg);
2312 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2313 MONO_ADD_INS (cfg->cbb, ins);
2314 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2316 MONO_INST_NEW (cfg, ins, OP_MOVE);
2317 ins->dreg = mono_alloc_ireg (cfg);
2318 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2319 MONO_ADD_INS (cfg->cbb, ins);
2320 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2321 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2322 if (ainfo->size == 4) {
2323 if (IS_SOFT_FLOAT) {
2324 /* mono_emit_call_args () have already done the r8->r4 conversion */
2325 /* The converted value is in an int vreg */
2326 MONO_INST_NEW (cfg, ins, OP_MOVE);
2327 ins->dreg = mono_alloc_ireg (cfg);
2328 ins->sreg1 = in->dreg;
2329 MONO_ADD_INS (cfg->cbb, ins);
2330 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2334 cfg->param_area = MAX (cfg->param_area, 8);
2335 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2336 creg = mono_alloc_ireg (cfg);
2337 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2338 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2341 if (IS_SOFT_FLOAT) {
2342 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2343 ins->dreg = mono_alloc_ireg (cfg);
2344 ins->sreg1 = in->dreg;
2345 MONO_ADD_INS (cfg->cbb, ins);
2346 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2348 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2349 ins->dreg = mono_alloc_ireg (cfg);
2350 ins->sreg1 = in->dreg;
2351 MONO_ADD_INS (cfg->cbb, ins);
2352 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2356 cfg->param_area = MAX (cfg->param_area, 8);
2357 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2358 creg = mono_alloc_ireg (cfg);
2359 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2360 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2361 creg = mono_alloc_ireg (cfg);
2362 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2363 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2366 cfg->flags |= MONO_CFG_HAS_FPOUT;
2368 MONO_INST_NEW (cfg, ins, OP_MOVE);
2369 ins->dreg = mono_alloc_ireg (cfg);
2370 ins->sreg1 = in->dreg;
2371 MONO_ADD_INS (cfg->cbb, ins);
2373 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2376 case RegTypeStructByAddr:
2379 /* FIXME: where si the data allocated? */
2380 arg->backend.reg3 = ainfo->reg;
2381 call->used_iregs |= 1 << ainfo->reg;
2382 g_assert_not_reached ();
2385 case RegTypeStructByVal:
2386 case RegTypeGSharedVtInReg:
2387 case RegTypeGSharedVtOnStack:
2389 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2390 ins->opcode = OP_OUTARG_VT;
2391 ins->sreg1 = in->dreg;
2392 ins->klass = in->klass;
2393 ins->inst_p0 = call;
2394 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2395 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2396 mono_call_inst_add_outarg_vt (cfg, call, ins);
2397 MONO_ADD_INS (cfg->cbb, ins);
2400 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2401 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2402 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2403 if (t->type == MONO_TYPE_R8) {
2404 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2407 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2409 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2412 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2415 case RegTypeBaseGen:
2416 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2417 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2418 MONO_INST_NEW (cfg, ins, OP_MOVE);
2419 ins->dreg = mono_alloc_ireg (cfg);
2420 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2421 MONO_ADD_INS (cfg->cbb, ins);
2422 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2423 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2426 /* This should work for soft-float as well */
2428 cfg->param_area = MAX (cfg->param_area, 8);
2429 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2430 creg = mono_alloc_ireg (cfg);
2431 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2432 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2433 creg = mono_alloc_ireg (cfg);
2434 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2435 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2436 cfg->flags |= MONO_CFG_HAS_FPOUT;
2438 g_assert_not_reached ();
2442 int fdreg = mono_alloc_freg (cfg);
2444 if (ainfo->size == 8) {
2445 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2446 ins->sreg1 = in->dreg;
2448 MONO_ADD_INS (cfg->cbb, ins);
2450 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2455 * Mono's register allocator doesn't speak single-precision registers that
2456 * overlap double-precision registers (i.e. armhf). So we have to work around
2457 * the register allocator and load the value from memory manually.
2459 * So we create a variable for the float argument and an instruction to store
2460 * the argument into the variable. We then store the list of these arguments
2461 * in cfg->float_args. This list is then used by emit_float_args later to
2462 * pass the arguments in the various call opcodes.
2464 * This is not very nice, and we should really try to fix the allocator.
2467 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2469 /* Make sure the instruction isn't seen as pointless and removed.
2471 float_arg->flags |= MONO_INST_VOLATILE;
2473 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2475 /* We use the dreg to look up the instruction later. The hreg is used to
2476 * emit the instruction that loads the value into the FP reg.
2478 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2479 fad->vreg = float_arg->dreg;
2480 fad->hreg = ainfo->reg;
2482 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2485 call->used_iregs |= 1 << ainfo->reg;
2486 cfg->flags |= MONO_CFG_HAS_FPOUT;
2490 g_assert_not_reached ();
2494 /* Handle the case where there are no implicit arguments */
2495 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2496 emit_sig_cookie (cfg, call, cinfo);
2498 call->call_info = cinfo;
2499 call->stack_usage = cinfo->stack_usage;
2503 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2509 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2510 ins->dreg = mono_alloc_freg (cfg);
2511 ins->sreg1 = arg->dreg;
2512 MONO_ADD_INS (cfg->cbb, ins);
2513 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2516 g_assert_not_reached ();
2522 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2524 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2526 ArgInfo *ainfo = ins->inst_p1;
2527 int ovf_size = ainfo->vtsize;
2528 int doffset = ainfo->offset;
2529 int struct_size = ainfo->struct_size;
2530 int i, soffset, dreg, tmpreg;
2532 switch (ainfo->storage) {
2533 case RegTypeGSharedVtInReg:
2535 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2537 case RegTypeGSharedVtOnStack:
2538 /* Pass by addr on stack */
2539 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2542 for (i = 0; i < ainfo->nregs; ++i) {
2543 if (ainfo->esize == 4)
2544 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2546 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2547 load->dreg = mono_alloc_freg (cfg);
2548 load->inst_basereg = src->dreg;
2549 load->inst_offset = i * ainfo->esize;
2550 MONO_ADD_INS (cfg->cbb, load);
2552 if (ainfo->esize == 4) {
2555 /* See RegTypeFP in mono_arch_emit_call () */
2556 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2557 float_arg->flags |= MONO_INST_VOLATILE;
2558 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2560 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2561 fad->vreg = float_arg->dreg;
2562 fad->hreg = ainfo->reg + i;
2564 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2566 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2572 for (i = 0; i < ainfo->size; ++i) {
2573 dreg = mono_alloc_ireg (cfg);
2574 switch (struct_size) {
2576 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2579 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2582 tmpreg = mono_alloc_ireg (cfg);
2583 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2584 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2585 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2586 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2587 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2588 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2589 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2592 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2595 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2596 soffset += sizeof (gpointer);
2597 struct_size -= sizeof (gpointer);
2599 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2601 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2607 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2609 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2612 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2615 if (COMPILE_LLVM (cfg)) {
2616 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2618 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2619 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2620 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2621 MONO_ADD_INS (cfg->cbb, ins);
2626 case MONO_ARM_FPU_NONE:
2627 if (ret->type == MONO_TYPE_R8) {
2630 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2631 ins->dreg = cfg->ret->dreg;
2632 ins->sreg1 = val->dreg;
2633 MONO_ADD_INS (cfg->cbb, ins);
2636 if (ret->type == MONO_TYPE_R4) {
2637 /* Already converted to an int in method_to_ir () */
2638 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2642 case MONO_ARM_FPU_VFP:
2643 case MONO_ARM_FPU_VFP_HARD:
2644 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2647 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2648 ins->dreg = cfg->ret->dreg;
2649 ins->sreg1 = val->dreg;
2650 MONO_ADD_INS (cfg->cbb, ins);
2655 g_assert_not_reached ();
2659 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2662 #endif /* #ifndef DISABLE_JIT */
2665 mono_arch_is_inst_imm (gint64 imm)
2671 MonoMethodSignature *sig;
2674 MonoType **param_types;
2678 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2682 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2685 switch (cinfo->ret.storage) {
2687 case RegTypeGeneral:
2688 case RegTypeIRegPair:
2689 case RegTypeStructByAddr:
2700 for (i = 0; i < cinfo->nargs; ++i) {
2701 ArgInfo *ainfo = &cinfo->args [i];
2704 switch (ainfo->storage) {
2705 case RegTypeGeneral:
2706 case RegTypeIRegPair:
2707 case RegTypeBaseGen:
2710 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2713 case RegTypeStructByVal:
2714 if (ainfo->size == 0)
2715 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2717 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2718 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2726 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2727 for (i = 0; i < sig->param_count; ++i) {
2728 MonoType *t = sig->params [i];
2733 t = mini_get_underlying_type (t);
2756 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2758 ArchDynCallInfo *info;
2762 cinfo = get_call_info (NULL, sig);
2764 if (!dyn_call_supported (cinfo, sig)) {
2769 info = g_new0 (ArchDynCallInfo, 1);
2770 // FIXME: Preprocess the info to speed up start_dyn_call ()
2772 info->cinfo = cinfo;
2773 info->rtype = mini_get_underlying_type (sig->ret);
2774 info->param_types = g_new0 (MonoType*, sig->param_count);
2775 for (i = 0; i < sig->param_count; ++i)
2776 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2778 return (MonoDynCallInfo*)info;
2782 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2784 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2786 g_free (ainfo->cinfo);
2791 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2793 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2794 DynCallArgs *p = (DynCallArgs*)buf;
2795 int arg_index, greg, i, j, pindex;
2796 MonoMethodSignature *sig = dinfo->sig;
2798 g_assert (buf_len >= sizeof (DynCallArgs));
2807 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2808 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2813 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2814 p->regs [greg ++] = (mgreg_t)ret;
2816 for (i = pindex; i < sig->param_count; i++) {
2817 MonoType *t = dinfo->param_types [i];
2818 gpointer *arg = args [arg_index ++];
2819 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2822 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2824 } else if (ainfo->storage == RegTypeBase) {
2825 slot = PARAM_REGS + (ainfo->offset / 4);
2826 } else if (ainfo->storage == RegTypeBaseGen) {
2827 /* slot + 1 is the first stack slot, so the code below will work */
2830 g_assert_not_reached ();
2834 p->regs [slot] = (mgreg_t)*arg;
2839 case MONO_TYPE_STRING:
2840 case MONO_TYPE_CLASS:
2841 case MONO_TYPE_ARRAY:
2842 case MONO_TYPE_SZARRAY:
2843 case MONO_TYPE_OBJECT:
2847 p->regs [slot] = (mgreg_t)*arg;
2850 p->regs [slot] = *(guint8*)arg;
2853 p->regs [slot] = *(gint8*)arg;
2856 p->regs [slot] = *(gint16*)arg;
2859 p->regs [slot] = *(guint16*)arg;
2862 p->regs [slot] = *(gint32*)arg;
2865 p->regs [slot] = *(guint32*)arg;
2869 p->regs [slot ++] = (mgreg_t)arg [0];
2870 p->regs [slot] = (mgreg_t)arg [1];
2873 p->regs [slot] = *(mgreg_t*)arg;
2876 p->regs [slot ++] = (mgreg_t)arg [0];
2877 p->regs [slot] = (mgreg_t)arg [1];
2879 case MONO_TYPE_GENERICINST:
2880 if (MONO_TYPE_IS_REFERENCE (t)) {
2881 p->regs [slot] = (mgreg_t)*arg;
2884 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2885 MonoClass *klass = mono_class_from_mono_type (t);
2886 guint8 *nullable_buf;
2889 size = mono_class_value_size (klass, NULL);
2890 nullable_buf = g_alloca (size);
2891 g_assert (nullable_buf);
2893 /* The argument pointed to by arg is either a boxed vtype or null */
2894 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2896 arg = (gpointer*)nullable_buf;
2902 case MONO_TYPE_VALUETYPE:
2903 g_assert (ainfo->storage == RegTypeStructByVal);
2905 if (ainfo->size == 0)
2906 slot = PARAM_REGS + (ainfo->offset / 4);
2910 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2911 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2914 g_assert_not_reached ();
2920 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2922 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2923 MonoType *ptype = ainfo->rtype;
2924 guint8 *ret = ((DynCallArgs*)buf)->ret;
2925 mgreg_t res = ((DynCallArgs*)buf)->res;
2926 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2928 switch (ptype->type) {
2929 case MONO_TYPE_VOID:
2930 *(gpointer*)ret = NULL;
2932 case MONO_TYPE_STRING:
2933 case MONO_TYPE_CLASS:
2934 case MONO_TYPE_ARRAY:
2935 case MONO_TYPE_SZARRAY:
2936 case MONO_TYPE_OBJECT:
2940 *(gpointer*)ret = (gpointer)res;
2946 *(guint8*)ret = res;
2949 *(gint16*)ret = res;
2952 *(guint16*)ret = res;
2955 *(gint32*)ret = res;
2958 *(guint32*)ret = res;
2962 /* This handles endianness as well */
2963 ((gint32*)ret) [0] = res;
2964 ((gint32*)ret) [1] = res2;
2966 case MONO_TYPE_GENERICINST:
2967 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2968 *(gpointer*)ret = (gpointer)res;
2973 case MONO_TYPE_VALUETYPE:
2974 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2979 *(float*)ret = *(float*)&res;
2981 case MONO_TYPE_R8: {
2988 *(double*)ret = *(double*)®s;
2992 g_assert_not_reached ();
2999 * Allow tracing to work with this interface (with an optional argument)
3003 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3007 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3008 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3009 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3010 code = emit_call_reg (code, ARMREG_R2);
3024 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3027 int save_mode = SAVE_NONE;
3029 MonoMethod *method = cfg->method;
3030 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3031 int rtype = ret_type->type;
3032 int save_offset = cfg->param_area;
3036 offset = code - cfg->native_code;
3037 /* we need about 16 instructions */
3038 if (offset > (cfg->code_size - 16 * 4)) {
3039 cfg->code_size *= 2;
3040 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3041 code = cfg->native_code + offset;
3044 case MONO_TYPE_VOID:
3045 /* special case string .ctor icall */
3046 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3047 save_mode = SAVE_ONE;
3049 save_mode = SAVE_NONE;
3053 save_mode = SAVE_TWO;
3057 save_mode = SAVE_ONE_FP;
3059 save_mode = SAVE_ONE;
3063 save_mode = SAVE_TWO_FP;
3065 save_mode = SAVE_TWO;
3067 case MONO_TYPE_GENERICINST:
3068 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3069 save_mode = SAVE_ONE;
3073 case MONO_TYPE_VALUETYPE:
3074 save_mode = SAVE_STRUCT;
3077 save_mode = SAVE_ONE;
3081 switch (save_mode) {
3083 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3084 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3085 if (enable_arguments) {
3086 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3087 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3091 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3092 if (enable_arguments) {
3093 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3097 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3098 if (enable_arguments) {
3099 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3103 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3104 if (enable_arguments) {
3105 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3109 if (enable_arguments) {
3110 /* FIXME: get the actual address */
3111 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3119 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3120 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3121 code = emit_call_reg (code, ARMREG_IP);
3123 switch (save_mode) {
3125 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3126 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3129 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3132 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3135 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3146 * The immediate field for cond branches is big enough for all reasonable methods
3148 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3149 if (0 && ins->inst_true_bb->native_offset) { \
3150 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3152 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3153 ARM_B_COND (code, (condcode), 0); \
3156 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3158 /* emit an exception if condition is fail
3160 * We assign the extra code used to throw the implicit exceptions
3161 * to cfg->bb_exit as far as the big branch handling is concerned
3163 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3165 mono_add_patch_info (cfg, code - cfg->native_code, \
3166 MONO_PATCH_INFO_EXC, exc_name); \
3167 ARM_BL_COND (code, (condcode), 0); \
3170 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3173 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3178 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3182 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3183 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3185 switch (ins->opcode) {
3188 /* Already done by an arch-independent pass */
3190 case OP_LOAD_MEMBASE:
3191 case OP_LOADI4_MEMBASE:
3193 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3194 * OP_LOAD_MEMBASE offset(basereg), reg
3196 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3197 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3198 ins->inst_basereg == last_ins->inst_destbasereg &&
3199 ins->inst_offset == last_ins->inst_offset) {
3200 if (ins->dreg == last_ins->sreg1) {
3201 MONO_DELETE_INS (bb, ins);
3204 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3205 ins->opcode = OP_MOVE;
3206 ins->sreg1 = last_ins->sreg1;
3210 * Note: reg1 must be different from the basereg in the second load
3211 * OP_LOAD_MEMBASE offset(basereg), reg1
3212 * OP_LOAD_MEMBASE offset(basereg), reg2
3214 * OP_LOAD_MEMBASE offset(basereg), reg1
3215 * OP_MOVE reg1, reg2
3217 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3218 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3219 ins->inst_basereg != last_ins->dreg &&
3220 ins->inst_basereg == last_ins->inst_basereg &&
3221 ins->inst_offset == last_ins->inst_offset) {
3223 if (ins->dreg == last_ins->dreg) {
3224 MONO_DELETE_INS (bb, ins);
3227 ins->opcode = OP_MOVE;
3228 ins->sreg1 = last_ins->dreg;
3231 //g_assert_not_reached ();
3235 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3236 * OP_LOAD_MEMBASE offset(basereg), reg
3238 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3239 * OP_ICONST reg, imm
3241 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3242 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3243 ins->inst_basereg == last_ins->inst_destbasereg &&
3244 ins->inst_offset == last_ins->inst_offset) {
3245 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3246 ins->opcode = OP_ICONST;
3247 ins->inst_c0 = last_ins->inst_imm;
3248 g_assert_not_reached (); // check this rule
3252 case OP_LOADU1_MEMBASE:
3253 case OP_LOADI1_MEMBASE:
3254 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3255 ins->inst_basereg == last_ins->inst_destbasereg &&
3256 ins->inst_offset == last_ins->inst_offset) {
3257 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3258 ins->sreg1 = last_ins->sreg1;
3261 case OP_LOADU2_MEMBASE:
3262 case OP_LOADI2_MEMBASE:
3263 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3264 ins->inst_basereg == last_ins->inst_destbasereg &&
3265 ins->inst_offset == last_ins->inst_offset) {
3266 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3267 ins->sreg1 = last_ins->sreg1;
3271 ins->opcode = OP_MOVE;
3275 if (ins->dreg == ins->sreg1) {
3276 MONO_DELETE_INS (bb, ins);
3280 * OP_MOVE sreg, dreg
3281 * OP_MOVE dreg, sreg
3283 if (last_ins && last_ins->opcode == OP_MOVE &&
3284 ins->sreg1 == last_ins->dreg &&
3285 ins->dreg == last_ins->sreg1) {
3286 MONO_DELETE_INS (bb, ins);
3295 * the branch_cc_table should maintain the order of these
3309 branch_cc_table [] = {
3323 #define ADD_NEW_INS(cfg,dest,op) do { \
3324 MONO_INST_NEW ((cfg), (dest), (op)); \
3325 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3329 map_to_reg_reg_op (int op)
3338 case OP_COMPARE_IMM:
3340 case OP_ICOMPARE_IMM:
3354 case OP_LOAD_MEMBASE:
3355 return OP_LOAD_MEMINDEX;
3356 case OP_LOADI4_MEMBASE:
3357 return OP_LOADI4_MEMINDEX;
3358 case OP_LOADU4_MEMBASE:
3359 return OP_LOADU4_MEMINDEX;
3360 case OP_LOADU1_MEMBASE:
3361 return OP_LOADU1_MEMINDEX;
3362 case OP_LOADI2_MEMBASE:
3363 return OP_LOADI2_MEMINDEX;
3364 case OP_LOADU2_MEMBASE:
3365 return OP_LOADU2_MEMINDEX;
3366 case OP_LOADI1_MEMBASE:
3367 return OP_LOADI1_MEMINDEX;
3368 case OP_STOREI1_MEMBASE_REG:
3369 return OP_STOREI1_MEMINDEX;
3370 case OP_STOREI2_MEMBASE_REG:
3371 return OP_STOREI2_MEMINDEX;
3372 case OP_STOREI4_MEMBASE_REG:
3373 return OP_STOREI4_MEMINDEX;
3374 case OP_STORE_MEMBASE_REG:
3375 return OP_STORE_MEMINDEX;
3376 case OP_STORER4_MEMBASE_REG:
3377 return OP_STORER4_MEMINDEX;
3378 case OP_STORER8_MEMBASE_REG:
3379 return OP_STORER8_MEMINDEX;
3380 case OP_STORE_MEMBASE_IMM:
3381 return OP_STORE_MEMBASE_REG;
3382 case OP_STOREI1_MEMBASE_IMM:
3383 return OP_STOREI1_MEMBASE_REG;
3384 case OP_STOREI2_MEMBASE_IMM:
3385 return OP_STOREI2_MEMBASE_REG;
3386 case OP_STOREI4_MEMBASE_IMM:
3387 return OP_STOREI4_MEMBASE_REG;
3389 g_assert_not_reached ();
3393 * Remove from the instruction list the instructions that can't be
3394 * represented with very simple instructions with no register
3398 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3400 MonoInst *ins, *temp, *last_ins = NULL;
3401 int rot_amount, imm8, low_imm;
3403 MONO_BB_FOR_EACH_INS (bb, ins) {
3405 switch (ins->opcode) {
3409 case OP_COMPARE_IMM:
3410 case OP_ICOMPARE_IMM:
3424 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3425 int opcode2 = mono_op_imm_to_op (ins->opcode);
3426 ADD_NEW_INS (cfg, temp, OP_ICONST);
3427 temp->inst_c0 = ins->inst_imm;
3428 temp->dreg = mono_alloc_ireg (cfg);
3429 ins->sreg2 = temp->dreg;
3431 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3432 ins->opcode = opcode2;
3434 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3440 if (ins->inst_imm == 1) {
3441 ins->opcode = OP_MOVE;
3444 if (ins->inst_imm == 0) {
3445 ins->opcode = OP_ICONST;
3449 imm8 = mono_is_power_of_two (ins->inst_imm);
3451 ins->opcode = OP_SHL_IMM;
3452 ins->inst_imm = imm8;
3455 ADD_NEW_INS (cfg, temp, OP_ICONST);
3456 temp->inst_c0 = ins->inst_imm;
3457 temp->dreg = mono_alloc_ireg (cfg);
3458 ins->sreg2 = temp->dreg;
3459 ins->opcode = OP_IMUL;
3465 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3466 /* ARM sets the C flag to 1 if there was _no_ overflow */
3467 ins->next->opcode = OP_COND_EXC_NC;
3470 case OP_IDIV_UN_IMM:
3472 case OP_IREM_UN_IMM: {
3473 int opcode2 = mono_op_imm_to_op (ins->opcode);
3474 ADD_NEW_INS (cfg, temp, OP_ICONST);
3475 temp->inst_c0 = ins->inst_imm;
3476 temp->dreg = mono_alloc_ireg (cfg);
3477 ins->sreg2 = temp->dreg;
3479 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3480 ins->opcode = opcode2;
3483 case OP_LOCALLOC_IMM:
3484 ADD_NEW_INS (cfg, temp, OP_ICONST);
3485 temp->inst_c0 = ins->inst_imm;
3486 temp->dreg = mono_alloc_ireg (cfg);
3487 ins->sreg1 = temp->dreg;
3488 ins->opcode = OP_LOCALLOC;
3490 case OP_LOAD_MEMBASE:
3491 case OP_LOADI4_MEMBASE:
3492 case OP_LOADU4_MEMBASE:
3493 case OP_LOADU1_MEMBASE:
3494 /* we can do two things: load the immed in a register
3495 * and use an indexed load, or see if the immed can be
3496 * represented as an ad_imm + a load with a smaller offset
3497 * that fits. We just do the first for now, optimize later.
3499 if (arm_is_imm12 (ins->inst_offset))
3501 ADD_NEW_INS (cfg, temp, OP_ICONST);
3502 temp->inst_c0 = ins->inst_offset;
3503 temp->dreg = mono_alloc_ireg (cfg);
3504 ins->sreg2 = temp->dreg;
3505 ins->opcode = map_to_reg_reg_op (ins->opcode);
3507 case OP_LOADI2_MEMBASE:
3508 case OP_LOADU2_MEMBASE:
3509 case OP_LOADI1_MEMBASE:
3510 if (arm_is_imm8 (ins->inst_offset))
3512 ADD_NEW_INS (cfg, temp, OP_ICONST);
3513 temp->inst_c0 = ins->inst_offset;
3514 temp->dreg = mono_alloc_ireg (cfg);
3515 ins->sreg2 = temp->dreg;
3516 ins->opcode = map_to_reg_reg_op (ins->opcode);
3518 case OP_LOADR4_MEMBASE:
3519 case OP_LOADR8_MEMBASE:
3520 if (arm_is_fpimm8 (ins->inst_offset))
3522 low_imm = ins->inst_offset & 0x1ff;
3523 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3524 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3525 temp->inst_imm = ins->inst_offset & ~0x1ff;
3526 temp->sreg1 = ins->inst_basereg;
3527 temp->dreg = mono_alloc_ireg (cfg);
3528 ins->inst_basereg = temp->dreg;
3529 ins->inst_offset = low_imm;
3533 ADD_NEW_INS (cfg, temp, OP_ICONST);
3534 temp->inst_c0 = ins->inst_offset;
3535 temp->dreg = mono_alloc_ireg (cfg);
3537 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3538 add_ins->sreg1 = ins->inst_basereg;
3539 add_ins->sreg2 = temp->dreg;
3540 add_ins->dreg = mono_alloc_ireg (cfg);
3542 ins->inst_basereg = add_ins->dreg;
3543 ins->inst_offset = 0;
3546 case OP_STORE_MEMBASE_REG:
3547 case OP_STOREI4_MEMBASE_REG:
3548 case OP_STOREI1_MEMBASE_REG:
3549 if (arm_is_imm12 (ins->inst_offset))
3551 ADD_NEW_INS (cfg, temp, OP_ICONST);
3552 temp->inst_c0 = ins->inst_offset;
3553 temp->dreg = mono_alloc_ireg (cfg);
3554 ins->sreg2 = temp->dreg;
3555 ins->opcode = map_to_reg_reg_op (ins->opcode);
3557 case OP_STOREI2_MEMBASE_REG:
3558 if (arm_is_imm8 (ins->inst_offset))
3560 ADD_NEW_INS (cfg, temp, OP_ICONST);
3561 temp->inst_c0 = ins->inst_offset;
3562 temp->dreg = mono_alloc_ireg (cfg);
3563 ins->sreg2 = temp->dreg;
3564 ins->opcode = map_to_reg_reg_op (ins->opcode);
3566 case OP_STORER4_MEMBASE_REG:
3567 case OP_STORER8_MEMBASE_REG:
3568 if (arm_is_fpimm8 (ins->inst_offset))
3570 low_imm = ins->inst_offset & 0x1ff;
3571 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3572 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3573 temp->inst_imm = ins->inst_offset & ~0x1ff;
3574 temp->sreg1 = ins->inst_destbasereg;
3575 temp->dreg = mono_alloc_ireg (cfg);
3576 ins->inst_destbasereg = temp->dreg;
3577 ins->inst_offset = low_imm;
3581 ADD_NEW_INS (cfg, temp, OP_ICONST);
3582 temp->inst_c0 = ins->inst_offset;
3583 temp->dreg = mono_alloc_ireg (cfg);
3585 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3586 add_ins->sreg1 = ins->inst_destbasereg;
3587 add_ins->sreg2 = temp->dreg;
3588 add_ins->dreg = mono_alloc_ireg (cfg);
3590 ins->inst_destbasereg = add_ins->dreg;
3591 ins->inst_offset = 0;
3594 case OP_STORE_MEMBASE_IMM:
3595 case OP_STOREI1_MEMBASE_IMM:
3596 case OP_STOREI2_MEMBASE_IMM:
3597 case OP_STOREI4_MEMBASE_IMM:
3598 ADD_NEW_INS (cfg, temp, OP_ICONST);
3599 temp->inst_c0 = ins->inst_imm;
3600 temp->dreg = mono_alloc_ireg (cfg);
3601 ins->sreg1 = temp->dreg;
3602 ins->opcode = map_to_reg_reg_op (ins->opcode);
3604 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3607 gboolean swap = FALSE;
3611 /* Optimized away */
3616 /* Some fp compares require swapped operands */
3617 switch (ins->next->opcode) {
3619 ins->next->opcode = OP_FBLT;
3623 ins->next->opcode = OP_FBLT_UN;
3627 ins->next->opcode = OP_FBGE;
3631 ins->next->opcode = OP_FBGE_UN;
3639 ins->sreg1 = ins->sreg2;
3648 bb->last_ins = last_ins;
3649 bb->max_vreg = cfg->next_vreg;
3653 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3657 if (long_ins->opcode == OP_LNEG) {
3659 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3660 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3666 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3668 /* sreg is a float, dreg is an integer reg */
3670 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3672 ARM_TOSIZD (code, vfp_scratch1, sreg);
3674 ARM_TOUIZD (code, vfp_scratch1, sreg);
3675 ARM_FMRS (code, dreg, vfp_scratch1);
3676 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3680 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3681 else if (size == 2) {
3682 ARM_SHL_IMM (code, dreg, dreg, 16);
3683 ARM_SHR_IMM (code, dreg, dreg, 16);
3687 ARM_SHL_IMM (code, dreg, dreg, 24);
3688 ARM_SAR_IMM (code, dreg, dreg, 24);
3689 } else if (size == 2) {
3690 ARM_SHL_IMM (code, dreg, dreg, 16);
3691 ARM_SAR_IMM (code, dreg, dreg, 16);
3698 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3700 /* sreg is a float, dreg is an integer reg */
3702 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3704 ARM_TOSIZS (code, vfp_scratch1, sreg);
3706 ARM_TOUIZS (code, vfp_scratch1, sreg);
3707 ARM_FMRS (code, dreg, vfp_scratch1);
3708 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3712 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3713 else if (size == 2) {
3714 ARM_SHL_IMM (code, dreg, dreg, 16);
3715 ARM_SHR_IMM (code, dreg, dreg, 16);
3719 ARM_SHL_IMM (code, dreg, dreg, 24);
3720 ARM_SAR_IMM (code, dreg, dreg, 24);
3721 } else if (size == 2) {
3722 ARM_SHL_IMM (code, dreg, dreg, 16);
3723 ARM_SAR_IMM (code, dreg, dreg, 16);
3729 #endif /* #ifndef DISABLE_JIT */
3731 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3734 emit_thunk (guint8 *code, gconstpointer target)
3738 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3739 if (thumb_supported)
3740 ARM_BX (code, ARMREG_IP);
3742 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3743 *(guint32*)code = (guint32)target;
3745 mono_arch_flush_icache (p, code - p);
3749 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3751 MonoJitInfo *ji = NULL;
3752 MonoThunkJitInfo *info;
3755 guint8 *orig_target;
3756 guint8 *target_thunk;
3759 domain = mono_domain_get ();
3763 * This can be called multiple times during JITting,
3764 * save the current position in cfg->arch to avoid
3765 * doing a O(n^2) search.
3767 if (!cfg->arch.thunks) {
3768 cfg->arch.thunks = cfg->thunks;
3769 cfg->arch.thunks_size = cfg->thunk_area;
3771 thunks = cfg->arch.thunks;
3772 thunks_size = cfg->arch.thunks_size;
3774 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3775 g_assert_not_reached ();
3778 g_assert (*(guint32*)thunks == 0);
3779 emit_thunk (thunks, target);
3780 arm_patch (code, thunks);
3782 cfg->arch.thunks += THUNK_SIZE;
3783 cfg->arch.thunks_size -= THUNK_SIZE;
3785 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3787 info = mono_jit_info_get_thunk_info (ji);
3790 thunks = (guint8*)ji->code_start + info->thunks_offset;
3791 thunks_size = info->thunks_size;
3793 orig_target = mono_arch_get_call_target (code + 4);
3795 mono_mini_arch_lock ();
3797 target_thunk = NULL;
3798 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3799 /* The call already points to a thunk, because of trampolines etc. */
3800 target_thunk = orig_target;
3802 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3803 if (((guint32*)p) [0] == 0) {
3807 } else if (((guint32*)p) [2] == (guint32)target) {
3808 /* Thunk already points to target */
3815 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3817 if (!target_thunk) {
3818 mono_mini_arch_unlock ();
3819 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3820 g_assert_not_reached ();
3823 emit_thunk (target_thunk, target);
3824 arm_patch (code, target_thunk);
3825 mono_arch_flush_icache (code, 4);
3827 mono_mini_arch_unlock ();
3832 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3834 guint32 *code32 = (void*)code;
3835 guint32 ins = *code32;
3836 guint32 prim = (ins >> 25) & 7;
3837 guint32 tval = GPOINTER_TO_UINT (target);
3839 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3840 if (prim == 5) { /* 101b */
3841 /* the diff starts 8 bytes from the branch opcode */
3842 gint diff = target - code - 8;
3844 gint tmask = 0xffffffff;
3845 if (tval & 1) { /* entering thumb mode */
3846 diff = target - 1 - code - 8;
3847 g_assert (thumb_supported);
3848 tbits = 0xf << 28; /* bl->blx bit pattern */
3849 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3850 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3854 tmask = ~(1 << 24); /* clear the link bit */
3855 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3860 if (diff <= 33554431) {
3862 ins = (ins & 0xff000000) | diff;
3864 *code32 = ins | tbits;
3868 /* diff between 0 and -33554432 */
3869 if (diff >= -33554432) {
3871 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3873 *code32 = ins | tbits;
3878 handle_thunk (cfg, domain, code, target);
3882 #ifdef USE_JUMP_TABLES
3884 gpointer *jte = mono_jumptable_get_entry (code);
3886 jte [0] = (gpointer) target;
3890 * The alternative call sequences looks like this:
3892 * ldr ip, [pc] // loads the address constant
3893 * b 1f // jumps around the constant
3894 * address constant embedded in the code
3899 * There are two cases for patching:
3900 * a) at the end of method emission: in this case code points to the start
3901 * of the call sequence
3902 * b) during runtime patching of the call site: in this case code points
3903 * to the mov pc, ip instruction
3905 * We have to handle also the thunk jump code sequence:
3909 * address constant // execution never reaches here
3911 if ((ins & 0x0ffffff0) == 0x12fff10) {
3912 /* Branch and exchange: the address is constructed in a reg
3913 * We can patch BX when the code sequence is the following:
3914 * ldr ip, [pc, #0] ; 0x8
3921 guint8 *emit = (guint8*)ccode;
3922 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3924 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3925 ARM_BX (emit, ARMREG_IP);
3927 /*patching from magic trampoline*/
3928 if (ins == ccode [3]) {
3929 g_assert (code32 [-4] == ccode [0]);
3930 g_assert (code32 [-3] == ccode [1]);
3931 g_assert (code32 [-1] == ccode [2]);
3932 code32 [-2] = (guint32)target;
3935 /*patching from JIT*/
3936 if (ins == ccode [0]) {
3937 g_assert (code32 [1] == ccode [1]);
3938 g_assert (code32 [3] == ccode [2]);
3939 g_assert (code32 [4] == ccode [3]);
3940 code32 [2] = (guint32)target;
3943 g_assert_not_reached ();
3944 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3952 guint8 *emit = (guint8*)ccode;
3953 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3955 ARM_BLX_REG (emit, ARMREG_IP);
3957 g_assert (code32 [-3] == ccode [0]);
3958 g_assert (code32 [-2] == ccode [1]);
3959 g_assert (code32 [0] == ccode [2]);
3961 code32 [-1] = (guint32)target;
3964 guint32 *tmp = ccode;
3965 guint8 *emit = (guint8*)tmp;
3966 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3967 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3968 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3969 ARM_BX (emit, ARMREG_IP);
3970 if (ins == ccode [2]) {
3971 g_assert_not_reached (); // should be -2 ...
3972 code32 [-1] = (guint32)target;
3975 if (ins == ccode [0]) {
3976 /* handles both thunk jump code and the far call sequence */
3977 code32 [2] = (guint32)target;
3980 g_assert_not_reached ();
3982 // g_print ("patched with 0x%08x\n", ins);
3987 arm_patch (guchar *code, const guchar *target)
3989 arm_patch_general (NULL, NULL, code, target);
3993 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3994 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3995 * to be used with the emit macros.
3996 * Return -1 otherwise.
3999 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4002 for (i = 0; i < 31; i+= 2) {
4003 res = (val << (32 - i)) | (val >> i);
4006 *rot_amount = i? 32 - i: 0;
4013 * Emits in code a sequence of instructions that load the value 'val'
4014 * into the dreg register. Uses at most 4 instructions.
4017 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4019 int imm8, rot_amount;
4021 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4022 /* skip the constant pool */
4028 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4029 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4030 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4034 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4035 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4036 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4037 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4040 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4042 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4046 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4048 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4050 if (val & 0xFF0000) {
4051 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4053 if (val & 0xFF000000) {
4054 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4056 } else if (val & 0xFF00) {
4057 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4058 if (val & 0xFF0000) {
4059 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4061 if (val & 0xFF000000) {
4062 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4064 } else if (val & 0xFF0000) {
4065 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4066 if (val & 0xFF000000) {
4067 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4070 //g_assert_not_reached ();
4076 mono_arm_thumb_supported (void)
4078 return thumb_supported;
4084 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4089 call = (MonoCallInst*)ins;
4090 cinfo = call->call_info;
4092 switch (cinfo->ret.storage) {
4094 MonoInst *loc = cfg->arch.vret_addr_loc;
4097 /* Load the destination address */
4098 g_assert (loc && loc->opcode == OP_REGOFFSET);
4100 if (arm_is_imm12 (loc->inst_offset)) {
4101 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4103 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4104 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4106 for (i = 0; i < cinfo->ret.nregs; ++i) {
4107 if (cinfo->ret.esize == 4)
4108 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4110 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4118 switch (ins->opcode) {
4121 case OP_FCALL_MEMBASE:
4123 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4124 if (sig_ret->type == MONO_TYPE_R4) {
4125 if (IS_HARD_FLOAT) {
4126 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4128 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4129 ARM_CVTS (code, ins->dreg, ins->dreg);
4132 if (IS_HARD_FLOAT) {
4133 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4135 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4142 case OP_RCALL_MEMBASE: {
4147 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4148 g_assert (sig_ret->type == MONO_TYPE_R4);
4149 if (IS_HARD_FLOAT) {
4150 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4152 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4153 ARM_CPYS (code, ins->dreg, ins->dreg);
4165 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4170 guint8 *code = cfg->native_code + cfg->code_len;
4171 MonoInst *last_ins = NULL;
4172 guint last_offset = 0;
4174 int imm8, rot_amount;
4176 /* we don't align basic blocks of loops on arm */
4178 if (cfg->verbose_level > 2)
4179 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4181 cpos = bb->max_offset;
4183 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4184 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4185 //g_assert (!mono_compile_aot);
4188 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4189 /* this is not thread save, but good enough */
4190 /* fixme: howto handle overflows? */
4191 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4194 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4195 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4196 (gpointer)"mono_break");
4197 code = emit_call_seq (cfg, code);
4200 MONO_BB_FOR_EACH_INS (bb, ins) {
4201 offset = code - cfg->native_code;
4203 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4205 if (offset > (cfg->code_size - max_len - 16)) {
4206 cfg->code_size *= 2;
4207 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4208 code = cfg->native_code + offset;
4210 // if (ins->cil_code)
4211 // g_print ("cil code\n");
4212 mono_debug_record_line_number (cfg, ins, offset);
4214 switch (ins->opcode) {
4215 case OP_MEMORY_BARRIER:
4217 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4218 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4222 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4224 case OP_TLS_GET_REG:
4225 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4228 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4230 case OP_TLS_SET_REG:
4231 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4233 case OP_ATOMIC_EXCHANGE_I4:
4234 case OP_ATOMIC_CAS_I4:
4235 case OP_ATOMIC_ADD_I4: {
4239 g_assert (v7_supported);
4242 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4244 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4246 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4250 g_assert (cfg->arch.atomic_tmp_offset != -1);
4251 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4253 switch (ins->opcode) {
4254 case OP_ATOMIC_EXCHANGE_I4:
4256 ARM_DMB (code, ARM_DMB_SY);
4257 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4258 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4259 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4261 ARM_B_COND (code, ARMCOND_NE, 0);
4262 arm_patch (buf [1], buf [0]);
4264 case OP_ATOMIC_CAS_I4:
4265 ARM_DMB (code, ARM_DMB_SY);
4267 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4268 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4270 ARM_B_COND (code, ARMCOND_NE, 0);
4271 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4272 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4274 ARM_B_COND (code, ARMCOND_NE, 0);
4275 arm_patch (buf [2], buf [0]);
4276 arm_patch (buf [1], code);
4278 case OP_ATOMIC_ADD_I4:
4280 ARM_DMB (code, ARM_DMB_SY);
4281 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4282 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4283 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4284 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4286 ARM_B_COND (code, ARMCOND_NE, 0);
4287 arm_patch (buf [1], buf [0]);
4290 g_assert_not_reached ();
4293 ARM_DMB (code, ARM_DMB_SY);
4294 if (tmpreg != ins->dreg)
4295 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4296 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4299 case OP_ATOMIC_LOAD_I1:
4300 case OP_ATOMIC_LOAD_U1:
4301 case OP_ATOMIC_LOAD_I2:
4302 case OP_ATOMIC_LOAD_U2:
4303 case OP_ATOMIC_LOAD_I4:
4304 case OP_ATOMIC_LOAD_U4:
4305 case OP_ATOMIC_LOAD_R4:
4306 case OP_ATOMIC_LOAD_R8: {
4307 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4308 ARM_DMB (code, ARM_DMB_SY);
4310 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4312 switch (ins->opcode) {
4313 case OP_ATOMIC_LOAD_I1:
4314 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4316 case OP_ATOMIC_LOAD_U1:
4317 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4319 case OP_ATOMIC_LOAD_I2:
4320 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4322 case OP_ATOMIC_LOAD_U2:
4323 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4325 case OP_ATOMIC_LOAD_I4:
4326 case OP_ATOMIC_LOAD_U4:
4327 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4329 case OP_ATOMIC_LOAD_R4:
4331 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4332 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4334 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4335 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4336 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4337 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4338 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4341 case OP_ATOMIC_LOAD_R8:
4342 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4343 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4347 ARM_DMB (code, ARM_DMB_SY);
4350 case OP_ATOMIC_STORE_I1:
4351 case OP_ATOMIC_STORE_U1:
4352 case OP_ATOMIC_STORE_I2:
4353 case OP_ATOMIC_STORE_U2:
4354 case OP_ATOMIC_STORE_I4:
4355 case OP_ATOMIC_STORE_U4:
4356 case OP_ATOMIC_STORE_R4:
4357 case OP_ATOMIC_STORE_R8: {
4358 ARM_DMB (code, ARM_DMB_SY);
4360 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4362 switch (ins->opcode) {
4363 case OP_ATOMIC_STORE_I1:
4364 case OP_ATOMIC_STORE_U1:
4365 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4367 case OP_ATOMIC_STORE_I2:
4368 case OP_ATOMIC_STORE_U2:
4369 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4371 case OP_ATOMIC_STORE_I4:
4372 case OP_ATOMIC_STORE_U4:
4373 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4375 case OP_ATOMIC_STORE_R4:
4377 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4378 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4380 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4381 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4382 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4383 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4384 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4387 case OP_ATOMIC_STORE_R8:
4388 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4389 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4393 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4394 ARM_DMB (code, ARM_DMB_SY);
4398 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4399 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4402 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4403 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4405 case OP_STOREI1_MEMBASE_IMM:
4406 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4407 g_assert (arm_is_imm12 (ins->inst_offset));
4408 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4410 case OP_STOREI2_MEMBASE_IMM:
4411 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4412 g_assert (arm_is_imm8 (ins->inst_offset));
4413 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4415 case OP_STORE_MEMBASE_IMM:
4416 case OP_STOREI4_MEMBASE_IMM:
4417 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4418 g_assert (arm_is_imm12 (ins->inst_offset));
4419 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4421 case OP_STOREI1_MEMBASE_REG:
4422 g_assert (arm_is_imm12 (ins->inst_offset));
4423 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4425 case OP_STOREI2_MEMBASE_REG:
4426 g_assert (arm_is_imm8 (ins->inst_offset));
4427 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4429 case OP_STORE_MEMBASE_REG:
4430 case OP_STOREI4_MEMBASE_REG:
4431 /* this case is special, since it happens for spill code after lowering has been called */
4432 if (arm_is_imm12 (ins->inst_offset)) {
4433 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4435 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4436 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4439 case OP_STOREI1_MEMINDEX:
4440 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4442 case OP_STOREI2_MEMINDEX:
4443 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4445 case OP_STORE_MEMINDEX:
4446 case OP_STOREI4_MEMINDEX:
4447 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4450 g_assert_not_reached ();
4452 case OP_LOAD_MEMINDEX:
4453 case OP_LOADI4_MEMINDEX:
4454 case OP_LOADU4_MEMINDEX:
4455 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4457 case OP_LOADI1_MEMINDEX:
4458 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4460 case OP_LOADU1_MEMINDEX:
4461 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4463 case OP_LOADI2_MEMINDEX:
4464 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4466 case OP_LOADU2_MEMINDEX:
4467 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4469 case OP_LOAD_MEMBASE:
4470 case OP_LOADI4_MEMBASE:
4471 case OP_LOADU4_MEMBASE:
4472 /* this case is special, since it happens for spill code after lowering has been called */
4473 if (arm_is_imm12 (ins->inst_offset)) {
4474 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4476 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4477 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4480 case OP_LOADI1_MEMBASE:
4481 g_assert (arm_is_imm8 (ins->inst_offset));
4482 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4484 case OP_LOADU1_MEMBASE:
4485 g_assert (arm_is_imm12 (ins->inst_offset));
4486 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4488 case OP_LOADU2_MEMBASE:
4489 g_assert (arm_is_imm8 (ins->inst_offset));
4490 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4492 case OP_LOADI2_MEMBASE:
4493 g_assert (arm_is_imm8 (ins->inst_offset));
4494 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4496 case OP_ICONV_TO_I1:
4497 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4498 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4500 case OP_ICONV_TO_I2:
4501 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4502 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4504 case OP_ICONV_TO_U1:
4505 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4507 case OP_ICONV_TO_U2:
4508 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4509 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4513 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4515 case OP_COMPARE_IMM:
4516 case OP_ICOMPARE_IMM:
4517 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4518 g_assert (imm8 >= 0);
4519 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4523 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4524 * So instead of emitting a trap, we emit a call a C function and place a
4527 //*(int*)code = 0xef9f0001;
4530 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4531 (gpointer)"mono_break");
4532 code = emit_call_seq (cfg, code);
4534 case OP_RELAXED_NOP:
4539 case OP_DUMMY_STORE:
4540 case OP_DUMMY_ICONST:
4541 case OP_DUMMY_R8CONST:
4542 case OP_NOT_REACHED:
4545 case OP_IL_SEQ_POINT:
4546 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4548 case OP_SEQ_POINT: {
4550 MonoInst *info_var = cfg->arch.seq_point_info_var;
4551 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4552 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4553 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4555 int dreg = ARMREG_LR;
4557 if (cfg->soft_breakpoints) {
4558 g_assert (!cfg->compile_aot);
4562 * For AOT, we use one got slot per method, which will point to a
4563 * SeqPointInfo structure, containing all the information required
4564 * by the code below.
4566 if (cfg->compile_aot) {
4567 g_assert (info_var);
4568 g_assert (info_var->opcode == OP_REGOFFSET);
4569 g_assert (arm_is_imm12 (info_var->inst_offset));
4572 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4574 * Read from the single stepping trigger page. This will cause a
4575 * SIGSEGV when single stepping is enabled.
4576 * We do this _before_ the breakpoint, so single stepping after
4577 * a breakpoint is hit will step to the next IL offset.
4579 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4582 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4583 if (cfg->soft_breakpoints) {
4584 /* Load the address of the sequence point method variable. */
4585 var = ss_method_var;
4587 g_assert (var->opcode == OP_REGOFFSET);
4588 g_assert (arm_is_imm12 (var->inst_offset));
4589 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4591 /* Read the value and check whether it is non-zero. */
4592 ARM_LDR_IMM (code, dreg, dreg, 0);
4593 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4594 /* Call it conditionally. */
4595 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4597 if (cfg->compile_aot) {
4598 /* Load the trigger page addr from the variable initialized in the prolog */
4599 var = ss_trigger_page_var;
4601 g_assert (var->opcode == OP_REGOFFSET);
4602 g_assert (arm_is_imm12 (var->inst_offset));
4603 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4605 #ifdef USE_JUMP_TABLES
4606 gpointer *jte = mono_jumptable_add_entry ();
4607 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4608 jte [0] = ss_trigger_page;
4610 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4612 *(int*)code = (int)ss_trigger_page;
4616 ARM_LDR_IMM (code, dreg, dreg, 0);
4620 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4622 if (cfg->soft_breakpoints) {
4623 /* Load the address of the breakpoint method into ip. */
4624 var = bp_method_var;
4626 g_assert (var->opcode == OP_REGOFFSET);
4627 g_assert (arm_is_imm12 (var->inst_offset));
4628 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4631 * A placeholder for a possible breakpoint inserted by
4632 * mono_arch_set_breakpoint ().
4635 } else if (cfg->compile_aot) {
4636 guint32 offset = code - cfg->native_code;
4639 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4640 /* Add the offset */
4641 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4642 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4643 if (arm_is_imm12 ((int)val)) {
4644 ARM_LDR_IMM (code, dreg, dreg, val);
4646 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4648 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4650 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4651 g_assert (!(val & 0xFF000000));
4653 ARM_LDR_IMM (code, dreg, dreg, 0);
4655 /* What is faster, a branch or a load ? */
4656 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4657 /* The breakpoint instruction */
4658 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4661 * A placeholder for a possible breakpoint inserted by
4662 * mono_arch_set_breakpoint ().
4664 for (i = 0; i < 4; ++i)
4669 * Add an additional nop so skipping the bp doesn't cause the ip to point
4670 * to another IL offset.
4678 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4681 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4685 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4688 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4689 g_assert (imm8 >= 0);
4690 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4694 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4695 g_assert (imm8 >= 0);
4696 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4700 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4701 g_assert (imm8 >= 0);
4702 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4705 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4706 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4708 case OP_IADD_OVF_UN:
4709 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4710 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4713 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4714 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4716 case OP_ISUB_OVF_UN:
4717 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4718 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4720 case OP_ADD_OVF_CARRY:
4721 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4722 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4724 case OP_ADD_OVF_UN_CARRY:
4725 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4728 case OP_SUB_OVF_CARRY:
4729 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4732 case OP_SUB_OVF_UN_CARRY:
4733 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4734 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4738 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4741 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4742 g_assert (imm8 >= 0);
4743 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4746 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4750 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4754 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4755 g_assert (imm8 >= 0);
4756 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4760 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4761 g_assert (imm8 >= 0);
4762 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4764 case OP_ARM_RSBS_IMM:
4765 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4766 g_assert (imm8 >= 0);
4767 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4769 case OP_ARM_RSC_IMM:
4770 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4771 g_assert (imm8 >= 0);
4772 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4775 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4779 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4780 g_assert (imm8 >= 0);
4781 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4784 g_assert (v7s_supported || v7k_supported);
4785 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4788 g_assert (v7s_supported || v7k_supported);
4789 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4792 g_assert (v7s_supported || v7k_supported);
4793 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4794 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4797 g_assert (v7s_supported || v7k_supported);
4798 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4799 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4803 g_assert_not_reached ();
4805 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4810 g_assert (imm8 >= 0);
4811 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4814 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4818 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4819 g_assert (imm8 >= 0);
4820 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4823 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4828 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4829 else if (ins->dreg != ins->sreg1)
4830 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4833 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4838 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4839 else if (ins->dreg != ins->sreg1)
4840 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4843 case OP_ISHR_UN_IMM:
4845 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4846 else if (ins->dreg != ins->sreg1)
4847 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4850 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4853 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4856 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4859 if (ins->dreg == ins->sreg2)
4860 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4862 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4865 g_assert_not_reached ();
4868 /* FIXME: handle ovf/ sreg2 != dreg */
4869 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4870 /* FIXME: MUL doesn't set the C/O flags on ARM */
4872 case OP_IMUL_OVF_UN:
4873 /* FIXME: handle ovf/ sreg2 != dreg */
4874 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4875 /* FIXME: MUL doesn't set the C/O flags on ARM */
4878 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4881 /* Load the GOT offset */
4882 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4883 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4885 *(gpointer*)code = NULL;
4887 /* Load the value from the GOT */
4888 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4890 case OP_OBJC_GET_SELECTOR:
4891 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4892 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4894 *(gpointer*)code = NULL;
4896 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4898 case OP_ICONV_TO_I4:
4899 case OP_ICONV_TO_U4:
4901 if (ins->dreg != ins->sreg1)
4902 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4905 int saved = ins->sreg2;
4906 if (ins->sreg2 == ARM_LSW_REG) {
4907 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4910 if (ins->sreg1 != ARM_LSW_REG)
4911 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4912 if (saved != ARM_MSW_REG)
4913 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4917 if (IS_VFP && ins->dreg != ins->sreg1)
4918 ARM_CPYD (code, ins->dreg, ins->sreg1);
4921 if (IS_VFP && ins->dreg != ins->sreg1)
4922 ARM_CPYS (code, ins->dreg, ins->sreg1);
4924 case OP_MOVE_F_TO_I4:
4926 ARM_FMRS (code, ins->dreg, ins->sreg1);
4928 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4929 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4930 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4931 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4934 case OP_MOVE_I4_TO_F:
4936 ARM_FMSR (code, ins->dreg, ins->sreg1);
4938 ARM_FMSR (code, ins->dreg, ins->sreg1);
4939 ARM_CVTS (code, ins->dreg, ins->dreg);
4942 case OP_FCONV_TO_R4:
4945 ARM_CVTD (code, ins->dreg, ins->sreg1);
4947 ARM_CVTD (code, ins->dreg, ins->sreg1);
4948 ARM_CVTS (code, ins->dreg, ins->dreg);
4953 MonoCallInst *call = (MonoCallInst*)ins;
4956 * The stack looks like the following:
4957 * <caller argument area>
4960 * <callee argument area>
4961 * Need to copy the arguments from the callee argument area to
4962 * the caller argument area, and pop the frame.
4964 if (call->stack_usage) {
4965 int i, prev_sp_offset = 0;
4967 /* Compute size of saved registers restored below */
4969 prev_sp_offset = 2 * 4;
4971 prev_sp_offset = 1 * 4;
4972 for (i = 0; i < 16; ++i) {
4973 if (cfg->used_int_regs & (1 << i))
4974 prev_sp_offset += 4;
4977 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4979 /* Copy arguments on the stack to our argument area */
4980 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4981 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4982 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4987 * Keep in sync with mono_arch_emit_epilog
4989 g_assert (!cfg->method->save_lmf);
4991 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4993 if (cfg->used_int_regs)
4994 ARM_POP (code, cfg->used_int_regs);
4995 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4997 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5000 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5001 if (cfg->compile_aot) {
5002 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5004 *(gpointer*)code = NULL;
5006 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5008 code = mono_arm_patchable_b (code, ARMCOND_AL);
5009 cfg->thunk_area += THUNK_SIZE;
5014 /* ensure ins->sreg1 is not NULL */
5015 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5018 g_assert (cfg->sig_cookie < 128);
5019 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5020 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5030 call = (MonoCallInst*)ins;
5033 code = emit_float_args (cfg, call, code, &max_len, &offset);
5035 if (ins->flags & MONO_INST_HAS_METHOD)
5036 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5038 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5039 code = emit_call_seq (cfg, code);
5040 ins->flags |= MONO_INST_GC_CALLSITE;
5041 ins->backend.pc_offset = code - cfg->native_code;
5042 code = emit_move_return_value (cfg, ins, code);
5049 case OP_VOIDCALL_REG:
5052 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5054 code = emit_call_reg (code, ins->sreg1);
5055 ins->flags |= MONO_INST_GC_CALLSITE;
5056 ins->backend.pc_offset = code - cfg->native_code;
5057 code = emit_move_return_value (cfg, ins, code);
5059 case OP_FCALL_MEMBASE:
5060 case OP_RCALL_MEMBASE:
5061 case OP_LCALL_MEMBASE:
5062 case OP_VCALL_MEMBASE:
5063 case OP_VCALL2_MEMBASE:
5064 case OP_VOIDCALL_MEMBASE:
5065 case OP_CALL_MEMBASE: {
5066 g_assert (ins->sreg1 != ARMREG_LR);
5067 call = (MonoCallInst*)ins;
5070 code = emit_float_args (cfg, call, code, &max_len, &offset);
5071 if (!arm_is_imm12 (ins->inst_offset)) {
5072 /* sreg1 might be IP */
5073 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5074 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5075 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5076 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5077 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5079 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5080 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5082 ins->flags |= MONO_INST_GC_CALLSITE;
5083 ins->backend.pc_offset = code - cfg->native_code;
5084 code = emit_move_return_value (cfg, ins, code);
5087 case OP_GENERIC_CLASS_INIT: {
5088 static int byte_offset = -1;
5089 static guint8 bitmask;
5093 if (byte_offset < 0)
5094 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5096 g_assert (arm_is_imm8 (byte_offset));
5097 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5098 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5099 g_assert (imm8 >= 0);
5100 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5101 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5103 ARM_B_COND (code, ARMCOND_NE, 0);
5105 /* Uninitialized case */
5106 g_assert (ins->sreg1 == ARMREG_R0);
5108 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5109 (gpointer)"mono_generic_class_init");
5110 code = emit_call_seq (cfg, code);
5112 /* Initialized case */
5113 arm_patch (jump, code);
5117 /* round the size to 8 bytes */
5118 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5119 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5120 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5121 /* memzero the area: dreg holds the size, sp is the pointer */
5122 if (ins->flags & MONO_INST_INIT) {
5123 guint8 *start_loop, *branch_to_cond;
5124 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5125 branch_to_cond = code;
5128 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5129 arm_patch (branch_to_cond, code);
5130 /* decrement by 4 and set flags */
5131 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5132 ARM_B_COND (code, ARMCOND_GE, 0);
5133 arm_patch (code - 4, start_loop);
5135 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5136 if (cfg->param_area)
5137 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5142 MonoInst *var = cfg->dyn_call_var;
5144 g_assert (var->opcode == OP_REGOFFSET);
5145 g_assert (arm_is_imm12 (var->inst_offset));
5147 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5148 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5150 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5152 /* Save args buffer */
5153 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5155 /* Set stack slots using R0 as scratch reg */
5156 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5157 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5158 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5159 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5162 /* Set argument registers */
5163 for (i = 0; i < PARAM_REGS; ++i)
5164 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5167 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5168 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5171 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5172 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5173 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5177 if (ins->sreg1 != ARMREG_R0)
5178 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5179 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5180 (gpointer)"mono_arch_throw_exception");
5181 code = emit_call_seq (cfg, code);
5185 if (ins->sreg1 != ARMREG_R0)
5186 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5187 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5188 (gpointer)"mono_arch_rethrow_exception");
5189 code = emit_call_seq (cfg, code);
5192 case OP_START_HANDLER: {
5193 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5194 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5197 /* Reserve a param area, see filter-stack.exe */
5199 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5200 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5202 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5203 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5207 if (arm_is_imm12 (spvar->inst_offset)) {
5208 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5210 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5211 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5215 case OP_ENDFILTER: {
5216 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5217 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5220 /* Free the param area */
5222 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5223 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5225 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5226 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5230 if (ins->sreg1 != ARMREG_R0)
5231 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5232 if (arm_is_imm12 (spvar->inst_offset)) {
5233 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5235 g_assert (ARMREG_IP != spvar->inst_basereg);
5236 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5237 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5239 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5242 case OP_ENDFINALLY: {
5243 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5244 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5247 /* Free the param area */
5249 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5250 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5252 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5253 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5257 if (arm_is_imm12 (spvar->inst_offset)) {
5258 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5260 g_assert (ARMREG_IP != spvar->inst_basereg);
5261 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5262 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5264 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5267 case OP_CALL_HANDLER:
5268 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5269 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5270 cfg->thunk_area += THUNK_SIZE;
5271 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5274 if (ins->dreg != ARMREG_R0)
5275 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5279 ins->inst_c0 = code - cfg->native_code;
5282 /*if (ins->inst_target_bb->native_offset) {
5284 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5286 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5287 code = mono_arm_patchable_b (code, ARMCOND_AL);
5291 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5295 * In the normal case we have:
5296 * ldr pc, [pc, ins->sreg1 << 2]
5299 * ldr lr, [pc, ins->sreg1 << 2]
5301 * After follows the data.
5302 * FIXME: add aot support.
5304 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5305 #ifdef USE_JUMP_TABLES
5307 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5308 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5309 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5313 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5314 if (offset + max_len > (cfg->code_size - 16)) {
5315 cfg->code_size += max_len;
5316 cfg->code_size *= 2;
5317 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5318 code = cfg->native_code + offset;
5320 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5322 code += 4 * GPOINTER_TO_INT (ins->klass);
5327 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5328 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5332 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5333 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5337 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5338 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5342 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5343 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5347 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5348 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5351 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5352 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5355 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5356 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5359 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5360 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5363 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5364 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5367 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5368 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5370 case OP_COND_EXC_EQ:
5371 case OP_COND_EXC_NE_UN:
5372 case OP_COND_EXC_LT:
5373 case OP_COND_EXC_LT_UN:
5374 case OP_COND_EXC_GT:
5375 case OP_COND_EXC_GT_UN:
5376 case OP_COND_EXC_GE:
5377 case OP_COND_EXC_GE_UN:
5378 case OP_COND_EXC_LE:
5379 case OP_COND_EXC_LE_UN:
5380 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5382 case OP_COND_EXC_IEQ:
5383 case OP_COND_EXC_INE_UN:
5384 case OP_COND_EXC_ILT:
5385 case OP_COND_EXC_ILT_UN:
5386 case OP_COND_EXC_IGT:
5387 case OP_COND_EXC_IGT_UN:
5388 case OP_COND_EXC_IGE:
5389 case OP_COND_EXC_IGE_UN:
5390 case OP_COND_EXC_ILE:
5391 case OP_COND_EXC_ILE_UN:
5392 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5395 case OP_COND_EXC_IC:
5396 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5398 case OP_COND_EXC_OV:
5399 case OP_COND_EXC_IOV:
5400 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5402 case OP_COND_EXC_NC:
5403 case OP_COND_EXC_INC:
5404 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5406 case OP_COND_EXC_NO:
5407 case OP_COND_EXC_INO:
5408 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5420 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5423 /* floating point opcodes */
5425 if (cfg->compile_aot) {
5426 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5428 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5430 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5433 /* FIXME: we can optimize the imm load by dealing with part of
5434 * the displacement in LDFD (aligning to 512).
5436 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5437 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5441 if (cfg->compile_aot) {
5442 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5444 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5447 ARM_CVTS (code, ins->dreg, ins->dreg);
5449 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5450 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5452 ARM_CVTS (code, ins->dreg, ins->dreg);
5455 case OP_STORER8_MEMBASE_REG:
5456 /* This is generated by the local regalloc pass which runs after the lowering pass */
5457 if (!arm_is_fpimm8 (ins->inst_offset)) {
5458 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5459 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5460 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5462 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5465 case OP_LOADR8_MEMBASE:
5466 /* This is generated by the local regalloc pass which runs after the lowering pass */
5467 if (!arm_is_fpimm8 (ins->inst_offset)) {
5468 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5469 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5470 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5472 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5475 case OP_STORER4_MEMBASE_REG:
5476 g_assert (arm_is_fpimm8 (ins->inst_offset));
5478 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5480 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5481 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5482 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5483 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5486 case OP_LOADR4_MEMBASE:
5488 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5490 g_assert (arm_is_fpimm8 (ins->inst_offset));
5491 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5492 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5493 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5494 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5497 case OP_ICONV_TO_R_UN: {
5498 g_assert_not_reached ();
5501 case OP_ICONV_TO_R4:
5503 ARM_FMSR (code, ins->dreg, ins->sreg1);
5504 ARM_FSITOS (code, ins->dreg, ins->dreg);
5506 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5507 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5508 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5509 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5510 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5513 case OP_ICONV_TO_R8:
5514 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5515 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5516 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5517 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5521 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5522 if (sig_ret->type == MONO_TYPE_R4) {
5524 g_assert (!IS_HARD_FLOAT);
5525 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5527 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5530 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5534 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5536 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5540 case OP_FCONV_TO_I1:
5541 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5543 case OP_FCONV_TO_U1:
5544 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5546 case OP_FCONV_TO_I2:
5547 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5549 case OP_FCONV_TO_U2:
5550 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5552 case OP_FCONV_TO_I4:
5554 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5556 case OP_FCONV_TO_U4:
5558 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5560 case OP_FCONV_TO_I8:
5561 case OP_FCONV_TO_U8:
5562 g_assert_not_reached ();
5563 /* Implemented as helper calls */
5565 case OP_LCONV_TO_R_UN:
5566 g_assert_not_reached ();
5567 /* Implemented as helper calls */
5569 case OP_LCONV_TO_OVF_I4_2: {
5570 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5572 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5575 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5576 high_bit_not_set = code;
5577 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5579 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5580 valid_negative = code;
5581 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5582 invalid_negative = code;
5583 ARM_B_COND (code, ARMCOND_AL, 0);
5585 arm_patch (high_bit_not_set, code);
5587 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5588 valid_positive = code;
5589 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5591 arm_patch (invalid_negative, code);
5592 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5594 arm_patch (valid_negative, code);
5595 arm_patch (valid_positive, code);
5597 if (ins->dreg != ins->sreg1)
5598 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5602 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5605 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5608 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5611 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5614 ARM_NEGD (code, ins->dreg, ins->sreg1);
5618 g_assert_not_reached ();
5622 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5628 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5633 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5636 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5637 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5641 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5644 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5645 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5649 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5652 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5653 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5654 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5658 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5661 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5662 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5666 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5669 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5670 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5671 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5675 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5678 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5679 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5683 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5686 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5687 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5691 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5694 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5695 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5698 /* ARM FPA flags table:
5699 * N Less than ARMCOND_MI
5700 * Z Equal ARMCOND_EQ
5701 * C Greater Than or Equal ARMCOND_CS
5702 * V Unordered ARMCOND_VS
5705 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5708 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5711 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5714 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5715 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5721 g_assert_not_reached ();
5725 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5727 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5728 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5729 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5733 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5734 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5739 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5740 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5742 #ifdef USE_JUMP_TABLES
5744 gpointer *jte = mono_jumptable_add_entries (2);
5745 jte [0] = GUINT_TO_POINTER (0xffffffff);
5746 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5747 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5748 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5751 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5752 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5754 *(guint32*)code = 0xffffffff;
5756 *(guint32*)code = 0x7fefffff;
5759 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5761 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5762 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5764 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5765 ARM_CPYD (code, ins->dreg, ins->sreg1);
5767 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5768 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5773 case OP_RCONV_TO_I1:
5774 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5776 case OP_RCONV_TO_U1:
5777 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5779 case OP_RCONV_TO_I2:
5780 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5782 case OP_RCONV_TO_U2:
5783 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5785 case OP_RCONV_TO_I4:
5786 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5788 case OP_RCONV_TO_U4:
5789 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5791 case OP_RCONV_TO_R4:
5793 if (ins->dreg != ins->sreg1)
5794 ARM_CPYS (code, ins->dreg, ins->sreg1);
5796 case OP_RCONV_TO_R8:
5798 ARM_CVTS (code, ins->dreg, ins->sreg1);
5801 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5804 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5807 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5810 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5813 ARM_NEGS (code, ins->dreg, ins->sreg1);
5817 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5820 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5821 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5825 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5828 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5829 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5833 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5836 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5837 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5838 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5842 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5845 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5846 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5850 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5853 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5854 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5855 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5859 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5862 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5863 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5867 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5870 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5871 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5875 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5878 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5879 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5882 case OP_GC_LIVENESS_DEF:
5883 case OP_GC_LIVENESS_USE:
5884 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5885 ins->backend.pc_offset = code - cfg->native_code;
5887 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5888 ins->backend.pc_offset = code - cfg->native_code;
5889 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5891 case OP_GC_SAFE_POINT: {
5892 const char *polling_func = NULL;
5895 g_assert (mono_threads_is_coop_enabled ());
5897 polling_func = "mono_threads_state_poll";
5898 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5899 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5901 ARM_B_COND (code, ARMCOND_EQ, 0);
5902 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5903 code = emit_call_seq (cfg, code);
5904 arm_patch (buf [0], code);
5909 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5910 g_assert_not_reached ();
5913 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5914 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5915 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5916 g_assert_not_reached ();
5922 last_offset = offset;
5925 cfg->code_len = code - cfg->native_code;
5928 #endif /* DISABLE_JIT */
5931 mono_arch_register_lowlevel_calls (void)
5933 /* The signature doesn't matter */
5934 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5935 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5936 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5938 #ifndef MONO_CROSS_COMPILE
5939 if (mono_arm_have_tls_get ()) {
5940 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5942 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5943 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5945 if (tls_imp.get_tls_thunk_end) {
5946 mono_tramp_info_register (
5947 mono_tramp_info_create (
5949 (guint8*)tls_imp.get_tls_thunk,
5950 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5952 mono_arch_get_cie_program ()
5956 mono_tramp_info_register (
5957 mono_tramp_info_create (
5959 (guint8*)tls_imp.set_tls_thunk,
5960 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
5962 mono_arch_get_cie_program ()
5971 #define patch_lis_ori(ip,val) do {\
5972 guint16 *__lis_ori = (guint16*)(ip); \
5973 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5974 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5978 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5980 unsigned char *ip = ji->ip.i + code;
5982 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5986 case MONO_PATCH_INFO_SWITCH: {
5987 #ifdef USE_JUMP_TABLES
5988 gpointer *jt = mono_jumptable_get_entry (ip);
5990 gpointer *jt = (gpointer*)(ip + 8);
5993 /* jt is the inlined jump table, 2 instructions after ip
5994 * In the normal case we store the absolute addresses,
5995 * otherwise the displacements.
5997 for (i = 0; i < ji->data.table->table_size; i++)
5998 jt [i] = code + (int)ji->data.table->table [i];
6001 case MONO_PATCH_INFO_IP:
6002 g_assert_not_reached ();
6003 patch_lis_ori (ip, ip);
6005 case MONO_PATCH_INFO_METHOD_REL:
6006 g_assert_not_reached ();
6007 *((gpointer *)(ip)) = target;
6009 case MONO_PATCH_INFO_METHODCONST:
6010 case MONO_PATCH_INFO_CLASS:
6011 case MONO_PATCH_INFO_IMAGE:
6012 case MONO_PATCH_INFO_FIELD:
6013 case MONO_PATCH_INFO_VTABLE:
6014 case MONO_PATCH_INFO_IID:
6015 case MONO_PATCH_INFO_SFLDA:
6016 case MONO_PATCH_INFO_LDSTR:
6017 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6018 case MONO_PATCH_INFO_LDTOKEN:
6019 g_assert_not_reached ();
6020 /* from OP_AOTCONST : lis + ori */
6021 patch_lis_ori (ip, target);
6023 case MONO_PATCH_INFO_R4:
6024 case MONO_PATCH_INFO_R8:
6025 g_assert_not_reached ();
6026 *((gconstpointer *)(ip + 2)) = target;
6028 case MONO_PATCH_INFO_EXC_NAME:
6029 g_assert_not_reached ();
6030 *((gconstpointer *)(ip + 1)) = target;
6032 case MONO_PATCH_INFO_NONE:
6033 case MONO_PATCH_INFO_BB_OVF:
6034 case MONO_PATCH_INFO_EXC_OVF:
6035 /* everything is dealt with at epilog output time */
6038 arm_patch_general (cfg, domain, ip, target);
6044 mono_arm_unaligned_stack (MonoMethod *method)
6046 g_assert_not_reached ();
6052 * Stack frame layout:
6054 * ------------------- fp
6055 * MonoLMF structure or saved registers
6056 * -------------------
6058 * -------------------
6060 * -------------------
6061 * optional 8 bytes for tracing
6062 * -------------------
6063 * param area size is cfg->param_area
6064 * ------------------- sp
6067 mono_arch_emit_prolog (MonoCompile *cfg)
6069 MonoMethod *method = cfg->method;
6071 MonoMethodSignature *sig;
6073 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6078 int prev_sp_offset, reg_offset;
6080 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6083 sig = mono_method_signature (method);
6084 cfg->code_size = 256 + sig->param_count * 64;
6085 code = cfg->native_code = g_malloc (cfg->code_size);
6087 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6089 alloc_size = cfg->stack_offset;
6095 * The iphone uses R7 as the frame pointer, and it points at the saved
6100 * We can't use r7 as a frame pointer since it points into the middle of
6101 * the frame, so we keep using our own frame pointer.
6102 * FIXME: Optimize this.
6104 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6105 prev_sp_offset += 8; /* r7 and lr */
6106 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6107 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6108 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6111 if (!method->save_lmf) {
6113 /* No need to push LR again */
6114 if (cfg->used_int_regs)
6115 ARM_PUSH (code, cfg->used_int_regs);
6117 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6118 prev_sp_offset += 4;
6120 for (i = 0; i < 16; ++i) {
6121 if (cfg->used_int_regs & (1 << i))
6122 prev_sp_offset += 4;
6124 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6126 for (i = 0; i < 16; ++i) {
6127 if ((cfg->used_int_regs & (1 << i))) {
6128 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6129 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6134 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6135 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6137 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6138 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6141 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6142 ARM_PUSH (code, 0x5ff0);
6143 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6144 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6146 for (i = 0; i < 16; ++i) {
6147 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6148 /* The original r7 is saved at the start */
6149 if (!(iphone_abi && i == ARMREG_R7))
6150 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6154 g_assert (reg_offset == 4 * 10);
6155 pos += sizeof (MonoLMF) - (4 * 10);
6159 orig_alloc_size = alloc_size;
6160 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6161 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6162 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6163 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6166 /* the stack used in the pushed regs */
6167 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6168 cfg->stack_usage = alloc_size;
6170 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6171 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6173 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6174 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6176 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6178 if (cfg->frame_reg != ARMREG_SP) {
6179 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6180 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6182 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6183 prev_sp_offset += alloc_size;
6185 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6186 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6188 /* compute max_offset in order to use short forward jumps
6189 * we could skip do it on arm because the immediate displacement
6190 * for jumps is large enough, it may be useful later for constant pools
6193 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6194 MonoInst *ins = bb->code;
6195 bb->max_offset = max_offset;
6197 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6200 MONO_BB_FOR_EACH_INS (bb, ins)
6201 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6204 /* stack alignment check */
6208 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6209 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6210 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6211 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6213 ARM_B_COND (code, ARMCOND_EQ, 0);
6214 if (cfg->compile_aot)
6215 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6217 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6218 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6219 code = emit_call_seq (cfg, code);
6220 arm_patch (buf [0], code);
6224 /* store runtime generic context */
6225 if (cfg->rgctx_var) {
6226 MonoInst *ins = cfg->rgctx_var;
6228 g_assert (ins->opcode == OP_REGOFFSET);
6230 if (arm_is_imm12 (ins->inst_offset)) {
6231 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6233 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6234 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6238 /* load arguments allocated to register from the stack */
6241 cinfo = get_call_info (NULL, sig);
6243 if (cinfo->ret.storage == RegTypeStructByAddr) {
6244 ArgInfo *ainfo = &cinfo->ret;
6245 inst = cfg->vret_addr;
6246 g_assert (arm_is_imm12 (inst->inst_offset));
6247 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6250 if (sig->call_convention == MONO_CALL_VARARG) {
6251 ArgInfo *cookie = &cinfo->sig_cookie;
6253 /* Save the sig cookie address */
6254 g_assert (cookie->storage == RegTypeBase);
6256 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6257 g_assert (arm_is_imm12 (cfg->sig_cookie));
6258 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6259 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6262 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6263 ArgInfo *ainfo = cinfo->args + i;
6264 inst = cfg->args [pos];
6266 if (cfg->verbose_level > 2)
6267 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6269 if (inst->opcode == OP_REGVAR) {
6270 if (ainfo->storage == RegTypeGeneral)
6271 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6272 else if (ainfo->storage == RegTypeFP) {
6273 g_assert_not_reached ();
6274 } else if (ainfo->storage == RegTypeBase) {
6275 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6276 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6278 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6279 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6282 g_assert_not_reached ();
6284 if (cfg->verbose_level > 2)
6285 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6287 switch (ainfo->storage) {
6289 for (part = 0; part < ainfo->nregs; part ++) {
6290 if (ainfo->esize == 4)
6291 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6293 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6296 case RegTypeGeneral:
6297 case RegTypeIRegPair:
6298 case RegTypeGSharedVtInReg:
6299 switch (ainfo->size) {
6301 if (arm_is_imm12 (inst->inst_offset))
6302 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6304 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6305 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6309 if (arm_is_imm8 (inst->inst_offset)) {
6310 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6312 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6313 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6317 if (arm_is_imm12 (inst->inst_offset)) {
6318 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6320 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6321 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6323 if (arm_is_imm12 (inst->inst_offset + 4)) {
6324 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6326 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6327 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6331 if (arm_is_imm12 (inst->inst_offset)) {
6332 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6334 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6335 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6340 case RegTypeBaseGen:
6341 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6342 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6344 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6345 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6347 if (arm_is_imm12 (inst->inst_offset + 4)) {
6348 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6349 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6351 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6352 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6353 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6354 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6358 case RegTypeGSharedVtOnStack:
6359 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6360 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6362 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6363 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6366 switch (ainfo->size) {
6368 if (arm_is_imm8 (inst->inst_offset)) {
6369 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6371 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6372 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6376 if (arm_is_imm8 (inst->inst_offset)) {
6377 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6379 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6380 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6384 if (arm_is_imm12 (inst->inst_offset)) {
6385 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6387 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6388 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6390 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6391 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6393 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6394 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6396 if (arm_is_imm12 (inst->inst_offset + 4)) {
6397 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6399 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6400 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6404 if (arm_is_imm12 (inst->inst_offset)) {
6405 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6407 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6408 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6414 int imm8, rot_amount;
6416 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6417 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6418 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6420 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6422 if (ainfo->size == 8)
6423 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6425 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6428 case RegTypeStructByVal: {
6429 int doffset = inst->inst_offset;
6433 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6434 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6435 if (arm_is_imm12 (doffset)) {
6436 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6438 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6439 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6441 soffset += sizeof (gpointer);
6442 doffset += sizeof (gpointer);
6444 if (ainfo->vtsize) {
6445 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6446 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6447 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6451 case RegTypeStructByAddr:
6452 g_assert_not_reached ();
6453 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6454 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6456 g_assert_not_reached ();
6463 if (method->save_lmf)
6464 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6467 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6469 if (cfg->arch.seq_point_info_var) {
6470 MonoInst *ins = cfg->arch.seq_point_info_var;
6472 /* Initialize the variable from a GOT slot */
6473 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6474 #ifdef USE_JUMP_TABLES
6476 gpointer *jte = mono_jumptable_add_entry ();
6477 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6478 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6480 /** XXX: is it correct? */
6482 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6484 *(gpointer*)code = NULL;
6487 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6489 g_assert (ins->opcode == OP_REGOFFSET);
6491 if (arm_is_imm12 (ins->inst_offset)) {
6492 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6494 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6495 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6499 /* Initialize ss_trigger_page_var */
6500 if (!cfg->soft_breakpoints) {
6501 MonoInst *info_var = cfg->arch.seq_point_info_var;
6502 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6503 int dreg = ARMREG_LR;
6506 g_assert (info_var->opcode == OP_REGOFFSET);
6507 g_assert (arm_is_imm12 (info_var->inst_offset));
6509 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6510 /* Load the trigger page addr */
6511 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6512 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6516 if (cfg->arch.seq_point_ss_method_var) {
6517 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6518 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6519 #ifdef USE_JUMP_TABLES
6522 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6523 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6524 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6525 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6527 #ifdef USE_JUMP_TABLES
6528 jte = mono_jumptable_add_entries (3);
6529 jte [0] = &single_step_tramp;
6530 jte [1] = breakpoint_tramp;
6531 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6533 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6535 *(gpointer*)code = &single_step_tramp;
6537 *(gpointer*)code = breakpoint_tramp;
6541 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6542 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6543 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6544 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6547 cfg->code_len = code - cfg->native_code;
6548 g_assert (cfg->code_len < cfg->code_size);
6555 mono_arch_emit_epilog (MonoCompile *cfg)
6557 MonoMethod *method = cfg->method;
6558 int pos, i, rot_amount;
6559 int max_epilog_size = 16 + 20*4;
6563 if (cfg->method->save_lmf)
6564 max_epilog_size += 128;
6566 if (mono_jit_trace_calls != NULL)
6567 max_epilog_size += 50;
6569 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6570 max_epilog_size += 50;
6572 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6573 cfg->code_size *= 2;
6574 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6575 cfg->stat_code_reallocs++;
6579 * Keep in sync with OP_JMP
6581 code = cfg->native_code + cfg->code_len;
6583 /* Save the uwind state which is needed by the out-of-line code */
6584 mono_emit_unwind_op_remember_state (cfg, code);
6586 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6587 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6591 /* Load returned vtypes into registers if needed */
6592 cinfo = cfg->arch.cinfo;
6593 switch (cinfo->ret.storage) {
6594 case RegTypeStructByVal: {
6595 MonoInst *ins = cfg->ret;
6597 if (arm_is_imm12 (ins->inst_offset)) {
6598 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6600 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6601 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6606 MonoInst *ins = cfg->ret;
6608 for (i = 0; i < cinfo->ret.nregs; ++i) {
6609 if (cinfo->ret.esize == 4)
6610 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6612 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6620 if (method->save_lmf) {
6621 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6622 /* all but r0-r3, sp and pc */
6623 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6626 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6628 /* This points to r4 inside MonoLMF->iregs */
6629 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6631 regmask = 0x9ff0; /* restore lr to pc */
6632 /* Skip caller saved registers not used by the method */
6633 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6634 regmask &= ~(1 << reg);
6639 /* Restored later */
6640 regmask &= ~(1 << ARMREG_PC);
6641 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6642 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6643 for (i = 0; i < 16; i++) {
6644 if (regmask & (1 << i))
6647 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6649 ARM_POP (code, regmask);
6651 for (i = 0; i < 16; i++) {
6652 if (regmask & (1 << i))
6653 mono_emit_unwind_op_same_value (cfg, code, i);
6655 /* Restore saved r7, restore LR to PC */
6656 /* Skip lr from the lmf */
6657 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6658 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6659 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6660 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6663 int i, nused_int_regs = 0;
6665 for (i = 0; i < 16; i++) {
6666 if (cfg->used_int_regs & (1 << i))
6670 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6671 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6673 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6674 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6677 if (cfg->frame_reg != ARMREG_SP) {
6678 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6682 /* Restore saved gregs */
6683 if (cfg->used_int_regs) {
6684 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6685 ARM_POP (code, cfg->used_int_regs);
6686 for (i = 0; i < 16; i++) {
6687 if (cfg->used_int_regs & (1 << i))
6688 mono_emit_unwind_op_same_value (cfg, code, i);
6691 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6692 /* Restore saved r7, restore LR to PC */
6693 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6695 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6696 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6700 /* Restore the unwind state to be the same as before the epilog */
6701 mono_emit_unwind_op_restore_state (cfg, code);
6703 cfg->code_len = code - cfg->native_code;
6705 g_assert (cfg->code_len < cfg->code_size);
6710 mono_arch_emit_exceptions (MonoCompile *cfg)
6712 MonoJumpInfo *patch_info;
6715 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6716 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6717 int max_epilog_size = 50;
6719 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6720 exc_throw_pos [i] = NULL;
6721 exc_throw_found [i] = 0;
6724 /* count the number of exception infos */
6727 * make sure we have enough space for exceptions
6729 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6730 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6731 i = mini_exception_id_by_name (patch_info->data.target);
6732 if (!exc_throw_found [i]) {
6733 max_epilog_size += 32;
6734 exc_throw_found [i] = TRUE;
6739 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6740 cfg->code_size *= 2;
6741 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6742 cfg->stat_code_reallocs++;
6745 code = cfg->native_code + cfg->code_len;
6747 /* add code to raise exceptions */
6748 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6749 switch (patch_info->type) {
6750 case MONO_PATCH_INFO_EXC: {
6751 MonoClass *exc_class;
6752 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6754 i = mini_exception_id_by_name (patch_info->data.target);
6755 if (exc_throw_pos [i]) {
6756 arm_patch (ip, exc_throw_pos [i]);
6757 patch_info->type = MONO_PATCH_INFO_NONE;
6760 exc_throw_pos [i] = code;
6762 arm_patch (ip, code);
6764 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6766 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6767 #ifdef USE_JUMP_TABLES
6769 gpointer *jte = mono_jumptable_add_entries (2);
6770 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6771 patch_info->data.name = "mono_arch_throw_corlib_exception";
6772 patch_info->ip.i = code - cfg->native_code;
6773 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6774 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6775 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6776 ARM_BLX_REG (code, ARMREG_IP);
6777 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6780 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6781 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6782 patch_info->data.name = "mono_arch_throw_corlib_exception";
6783 patch_info->ip.i = code - cfg->native_code;
6785 cfg->thunk_area += THUNK_SIZE;
6786 *(guint32*)(gpointer)code = exc_class->type_token;
6797 cfg->code_len = code - cfg->native_code;
6799 g_assert (cfg->code_len < cfg->code_size);
6803 #endif /* #ifndef DISABLE_JIT */
6806 mono_arch_finish_init (void)
6811 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6816 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6823 mono_arch_print_tree (MonoInst *tree, int arity)
6833 mono_arch_get_patch_offset (guint8 *code)
6840 mono_arch_flush_register_windows (void)
6845 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6847 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6851 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6853 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6857 mono_arch_get_cie_program (void)
6861 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6866 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6867 #define BASE_SIZE (6 * 4)
6868 #define BSEARCH_ENTRY_SIZE (4 * 4)
6869 #define CMP_SIZE (3 * 4)
6870 #define BRANCH_SIZE (1 * 4)
6871 #define CALL_SIZE (2 * 4)
6872 #define WMC_SIZE (8 * 4)
6873 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6875 #ifdef USE_JUMP_TABLES
6877 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6879 g_assert (base [index] == NULL);
6880 base [index] = value;
6883 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6885 if (arm_is_imm12 (jti * 4)) {
6886 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6888 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6889 if ((jti * 4) >> 16)
6890 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6891 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6897 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6899 guint32 delta = DISTANCE (target, code);
6901 g_assert (delta >= 0 && delta <= 0xFFF);
6902 *target = *target | delta;
6908 #ifdef ENABLE_WRONG_METHOD_CHECK
6910 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6912 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6918 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6919 gpointer fail_tramp)
6922 arminstr_t *code, *start;
6923 #ifdef USE_JUMP_TABLES
6926 gboolean large_offsets = FALSE;
6927 guint32 **constant_pool_starts;
6928 arminstr_t *vtable_target = NULL;
6929 int extra_space = 0;
6931 #ifdef ENABLE_WRONG_METHOD_CHECK
6937 #ifdef USE_JUMP_TABLES
6938 for (i = 0; i < count; ++i) {
6939 MonoIMTCheckItem *item = imt_entries [i];
6940 item->chunk_size += 4 * 16;
6941 if (!item->is_equals)
6942 imt_entries [item->check_target_idx]->compare_done = TRUE;
6943 size += item->chunk_size;
6946 constant_pool_starts = g_new0 (guint32*, count);
6948 for (i = 0; i < count; ++i) {
6949 MonoIMTCheckItem *item = imt_entries [i];
6950 if (item->is_equals) {
6951 gboolean fail_case = !item->check_target_idx && fail_tramp;
6953 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6954 item->chunk_size += 32;
6955 large_offsets = TRUE;
6958 if (item->check_target_idx || fail_case) {
6959 if (!item->compare_done || fail_case)
6960 item->chunk_size += CMP_SIZE;
6961 item->chunk_size += BRANCH_SIZE;
6963 #ifdef ENABLE_WRONG_METHOD_CHECK
6964 item->chunk_size += WMC_SIZE;
6968 item->chunk_size += 16;
6969 large_offsets = TRUE;
6971 item->chunk_size += CALL_SIZE;
6973 item->chunk_size += BSEARCH_ENTRY_SIZE;
6974 imt_entries [item->check_target_idx]->compare_done = TRUE;
6976 size += item->chunk_size;
6980 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6984 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6986 code = mono_domain_code_reserve (domain, size);
6989 unwind_ops = mono_arch_get_cie_program ();
6992 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6993 for (i = 0; i < count; ++i) {
6994 MonoIMTCheckItem *item = imt_entries [i];
6995 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6999 #ifdef USE_JUMP_TABLES
7000 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7001 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7002 #define VTABLE_JTI 0
7003 #define IMT_METHOD_OFFSET 0
7004 #define TARGET_CODE_OFFSET 1
7005 #define JUMP_CODE_OFFSET 2
7006 #define RECORDS_PER_ENTRY 3
7007 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7008 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7009 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7011 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7012 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7013 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7014 set_jumptable_element (jte, VTABLE_JTI, vtable);
7016 if (large_offsets) {
7017 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7018 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7020 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7021 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7023 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7024 vtable_target = code;
7025 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7027 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7029 for (i = 0; i < count; ++i) {
7030 MonoIMTCheckItem *item = imt_entries [i];
7031 #ifdef USE_JUMP_TABLES
7032 guint32 imt_method_jti = 0, target_code_jti = 0;
7034 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7036 gint32 vtable_offset;
7038 item->code_target = (guint8*)code;
7040 if (item->is_equals) {
7041 gboolean fail_case = !item->check_target_idx && fail_tramp;
7043 if (item->check_target_idx || fail_case) {
7044 if (!item->compare_done || fail_case) {
7045 #ifdef USE_JUMP_TABLES
7046 imt_method_jti = IMT_METHOD_JTI (i);
7047 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7050 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7052 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7054 #ifdef USE_JUMP_TABLES
7055 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7056 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7057 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7059 item->jmp_code = (guint8*)code;
7060 ARM_B_COND (code, ARMCOND_NE, 0);
7063 /*Enable the commented code to assert on wrong method*/
7064 #ifdef ENABLE_WRONG_METHOD_CHECK
7065 #ifdef USE_JUMP_TABLES
7066 imt_method_jti = IMT_METHOD_JTI (i);
7067 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7070 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7072 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7074 ARM_B_COND (code, ARMCOND_EQ, 0);
7076 /* Define this if your system is so bad that gdb is failing. */
7077 #ifdef BROKEN_DEV_ENV
7078 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7080 arm_patch (code - 1, mini_dump_bad_imt);
7084 arm_patch (cond, code);
7088 if (item->has_target_code) {
7089 /* Load target address */
7090 #ifdef USE_JUMP_TABLES
7091 target_code_jti = TARGET_CODE_JTI (i);
7092 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7093 /* Restore registers */
7094 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7095 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7097 ARM_BX (code, ARMREG_R1);
7098 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7100 target_code_ins = code;
7101 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7102 /* Save it to the fourth slot */
7103 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7104 /* Restore registers and branch */
7105 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7107 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7110 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7111 if (!arm_is_imm12 (vtable_offset)) {
7113 * We need to branch to a computed address but we don't have
7114 * a free register to store it, since IP must contain the
7115 * vtable address. So we push the two values to the stack, and
7116 * load them both using LDM.
7118 /* Compute target address */
7119 #ifdef USE_JUMP_TABLES
7120 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7121 if (vtable_offset >> 16)
7122 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7123 /* IP had vtable base. */
7124 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7125 /* Restore registers and branch */
7126 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7127 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7128 ARM_BX (code, ARMREG_IP);
7130 vtable_offset_ins = code;
7131 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7132 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7133 /* Save it to the fourth slot */
7134 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7135 /* Restore registers and branch */
7136 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7138 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7141 #ifdef USE_JUMP_TABLES
7142 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7143 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7144 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7145 ARM_BX (code, ARMREG_IP);
7147 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7148 if (large_offsets) {
7149 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7150 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7152 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7153 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7159 #ifdef USE_JUMP_TABLES
7160 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7161 target_code_jti = TARGET_CODE_JTI (i);
7162 /* Load target address */
7163 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7164 /* Restore registers */
7165 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7166 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7168 ARM_BX (code, ARMREG_R1);
7169 set_jumptable_element (jte, target_code_jti, fail_tramp);
7171 arm_patch (item->jmp_code, (guchar*)code);
7173 target_code_ins = code;
7174 /* Load target address */
7175 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7176 /* Save it to the fourth slot */
7177 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7178 /* Restore registers and branch */
7179 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7181 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7183 item->jmp_code = NULL;
7186 #ifdef USE_JUMP_TABLES
7188 set_jumptable_element (jte, imt_method_jti, item->key);
7191 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7193 /*must emit after unconditional branch*/
7194 if (vtable_target) {
7195 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7196 item->chunk_size += 4;
7197 vtable_target = NULL;
7200 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7201 constant_pool_starts [i] = code;
7203 code += extra_space;
7208 #ifdef USE_JUMP_TABLES
7209 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7210 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7211 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7212 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7213 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7215 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7216 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7218 item->jmp_code = (guint8*)code;
7219 ARM_B_COND (code, ARMCOND_HS, 0);
7225 for (i = 0; i < count; ++i) {
7226 MonoIMTCheckItem *item = imt_entries [i];
7227 if (item->jmp_code) {
7228 if (item->check_target_idx)
7229 #ifdef USE_JUMP_TABLES
7230 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7232 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7235 if (i > 0 && item->is_equals) {
7237 #ifdef USE_JUMP_TABLES
7238 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7239 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7241 arminstr_t *space_start = constant_pool_starts [i];
7242 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7243 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7251 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7252 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7257 #ifndef USE_JUMP_TABLES
7258 g_free (constant_pool_starts);
7261 mono_arch_flush_icache ((guint8*)start, size);
7262 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7263 mono_stats.imt_thunks_size += code - start;
7265 g_assert (DISTANCE (start, code) <= size);
7267 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7273 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7275 return ctx->regs [reg];
7279 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7281 ctx->regs [reg] = val;
7285 * mono_arch_get_trampolines:
7287 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7291 mono_arch_get_trampolines (gboolean aot)
7293 return mono_arm_get_exception_trampolines (aot);
7297 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7304 bp = MONO_CONTEXT_GET_BP (ctx);
7305 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7307 old_value = *lr_loc;
7308 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7311 *lr_loc = new_value;
7316 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7318 * mono_arch_set_breakpoint:
7320 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7321 * The location should contain code emitted by OP_SEQ_POINT.
7324 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7327 guint32 native_offset = ip - (guint8*)ji->code_start;
7328 MonoDebugOptions *opt = mini_get_debug_options ();
7330 if (opt->soft_breakpoints) {
7331 g_assert (!ji->from_aot);
7333 ARM_BLX_REG (code, ARMREG_LR);
7334 mono_arch_flush_icache (code - 4, 4);
7335 } else if (ji->from_aot) {
7336 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7338 g_assert (native_offset % 4 == 0);
7339 g_assert (info->bp_addrs [native_offset / 4] == 0);
7340 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7342 int dreg = ARMREG_LR;
7344 /* Read from another trigger page */
7345 #ifdef USE_JUMP_TABLES
7346 gpointer *jte = mono_jumptable_add_entry ();
7347 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7348 jte [0] = bp_trigger_page;
7350 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7352 *(int*)code = (int)bp_trigger_page;
7355 ARM_LDR_IMM (code, dreg, dreg, 0);
7357 mono_arch_flush_icache (code - 16, 16);
7360 /* This is currently implemented by emitting an SWI instruction, which
7361 * qemu/linux seems to convert to a SIGILL.
7363 *(int*)code = (0xef << 24) | 8;
7365 mono_arch_flush_icache (code - 4, 4);
7371 * mono_arch_clear_breakpoint:
7373 * Clear the breakpoint at IP.
7376 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7378 MonoDebugOptions *opt = mini_get_debug_options ();
7382 if (opt->soft_breakpoints) {
7383 g_assert (!ji->from_aot);
7386 mono_arch_flush_icache (code - 4, 4);
7387 } else if (ji->from_aot) {
7388 guint32 native_offset = ip - (guint8*)ji->code_start;
7389 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7391 g_assert (native_offset % 4 == 0);
7392 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7393 info->bp_addrs [native_offset / 4] = 0;
7395 for (i = 0; i < 4; ++i)
7398 mono_arch_flush_icache (ip, code - ip);
7403 * mono_arch_start_single_stepping:
7405 * Start single stepping.
7408 mono_arch_start_single_stepping (void)
7410 if (ss_trigger_page)
7411 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7413 single_step_tramp = mini_get_single_step_trampoline ();
7417 * mono_arch_stop_single_stepping:
7419 * Stop single stepping.
7422 mono_arch_stop_single_stepping (void)
7424 if (ss_trigger_page)
7425 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7427 single_step_tramp = NULL;
7431 #define DBG_SIGNAL SIGBUS
7433 #define DBG_SIGNAL SIGSEGV
7437 * mono_arch_is_single_step_event:
7439 * Return whenever the machine state in SIGCTX corresponds to a single
7443 mono_arch_is_single_step_event (void *info, void *sigctx)
7445 siginfo_t *sinfo = info;
7447 if (!ss_trigger_page)
7450 /* Sometimes the address is off by 4 */
7451 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7458 * mono_arch_is_breakpoint_event:
7460 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7463 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7465 siginfo_t *sinfo = info;
7467 if (!ss_trigger_page)
7470 if (sinfo->si_signo == DBG_SIGNAL) {
7471 /* Sometimes the address is off by 4 */
7472 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7482 * mono_arch_skip_breakpoint:
7484 * See mini-amd64.c for docs.
7487 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7489 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7493 * mono_arch_skip_single_step:
7495 * See mini-amd64.c for docs.
7498 mono_arch_skip_single_step (MonoContext *ctx)
7500 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7503 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7506 * mono_arch_get_seq_point_info:
7508 * See mini-amd64.c for docs.
7511 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7516 // FIXME: Add a free function
7518 mono_domain_lock (domain);
7519 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7521 mono_domain_unlock (domain);
7524 ji = mono_jit_info_table_find (domain, (char*)code);
7527 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7529 info->ss_trigger_page = ss_trigger_page;
7530 info->bp_trigger_page = bp_trigger_page;
7532 mono_domain_lock (domain);
7533 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7535 mono_domain_unlock (domain);
7542 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7544 ext->lmf.previous_lmf = prev_lmf;
7545 /* Mark that this is a MonoLMFExt */
7546 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7547 ext->lmf.sp = (gssize)ext;
7551 * mono_arch_set_target:
7553 * Set the target architecture the JIT backend should generate code for, in the form
7554 * of a GNU target triplet. Only used in AOT mode.
7557 mono_arch_set_target (char *mtriple)
7559 /* The GNU target triple format is not very well documented */
7560 if (strstr (mtriple, "armv7")) {
7561 v5_supported = TRUE;
7562 v6_supported = TRUE;
7563 v7_supported = TRUE;
7565 if (strstr (mtriple, "armv6")) {
7566 v5_supported = TRUE;
7567 v6_supported = TRUE;
7569 if (strstr (mtriple, "armv7s")) {
7570 v7s_supported = TRUE;
7572 if (strstr (mtriple, "armv7k")) {
7573 v7k_supported = TRUE;
7575 if (strstr (mtriple, "thumbv7s")) {
7576 v5_supported = TRUE;
7577 v6_supported = TRUE;
7578 v7_supported = TRUE;
7579 v7s_supported = TRUE;
7580 thumb_supported = TRUE;
7581 thumb2_supported = TRUE;
7583 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7584 v5_supported = TRUE;
7585 v6_supported = TRUE;
7586 thumb_supported = TRUE;
7589 if (strstr (mtriple, "gnueabi"))
7590 eabi_supported = TRUE;
7594 mono_arch_opcode_supported (int opcode)
7597 case OP_ATOMIC_ADD_I4:
7598 case OP_ATOMIC_EXCHANGE_I4:
7599 case OP_ATOMIC_CAS_I4:
7600 case OP_ATOMIC_LOAD_I1:
7601 case OP_ATOMIC_LOAD_I2:
7602 case OP_ATOMIC_LOAD_I4:
7603 case OP_ATOMIC_LOAD_U1:
7604 case OP_ATOMIC_LOAD_U2:
7605 case OP_ATOMIC_LOAD_U4:
7606 case OP_ATOMIC_STORE_I1:
7607 case OP_ATOMIC_STORE_I2:
7608 case OP_ATOMIC_STORE_I4:
7609 case OP_ATOMIC_STORE_U1:
7610 case OP_ATOMIC_STORE_U2:
7611 case OP_ATOMIC_STORE_U4:
7612 return v7_supported;
7613 case OP_ATOMIC_LOAD_R4:
7614 case OP_ATOMIC_LOAD_R8:
7615 case OP_ATOMIC_STORE_R4:
7616 case OP_ATOMIC_STORE_R8:
7617 return v7_supported && IS_VFP;
7624 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7626 return get_call_info (mp, sig);