3 * ARM backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
11 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
17 #include <mono/metadata/abi-details.h>
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/utils/mono-mmap.h>
22 #include <mono/utils/mono-hwcap.h>
23 #include <mono/utils/mono-memory-model.h>
24 #include <mono/utils/mono-threads-coop.h>
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 /* Sanity check: This makes no sense */
35 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
36 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
40 * IS_SOFT_FLOAT: Is full software floating point used?
41 * IS_HARD_FLOAT: Is full hardware floating point used?
42 * IS_VFP: Is hardware floating point with software ABI used?
44 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
45 * IS_VFP may delegate to mono_arch_is_soft_float ().
48 #if defined(ARM_FPU_VFP_HARD)
49 #define IS_SOFT_FLOAT (FALSE)
50 #define IS_HARD_FLOAT (TRUE)
52 #elif defined(ARM_FPU_NONE)
53 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
54 #define IS_HARD_FLOAT (FALSE)
55 #define IS_VFP (!mono_arch_is_soft_float ())
57 #define IS_SOFT_FLOAT (FALSE)
58 #define IS_HARD_FLOAT (FALSE)
62 #define THUNK_SIZE (3 * 4)
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
67 void sys_icache_invalidate (void *start, size_t len);
70 /* This mutex protects architecture specific caches */
71 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
72 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
73 static mono_mutex_t mini_arch_mutex;
75 static gboolean v5_supported = FALSE;
76 static gboolean v6_supported = FALSE;
77 static gboolean v7_supported = FALSE;
78 static gboolean v7s_supported = FALSE;
79 static gboolean v7k_supported = FALSE;
80 static gboolean thumb_supported = FALSE;
81 static gboolean thumb2_supported = FALSE;
83 * Whenever to use the ARM EABI
85 static gboolean eabi_supported = FALSE;
88 * Whenever to use the iphone ABI extensions:
89 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
90 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
91 * This is required for debugging/profiling tools to work, but it has some overhead so it should
92 * only be turned on in debug builds.
94 static gboolean iphone_abi = FALSE;
97 * The FPU we are generating code for. This is NOT runtime configurable right now,
98 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
100 static MonoArmFPU arm_fpu;
102 #if defined(ARM_FPU_VFP_HARD)
104 * On armhf, d0-d7 are used for argument passing and d8-d15
105 * must be preserved across calls, which leaves us no room
106 * for scratch registers. So we use d14-d15 but back up their
107 * previous contents to a stack slot before using them - see
108 * mono_arm_emit_vfp_scratch_save/_restore ().
110 static int vfp_scratch1 = ARM_VFP_D14;
111 static int vfp_scratch2 = ARM_VFP_D15;
114 * On armel, d0-d7 do not need to be preserved, so we can
115 * freely make use of them as scratch registers.
117 static int vfp_scratch1 = ARM_VFP_D0;
118 static int vfp_scratch2 = ARM_VFP_D1;
123 static gpointer single_step_tramp, breakpoint_tramp;
124 static gpointer get_tls_tramp;
127 * The code generated for sequence points reads from this location, which is
128 * made read-only when single stepping is enabled.
130 static gpointer ss_trigger_page;
132 /* Enabled breakpoints read from this trigger page */
133 static gpointer bp_trigger_page;
137 * floating point support: on ARM it is a mess, there are at least 3
138 * different setups, each of which binary incompat with the other.
139 * 1) FPA: old and ugly, but unfortunately what current distros use
140 * the double binary format has the two words swapped. 8 double registers.
141 * Implemented usually by kernel emulation.
142 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
143 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
144 * 3) VFP: the new and actually sensible and useful FP support. Implemented
145 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
147 * We do not care about FPA. We will support soft float and VFP.
149 int mono_exc_esp_offset = 0;
151 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
152 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
153 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
155 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
156 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
157 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
159 //#define DEBUG_IMT 0
162 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
166 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
169 mono_arch_regname (int reg)
171 static const char * rnames[] = {
172 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
173 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
174 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
177 if (reg >= 0 && reg < 16)
183 mono_arch_fregname (int reg)
185 static const char * rnames[] = {
186 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
187 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
188 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
189 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
190 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
191 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
194 if (reg >= 0 && reg < 32)
202 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
204 int imm8, rot_amount;
205 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
206 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
210 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
211 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
213 code = mono_arm_emit_load_imm (code, dreg, imm);
214 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
219 /* If dreg == sreg, this clobbers IP */
221 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
223 int imm8, rot_amount;
224 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
225 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
229 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
230 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
232 code = mono_arm_emit_load_imm (code, dreg, imm);
233 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
239 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
241 /* we can use r0-r3, since this is called only for incoming args on the stack */
242 if (size > sizeof (gpointer) * 4) {
244 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
245 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
246 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
247 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
248 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
250 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
251 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
252 ARM_B_COND (code, ARMCOND_NE, 0);
253 arm_patch (code - 4, start_loop);
256 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
257 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
259 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
260 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
266 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
267 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
268 doffset = soffset = 0;
270 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
271 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
277 g_assert (size == 0);
282 emit_call_reg (guint8 *code, int reg)
285 ARM_BLX_REG (code, reg);
287 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
291 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
297 emit_call_seq (MonoCompile *cfg, guint8 *code)
299 if (cfg->method->dynamic) {
300 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
302 *(gpointer*)code = NULL;
304 code = emit_call_reg (code, ARMREG_IP);
308 cfg->thunk_area += THUNK_SIZE;
313 mono_arm_patchable_b (guint8 *code, int cond)
315 ARM_B_COND (code, cond, 0);
320 mono_arm_patchable_bl (guint8 *code, int cond)
322 ARM_BL_COND (code, cond, 0);
326 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__) && !defined(MONO_CROSS_COMPILE)
327 #define HAVE_AEABI_READ_TP 1
330 #ifdef HAVE_AEABI_READ_TP
331 gpointer __aeabi_read_tp (void);
335 mono_arch_have_fast_tls (void)
337 #ifdef HAVE_AEABI_READ_TP
338 static gboolean have_fast_tls = FALSE;
339 static gboolean inited = FALSE;
341 if (mini_get_debug_options ()->use_fallback_tls)
345 return have_fast_tls;
350 tp1 = __aeabi_read_tp ();
351 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
353 have_fast_tls = tp1 && tp1 == tp2;
356 return have_fast_tls;
363 emit_tls_get (guint8 *code, int dreg, int tls_offset)
365 g_assert (v7_supported);
366 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
367 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
372 emit_tls_set (guint8 *code, int sreg, int tls_offset)
374 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
375 g_assert (v7_supported);
376 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
377 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
384 * Emit code to push an LMF structure on the LMF stack.
385 * On arm, this is intermixed with the initialization of other fields of the structure.
388 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
392 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
393 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
395 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
396 (gpointer)"mono_tls_get_lmf_addr");
397 code = emit_call_seq (cfg, code);
399 /* we build the MonoLMF structure on the stack - see mini-arm.h */
400 /* lmf_offset is the offset from the previous stack pointer,
401 * alloc_size is the total stack space allocated, so the offset
402 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
403 * The pointer to the struct is put in r1 (new_lmf).
404 * ip is used as scratch
405 * The callee-saved registers are already in the MonoLMF structure
407 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
408 /* r0 is the result from mono_get_lmf_addr () */
409 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
410 /* new_lmf->previous_lmf = *lmf_addr */
411 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
412 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
413 /* *(lmf_addr) = r1 */
414 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
415 /* Skip method (only needed for trampoline LMF frames) */
416 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
417 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
418 /* save the current IP */
419 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
420 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
422 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
423 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
434 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
438 for (list = inst->float_args; list; list = list->next) {
439 FloatArgData *fad = list->data;
440 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
441 gboolean imm = arm_is_fpimm8 (var->inst_offset);
443 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
449 if (*offset + *max_len > cfg->code_size) {
450 cfg->code_size += *max_len;
451 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
453 code = cfg->native_code + *offset;
457 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
458 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
460 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
462 *offset = code - cfg->native_code;
469 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
473 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
475 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
478 if (!arm_is_fpimm8 (inst->inst_offset)) {
479 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
480 ARM_FSTD (code, reg, ARMREG_LR, 0);
482 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
489 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
493 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
495 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
498 if (!arm_is_fpimm8 (inst->inst_offset)) {
499 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
500 ARM_FLDD (code, reg, ARMREG_LR, 0);
502 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
511 * Emit code to pop an LMF structure from the LMF stack.
514 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
518 if (lmf_offset < 32) {
519 basereg = cfg->frame_reg;
524 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
527 /* ip = previous_lmf */
528 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
530 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
531 /* *(lmf_addr) = previous_lmf */
532 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
537 #endif /* #ifndef DISABLE_JIT */
540 * mono_arch_get_argument_info:
541 * @csig: a method signature
542 * @param_count: the number of parameters to consider
543 * @arg_info: an array to store the result infos
545 * Gathers information on parameters such as size, alignment and
546 * padding. arg_info should be large enought to hold param_count + 1 entries.
548 * Returns the size of the activation frame.
551 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
553 int k, frame_size = 0;
554 guint32 size, align, pad;
558 t = mini_get_underlying_type (csig->ret);
559 if (MONO_TYPE_ISSTRUCT (t)) {
560 frame_size += sizeof (gpointer);
564 arg_info [0].offset = offset;
567 frame_size += sizeof (gpointer);
571 arg_info [0].size = frame_size;
573 for (k = 0; k < param_count; k++) {
574 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
576 /* ignore alignment for now */
579 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
580 arg_info [k].pad = pad;
582 arg_info [k + 1].pad = 0;
583 arg_info [k + 1].size = size;
585 arg_info [k + 1].offset = offset;
589 align = MONO_ARCH_FRAME_ALIGNMENT;
590 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
591 arg_info [k].pad = pad;
596 #define MAX_ARCH_DELEGATE_PARAMS 3
599 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
601 guint8 *code, *start;
602 GSList *unwind_ops = mono_arch_get_cie_program ();
605 start = code = mono_global_codeman_reserve (12);
607 /* Replace the this argument with the target */
608 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
609 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
610 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
612 g_assert ((code - start) <= 12);
614 mono_arch_flush_icache (start, 12);
618 size = 8 + param_count * 4;
619 start = code = mono_global_codeman_reserve (size);
621 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
622 /* slide down the arguments */
623 for (i = 0; i < param_count; ++i) {
624 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
626 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
628 g_assert ((code - start) <= size);
630 mono_arch_flush_icache (start, size);
634 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
636 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
637 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
641 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
647 * mono_arch_get_delegate_invoke_impls:
649 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
653 mono_arch_get_delegate_invoke_impls (void)
659 get_delegate_invoke_impl (&info, TRUE, 0);
660 res = g_slist_prepend (res, info);
662 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
663 get_delegate_invoke_impl (&info, FALSE, i);
664 res = g_slist_prepend (res, info);
671 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
673 guint8 *code, *start;
676 /* FIXME: Support more cases */
677 sig_ret = mini_get_underlying_type (sig->ret);
678 if (MONO_TYPE_ISSTRUCT (sig_ret))
682 static guint8* cached = NULL;
683 mono_mini_arch_lock ();
685 mono_mini_arch_unlock ();
690 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
693 start = get_delegate_invoke_impl (&info, TRUE, 0);
694 mono_tramp_info_register (info, NULL);
697 mono_mini_arch_unlock ();
700 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
703 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
705 for (i = 0; i < sig->param_count; ++i)
706 if (!mono_is_regsize_var (sig->params [i]))
709 mono_mini_arch_lock ();
710 code = cache [sig->param_count];
712 mono_mini_arch_unlock ();
717 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
718 start = mono_aot_get_trampoline (name);
722 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
723 mono_tramp_info_register (info, NULL);
725 cache [sig->param_count] = start;
726 mono_mini_arch_unlock ();
734 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
740 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
742 return (gpointer)regs [ARMREG_R0];
746 * Initialize the cpu to execute managed code.
749 mono_arch_cpu_init (void)
751 i8_align = MONO_ABI_ALIGNOF (gint64);
752 #ifdef MONO_CROSS_COMPILE
753 /* Need to set the alignment of i8 since it can different on the target */
754 #ifdef TARGET_ANDROID
756 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
762 * Initialize architecture specific code.
765 mono_arch_init (void)
767 const char *cpu_arch;
769 #ifdef TARGET_WATCHOS
770 mini_get_debug_options ()->soft_breakpoints = TRUE;
773 mono_os_mutex_init_recursive (&mini_arch_mutex);
774 if (mini_get_debug_options ()->soft_breakpoints) {
776 breakpoint_tramp = mini_get_breakpoint_trampoline ();
778 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
779 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
780 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
783 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
784 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
785 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
786 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
787 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
789 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
790 mono_aot_register_jit_icall ("mono_arm_handler_block_trampoline_helper", mono_arm_handler_block_trampoline_helper);
791 #if defined(__ARM_EABI__)
792 eabi_supported = TRUE;
795 #if defined(ARM_FPU_VFP_HARD)
796 arm_fpu = MONO_ARM_FPU_VFP_HARD;
798 arm_fpu = MONO_ARM_FPU_VFP;
800 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
802 * If we're compiling with a soft float fallback and it
803 * turns out that no VFP unit is available, we need to
804 * switch to soft float. We don't do this for iOS, since
805 * iOS devices always have a VFP unit.
807 if (!mono_hwcap_arm_has_vfp)
808 arm_fpu = MONO_ARM_FPU_NONE;
811 * This environment variable can be useful in testing
812 * environments to make sure the soft float fallback
813 * works. Most ARM devices have VFP units these days, so
814 * normally soft float code would not be exercised much.
816 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
818 if (soft && !strncmp (soft, "1", 1))
819 arm_fpu = MONO_ARM_FPU_NONE;
824 v5_supported = mono_hwcap_arm_is_v5;
825 v6_supported = mono_hwcap_arm_is_v6;
826 v7_supported = mono_hwcap_arm_is_v7;
829 * On weird devices, the hwcap code may fail to detect
830 * the ARM version. In that case, we can at least safely
831 * assume the version the runtime was compiled for.
843 #if defined(TARGET_IOS)
844 /* iOS is special-cased here because we don't yet
845 have a way to properly detect CPU features on it. */
846 thumb_supported = TRUE;
849 thumb_supported = mono_hwcap_arm_has_thumb;
850 thumb2_supported = mono_hwcap_arm_has_thumb2;
853 /* Format: armv(5|6|7[s])[-thumb[2]] */
854 cpu_arch = g_getenv ("MONO_CPU_ARCH");
856 /* Do this here so it overrides any detection. */
858 if (strncmp (cpu_arch, "armv", 4) == 0) {
859 v5_supported = cpu_arch [4] >= '5';
860 v6_supported = cpu_arch [4] >= '6';
861 v7_supported = cpu_arch [4] >= '7';
862 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
863 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
866 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
867 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
873 * Cleanup architecture specific code.
876 mono_arch_cleanup (void)
881 * This function returns the optimizations supported on this cpu.
884 mono_arch_cpu_optimizations (guint32 *exclude_mask)
886 /* no arm-specific optimizations yet */
892 * This function test for all SIMD functions supported.
894 * Returns a bitmask corresponding to all supported versions.
898 mono_arch_cpu_enumerate_simd_versions (void)
900 /* SIMD is currently unimplemented */
905 mono_arm_is_hard_float (void)
907 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
913 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
915 if (v7s_supported || v7k_supported) {
929 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
931 mono_arch_is_soft_float (void)
933 return arm_fpu == MONO_ARM_FPU_NONE;
938 is_regsize_var (MonoType *t)
942 t = mini_get_underlying_type (t);
949 case MONO_TYPE_FNPTR:
951 case MONO_TYPE_OBJECT:
953 case MONO_TYPE_GENERICINST:
954 if (!mono_type_generic_inst_is_valuetype (t))
957 case MONO_TYPE_VALUETYPE:
964 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
969 for (i = 0; i < cfg->num_varinfo; i++) {
970 MonoInst *ins = cfg->varinfo [i];
971 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
974 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
977 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
980 /* we can only allocate 32 bit values */
981 if (is_regsize_var (ins->inst_vtype)) {
982 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
983 g_assert (i == vmv->idx);
984 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
992 mono_arch_get_global_int_regs (MonoCompile *cfg)
996 mono_arch_compute_omit_fp (cfg);
999 * FIXME: Interface calls might go through a static rgctx trampoline which
1000 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1003 if (cfg->flags & MONO_CFG_HAS_CALLS)
1004 cfg->uses_rgctx_reg = TRUE;
1006 if (cfg->arch.omit_fp)
1007 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1008 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1009 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1010 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1012 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1013 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1015 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1016 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1017 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1018 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1019 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1020 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1026 * mono_arch_regalloc_cost:
1028 * Return the cost, in number of memory references, of the action of
1029 * allocating the variable VMV into a register during global register
1033 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1039 #endif /* #ifndef DISABLE_JIT */
1042 mono_arch_flush_icache (guint8 *code, gint size)
1044 #if defined(MONO_CROSS_COMPILE)
1046 sys_icache_invalidate (code, size);
1048 __builtin___clear_cache (code, code + size);
1055 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1058 if (*gr > ARMREG_R3) {
1060 ainfo->offset = *stack_size;
1061 ainfo->reg = ARMREG_SP; /* in the caller */
1062 ainfo->storage = RegTypeBase;
1065 ainfo->storage = RegTypeGeneral;
1072 split = i8_align == 4;
1077 if (*gr == ARMREG_R3 && split) {
1078 /* first word in r3 and the second on the stack */
1079 ainfo->offset = *stack_size;
1080 ainfo->reg = ARMREG_SP; /* in the caller */
1081 ainfo->storage = RegTypeBaseGen;
1083 } else if (*gr >= ARMREG_R3) {
1084 if (eabi_supported) {
1085 /* darwin aligns longs to 4 byte only */
1086 if (i8_align == 8) {
1091 ainfo->offset = *stack_size;
1092 ainfo->reg = ARMREG_SP; /* in the caller */
1093 ainfo->storage = RegTypeBase;
1096 if (eabi_supported) {
1097 if (i8_align == 8 && ((*gr) & 1))
1100 ainfo->storage = RegTypeIRegPair;
1109 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1112 * If we're calling a function like this:
1114 * void foo(float a, double b, float c)
1116 * We pass a in s0 and b in d1. That leaves us
1117 * with s1 being unused. The armhf ABI recognizes
1118 * this and requires register assignment to then
1119 * use that for the next single-precision arg,
1120 * i.e. c in this example. So float_spare either
1121 * tells us which reg to use for the next single-
1122 * precision arg, or it's -1, meaning use *fpr.
1124 * Note that even though most of the JIT speaks
1125 * double-precision, fpr represents single-
1126 * precision registers.
1128 * See parts 5.5 and 6.1.2 of the AAPCS for how
1132 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1133 ainfo->storage = RegTypeFP;
1137 * If we're passing a double-precision value
1138 * and *fpr is odd (e.g. it's s1, s3, ...)
1139 * we need to use the next even register. So
1140 * we mark the current *fpr as a spare that
1141 * can be used for the next single-precision
1145 *float_spare = *fpr;
1150 * At this point, we have an even register
1151 * so we assign that and move along.
1155 } else if (*float_spare >= 0) {
1157 * We're passing a single-precision value
1158 * and it looks like a spare single-
1159 * precision register is available. Let's
1163 ainfo->reg = *float_spare;
1167 * If we hit this branch, we're passing a
1168 * single-precision value and we can simply
1169 * use the next available register.
1177 * We've exhausted available floating point
1178 * regs, so pass the rest on the stack.
1186 ainfo->offset = *stack_size;
1187 ainfo->reg = ARMREG_SP;
1188 ainfo->storage = RegTypeBase;
1195 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1199 MonoClassField *field;
1200 MonoType *ftype, *prev_ftype = NULL;
1203 klass = mono_class_from_mono_type (t);
1205 while ((field = mono_class_get_fields (klass, &iter))) {
1206 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1208 ftype = mono_field_get_type (field);
1209 ftype = mini_get_underlying_type (ftype);
1211 if (MONO_TYPE_ISSTRUCT (ftype)) {
1212 int nested_nfields, nested_esize;
1214 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1216 if (nested_esize == 4)
1217 ftype = &mono_defaults.single_class->byval_arg;
1219 ftype = &mono_defaults.double_class->byval_arg;
1220 if (prev_ftype && prev_ftype->type != ftype->type)
1223 nfields += nested_nfields;
1225 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1227 if (prev_ftype && prev_ftype->type != ftype->type)
1233 if (nfields == 0 || nfields > 4)
1235 *out_nfields = nfields;
1236 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1241 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1243 guint i, gr, fpr, pstart;
1245 int n = sig->hasthis + sig->param_count;
1249 guint32 stack_size = 0;
1251 gboolean is_pinvoke = sig->pinvoke;
1252 gboolean vtype_retaddr = FALSE;
1255 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1257 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1264 t = mini_get_underlying_type (sig->ret);
1275 case MONO_TYPE_FNPTR:
1276 case MONO_TYPE_OBJECT:
1277 cinfo->ret.storage = RegTypeGeneral;
1278 cinfo->ret.reg = ARMREG_R0;
1282 cinfo->ret.storage = RegTypeIRegPair;
1283 cinfo->ret.reg = ARMREG_R0;
1287 cinfo->ret.storage = RegTypeFP;
1289 if (t->type == MONO_TYPE_R4)
1290 cinfo->ret.size = 4;
1292 cinfo->ret.size = 8;
1294 if (IS_HARD_FLOAT) {
1295 cinfo->ret.reg = ARM_VFP_F0;
1297 cinfo->ret.reg = ARMREG_R0;
1300 case MONO_TYPE_GENERICINST:
1301 if (!mono_type_generic_inst_is_valuetype (t)) {
1302 cinfo->ret.storage = RegTypeGeneral;
1303 cinfo->ret.reg = ARMREG_R0;
1306 if (mini_is_gsharedvt_variable_type (t)) {
1307 cinfo->ret.storage = RegTypeStructByAddr;
1311 case MONO_TYPE_VALUETYPE:
1312 case MONO_TYPE_TYPEDBYREF:
1313 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1314 cinfo->ret.storage = RegTypeHFA;
1316 cinfo->ret.nregs = nfields;
1317 cinfo->ret.esize = esize;
1320 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1323 #ifdef TARGET_WATCHOS
1328 if (native_size <= max_size) {
1329 cinfo->ret.storage = RegTypeStructByVal;
1330 cinfo->ret.struct_size = native_size;
1331 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1333 cinfo->ret.storage = RegTypeStructByAddr;
1336 cinfo->ret.storage = RegTypeStructByAddr;
1341 case MONO_TYPE_MVAR:
1342 g_assert (mini_is_gsharedvt_type (t));
1343 cinfo->ret.storage = RegTypeStructByAddr;
1345 case MONO_TYPE_VOID:
1348 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1351 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1356 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1357 * the first argument, allowing 'this' to be always passed in the first arg reg.
1358 * Also do this if the first argument is a reference type, since virtual calls
1359 * are sometimes made using calli without sig->hasthis set, like in the delegate
1362 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1364 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1366 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1370 cinfo->ret.reg = gr;
1372 cinfo->vret_arg_index = 1;
1376 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1379 if (vtype_retaddr) {
1380 cinfo->ret.reg = gr;
1385 DEBUG(g_print("params: %d\n", sig->param_count));
1386 for (i = pstart; i < sig->param_count; ++i) {
1387 ArgInfo *ainfo = &cinfo->args [n];
1389 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1390 /* Prevent implicit arguments and sig_cookie from
1391 being passed in registers */
1394 /* Emit the signature cookie just before the implicit arguments */
1395 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1397 DEBUG(g_print("param %d: ", i));
1398 if (sig->params [i]->byref) {
1399 DEBUG(g_print("byref\n"));
1400 add_general (&gr, &stack_size, ainfo, TRUE);
1404 t = mini_get_underlying_type (sig->params [i]);
1408 cinfo->args [n].size = 1;
1409 add_general (&gr, &stack_size, ainfo, TRUE);
1413 cinfo->args [n].size = 2;
1414 add_general (&gr, &stack_size, ainfo, TRUE);
1418 cinfo->args [n].size = 4;
1419 add_general (&gr, &stack_size, ainfo, TRUE);
1424 case MONO_TYPE_FNPTR:
1425 case MONO_TYPE_OBJECT:
1426 cinfo->args [n].size = sizeof (gpointer);
1427 add_general (&gr, &stack_size, ainfo, TRUE);
1429 case MONO_TYPE_GENERICINST:
1430 if (!mono_type_generic_inst_is_valuetype (t)) {
1431 cinfo->args [n].size = sizeof (gpointer);
1432 add_general (&gr, &stack_size, ainfo, TRUE);
1435 if (mini_is_gsharedvt_variable_type (t)) {
1436 /* gsharedvt arguments are passed by ref */
1437 g_assert (mini_is_gsharedvt_type (t));
1438 add_general (&gr, &stack_size, ainfo, TRUE);
1439 switch (ainfo->storage) {
1440 case RegTypeGeneral:
1441 ainfo->storage = RegTypeGSharedVtInReg;
1444 ainfo->storage = RegTypeGSharedVtOnStack;
1447 g_assert_not_reached ();
1452 case MONO_TYPE_TYPEDBYREF:
1453 case MONO_TYPE_VALUETYPE: {
1456 int nwords, nfields, esize;
1459 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1460 if (fpr + nfields < ARM_VFP_F16) {
1461 ainfo->storage = RegTypeHFA;
1463 ainfo->nregs = nfields;
1464 ainfo->esize = esize;
1475 if (t->type == MONO_TYPE_TYPEDBYREF) {
1476 size = sizeof (MonoTypedRef);
1477 align = sizeof (gpointer);
1479 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1481 size = mono_class_native_size (klass, &align);
1483 size = mini_type_stack_size_full (t, &align, FALSE);
1485 DEBUG(g_print ("load %d bytes struct\n", size));
1487 #ifdef TARGET_WATCHOS
1488 /* Watchos pass large structures by ref */
1489 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1490 if (sig->pinvoke && size > 16) {
1491 add_general (&gr, &stack_size, ainfo, TRUE);
1492 switch (ainfo->storage) {
1493 case RegTypeGeneral:
1494 ainfo->storage = RegTypeStructByAddr;
1497 ainfo->storage = RegTypeStructByAddrOnStack;
1500 g_assert_not_reached ();
1509 align_size += (sizeof (gpointer) - 1);
1510 align_size &= ~(sizeof (gpointer) - 1);
1511 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1512 ainfo->storage = RegTypeStructByVal;
1513 ainfo->struct_size = size;
1514 ainfo->align = align;
1515 /* FIXME: align stack_size if needed */
1516 if (eabi_supported) {
1517 if (align >= 8 && (gr & 1))
1520 if (gr > ARMREG_R3) {
1522 ainfo->vtsize = nwords;
1524 int rest = ARMREG_R3 - gr + 1;
1525 int n_in_regs = rest >= nwords? nwords: rest;
1527 ainfo->size = n_in_regs;
1528 ainfo->vtsize = nwords - n_in_regs;
1531 nwords -= n_in_regs;
1533 if (sig->call_convention == MONO_CALL_VARARG)
1534 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1535 stack_size = ALIGN_TO (stack_size, align);
1536 ainfo->offset = stack_size;
1537 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1538 stack_size += nwords * sizeof (gpointer);
1544 add_general (&gr, &stack_size, ainfo, FALSE);
1550 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1552 add_general (&gr, &stack_size, ainfo, TRUE);
1558 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1560 add_general (&gr, &stack_size, ainfo, FALSE);
1563 case MONO_TYPE_MVAR:
1564 /* gsharedvt arguments are passed by ref */
1565 g_assert (mini_is_gsharedvt_type (t));
1566 add_general (&gr, &stack_size, ainfo, TRUE);
1567 switch (ainfo->storage) {
1568 case RegTypeGeneral:
1569 ainfo->storage = RegTypeGSharedVtInReg;
1572 ainfo->storage = RegTypeGSharedVtOnStack;
1575 g_assert_not_reached ();
1579 g_error ("Can't handle 0x%x", sig->params [i]->type);
1584 /* Handle the case where there are no implicit arguments */
1585 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1586 /* Prevent implicit arguments and sig_cookie from
1587 being passed in registers */
1590 /* Emit the signature cookie just before the implicit arguments */
1591 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1594 /* align stack size to 8 */
1595 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1596 stack_size = (stack_size + 7) & ~7;
1598 cinfo->stack_usage = stack_size;
1604 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1606 MonoType *callee_ret;
1610 c1 = get_call_info (NULL, caller_sig);
1611 c2 = get_call_info (NULL, callee_sig);
1614 * Tail calls with more callee stack usage than the caller cannot be supported, since
1615 * the extra stack space would be left on the stack after the tail call.
1617 res = c1->stack_usage >= c2->stack_usage;
1618 callee_ret = mini_get_underlying_type (callee_sig->ret);
1619 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1620 /* An address on the callee's stack is passed as the first argument */
1623 if (c2->stack_usage > 16 * 4)
1635 debug_omit_fp (void)
1638 return mono_debug_count ();
1645 * mono_arch_compute_omit_fp:
1646 * Determine whether the frame pointer can be eliminated.
1649 mono_arch_compute_omit_fp (MonoCompile *cfg)
1651 MonoMethodSignature *sig;
1652 MonoMethodHeader *header;
1656 if (cfg->arch.omit_fp_computed)
1659 header = cfg->header;
1661 sig = mono_method_signature (cfg->method);
1663 if (!cfg->arch.cinfo)
1664 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1665 cinfo = cfg->arch.cinfo;
1668 * FIXME: Remove some of the restrictions.
1670 cfg->arch.omit_fp = TRUE;
1671 cfg->arch.omit_fp_computed = TRUE;
1673 if (cfg->disable_omit_fp)
1674 cfg->arch.omit_fp = FALSE;
1675 if (!debug_omit_fp ())
1676 cfg->arch.omit_fp = FALSE;
1678 if (cfg->method->save_lmf)
1679 cfg->arch.omit_fp = FALSE;
1681 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1682 cfg->arch.omit_fp = FALSE;
1683 if (header->num_clauses)
1684 cfg->arch.omit_fp = FALSE;
1685 if (cfg->param_area)
1686 cfg->arch.omit_fp = FALSE;
1687 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1688 cfg->arch.omit_fp = FALSE;
1689 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1690 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1691 cfg->arch.omit_fp = FALSE;
1692 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1693 ArgInfo *ainfo = &cinfo->args [i];
1695 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1697 * The stack offset can only be determined when the frame
1700 cfg->arch.omit_fp = FALSE;
1705 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1706 MonoInst *ins = cfg->varinfo [i];
1709 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1714 * Set var information according to the calling convention. arm version.
1715 * The locals var stuff should most likely be split in another method.
1718 mono_arch_allocate_vars (MonoCompile *cfg)
1720 MonoMethodSignature *sig;
1721 MonoMethodHeader *header;
1724 int i, offset, size, align, curinst;
1729 sig = mono_method_signature (cfg->method);
1731 if (!cfg->arch.cinfo)
1732 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1733 cinfo = cfg->arch.cinfo;
1734 sig_ret = mini_get_underlying_type (sig->ret);
1736 mono_arch_compute_omit_fp (cfg);
1738 if (cfg->arch.omit_fp)
1739 cfg->frame_reg = ARMREG_SP;
1741 cfg->frame_reg = ARMREG_FP;
1743 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1745 /* allow room for the vararg method args: void* and long/double */
1746 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1747 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1749 header = cfg->header;
1751 /* See mono_arch_get_global_int_regs () */
1752 if (cfg->flags & MONO_CFG_HAS_CALLS)
1753 cfg->uses_rgctx_reg = TRUE;
1755 if (cfg->frame_reg != ARMREG_SP)
1756 cfg->used_int_regs |= 1 << cfg->frame_reg;
1758 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1759 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1760 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1764 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1765 if (sig_ret->type != MONO_TYPE_VOID) {
1766 cfg->ret->opcode = OP_REGVAR;
1767 cfg->ret->inst_c0 = ARMREG_R0;
1770 /* local vars are at a positive offset from the stack pointer */
1772 * also note that if the function uses alloca, we use FP
1773 * to point at the local variables.
1775 offset = 0; /* linkage area */
1776 /* align the offset to 16 bytes: not sure this is needed here */
1778 //offset &= ~(8 - 1);
1780 /* add parameter area size for called functions */
1781 offset += cfg->param_area;
1784 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1787 /* allow room to save the return value */
1788 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1791 switch (cinfo->ret.storage) {
1792 case RegTypeStructByVal:
1794 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1795 offset = ALIGN_TO (offset, 8);
1796 cfg->ret->opcode = OP_REGOFFSET;
1797 cfg->ret->inst_basereg = cfg->frame_reg;
1798 cfg->ret->inst_offset = offset;
1799 if (cinfo->ret.storage == RegTypeStructByVal)
1800 offset += cinfo->ret.nregs * sizeof (gpointer);
1804 case RegTypeStructByAddr:
1805 ins = cfg->vret_addr;
1806 offset += sizeof(gpointer) - 1;
1807 offset &= ~(sizeof(gpointer) - 1);
1808 ins->inst_offset = offset;
1809 ins->opcode = OP_REGOFFSET;
1810 ins->inst_basereg = cfg->frame_reg;
1811 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1812 g_print ("vret_addr =");
1813 mono_print_ins (cfg->vret_addr);
1815 offset += sizeof(gpointer);
1821 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1822 if (cfg->arch.seq_point_info_var) {
1825 ins = cfg->arch.seq_point_info_var;
1829 offset += align - 1;
1830 offset &= ~(align - 1);
1831 ins->opcode = OP_REGOFFSET;
1832 ins->inst_basereg = cfg->frame_reg;
1833 ins->inst_offset = offset;
1836 if (cfg->arch.ss_trigger_page_var) {
1839 ins = cfg->arch.ss_trigger_page_var;
1842 offset += align - 1;
1843 offset &= ~(align - 1);
1844 ins->opcode = OP_REGOFFSET;
1845 ins->inst_basereg = cfg->frame_reg;
1846 ins->inst_offset = offset;
1850 if (cfg->arch.seq_point_ss_method_var) {
1853 ins = cfg->arch.seq_point_ss_method_var;
1856 offset += align - 1;
1857 offset &= ~(align - 1);
1858 ins->opcode = OP_REGOFFSET;
1859 ins->inst_basereg = cfg->frame_reg;
1860 ins->inst_offset = offset;
1863 if (cfg->arch.seq_point_bp_method_var) {
1866 ins = cfg->arch.seq_point_bp_method_var;
1869 offset += align - 1;
1870 offset &= ~(align - 1);
1871 ins->opcode = OP_REGOFFSET;
1872 ins->inst_basereg = cfg->frame_reg;
1873 ins->inst_offset = offset;
1877 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1878 /* Allocate a temporary used by the atomic ops */
1882 /* Allocate a local slot to hold the sig cookie address */
1883 offset += align - 1;
1884 offset &= ~(align - 1);
1885 cfg->arch.atomic_tmp_offset = offset;
1888 cfg->arch.atomic_tmp_offset = -1;
1891 cfg->locals_min_stack_offset = offset;
1893 curinst = cfg->locals_start;
1894 for (i = curinst; i < cfg->num_varinfo; ++i) {
1897 ins = cfg->varinfo [i];
1898 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1901 t = ins->inst_vtype;
1902 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1905 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1906 * pinvoke wrappers when they call functions returning structure */
1907 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1908 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1912 size = mono_type_size (t, &align);
1914 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1915 * since it loads/stores misaligned words, which don't do the right thing.
1917 if (align < 4 && size >= 4)
1919 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1920 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1921 offset += align - 1;
1922 offset &= ~(align - 1);
1923 ins->opcode = OP_REGOFFSET;
1924 ins->inst_offset = offset;
1925 ins->inst_basereg = cfg->frame_reg;
1927 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1930 cfg->locals_max_stack_offset = offset;
1934 ins = cfg->args [curinst];
1935 if (ins->opcode != OP_REGVAR) {
1936 ins->opcode = OP_REGOFFSET;
1937 ins->inst_basereg = cfg->frame_reg;
1938 offset += sizeof (gpointer) - 1;
1939 offset &= ~(sizeof (gpointer) - 1);
1940 ins->inst_offset = offset;
1941 offset += sizeof (gpointer);
1946 if (sig->call_convention == MONO_CALL_VARARG) {
1950 /* Allocate a local slot to hold the sig cookie address */
1951 offset += align - 1;
1952 offset &= ~(align - 1);
1953 cfg->sig_cookie = offset;
1957 for (i = 0; i < sig->param_count; ++i) {
1958 ainfo = cinfo->args + i;
1960 ins = cfg->args [curinst];
1962 switch (ainfo->storage) {
1964 offset = ALIGN_TO (offset, 8);
1965 ins->opcode = OP_REGOFFSET;
1966 ins->inst_basereg = cfg->frame_reg;
1967 /* These arguments are saved to the stack in the prolog */
1968 ins->inst_offset = offset;
1969 if (cfg->verbose_level >= 2)
1970 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1978 if (ins->opcode != OP_REGVAR) {
1979 ins->opcode = OP_REGOFFSET;
1980 ins->inst_basereg = cfg->frame_reg;
1981 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1983 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1984 * since it loads/stores misaligned words, which don't do the right thing.
1986 if (align < 4 && size >= 4)
1988 /* The code in the prolog () stores words when storing vtypes received in a register */
1989 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1991 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1992 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1993 offset += align - 1;
1994 offset &= ~(align - 1);
1995 ins->inst_offset = offset;
2001 /* align the offset to 8 bytes */
2002 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2003 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2008 cfg->stack_offset = offset;
2012 mono_arch_create_vars (MonoCompile *cfg)
2014 MonoMethodSignature *sig;
2018 sig = mono_method_signature (cfg->method);
2020 if (!cfg->arch.cinfo)
2021 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2022 cinfo = cfg->arch.cinfo;
2024 if (IS_HARD_FLOAT) {
2025 for (i = 0; i < 2; i++) {
2026 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2027 inst->flags |= MONO_INST_VOLATILE;
2029 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2033 if (cinfo->ret.storage == RegTypeStructByVal)
2034 cfg->ret_var_is_local = TRUE;
2036 if (cinfo->ret.storage == RegTypeStructByAddr) {
2037 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2038 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2039 g_print ("vret_addr = ");
2040 mono_print_ins (cfg->vret_addr);
2044 if (cfg->gen_sdb_seq_points) {
2045 if (cfg->compile_aot) {
2046 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2047 ins->flags |= MONO_INST_VOLATILE;
2048 cfg->arch.seq_point_info_var = ins;
2050 if (!cfg->soft_breakpoints) {
2051 /* Allocate a separate variable for this to save 1 load per seq point */
2052 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2053 ins->flags |= MONO_INST_VOLATILE;
2054 cfg->arch.ss_trigger_page_var = ins;
2057 if (cfg->soft_breakpoints) {
2060 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2061 ins->flags |= MONO_INST_VOLATILE;
2062 cfg->arch.seq_point_ss_method_var = ins;
2064 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2065 ins->flags |= MONO_INST_VOLATILE;
2066 cfg->arch.seq_point_bp_method_var = ins;
2072 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2074 MonoMethodSignature *tmp_sig;
2077 if (call->tail_call)
2080 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2083 * mono_ArgIterator_Setup assumes the signature cookie is
2084 * passed first and all the arguments which were before it are
2085 * passed on the stack after the signature. So compensate by
2086 * passing a different signature.
2088 tmp_sig = mono_metadata_signature_dup (call->signature);
2089 tmp_sig->param_count -= call->signature->sentinelpos;
2090 tmp_sig->sentinelpos = 0;
2091 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2093 sig_reg = mono_alloc_ireg (cfg);
2094 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2096 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2101 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2106 LLVMCallInfo *linfo;
2108 n = sig->param_count + sig->hasthis;
2110 cinfo = get_call_info (cfg->mempool, sig);
2112 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2115 * LLVM always uses the native ABI while we use our own ABI, the
2116 * only difference is the handling of vtypes:
2117 * - we only pass/receive them in registers in some cases, and only
2118 * in 1 or 2 integer registers.
2120 switch (cinfo->ret.storage) {
2121 case RegTypeGeneral:
2124 case RegTypeIRegPair:
2126 case RegTypeStructByAddr:
2127 /* Vtype returned using a hidden argument */
2128 linfo->ret.storage = LLVMArgVtypeRetAddr;
2129 linfo->vret_arg_index = cinfo->vret_arg_index;
2132 case RegTypeStructByVal:
2133 /* LLVM models this by returning an int array */
2134 linfo->ret.storage = LLVMArgAsIArgs;
2135 linfo->ret.nslots = cinfo->ret.nregs;
2139 linfo->ret.storage = LLVMArgFpStruct;
2140 linfo->ret.nslots = cinfo->ret.nregs;
2141 linfo->ret.esize = cinfo->ret.esize;
2144 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2145 cfg->disable_llvm = TRUE;
2149 for (i = 0; i < n; ++i) {
2150 LLVMArgInfo *lainfo = &linfo->args [i];
2151 ainfo = cinfo->args + i;
2153 lainfo->storage = LLVMArgNone;
2155 switch (ainfo->storage) {
2156 case RegTypeGeneral:
2157 case RegTypeIRegPair:
2159 case RegTypeBaseGen:
2161 lainfo->storage = LLVMArgNormal;
2163 case RegTypeStructByVal:
2164 lainfo->storage = LLVMArgAsIArgs;
2165 if (eabi_supported && ainfo->align == 8) {
2166 /* LLVM models this by passing an int64 array */
2167 lainfo->nslots = ALIGN_TO (ainfo->struct_size, 8) / 8;
2170 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2174 case RegTypeStructByAddr:
2175 case RegTypeStructByAddrOnStack:
2176 lainfo->storage = LLVMArgVtypeByRef;
2181 lainfo->storage = LLVMArgAsFpArgs;
2182 lainfo->nslots = ainfo->nregs;
2183 lainfo->esize = ainfo->esize;
2184 for (j = 0; j < ainfo->nregs; ++j)
2185 lainfo->pair_storage [j] = LLVMArgInFPReg;
2189 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2190 cfg->disable_llvm = TRUE;
2200 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2203 MonoMethodSignature *sig;
2207 sig = call->signature;
2208 n = sig->param_count + sig->hasthis;
2210 cinfo = get_call_info (cfg->mempool, sig);
2212 switch (cinfo->ret.storage) {
2213 case RegTypeStructByVal:
2215 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2216 /* The JIT will transform this into a normal call */
2217 call->vret_in_reg = TRUE;
2220 if (call->inst.opcode == OP_TAILCALL)
2223 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2224 * the location pointed to by it after call in emit_move_return_value ().
2226 if (!cfg->arch.vret_addr_loc) {
2227 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2228 /* Prevent it from being register allocated or optimized away */
2229 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2232 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2234 case RegTypeStructByAddr: {
2236 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2237 vtarg->sreg1 = call->vret_var->dreg;
2238 vtarg->dreg = mono_alloc_preg (cfg);
2239 MONO_ADD_INS (cfg->cbb, vtarg);
2241 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2248 for (i = 0; i < n; ++i) {
2249 ArgInfo *ainfo = cinfo->args + i;
2252 if (i >= sig->hasthis)
2253 t = sig->params [i - sig->hasthis];
2255 t = &mono_defaults.int_class->byval_arg;
2256 t = mini_get_underlying_type (t);
2258 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2259 /* Emit the signature cookie just before the implicit arguments */
2260 emit_sig_cookie (cfg, call, cinfo);
2263 in = call->args [i];
2265 switch (ainfo->storage) {
2266 case RegTypeGeneral:
2267 case RegTypeIRegPair:
2268 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2269 MONO_INST_NEW (cfg, ins, OP_MOVE);
2270 ins->dreg = mono_alloc_ireg (cfg);
2271 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2272 MONO_ADD_INS (cfg->cbb, ins);
2273 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2275 MONO_INST_NEW (cfg, ins, OP_MOVE);
2276 ins->dreg = mono_alloc_ireg (cfg);
2277 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2278 MONO_ADD_INS (cfg->cbb, ins);
2279 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2280 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2281 if (ainfo->size == 4) {
2282 if (IS_SOFT_FLOAT) {
2283 /* mono_emit_call_args () have already done the r8->r4 conversion */
2284 /* The converted value is in an int vreg */
2285 MONO_INST_NEW (cfg, ins, OP_MOVE);
2286 ins->dreg = mono_alloc_ireg (cfg);
2287 ins->sreg1 = in->dreg;
2288 MONO_ADD_INS (cfg->cbb, ins);
2289 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2293 cfg->param_area = MAX (cfg->param_area, 8);
2294 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2295 creg = mono_alloc_ireg (cfg);
2296 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2297 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2300 if (IS_SOFT_FLOAT) {
2301 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2302 ins->dreg = mono_alloc_ireg (cfg);
2303 ins->sreg1 = in->dreg;
2304 MONO_ADD_INS (cfg->cbb, ins);
2305 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2307 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2308 ins->dreg = mono_alloc_ireg (cfg);
2309 ins->sreg1 = in->dreg;
2310 MONO_ADD_INS (cfg->cbb, ins);
2311 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2315 cfg->param_area = MAX (cfg->param_area, 8);
2316 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2317 creg = mono_alloc_ireg (cfg);
2318 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2319 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2320 creg = mono_alloc_ireg (cfg);
2321 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2322 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2325 cfg->flags |= MONO_CFG_HAS_FPOUT;
2327 MONO_INST_NEW (cfg, ins, OP_MOVE);
2328 ins->dreg = mono_alloc_ireg (cfg);
2329 ins->sreg1 = in->dreg;
2330 MONO_ADD_INS (cfg->cbb, ins);
2332 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2335 case RegTypeStructByVal:
2336 case RegTypeGSharedVtInReg:
2337 case RegTypeGSharedVtOnStack:
2339 case RegTypeStructByAddr:
2340 case RegTypeStructByAddrOnStack:
2341 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2342 ins->opcode = OP_OUTARG_VT;
2343 ins->sreg1 = in->dreg;
2344 ins->klass = in->klass;
2345 ins->inst_p0 = call;
2346 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2347 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2348 mono_call_inst_add_outarg_vt (cfg, call, ins);
2349 MONO_ADD_INS (cfg->cbb, ins);
2352 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2353 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2354 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2355 if (t->type == MONO_TYPE_R8) {
2356 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2359 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2361 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2367 case RegTypeBaseGen:
2368 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2369 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2370 MONO_INST_NEW (cfg, ins, OP_MOVE);
2371 ins->dreg = mono_alloc_ireg (cfg);
2372 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2373 MONO_ADD_INS (cfg->cbb, ins);
2374 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2375 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2378 /* This should work for soft-float as well */
2380 cfg->param_area = MAX (cfg->param_area, 8);
2381 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2382 creg = mono_alloc_ireg (cfg);
2383 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2384 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2385 creg = mono_alloc_ireg (cfg);
2386 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2387 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2388 cfg->flags |= MONO_CFG_HAS_FPOUT;
2390 g_assert_not_reached ();
2394 int fdreg = mono_alloc_freg (cfg);
2396 if (ainfo->size == 8) {
2397 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2398 ins->sreg1 = in->dreg;
2400 MONO_ADD_INS (cfg->cbb, ins);
2402 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2407 * Mono's register allocator doesn't speak single-precision registers that
2408 * overlap double-precision registers (i.e. armhf). So we have to work around
2409 * the register allocator and load the value from memory manually.
2411 * So we create a variable for the float argument and an instruction to store
2412 * the argument into the variable. We then store the list of these arguments
2413 * in call->float_args. This list is then used by emit_float_args later to
2414 * pass the arguments in the various call opcodes.
2416 * This is not very nice, and we should really try to fix the allocator.
2419 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2421 /* Make sure the instruction isn't seen as pointless and removed.
2423 float_arg->flags |= MONO_INST_VOLATILE;
2425 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2427 /* We use the dreg to look up the instruction later. The hreg is used to
2428 * emit the instruction that loads the value into the FP reg.
2430 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2431 fad->vreg = float_arg->dreg;
2432 fad->hreg = ainfo->reg;
2434 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2437 call->used_iregs |= 1 << ainfo->reg;
2438 cfg->flags |= MONO_CFG_HAS_FPOUT;
2442 g_assert_not_reached ();
2446 /* Handle the case where there are no implicit arguments */
2447 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2448 emit_sig_cookie (cfg, call, cinfo);
2450 call->call_info = cinfo;
2451 call->stack_usage = cinfo->stack_usage;
2455 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2461 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2462 ins->dreg = mono_alloc_freg (cfg);
2463 ins->sreg1 = arg->dreg;
2464 MONO_ADD_INS (cfg->cbb, ins);
2465 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2468 g_assert_not_reached ();
2474 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2476 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2478 ArgInfo *ainfo = ins->inst_p1;
2479 int ovf_size = ainfo->vtsize;
2480 int doffset = ainfo->offset;
2481 int struct_size = ainfo->struct_size;
2482 int i, soffset, dreg, tmpreg;
2484 switch (ainfo->storage) {
2485 case RegTypeGSharedVtInReg:
2486 case RegTypeStructByAddr:
2488 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2490 case RegTypeGSharedVtOnStack:
2491 case RegTypeStructByAddrOnStack:
2492 /* Pass by addr on stack */
2493 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2496 for (i = 0; i < ainfo->nregs; ++i) {
2497 if (ainfo->esize == 4)
2498 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2500 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2501 load->dreg = mono_alloc_freg (cfg);
2502 load->inst_basereg = src->dreg;
2503 load->inst_offset = i * ainfo->esize;
2504 MONO_ADD_INS (cfg->cbb, load);
2506 if (ainfo->esize == 4) {
2509 /* See RegTypeFP in mono_arch_emit_call () */
2510 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2511 float_arg->flags |= MONO_INST_VOLATILE;
2512 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2514 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2515 fad->vreg = float_arg->dreg;
2516 fad->hreg = ainfo->reg + i;
2518 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2520 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2526 for (i = 0; i < ainfo->size; ++i) {
2527 dreg = mono_alloc_ireg (cfg);
2528 switch (struct_size) {
2530 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2533 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2536 tmpreg = mono_alloc_ireg (cfg);
2537 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2538 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2539 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2540 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2541 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2542 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2543 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2546 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2549 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2550 soffset += sizeof (gpointer);
2551 struct_size -= sizeof (gpointer);
2553 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2555 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2561 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2563 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2566 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2569 if (COMPILE_LLVM (cfg)) {
2570 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2572 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2573 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2574 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2575 MONO_ADD_INS (cfg->cbb, ins);
2580 case MONO_ARM_FPU_NONE:
2581 if (ret->type == MONO_TYPE_R8) {
2584 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2585 ins->dreg = cfg->ret->dreg;
2586 ins->sreg1 = val->dreg;
2587 MONO_ADD_INS (cfg->cbb, ins);
2590 if (ret->type == MONO_TYPE_R4) {
2591 /* Already converted to an int in method_to_ir () */
2592 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2596 case MONO_ARM_FPU_VFP:
2597 case MONO_ARM_FPU_VFP_HARD:
2598 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2601 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2602 ins->dreg = cfg->ret->dreg;
2603 ins->sreg1 = val->dreg;
2604 MONO_ADD_INS (cfg->cbb, ins);
2609 g_assert_not_reached ();
2613 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2616 #endif /* #ifndef DISABLE_JIT */
2619 mono_arch_is_inst_imm (gint64 imm)
2625 MonoMethodSignature *sig;
2628 MonoType **param_types;
2632 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2636 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2639 switch (cinfo->ret.storage) {
2641 case RegTypeGeneral:
2642 case RegTypeIRegPair:
2643 case RegTypeStructByAddr:
2654 for (i = 0; i < cinfo->nargs; ++i) {
2655 ArgInfo *ainfo = &cinfo->args [i];
2658 switch (ainfo->storage) {
2659 case RegTypeGeneral:
2660 case RegTypeIRegPair:
2661 case RegTypeBaseGen:
2665 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2668 case RegTypeStructByVal:
2669 if (ainfo->size == 0)
2670 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2672 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2673 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2681 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2682 for (i = 0; i < sig->param_count; ++i) {
2683 MonoType *t = sig->params [i];
2688 t = mini_get_underlying_type (t);
2711 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2713 ArchDynCallInfo *info;
2717 cinfo = get_call_info (NULL, sig);
2719 if (!dyn_call_supported (cinfo, sig)) {
2724 info = g_new0 (ArchDynCallInfo, 1);
2725 // FIXME: Preprocess the info to speed up start_dyn_call ()
2727 info->cinfo = cinfo;
2728 info->rtype = mini_get_underlying_type (sig->ret);
2729 info->param_types = g_new0 (MonoType*, sig->param_count);
2730 for (i = 0; i < sig->param_count; ++i)
2731 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2733 return (MonoDynCallInfo*)info;
2737 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2739 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2741 g_free (ainfo->cinfo);
2746 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2748 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2749 DynCallArgs *p = (DynCallArgs*)buf;
2750 int arg_index, greg, i, j, pindex;
2751 MonoMethodSignature *sig = dinfo->sig;
2753 g_assert (buf_len >= sizeof (DynCallArgs));
2763 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2764 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2769 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2770 p->regs [greg ++] = (mgreg_t)ret;
2772 for (i = pindex; i < sig->param_count; i++) {
2773 MonoType *t = dinfo->param_types [i];
2774 gpointer *arg = args [arg_index ++];
2775 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2778 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2780 } else if (ainfo->storage == RegTypeFP) {
2781 } else if (ainfo->storage == RegTypeBase) {
2782 slot = PARAM_REGS + (ainfo->offset / 4);
2783 } else if (ainfo->storage == RegTypeBaseGen) {
2784 /* slot + 1 is the first stack slot, so the code below will work */
2787 g_assert_not_reached ();
2791 p->regs [slot] = (mgreg_t)*arg;
2796 case MONO_TYPE_OBJECT:
2800 p->regs [slot] = (mgreg_t)*arg;
2803 p->regs [slot] = *(guint8*)arg;
2806 p->regs [slot] = *(gint8*)arg;
2809 p->regs [slot] = *(gint16*)arg;
2812 p->regs [slot] = *(guint16*)arg;
2815 p->regs [slot] = *(gint32*)arg;
2818 p->regs [slot] = *(guint32*)arg;
2822 p->regs [slot ++] = (mgreg_t)arg [0];
2823 p->regs [slot] = (mgreg_t)arg [1];
2826 if (ainfo->storage == RegTypeFP) {
2827 float f = *(float*)arg;
2828 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2831 p->regs [slot] = *(mgreg_t*)arg;
2835 if (ainfo->storage == RegTypeFP) {
2836 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2839 p->regs [slot ++] = (mgreg_t)arg [0];
2840 p->regs [slot] = (mgreg_t)arg [1];
2843 case MONO_TYPE_GENERICINST:
2844 if (MONO_TYPE_IS_REFERENCE (t)) {
2845 p->regs [slot] = (mgreg_t)*arg;
2848 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2849 MonoClass *klass = mono_class_from_mono_type (t);
2850 guint8 *nullable_buf;
2853 size = mono_class_value_size (klass, NULL);
2854 nullable_buf = g_alloca (size);
2855 g_assert (nullable_buf);
2857 /* The argument pointed to by arg is either a boxed vtype or null */
2858 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2860 arg = (gpointer*)nullable_buf;
2866 case MONO_TYPE_VALUETYPE:
2867 g_assert (ainfo->storage == RegTypeStructByVal);
2869 if (ainfo->size == 0)
2870 slot = PARAM_REGS + (ainfo->offset / 4);
2874 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2875 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2878 g_assert_not_reached ();
2884 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2886 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2887 DynCallArgs *p = (DynCallArgs*)buf;
2888 MonoType *ptype = ainfo->rtype;
2889 guint8 *ret = p->ret;
2890 mgreg_t res = p->res;
2891 mgreg_t res2 = p->res2;
2893 switch (ptype->type) {
2894 case MONO_TYPE_VOID:
2895 *(gpointer*)ret = NULL;
2897 case MONO_TYPE_OBJECT:
2901 *(gpointer*)ret = (gpointer)res;
2907 *(guint8*)ret = res;
2910 *(gint16*)ret = res;
2913 *(guint16*)ret = res;
2916 *(gint32*)ret = res;
2919 *(guint32*)ret = res;
2923 /* This handles endianness as well */
2924 ((gint32*)ret) [0] = res;
2925 ((gint32*)ret) [1] = res2;
2927 case MONO_TYPE_GENERICINST:
2928 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2929 *(gpointer*)ret = (gpointer)res;
2934 case MONO_TYPE_VALUETYPE:
2935 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2941 *(float*)ret = *(float*)&p->fpregs [0];
2943 *(float*)ret = *(float*)&res;
2945 case MONO_TYPE_R8: {
2949 if (IS_HARD_FLOAT) {
2950 *(double*)ret = p->fpregs [0];
2955 *(double*)ret = *(double*)®s;
2960 g_assert_not_reached ();
2967 * Allow tracing to work with this interface (with an optional argument)
2971 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2975 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2976 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2977 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2978 code = emit_call_reg (code, ARMREG_R2);
2992 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2995 int save_mode = SAVE_NONE;
2997 MonoMethod *method = cfg->method;
2998 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
2999 int rtype = ret_type->type;
3000 int save_offset = cfg->param_area;
3004 offset = code - cfg->native_code;
3005 /* we need about 16 instructions */
3006 if (offset > (cfg->code_size - 16 * 4)) {
3007 cfg->code_size *= 2;
3008 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3009 code = cfg->native_code + offset;
3012 case MONO_TYPE_VOID:
3013 /* special case string .ctor icall */
3014 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3015 save_mode = SAVE_ONE;
3017 save_mode = SAVE_NONE;
3021 save_mode = SAVE_TWO;
3025 save_mode = SAVE_ONE_FP;
3027 save_mode = SAVE_ONE;
3031 save_mode = SAVE_TWO_FP;
3033 save_mode = SAVE_TWO;
3035 case MONO_TYPE_GENERICINST:
3036 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3037 save_mode = SAVE_ONE;
3041 case MONO_TYPE_VALUETYPE:
3042 save_mode = SAVE_STRUCT;
3045 save_mode = SAVE_ONE;
3049 switch (save_mode) {
3051 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3052 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3053 if (enable_arguments) {
3054 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3055 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3059 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3060 if (enable_arguments) {
3061 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3065 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3066 if (enable_arguments) {
3067 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3071 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3072 if (enable_arguments) {
3073 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3077 if (enable_arguments) {
3078 /* FIXME: get the actual address */
3079 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3087 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3088 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3089 code = emit_call_reg (code, ARMREG_IP);
3091 switch (save_mode) {
3093 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3094 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3097 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3100 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3103 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3114 * The immediate field for cond branches is big enough for all reasonable methods
3116 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3117 if (0 && ins->inst_true_bb->native_offset) { \
3118 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3120 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3121 ARM_B_COND (code, (condcode), 0); \
3124 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3126 /* emit an exception if condition is fail
3128 * We assign the extra code used to throw the implicit exceptions
3129 * to cfg->bb_exit as far as the big branch handling is concerned
3131 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3133 mono_add_patch_info (cfg, code - cfg->native_code, \
3134 MONO_PATCH_INFO_EXC, exc_name); \
3135 ARM_BL_COND (code, (condcode), 0); \
3138 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3141 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3146 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3150 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3151 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3153 switch (ins->opcode) {
3156 /* Already done by an arch-independent pass */
3158 case OP_LOAD_MEMBASE:
3159 case OP_LOADI4_MEMBASE:
3161 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3162 * OP_LOAD_MEMBASE offset(basereg), reg
3164 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3165 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3166 ins->inst_basereg == last_ins->inst_destbasereg &&
3167 ins->inst_offset == last_ins->inst_offset) {
3168 if (ins->dreg == last_ins->sreg1) {
3169 MONO_DELETE_INS (bb, ins);
3172 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3173 ins->opcode = OP_MOVE;
3174 ins->sreg1 = last_ins->sreg1;
3178 * Note: reg1 must be different from the basereg in the second load
3179 * OP_LOAD_MEMBASE offset(basereg), reg1
3180 * OP_LOAD_MEMBASE offset(basereg), reg2
3182 * OP_LOAD_MEMBASE offset(basereg), reg1
3183 * OP_MOVE reg1, reg2
3185 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3186 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3187 ins->inst_basereg != last_ins->dreg &&
3188 ins->inst_basereg == last_ins->inst_basereg &&
3189 ins->inst_offset == last_ins->inst_offset) {
3191 if (ins->dreg == last_ins->dreg) {
3192 MONO_DELETE_INS (bb, ins);
3195 ins->opcode = OP_MOVE;
3196 ins->sreg1 = last_ins->dreg;
3199 //g_assert_not_reached ();
3203 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3204 * OP_LOAD_MEMBASE offset(basereg), reg
3206 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3207 * OP_ICONST reg, imm
3209 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3210 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3211 ins->inst_basereg == last_ins->inst_destbasereg &&
3212 ins->inst_offset == last_ins->inst_offset) {
3213 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3214 ins->opcode = OP_ICONST;
3215 ins->inst_c0 = last_ins->inst_imm;
3216 g_assert_not_reached (); // check this rule
3220 case OP_LOADU1_MEMBASE:
3221 case OP_LOADI1_MEMBASE:
3222 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3223 ins->inst_basereg == last_ins->inst_destbasereg &&
3224 ins->inst_offset == last_ins->inst_offset) {
3225 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3226 ins->sreg1 = last_ins->sreg1;
3229 case OP_LOADU2_MEMBASE:
3230 case OP_LOADI2_MEMBASE:
3231 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3232 ins->inst_basereg == last_ins->inst_destbasereg &&
3233 ins->inst_offset == last_ins->inst_offset) {
3234 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3235 ins->sreg1 = last_ins->sreg1;
3239 ins->opcode = OP_MOVE;
3243 if (ins->dreg == ins->sreg1) {
3244 MONO_DELETE_INS (bb, ins);
3248 * OP_MOVE sreg, dreg
3249 * OP_MOVE dreg, sreg
3251 if (last_ins && last_ins->opcode == OP_MOVE &&
3252 ins->sreg1 == last_ins->dreg &&
3253 ins->dreg == last_ins->sreg1) {
3254 MONO_DELETE_INS (bb, ins);
3263 * the branch_cc_table should maintain the order of these
3277 branch_cc_table [] = {
3291 #define ADD_NEW_INS(cfg,dest,op) do { \
3292 MONO_INST_NEW ((cfg), (dest), (op)); \
3293 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3297 map_to_reg_reg_op (int op)
3306 case OP_COMPARE_IMM:
3308 case OP_ICOMPARE_IMM:
3322 case OP_LOAD_MEMBASE:
3323 return OP_LOAD_MEMINDEX;
3324 case OP_LOADI4_MEMBASE:
3325 return OP_LOADI4_MEMINDEX;
3326 case OP_LOADU4_MEMBASE:
3327 return OP_LOADU4_MEMINDEX;
3328 case OP_LOADU1_MEMBASE:
3329 return OP_LOADU1_MEMINDEX;
3330 case OP_LOADI2_MEMBASE:
3331 return OP_LOADI2_MEMINDEX;
3332 case OP_LOADU2_MEMBASE:
3333 return OP_LOADU2_MEMINDEX;
3334 case OP_LOADI1_MEMBASE:
3335 return OP_LOADI1_MEMINDEX;
3336 case OP_STOREI1_MEMBASE_REG:
3337 return OP_STOREI1_MEMINDEX;
3338 case OP_STOREI2_MEMBASE_REG:
3339 return OP_STOREI2_MEMINDEX;
3340 case OP_STOREI4_MEMBASE_REG:
3341 return OP_STOREI4_MEMINDEX;
3342 case OP_STORE_MEMBASE_REG:
3343 return OP_STORE_MEMINDEX;
3344 case OP_STORER4_MEMBASE_REG:
3345 return OP_STORER4_MEMINDEX;
3346 case OP_STORER8_MEMBASE_REG:
3347 return OP_STORER8_MEMINDEX;
3348 case OP_STORE_MEMBASE_IMM:
3349 return OP_STORE_MEMBASE_REG;
3350 case OP_STOREI1_MEMBASE_IMM:
3351 return OP_STOREI1_MEMBASE_REG;
3352 case OP_STOREI2_MEMBASE_IMM:
3353 return OP_STOREI2_MEMBASE_REG;
3354 case OP_STOREI4_MEMBASE_IMM:
3355 return OP_STOREI4_MEMBASE_REG;
3357 g_assert_not_reached ();
3361 * Remove from the instruction list the instructions that can't be
3362 * represented with very simple instructions with no register
3366 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3368 MonoInst *ins, *temp, *last_ins = NULL;
3369 int rot_amount, imm8, low_imm;
3371 MONO_BB_FOR_EACH_INS (bb, ins) {
3373 switch (ins->opcode) {
3377 case OP_COMPARE_IMM:
3378 case OP_ICOMPARE_IMM:
3392 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3393 int opcode2 = mono_op_imm_to_op (ins->opcode);
3394 ADD_NEW_INS (cfg, temp, OP_ICONST);
3395 temp->inst_c0 = ins->inst_imm;
3396 temp->dreg = mono_alloc_ireg (cfg);
3397 ins->sreg2 = temp->dreg;
3399 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3400 ins->opcode = opcode2;
3402 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3408 if (ins->inst_imm == 1) {
3409 ins->opcode = OP_MOVE;
3412 if (ins->inst_imm == 0) {
3413 ins->opcode = OP_ICONST;
3417 imm8 = mono_is_power_of_two (ins->inst_imm);
3419 ins->opcode = OP_SHL_IMM;
3420 ins->inst_imm = imm8;
3423 ADD_NEW_INS (cfg, temp, OP_ICONST);
3424 temp->inst_c0 = ins->inst_imm;
3425 temp->dreg = mono_alloc_ireg (cfg);
3426 ins->sreg2 = temp->dreg;
3427 ins->opcode = OP_IMUL;
3433 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3434 /* ARM sets the C flag to 1 if there was _no_ overflow */
3435 ins->next->opcode = OP_COND_EXC_NC;
3438 case OP_IDIV_UN_IMM:
3440 case OP_IREM_UN_IMM: {
3441 int opcode2 = mono_op_imm_to_op (ins->opcode);
3442 ADD_NEW_INS (cfg, temp, OP_ICONST);
3443 temp->inst_c0 = ins->inst_imm;
3444 temp->dreg = mono_alloc_ireg (cfg);
3445 ins->sreg2 = temp->dreg;
3447 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3448 ins->opcode = opcode2;
3451 case OP_LOCALLOC_IMM:
3452 ADD_NEW_INS (cfg, temp, OP_ICONST);
3453 temp->inst_c0 = ins->inst_imm;
3454 temp->dreg = mono_alloc_ireg (cfg);
3455 ins->sreg1 = temp->dreg;
3456 ins->opcode = OP_LOCALLOC;
3458 case OP_LOAD_MEMBASE:
3459 case OP_LOADI4_MEMBASE:
3460 case OP_LOADU4_MEMBASE:
3461 case OP_LOADU1_MEMBASE:
3462 /* we can do two things: load the immed in a register
3463 * and use an indexed load, or see if the immed can be
3464 * represented as an ad_imm + a load with a smaller offset
3465 * that fits. We just do the first for now, optimize later.
3467 if (arm_is_imm12 (ins->inst_offset))
3469 ADD_NEW_INS (cfg, temp, OP_ICONST);
3470 temp->inst_c0 = ins->inst_offset;
3471 temp->dreg = mono_alloc_ireg (cfg);
3472 ins->sreg2 = temp->dreg;
3473 ins->opcode = map_to_reg_reg_op (ins->opcode);
3475 case OP_LOADI2_MEMBASE:
3476 case OP_LOADU2_MEMBASE:
3477 case OP_LOADI1_MEMBASE:
3478 if (arm_is_imm8 (ins->inst_offset))
3480 ADD_NEW_INS (cfg, temp, OP_ICONST);
3481 temp->inst_c0 = ins->inst_offset;
3482 temp->dreg = mono_alloc_ireg (cfg);
3483 ins->sreg2 = temp->dreg;
3484 ins->opcode = map_to_reg_reg_op (ins->opcode);
3486 case OP_LOADR4_MEMBASE:
3487 case OP_LOADR8_MEMBASE:
3488 if (arm_is_fpimm8 (ins->inst_offset))
3490 low_imm = ins->inst_offset & 0x1ff;
3491 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3492 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3493 temp->inst_imm = ins->inst_offset & ~0x1ff;
3494 temp->sreg1 = ins->inst_basereg;
3495 temp->dreg = mono_alloc_ireg (cfg);
3496 ins->inst_basereg = temp->dreg;
3497 ins->inst_offset = low_imm;
3501 ADD_NEW_INS (cfg, temp, OP_ICONST);
3502 temp->inst_c0 = ins->inst_offset;
3503 temp->dreg = mono_alloc_ireg (cfg);
3505 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3506 add_ins->sreg1 = ins->inst_basereg;
3507 add_ins->sreg2 = temp->dreg;
3508 add_ins->dreg = mono_alloc_ireg (cfg);
3510 ins->inst_basereg = add_ins->dreg;
3511 ins->inst_offset = 0;
3514 case OP_STORE_MEMBASE_REG:
3515 case OP_STOREI4_MEMBASE_REG:
3516 case OP_STOREI1_MEMBASE_REG:
3517 if (arm_is_imm12 (ins->inst_offset))
3519 ADD_NEW_INS (cfg, temp, OP_ICONST);
3520 temp->inst_c0 = ins->inst_offset;
3521 temp->dreg = mono_alloc_ireg (cfg);
3522 ins->sreg2 = temp->dreg;
3523 ins->opcode = map_to_reg_reg_op (ins->opcode);
3525 case OP_STOREI2_MEMBASE_REG:
3526 if (arm_is_imm8 (ins->inst_offset))
3528 ADD_NEW_INS (cfg, temp, OP_ICONST);
3529 temp->inst_c0 = ins->inst_offset;
3530 temp->dreg = mono_alloc_ireg (cfg);
3531 ins->sreg2 = temp->dreg;
3532 ins->opcode = map_to_reg_reg_op (ins->opcode);
3534 case OP_STORER4_MEMBASE_REG:
3535 case OP_STORER8_MEMBASE_REG:
3536 if (arm_is_fpimm8 (ins->inst_offset))
3538 low_imm = ins->inst_offset & 0x1ff;
3539 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3540 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3541 temp->inst_imm = ins->inst_offset & ~0x1ff;
3542 temp->sreg1 = ins->inst_destbasereg;
3543 temp->dreg = mono_alloc_ireg (cfg);
3544 ins->inst_destbasereg = temp->dreg;
3545 ins->inst_offset = low_imm;
3549 ADD_NEW_INS (cfg, temp, OP_ICONST);
3550 temp->inst_c0 = ins->inst_offset;
3551 temp->dreg = mono_alloc_ireg (cfg);
3553 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3554 add_ins->sreg1 = ins->inst_destbasereg;
3555 add_ins->sreg2 = temp->dreg;
3556 add_ins->dreg = mono_alloc_ireg (cfg);
3558 ins->inst_destbasereg = add_ins->dreg;
3559 ins->inst_offset = 0;
3562 case OP_STORE_MEMBASE_IMM:
3563 case OP_STOREI1_MEMBASE_IMM:
3564 case OP_STOREI2_MEMBASE_IMM:
3565 case OP_STOREI4_MEMBASE_IMM:
3566 ADD_NEW_INS (cfg, temp, OP_ICONST);
3567 temp->inst_c0 = ins->inst_imm;
3568 temp->dreg = mono_alloc_ireg (cfg);
3569 ins->sreg1 = temp->dreg;
3570 ins->opcode = map_to_reg_reg_op (ins->opcode);
3572 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3575 gboolean swap = FALSE;
3579 /* Optimized away */
3584 /* Some fp compares require swapped operands */
3585 switch (ins->next->opcode) {
3587 ins->next->opcode = OP_FBLT;
3591 ins->next->opcode = OP_FBLT_UN;
3595 ins->next->opcode = OP_FBGE;
3599 ins->next->opcode = OP_FBGE_UN;
3607 ins->sreg1 = ins->sreg2;
3616 bb->last_ins = last_ins;
3617 bb->max_vreg = cfg->next_vreg;
3621 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3625 if (long_ins->opcode == OP_LNEG) {
3627 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3628 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3634 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3636 /* sreg is a float, dreg is an integer reg */
3638 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3640 ARM_TOSIZD (code, vfp_scratch1, sreg);
3642 ARM_TOUIZD (code, vfp_scratch1, sreg);
3643 ARM_FMRS (code, dreg, vfp_scratch1);
3644 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3648 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3649 else if (size == 2) {
3650 ARM_SHL_IMM (code, dreg, dreg, 16);
3651 ARM_SHR_IMM (code, dreg, dreg, 16);
3655 ARM_SHL_IMM (code, dreg, dreg, 24);
3656 ARM_SAR_IMM (code, dreg, dreg, 24);
3657 } else if (size == 2) {
3658 ARM_SHL_IMM (code, dreg, dreg, 16);
3659 ARM_SAR_IMM (code, dreg, dreg, 16);
3666 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3668 /* sreg is a float, dreg is an integer reg */
3670 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3672 ARM_TOSIZS (code, vfp_scratch1, sreg);
3674 ARM_TOUIZS (code, vfp_scratch1, sreg);
3675 ARM_FMRS (code, dreg, vfp_scratch1);
3676 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3680 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3681 else if (size == 2) {
3682 ARM_SHL_IMM (code, dreg, dreg, 16);
3683 ARM_SHR_IMM (code, dreg, dreg, 16);
3687 ARM_SHL_IMM (code, dreg, dreg, 24);
3688 ARM_SAR_IMM (code, dreg, dreg, 24);
3689 } else if (size == 2) {
3690 ARM_SHL_IMM (code, dreg, dreg, 16);
3691 ARM_SAR_IMM (code, dreg, dreg, 16);
3697 #endif /* #ifndef DISABLE_JIT */
3699 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3702 emit_thunk (guint8 *code, gconstpointer target)
3706 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3707 if (thumb_supported)
3708 ARM_BX (code, ARMREG_IP);
3710 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3711 *(guint32*)code = (guint32)target;
3713 mono_arch_flush_icache (p, code - p);
3717 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3719 MonoJitInfo *ji = NULL;
3720 MonoThunkJitInfo *info;
3723 guint8 *orig_target;
3724 guint8 *target_thunk;
3727 domain = mono_domain_get ();
3731 * This can be called multiple times during JITting,
3732 * save the current position in cfg->arch to avoid
3733 * doing a O(n^2) search.
3735 if (!cfg->arch.thunks) {
3736 cfg->arch.thunks = cfg->thunks;
3737 cfg->arch.thunks_size = cfg->thunk_area;
3739 thunks = cfg->arch.thunks;
3740 thunks_size = cfg->arch.thunks_size;
3742 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3743 g_assert_not_reached ();
3746 g_assert (*(guint32*)thunks == 0);
3747 emit_thunk (thunks, target);
3748 arm_patch (code, thunks);
3750 cfg->arch.thunks += THUNK_SIZE;
3751 cfg->arch.thunks_size -= THUNK_SIZE;
3753 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3755 info = mono_jit_info_get_thunk_info (ji);
3758 thunks = (guint8*)ji->code_start + info->thunks_offset;
3759 thunks_size = info->thunks_size;
3761 orig_target = mono_arch_get_call_target (code + 4);
3763 mono_mini_arch_lock ();
3765 target_thunk = NULL;
3766 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3767 /* The call already points to a thunk, because of trampolines etc. */
3768 target_thunk = orig_target;
3770 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3771 if (((guint32*)p) [0] == 0) {
3775 } else if (((guint32*)p) [2] == (guint32)target) {
3776 /* Thunk already points to target */
3783 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3785 if (!target_thunk) {
3786 mono_mini_arch_unlock ();
3787 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3788 g_assert_not_reached ();
3791 emit_thunk (target_thunk, target);
3792 arm_patch (code, target_thunk);
3793 mono_arch_flush_icache (code, 4);
3795 mono_mini_arch_unlock ();
3800 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3802 guint32 *code32 = (void*)code;
3803 guint32 ins = *code32;
3804 guint32 prim = (ins >> 25) & 7;
3805 guint32 tval = GPOINTER_TO_UINT (target);
3807 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3808 if (prim == 5) { /* 101b */
3809 /* the diff starts 8 bytes from the branch opcode */
3810 gint diff = target - code - 8;
3812 gint tmask = 0xffffffff;
3813 if (tval & 1) { /* entering thumb mode */
3814 diff = target - 1 - code - 8;
3815 g_assert (thumb_supported);
3816 tbits = 0xf << 28; /* bl->blx bit pattern */
3817 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3818 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3822 tmask = ~(1 << 24); /* clear the link bit */
3823 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3828 if (diff <= 33554431) {
3830 ins = (ins & 0xff000000) | diff;
3832 *code32 = ins | tbits;
3836 /* diff between 0 and -33554432 */
3837 if (diff >= -33554432) {
3839 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3841 *code32 = ins | tbits;
3846 handle_thunk (cfg, domain, code, target);
3851 * The alternative call sequences looks like this:
3853 * ldr ip, [pc] // loads the address constant
3854 * b 1f // jumps around the constant
3855 * address constant embedded in the code
3860 * There are two cases for patching:
3861 * a) at the end of method emission: in this case code points to the start
3862 * of the call sequence
3863 * b) during runtime patching of the call site: in this case code points
3864 * to the mov pc, ip instruction
3866 * We have to handle also the thunk jump code sequence:
3870 * address constant // execution never reaches here
3872 if ((ins & 0x0ffffff0) == 0x12fff10) {
3873 /* Branch and exchange: the address is constructed in a reg
3874 * We can patch BX when the code sequence is the following:
3875 * ldr ip, [pc, #0] ; 0x8
3882 guint8 *emit = (guint8*)ccode;
3883 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3885 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3886 ARM_BX (emit, ARMREG_IP);
3888 /*patching from magic trampoline*/
3889 if (ins == ccode [3]) {
3890 g_assert (code32 [-4] == ccode [0]);
3891 g_assert (code32 [-3] == ccode [1]);
3892 g_assert (code32 [-1] == ccode [2]);
3893 code32 [-2] = (guint32)target;
3896 /*patching from JIT*/
3897 if (ins == ccode [0]) {
3898 g_assert (code32 [1] == ccode [1]);
3899 g_assert (code32 [3] == ccode [2]);
3900 g_assert (code32 [4] == ccode [3]);
3901 code32 [2] = (guint32)target;
3904 g_assert_not_reached ();
3905 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3913 guint8 *emit = (guint8*)ccode;
3914 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3916 ARM_BLX_REG (emit, ARMREG_IP);
3918 g_assert (code32 [-3] == ccode [0]);
3919 g_assert (code32 [-2] == ccode [1]);
3920 g_assert (code32 [0] == ccode [2]);
3922 code32 [-1] = (guint32)target;
3925 guint32 *tmp = ccode;
3926 guint8 *emit = (guint8*)tmp;
3927 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3928 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3929 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3930 ARM_BX (emit, ARMREG_IP);
3931 if (ins == ccode [2]) {
3932 g_assert_not_reached (); // should be -2 ...
3933 code32 [-1] = (guint32)target;
3936 if (ins == ccode [0]) {
3937 /* handles both thunk jump code and the far call sequence */
3938 code32 [2] = (guint32)target;
3941 g_assert_not_reached ();
3943 // g_print ("patched with 0x%08x\n", ins);
3947 arm_patch (guchar *code, const guchar *target)
3949 arm_patch_general (NULL, NULL, code, target);
3953 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3954 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3955 * to be used with the emit macros.
3956 * Return -1 otherwise.
3959 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3962 for (i = 0; i < 31; i+= 2) {
3963 res = (val << (32 - i)) | (val >> i);
3966 *rot_amount = i? 32 - i: 0;
3973 * Emits in code a sequence of instructions that load the value 'val'
3974 * into the dreg register. Uses at most 4 instructions.
3977 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3979 int imm8, rot_amount;
3981 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3982 /* skip the constant pool */
3988 if (mini_get_debug_options()->single_imm_size && v7_supported) {
3989 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3990 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3994 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3995 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3996 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3997 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4000 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4002 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4006 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4008 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4010 if (val & 0xFF0000) {
4011 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4013 if (val & 0xFF000000) {
4014 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4016 } else if (val & 0xFF00) {
4017 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4018 if (val & 0xFF0000) {
4019 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4021 if (val & 0xFF000000) {
4022 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4024 } else if (val & 0xFF0000) {
4025 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4026 if (val & 0xFF000000) {
4027 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4030 //g_assert_not_reached ();
4036 mono_arm_thumb_supported (void)
4038 return thumb_supported;
4042 mono_arm_eabi_supported (void)
4044 return eabi_supported;
4048 mono_arm_i8_align (void)
4056 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4061 call = (MonoCallInst*)ins;
4062 cinfo = call->call_info;
4064 switch (cinfo->ret.storage) {
4065 case RegTypeStructByVal:
4067 MonoInst *loc = cfg->arch.vret_addr_loc;
4070 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4071 /* The JIT treats this as a normal call */
4075 /* Load the destination address */
4076 g_assert (loc && loc->opcode == OP_REGOFFSET);
4078 if (arm_is_imm12 (loc->inst_offset)) {
4079 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4081 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4082 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4085 if (cinfo->ret.storage == RegTypeStructByVal) {
4086 int rsize = cinfo->ret.struct_size;
4088 for (i = 0; i < cinfo->ret.nregs; ++i) {
4089 g_assert (rsize >= 0);
4094 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4097 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4100 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4106 for (i = 0; i < cinfo->ret.nregs; ++i) {
4107 if (cinfo->ret.esize == 4)
4108 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4110 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4119 switch (ins->opcode) {
4122 case OP_FCALL_MEMBASE:
4124 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4125 if (sig_ret->type == MONO_TYPE_R4) {
4126 if (IS_HARD_FLOAT) {
4127 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4129 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4130 ARM_CVTS (code, ins->dreg, ins->dreg);
4133 if (IS_HARD_FLOAT) {
4134 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4136 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4143 case OP_RCALL_MEMBASE: {
4148 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4149 g_assert (sig_ret->type == MONO_TYPE_R4);
4150 if (IS_HARD_FLOAT) {
4151 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4153 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4154 ARM_CPYS (code, ins->dreg, ins->dreg);
4166 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4171 guint8 *code = cfg->native_code + cfg->code_len;
4172 MonoInst *last_ins = NULL;
4173 guint last_offset = 0;
4175 int imm8, rot_amount;
4177 /* we don't align basic blocks of loops on arm */
4179 if (cfg->verbose_level > 2)
4180 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4182 cpos = bb->max_offset;
4184 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4185 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4186 //g_assert (!mono_compile_aot);
4189 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4190 /* this is not thread save, but good enough */
4191 /* fixme: howto handle overflows? */
4192 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4195 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4196 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4197 (gpointer)"mono_break");
4198 code = emit_call_seq (cfg, code);
4201 MONO_BB_FOR_EACH_INS (bb, ins) {
4202 offset = code - cfg->native_code;
4204 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4206 if (offset > (cfg->code_size - max_len - 16)) {
4207 cfg->code_size *= 2;
4208 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4209 code = cfg->native_code + offset;
4211 // if (ins->cil_code)
4212 // g_print ("cil code\n");
4213 mono_debug_record_line_number (cfg, ins, offset);
4215 switch (ins->opcode) {
4216 case OP_MEMORY_BARRIER:
4218 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4219 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4223 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4226 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4228 case OP_ATOMIC_EXCHANGE_I4:
4229 case OP_ATOMIC_CAS_I4:
4230 case OP_ATOMIC_ADD_I4: {
4234 g_assert (v7_supported);
4237 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4239 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4241 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4245 g_assert (cfg->arch.atomic_tmp_offset != -1);
4246 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4248 switch (ins->opcode) {
4249 case OP_ATOMIC_EXCHANGE_I4:
4251 ARM_DMB (code, ARM_DMB_SY);
4252 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4253 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4254 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4256 ARM_B_COND (code, ARMCOND_NE, 0);
4257 arm_patch (buf [1], buf [0]);
4259 case OP_ATOMIC_CAS_I4:
4260 ARM_DMB (code, ARM_DMB_SY);
4262 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4263 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4265 ARM_B_COND (code, ARMCOND_NE, 0);
4266 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4267 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4269 ARM_B_COND (code, ARMCOND_NE, 0);
4270 arm_patch (buf [2], buf [0]);
4271 arm_patch (buf [1], code);
4273 case OP_ATOMIC_ADD_I4:
4275 ARM_DMB (code, ARM_DMB_SY);
4276 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4277 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4278 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4279 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4281 ARM_B_COND (code, ARMCOND_NE, 0);
4282 arm_patch (buf [1], buf [0]);
4285 g_assert_not_reached ();
4288 ARM_DMB (code, ARM_DMB_SY);
4289 if (tmpreg != ins->dreg)
4290 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4291 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4294 case OP_ATOMIC_LOAD_I1:
4295 case OP_ATOMIC_LOAD_U1:
4296 case OP_ATOMIC_LOAD_I2:
4297 case OP_ATOMIC_LOAD_U2:
4298 case OP_ATOMIC_LOAD_I4:
4299 case OP_ATOMIC_LOAD_U4:
4300 case OP_ATOMIC_LOAD_R4:
4301 case OP_ATOMIC_LOAD_R8: {
4302 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4303 ARM_DMB (code, ARM_DMB_SY);
4305 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4307 switch (ins->opcode) {
4308 case OP_ATOMIC_LOAD_I1:
4309 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4311 case OP_ATOMIC_LOAD_U1:
4312 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4314 case OP_ATOMIC_LOAD_I2:
4315 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4317 case OP_ATOMIC_LOAD_U2:
4318 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4320 case OP_ATOMIC_LOAD_I4:
4321 case OP_ATOMIC_LOAD_U4:
4322 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4324 case OP_ATOMIC_LOAD_R4:
4326 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4327 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4329 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4330 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4331 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4332 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4333 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4336 case OP_ATOMIC_LOAD_R8:
4337 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4338 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4342 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4343 ARM_DMB (code, ARM_DMB_SY);
4346 case OP_ATOMIC_STORE_I1:
4347 case OP_ATOMIC_STORE_U1:
4348 case OP_ATOMIC_STORE_I2:
4349 case OP_ATOMIC_STORE_U2:
4350 case OP_ATOMIC_STORE_I4:
4351 case OP_ATOMIC_STORE_U4:
4352 case OP_ATOMIC_STORE_R4:
4353 case OP_ATOMIC_STORE_R8: {
4354 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4355 ARM_DMB (code, ARM_DMB_SY);
4357 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4359 switch (ins->opcode) {
4360 case OP_ATOMIC_STORE_I1:
4361 case OP_ATOMIC_STORE_U1:
4362 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4364 case OP_ATOMIC_STORE_I2:
4365 case OP_ATOMIC_STORE_U2:
4366 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4368 case OP_ATOMIC_STORE_I4:
4369 case OP_ATOMIC_STORE_U4:
4370 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4372 case OP_ATOMIC_STORE_R4:
4374 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4375 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4377 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4378 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4379 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4380 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4381 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4384 case OP_ATOMIC_STORE_R8:
4385 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4386 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4390 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4391 ARM_DMB (code, ARM_DMB_SY);
4395 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4398 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4400 case OP_STOREI1_MEMBASE_IMM:
4401 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4402 g_assert (arm_is_imm12 (ins->inst_offset));
4403 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4405 case OP_STOREI2_MEMBASE_IMM:
4406 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4407 g_assert (arm_is_imm8 (ins->inst_offset));
4408 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4410 case OP_STORE_MEMBASE_IMM:
4411 case OP_STOREI4_MEMBASE_IMM:
4412 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4413 g_assert (arm_is_imm12 (ins->inst_offset));
4414 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4416 case OP_STOREI1_MEMBASE_REG:
4417 g_assert (arm_is_imm12 (ins->inst_offset));
4418 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4420 case OP_STOREI2_MEMBASE_REG:
4421 g_assert (arm_is_imm8 (ins->inst_offset));
4422 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4424 case OP_STORE_MEMBASE_REG:
4425 case OP_STOREI4_MEMBASE_REG:
4426 /* this case is special, since it happens for spill code after lowering has been called */
4427 if (arm_is_imm12 (ins->inst_offset)) {
4428 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4430 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4431 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4434 case OP_STOREI1_MEMINDEX:
4435 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4437 case OP_STOREI2_MEMINDEX:
4438 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4440 case OP_STORE_MEMINDEX:
4441 case OP_STOREI4_MEMINDEX:
4442 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4445 g_assert_not_reached ();
4447 case OP_LOAD_MEMINDEX:
4448 case OP_LOADI4_MEMINDEX:
4449 case OP_LOADU4_MEMINDEX:
4450 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4452 case OP_LOADI1_MEMINDEX:
4453 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4455 case OP_LOADU1_MEMINDEX:
4456 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4458 case OP_LOADI2_MEMINDEX:
4459 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4461 case OP_LOADU2_MEMINDEX:
4462 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4464 case OP_LOAD_MEMBASE:
4465 case OP_LOADI4_MEMBASE:
4466 case OP_LOADU4_MEMBASE:
4467 /* this case is special, since it happens for spill code after lowering has been called */
4468 if (arm_is_imm12 (ins->inst_offset)) {
4469 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4471 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4472 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4475 case OP_LOADI1_MEMBASE:
4476 g_assert (arm_is_imm8 (ins->inst_offset));
4477 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4479 case OP_LOADU1_MEMBASE:
4480 g_assert (arm_is_imm12 (ins->inst_offset));
4481 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4483 case OP_LOADU2_MEMBASE:
4484 g_assert (arm_is_imm8 (ins->inst_offset));
4485 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4487 case OP_LOADI2_MEMBASE:
4488 g_assert (arm_is_imm8 (ins->inst_offset));
4489 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4491 case OP_ICONV_TO_I1:
4492 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4493 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4495 case OP_ICONV_TO_I2:
4496 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4497 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4499 case OP_ICONV_TO_U1:
4500 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4502 case OP_ICONV_TO_U2:
4503 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4504 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4508 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4510 case OP_COMPARE_IMM:
4511 case OP_ICOMPARE_IMM:
4512 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4513 g_assert (imm8 >= 0);
4514 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4518 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4519 * So instead of emitting a trap, we emit a call a C function and place a
4522 //*(int*)code = 0xef9f0001;
4525 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4526 (gpointer)"mono_break");
4527 code = emit_call_seq (cfg, code);
4529 case OP_RELAXED_NOP:
4534 case OP_DUMMY_STORE:
4535 case OP_DUMMY_ICONST:
4536 case OP_DUMMY_R8CONST:
4537 case OP_NOT_REACHED:
4540 case OP_IL_SEQ_POINT:
4541 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4543 case OP_SEQ_POINT: {
4545 MonoInst *info_var = cfg->arch.seq_point_info_var;
4546 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4547 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4548 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4550 int dreg = ARMREG_LR;
4553 if (cfg->soft_breakpoints) {
4554 g_assert (!cfg->compile_aot);
4559 * For AOT, we use one got slot per method, which will point to a
4560 * SeqPointInfo structure, containing all the information required
4561 * by the code below.
4563 if (cfg->compile_aot) {
4564 g_assert (info_var);
4565 g_assert (info_var->opcode == OP_REGOFFSET);
4566 g_assert (arm_is_imm12 (info_var->inst_offset));
4569 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4571 * Read from the single stepping trigger page. This will cause a
4572 * SIGSEGV when single stepping is enabled.
4573 * We do this _before_ the breakpoint, so single stepping after
4574 * a breakpoint is hit will step to the next IL offset.
4576 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4579 /* Single step check */
4580 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4581 if (cfg->soft_breakpoints) {
4582 /* Load the address of the sequence point method variable. */
4583 var = ss_method_var;
4585 g_assert (var->opcode == OP_REGOFFSET);
4586 g_assert (arm_is_imm12 (var->inst_offset));
4587 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4589 /* Read the value and check whether it is non-zero. */
4590 ARM_LDR_IMM (code, dreg, dreg, 0);
4591 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4592 /* Call it conditionally. */
4593 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4595 if (cfg->compile_aot) {
4596 /* Load the trigger page addr from the variable initialized in the prolog */
4597 var = ss_trigger_page_var;
4599 g_assert (var->opcode == OP_REGOFFSET);
4600 g_assert (arm_is_imm12 (var->inst_offset));
4601 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4603 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4605 *(int*)code = (int)ss_trigger_page;
4608 ARM_LDR_IMM (code, dreg, dreg, 0);
4612 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4614 /* Breakpoint check */
4615 if (cfg->compile_aot) {
4616 guint32 offset = code - cfg->native_code;
4619 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4620 /* Add the offset */
4621 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4622 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4623 if (arm_is_imm12 ((int)val)) {
4624 ARM_LDR_IMM (code, dreg, dreg, val);
4626 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4628 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4630 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4631 g_assert (!(val & 0xFF000000));
4633 ARM_LDR_IMM (code, dreg, dreg, 0);
4635 /* What is faster, a branch or a load ? */
4636 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4637 /* The breakpoint instruction */
4638 if (cfg->soft_breakpoints)
4639 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4641 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4642 } else if (cfg->soft_breakpoints) {
4643 /* Load the address of the breakpoint method into ip. */
4644 var = bp_method_var;
4646 g_assert (var->opcode == OP_REGOFFSET);
4647 g_assert (arm_is_imm12 (var->inst_offset));
4648 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4651 * A placeholder for a possible breakpoint inserted by
4652 * mono_arch_set_breakpoint ().
4657 * A placeholder for a possible breakpoint inserted by
4658 * mono_arch_set_breakpoint ().
4660 for (i = 0; i < 4; ++i)
4665 * Add an additional nop so skipping the bp doesn't cause the ip to point
4666 * to another IL offset.
4674 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4677 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4681 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4684 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4685 g_assert (imm8 >= 0);
4686 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4690 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4691 g_assert (imm8 >= 0);
4692 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4696 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4697 g_assert (imm8 >= 0);
4698 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4701 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4702 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4704 case OP_IADD_OVF_UN:
4705 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4706 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4709 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4710 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4712 case OP_ISUB_OVF_UN:
4713 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4714 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4716 case OP_ADD_OVF_CARRY:
4717 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4718 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4720 case OP_ADD_OVF_UN_CARRY:
4721 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4722 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4724 case OP_SUB_OVF_CARRY:
4725 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4726 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4728 case OP_SUB_OVF_UN_CARRY:
4729 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4730 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4734 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4737 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4738 g_assert (imm8 >= 0);
4739 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4742 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4746 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4750 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4751 g_assert (imm8 >= 0);
4752 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4756 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4757 g_assert (imm8 >= 0);
4758 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4760 case OP_ARM_RSBS_IMM:
4761 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4762 g_assert (imm8 >= 0);
4763 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4765 case OP_ARM_RSC_IMM:
4766 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4767 g_assert (imm8 >= 0);
4768 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4771 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4775 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4776 g_assert (imm8 >= 0);
4777 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4780 g_assert (v7s_supported || v7k_supported);
4781 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4784 g_assert (v7s_supported || v7k_supported);
4785 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4788 g_assert (v7s_supported || v7k_supported);
4789 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4790 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4793 g_assert (v7s_supported || v7k_supported);
4794 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4795 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4799 g_assert_not_reached ();
4801 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4805 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4806 g_assert (imm8 >= 0);
4807 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4810 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4814 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4815 g_assert (imm8 >= 0);
4816 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4819 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4824 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4825 else if (ins->dreg != ins->sreg1)
4826 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4829 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4834 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4835 else if (ins->dreg != ins->sreg1)
4836 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4839 case OP_ISHR_UN_IMM:
4841 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4842 else if (ins->dreg != ins->sreg1)
4843 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4846 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4849 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4852 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4855 if (ins->dreg == ins->sreg2)
4856 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4858 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4861 g_assert_not_reached ();
4864 /* FIXME: handle ovf/ sreg2 != dreg */
4865 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4866 /* FIXME: MUL doesn't set the C/O flags on ARM */
4868 case OP_IMUL_OVF_UN:
4869 /* FIXME: handle ovf/ sreg2 != dreg */
4870 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4871 /* FIXME: MUL doesn't set the C/O flags on ARM */
4874 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4877 /* Load the GOT offset */
4878 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4879 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4881 *(gpointer*)code = NULL;
4883 /* Load the value from the GOT */
4884 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4886 case OP_OBJC_GET_SELECTOR:
4887 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4888 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4890 *(gpointer*)code = NULL;
4892 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4894 case OP_ICONV_TO_I4:
4895 case OP_ICONV_TO_U4:
4897 if (ins->dreg != ins->sreg1)
4898 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4901 int saved = ins->sreg2;
4902 if (ins->sreg2 == ARM_LSW_REG) {
4903 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4906 if (ins->sreg1 != ARM_LSW_REG)
4907 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4908 if (saved != ARM_MSW_REG)
4909 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4913 if (IS_VFP && ins->dreg != ins->sreg1)
4914 ARM_CPYD (code, ins->dreg, ins->sreg1);
4917 if (IS_VFP && ins->dreg != ins->sreg1)
4918 ARM_CPYS (code, ins->dreg, ins->sreg1);
4920 case OP_MOVE_F_TO_I4:
4922 ARM_FMRS (code, ins->dreg, ins->sreg1);
4924 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4925 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4926 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4927 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4930 case OP_MOVE_I4_TO_F:
4932 ARM_FMSR (code, ins->dreg, ins->sreg1);
4934 ARM_FMSR (code, ins->dreg, ins->sreg1);
4935 ARM_CVTS (code, ins->dreg, ins->dreg);
4938 case OP_FCONV_TO_R4:
4941 ARM_CVTD (code, ins->dreg, ins->sreg1);
4943 ARM_CVTD (code, ins->dreg, ins->sreg1);
4944 ARM_CVTS (code, ins->dreg, ins->dreg);
4949 MonoCallInst *call = (MonoCallInst*)ins;
4952 * The stack looks like the following:
4953 * <caller argument area>
4956 * <callee argument area>
4957 * Need to copy the arguments from the callee argument area to
4958 * the caller argument area, and pop the frame.
4960 if (call->stack_usage) {
4961 int i, prev_sp_offset = 0;
4963 /* Compute size of saved registers restored below */
4965 prev_sp_offset = 2 * 4;
4967 prev_sp_offset = 1 * 4;
4968 for (i = 0; i < 16; ++i) {
4969 if (cfg->used_int_regs & (1 << i))
4970 prev_sp_offset += 4;
4973 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4975 /* Copy arguments on the stack to our argument area */
4976 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4977 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4978 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4983 * Keep in sync with mono_arch_emit_epilog
4985 g_assert (!cfg->method->save_lmf);
4987 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4989 if (cfg->used_int_regs)
4990 ARM_POP (code, cfg->used_int_regs);
4991 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4993 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4996 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4997 if (cfg->compile_aot) {
4998 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5000 *(gpointer*)code = NULL;
5002 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5004 code = mono_arm_patchable_b (code, ARMCOND_AL);
5005 cfg->thunk_area += THUNK_SIZE;
5010 /* ensure ins->sreg1 is not NULL */
5011 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5014 g_assert (cfg->sig_cookie < 128);
5015 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5016 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5026 call = (MonoCallInst*)ins;
5029 code = emit_float_args (cfg, call, code, &max_len, &offset);
5031 if (ins->flags & MONO_INST_HAS_METHOD)
5032 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5034 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5035 code = emit_call_seq (cfg, code);
5036 ins->flags |= MONO_INST_GC_CALLSITE;
5037 ins->backend.pc_offset = code - cfg->native_code;
5038 code = emit_move_return_value (cfg, ins, code);
5045 case OP_VOIDCALL_REG:
5048 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5050 code = emit_call_reg (code, ins->sreg1);
5051 ins->flags |= MONO_INST_GC_CALLSITE;
5052 ins->backend.pc_offset = code - cfg->native_code;
5053 code = emit_move_return_value (cfg, ins, code);
5055 case OP_FCALL_MEMBASE:
5056 case OP_RCALL_MEMBASE:
5057 case OP_LCALL_MEMBASE:
5058 case OP_VCALL_MEMBASE:
5059 case OP_VCALL2_MEMBASE:
5060 case OP_VOIDCALL_MEMBASE:
5061 case OP_CALL_MEMBASE: {
5062 g_assert (ins->sreg1 != ARMREG_LR);
5063 call = (MonoCallInst*)ins;
5066 code = emit_float_args (cfg, call, code, &max_len, &offset);
5067 if (!arm_is_imm12 (ins->inst_offset)) {
5068 /* sreg1 might be IP */
5069 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5070 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5071 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5072 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5073 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5075 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5076 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5078 ins->flags |= MONO_INST_GC_CALLSITE;
5079 ins->backend.pc_offset = code - cfg->native_code;
5080 code = emit_move_return_value (cfg, ins, code);
5083 case OP_GENERIC_CLASS_INIT: {
5087 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5089 g_assert (arm_is_imm8 (byte_offset));
5090 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5091 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5093 ARM_B_COND (code, ARMCOND_NE, 0);
5095 /* Uninitialized case */
5096 g_assert (ins->sreg1 == ARMREG_R0);
5098 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5099 (gpointer)"mono_generic_class_init");
5100 code = emit_call_seq (cfg, code);
5102 /* Initialized case */
5103 arm_patch (jump, code);
5107 /* round the size to 8 bytes */
5108 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5109 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5110 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5111 /* memzero the area: dreg holds the size, sp is the pointer */
5112 if (ins->flags & MONO_INST_INIT) {
5113 guint8 *start_loop, *branch_to_cond;
5114 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5115 branch_to_cond = code;
5118 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5119 arm_patch (branch_to_cond, code);
5120 /* decrement by 4 and set flags */
5121 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5122 ARM_B_COND (code, ARMCOND_GE, 0);
5123 arm_patch (code - 4, start_loop);
5125 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5126 if (cfg->param_area)
5127 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5132 MonoInst *var = cfg->dyn_call_var;
5135 g_assert (var->opcode == OP_REGOFFSET);
5136 g_assert (arm_is_imm12 (var->inst_offset));
5138 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5139 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5141 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5143 /* Save args buffer */
5144 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5146 /* Set stack slots using R0 as scratch reg */
5147 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5148 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5149 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5150 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5153 /* Set fp argument registers */
5154 if (IS_HARD_FLOAT) {
5155 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5156 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5158 ARM_B_COND (code, ARMCOND_EQ, 0);
5159 for (i = 0; i < FP_PARAM_REGS; ++i) {
5160 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5161 g_assert (arm_is_fpimm8 (offset));
5162 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5164 arm_patch (buf [0], code);
5167 /* Set argument registers */
5168 for (i = 0; i < PARAM_REGS; ++i)
5169 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5172 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5173 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5176 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5177 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5178 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5180 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5184 if (ins->sreg1 != ARMREG_R0)
5185 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5186 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5187 (gpointer)"mono_arch_throw_exception");
5188 code = emit_call_seq (cfg, code);
5192 if (ins->sreg1 != ARMREG_R0)
5193 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5194 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5195 (gpointer)"mono_arch_rethrow_exception");
5196 code = emit_call_seq (cfg, code);
5199 case OP_START_HANDLER: {
5200 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5201 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5204 /* Reserve a param area, see filter-stack.exe */
5206 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5207 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5209 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5210 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5214 if (arm_is_imm12 (spvar->inst_offset)) {
5215 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5217 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5218 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5222 case OP_ENDFILTER: {
5223 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5224 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5227 /* Free the param area */
5229 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5230 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5232 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5233 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5237 if (ins->sreg1 != ARMREG_R0)
5238 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5239 if (arm_is_imm12 (spvar->inst_offset)) {
5240 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5242 g_assert (ARMREG_IP != spvar->inst_basereg);
5243 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5244 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5246 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5249 case OP_ENDFINALLY: {
5250 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5251 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5254 /* Free the param area */
5256 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5257 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5259 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5260 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5264 if (arm_is_imm12 (spvar->inst_offset)) {
5265 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5267 g_assert (ARMREG_IP != spvar->inst_basereg);
5268 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5269 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5271 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5274 case OP_CALL_HANDLER:
5275 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5276 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5277 cfg->thunk_area += THUNK_SIZE;
5278 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5281 if (ins->dreg != ARMREG_R0)
5282 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5286 ins->inst_c0 = code - cfg->native_code;
5289 /*if (ins->inst_target_bb->native_offset) {
5291 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5293 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5294 code = mono_arm_patchable_b (code, ARMCOND_AL);
5298 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5302 * In the normal case we have:
5303 * ldr pc, [pc, ins->sreg1 << 2]
5306 * ldr lr, [pc, ins->sreg1 << 2]
5308 * After follows the data.
5309 * FIXME: add aot support.
5311 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5312 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5313 if (offset + max_len > (cfg->code_size - 16)) {
5314 cfg->code_size += max_len;
5315 cfg->code_size *= 2;
5316 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5317 code = cfg->native_code + offset;
5319 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5321 code += 4 * GPOINTER_TO_INT (ins->klass);
5325 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5326 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5330 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5331 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5335 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5336 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5340 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5341 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5345 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5346 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5349 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5350 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5353 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5354 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5357 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5358 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5361 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5362 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5365 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5366 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5368 case OP_COND_EXC_EQ:
5369 case OP_COND_EXC_NE_UN:
5370 case OP_COND_EXC_LT:
5371 case OP_COND_EXC_LT_UN:
5372 case OP_COND_EXC_GT:
5373 case OP_COND_EXC_GT_UN:
5374 case OP_COND_EXC_GE:
5375 case OP_COND_EXC_GE_UN:
5376 case OP_COND_EXC_LE:
5377 case OP_COND_EXC_LE_UN:
5378 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5380 case OP_COND_EXC_IEQ:
5381 case OP_COND_EXC_INE_UN:
5382 case OP_COND_EXC_ILT:
5383 case OP_COND_EXC_ILT_UN:
5384 case OP_COND_EXC_IGT:
5385 case OP_COND_EXC_IGT_UN:
5386 case OP_COND_EXC_IGE:
5387 case OP_COND_EXC_IGE_UN:
5388 case OP_COND_EXC_ILE:
5389 case OP_COND_EXC_ILE_UN:
5390 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5393 case OP_COND_EXC_IC:
5394 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5396 case OP_COND_EXC_OV:
5397 case OP_COND_EXC_IOV:
5398 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5400 case OP_COND_EXC_NC:
5401 case OP_COND_EXC_INC:
5402 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5404 case OP_COND_EXC_NO:
5405 case OP_COND_EXC_INO:
5406 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5418 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5421 /* floating point opcodes */
5423 if (cfg->compile_aot) {
5424 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5426 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5428 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5431 /* FIXME: we can optimize the imm load by dealing with part of
5432 * the displacement in LDFD (aligning to 512).
5434 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5435 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5439 if (cfg->compile_aot) {
5440 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5442 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5445 ARM_CVTS (code, ins->dreg, ins->dreg);
5447 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5448 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5450 ARM_CVTS (code, ins->dreg, ins->dreg);
5453 case OP_STORER8_MEMBASE_REG:
5454 /* This is generated by the local regalloc pass which runs after the lowering pass */
5455 if (!arm_is_fpimm8 (ins->inst_offset)) {
5456 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5457 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5458 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5460 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5463 case OP_LOADR8_MEMBASE:
5464 /* This is generated by the local regalloc pass which runs after the lowering pass */
5465 if (!arm_is_fpimm8 (ins->inst_offset)) {
5466 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5467 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5468 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5470 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5473 case OP_STORER4_MEMBASE_REG:
5474 g_assert (arm_is_fpimm8 (ins->inst_offset));
5476 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5478 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5479 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5480 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5481 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5484 case OP_LOADR4_MEMBASE:
5486 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5488 g_assert (arm_is_fpimm8 (ins->inst_offset));
5489 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5490 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5491 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5492 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5495 case OP_ICONV_TO_R_UN: {
5496 g_assert_not_reached ();
5499 case OP_ICONV_TO_R4:
5501 ARM_FMSR (code, ins->dreg, ins->sreg1);
5502 ARM_FSITOS (code, ins->dreg, ins->dreg);
5504 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5505 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5506 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5507 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5508 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5511 case OP_ICONV_TO_R8:
5512 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5513 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5514 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5515 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5519 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5520 if (sig_ret->type == MONO_TYPE_R4) {
5522 if (IS_HARD_FLOAT) {
5523 if (ins->sreg1 != ARM_VFP_D0)
5524 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5526 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5529 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5532 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5536 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5538 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5542 case OP_FCONV_TO_I1:
5543 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5545 case OP_FCONV_TO_U1:
5546 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5548 case OP_FCONV_TO_I2:
5549 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5551 case OP_FCONV_TO_U2:
5552 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5554 case OP_FCONV_TO_I4:
5556 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5558 case OP_FCONV_TO_U4:
5560 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5562 case OP_FCONV_TO_I8:
5563 case OP_FCONV_TO_U8:
5564 g_assert_not_reached ();
5565 /* Implemented as helper calls */
5567 case OP_LCONV_TO_R_UN:
5568 g_assert_not_reached ();
5569 /* Implemented as helper calls */
5571 case OP_LCONV_TO_OVF_I4_2: {
5572 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5574 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5577 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5578 high_bit_not_set = code;
5579 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5581 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5582 valid_negative = code;
5583 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5584 invalid_negative = code;
5585 ARM_B_COND (code, ARMCOND_AL, 0);
5587 arm_patch (high_bit_not_set, code);
5589 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5590 valid_positive = code;
5591 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5593 arm_patch (invalid_negative, code);
5594 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5596 arm_patch (valid_negative, code);
5597 arm_patch (valid_positive, code);
5599 if (ins->dreg != ins->sreg1)
5600 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5604 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5607 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5610 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5613 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5616 ARM_NEGD (code, ins->dreg, ins->sreg1);
5620 g_assert_not_reached ();
5624 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5630 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5635 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5638 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5639 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5643 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5646 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5647 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5651 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5654 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5655 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5656 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5660 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5663 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5664 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5668 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5671 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5672 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5673 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5677 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5680 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5681 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5685 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5688 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5689 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5693 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5696 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5697 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5700 /* ARM FPA flags table:
5701 * N Less than ARMCOND_MI
5702 * Z Equal ARMCOND_EQ
5703 * C Greater Than or Equal ARMCOND_CS
5704 * V Unordered ARMCOND_VS
5707 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5710 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5713 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5716 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5717 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5723 g_assert_not_reached ();
5727 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5729 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5730 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5731 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5735 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5736 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5741 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5742 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5744 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5745 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5747 *(guint32*)code = 0xffffffff;
5749 *(guint32*)code = 0x7fefffff;
5751 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5753 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5754 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5756 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5757 ARM_CPYD (code, ins->dreg, ins->sreg1);
5759 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5760 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5765 case OP_RCONV_TO_I1:
5766 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5768 case OP_RCONV_TO_U1:
5769 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5771 case OP_RCONV_TO_I2:
5772 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5774 case OP_RCONV_TO_U2:
5775 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5777 case OP_RCONV_TO_I4:
5778 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5780 case OP_RCONV_TO_U4:
5781 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5783 case OP_RCONV_TO_R4:
5785 if (ins->dreg != ins->sreg1)
5786 ARM_CPYS (code, ins->dreg, ins->sreg1);
5788 case OP_RCONV_TO_R8:
5790 ARM_CVTS (code, ins->dreg, ins->sreg1);
5793 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5796 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5799 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5802 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5805 ARM_NEGS (code, ins->dreg, ins->sreg1);
5809 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5812 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5813 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5817 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5820 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5821 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5825 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5828 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5829 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5830 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5834 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5837 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5838 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5842 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5845 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5846 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5847 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5851 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5854 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5855 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5859 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5862 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5863 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5867 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5870 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5871 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5874 case OP_GC_LIVENESS_DEF:
5875 case OP_GC_LIVENESS_USE:
5876 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5877 ins->backend.pc_offset = code - cfg->native_code;
5879 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5880 ins->backend.pc_offset = code - cfg->native_code;
5881 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5883 case OP_GC_SAFE_POINT: {
5886 g_assert (mono_threads_is_coop_enabled ());
5888 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5889 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5891 ARM_B_COND (code, ARMCOND_EQ, 0);
5892 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5893 code = emit_call_seq (cfg, code);
5894 arm_patch (buf [0], code);
5899 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5900 g_assert_not_reached ();
5903 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5904 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5905 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5906 g_assert_not_reached ();
5912 last_offset = offset;
5915 cfg->code_len = code - cfg->native_code;
5918 #endif /* DISABLE_JIT */
5921 mono_arch_register_lowlevel_calls (void)
5923 /* The signature doesn't matter */
5924 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5925 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5926 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5929 #define patch_lis_ori(ip,val) do {\
5930 guint16 *__lis_ori = (guint16*)(ip); \
5931 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5932 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5936 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5938 unsigned char *ip = ji->ip.i + code;
5940 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5944 case MONO_PATCH_INFO_SWITCH: {
5945 gpointer *jt = (gpointer*)(ip + 8);
5947 /* jt is the inlined jump table, 2 instructions after ip
5948 * In the normal case we store the absolute addresses,
5949 * otherwise the displacements.
5951 for (i = 0; i < ji->data.table->table_size; i++)
5952 jt [i] = code + (int)ji->data.table->table [i];
5955 case MONO_PATCH_INFO_IP:
5956 g_assert_not_reached ();
5957 patch_lis_ori (ip, ip);
5959 case MONO_PATCH_INFO_METHOD_REL:
5960 g_assert_not_reached ();
5961 *((gpointer *)(ip)) = target;
5963 case MONO_PATCH_INFO_METHODCONST:
5964 case MONO_PATCH_INFO_CLASS:
5965 case MONO_PATCH_INFO_IMAGE:
5966 case MONO_PATCH_INFO_FIELD:
5967 case MONO_PATCH_INFO_VTABLE:
5968 case MONO_PATCH_INFO_IID:
5969 case MONO_PATCH_INFO_SFLDA:
5970 case MONO_PATCH_INFO_LDSTR:
5971 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5972 case MONO_PATCH_INFO_LDTOKEN:
5973 g_assert_not_reached ();
5974 /* from OP_AOTCONST : lis + ori */
5975 patch_lis_ori (ip, target);
5977 case MONO_PATCH_INFO_R4:
5978 case MONO_PATCH_INFO_R8:
5979 g_assert_not_reached ();
5980 *((gconstpointer *)(ip + 2)) = target;
5982 case MONO_PATCH_INFO_EXC_NAME:
5983 g_assert_not_reached ();
5984 *((gconstpointer *)(ip + 1)) = target;
5986 case MONO_PATCH_INFO_NONE:
5987 case MONO_PATCH_INFO_BB_OVF:
5988 case MONO_PATCH_INFO_EXC_OVF:
5989 /* everything is dealt with at epilog output time */
5992 arm_patch_general (cfg, domain, ip, target);
5998 mono_arm_unaligned_stack (MonoMethod *method)
6000 g_assert_not_reached ();
6006 * Stack frame layout:
6008 * ------------------- fp
6009 * MonoLMF structure or saved registers
6010 * -------------------
6012 * -------------------
6014 * -------------------
6015 * optional 8 bytes for tracing
6016 * -------------------
6017 * param area size is cfg->param_area
6018 * ------------------- sp
6021 mono_arch_emit_prolog (MonoCompile *cfg)
6023 MonoMethod *method = cfg->method;
6025 MonoMethodSignature *sig;
6027 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6032 int prev_sp_offset, reg_offset;
6034 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6037 sig = mono_method_signature (method);
6038 cfg->code_size = 256 + sig->param_count * 64;
6039 code = cfg->native_code = g_malloc (cfg->code_size);
6041 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6043 alloc_size = cfg->stack_offset;
6049 * The iphone uses R7 as the frame pointer, and it points at the saved
6054 * We can't use r7 as a frame pointer since it points into the middle of
6055 * the frame, so we keep using our own frame pointer.
6056 * FIXME: Optimize this.
6058 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6059 prev_sp_offset += 8; /* r7 and lr */
6060 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6061 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6062 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6065 if (!method->save_lmf) {
6067 /* No need to push LR again */
6068 if (cfg->used_int_regs)
6069 ARM_PUSH (code, cfg->used_int_regs);
6071 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6072 prev_sp_offset += 4;
6074 for (i = 0; i < 16; ++i) {
6075 if (cfg->used_int_regs & (1 << i))
6076 prev_sp_offset += 4;
6078 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6080 for (i = 0; i < 16; ++i) {
6081 if ((cfg->used_int_regs & (1 << i))) {
6082 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6083 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6087 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6088 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6090 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6091 ARM_PUSH (code, 0x5ff0);
6092 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6093 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6095 for (i = 0; i < 16; ++i) {
6096 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6097 /* The original r7 is saved at the start */
6098 if (!(iphone_abi && i == ARMREG_R7))
6099 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6103 g_assert (reg_offset == 4 * 10);
6104 pos += sizeof (MonoLMF) - (4 * 10);
6108 orig_alloc_size = alloc_size;
6109 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6110 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6111 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6112 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6115 /* the stack used in the pushed regs */
6116 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6117 cfg->stack_usage = alloc_size;
6119 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6120 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6122 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6123 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6125 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6127 if (cfg->frame_reg != ARMREG_SP) {
6128 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6129 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6131 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6132 prev_sp_offset += alloc_size;
6134 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6135 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6137 /* compute max_offset in order to use short forward jumps
6138 * we could skip do it on arm because the immediate displacement
6139 * for jumps is large enough, it may be useful later for constant pools
6142 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6143 MonoInst *ins = bb->code;
6144 bb->max_offset = max_offset;
6146 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6149 MONO_BB_FOR_EACH_INS (bb, ins)
6150 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6153 /* stack alignment check */
6157 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6158 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6159 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6160 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6162 ARM_B_COND (code, ARMCOND_EQ, 0);
6163 if (cfg->compile_aot)
6164 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6166 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6167 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6168 code = emit_call_seq (cfg, code);
6169 arm_patch (buf [0], code);
6173 /* store runtime generic context */
6174 if (cfg->rgctx_var) {
6175 MonoInst *ins = cfg->rgctx_var;
6177 g_assert (ins->opcode == OP_REGOFFSET);
6179 if (arm_is_imm12 (ins->inst_offset)) {
6180 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6182 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6183 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6187 /* load arguments allocated to register from the stack */
6190 cinfo = get_call_info (NULL, sig);
6192 if (cinfo->ret.storage == RegTypeStructByAddr) {
6193 ArgInfo *ainfo = &cinfo->ret;
6194 inst = cfg->vret_addr;
6195 g_assert (arm_is_imm12 (inst->inst_offset));
6196 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6199 if (sig->call_convention == MONO_CALL_VARARG) {
6200 ArgInfo *cookie = &cinfo->sig_cookie;
6202 /* Save the sig cookie address */
6203 g_assert (cookie->storage == RegTypeBase);
6205 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6206 g_assert (arm_is_imm12 (cfg->sig_cookie));
6207 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6208 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6211 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6212 ArgInfo *ainfo = cinfo->args + i;
6213 inst = cfg->args [pos];
6215 if (cfg->verbose_level > 2)
6216 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6218 if (inst->opcode == OP_REGVAR) {
6219 if (ainfo->storage == RegTypeGeneral)
6220 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6221 else if (ainfo->storage == RegTypeFP) {
6222 g_assert_not_reached ();
6223 } else if (ainfo->storage == RegTypeBase) {
6224 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6225 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6227 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6228 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6231 g_assert_not_reached ();
6233 if (cfg->verbose_level > 2)
6234 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6236 switch (ainfo->storage) {
6238 for (part = 0; part < ainfo->nregs; part ++) {
6239 if (ainfo->esize == 4)
6240 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6242 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6245 case RegTypeGeneral:
6246 case RegTypeIRegPair:
6247 case RegTypeGSharedVtInReg:
6248 case RegTypeStructByAddr:
6249 switch (ainfo->size) {
6251 if (arm_is_imm12 (inst->inst_offset))
6252 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6254 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6255 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6259 if (arm_is_imm8 (inst->inst_offset)) {
6260 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6262 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6263 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6267 if (arm_is_imm12 (inst->inst_offset)) {
6268 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6270 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6271 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6273 if (arm_is_imm12 (inst->inst_offset + 4)) {
6274 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6276 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6277 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6281 if (arm_is_imm12 (inst->inst_offset)) {
6282 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6284 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6285 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6290 case RegTypeBaseGen:
6291 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6292 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6294 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6295 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6297 if (arm_is_imm12 (inst->inst_offset + 4)) {
6298 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6299 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6301 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6302 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6303 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6304 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6308 case RegTypeGSharedVtOnStack:
6309 case RegTypeStructByAddrOnStack:
6310 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6311 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6313 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6314 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6317 switch (ainfo->size) {
6319 if (arm_is_imm8 (inst->inst_offset)) {
6320 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6322 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6323 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6327 if (arm_is_imm8 (inst->inst_offset)) {
6328 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6330 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6331 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6335 if (arm_is_imm12 (inst->inst_offset)) {
6336 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6338 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6339 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6341 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6342 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6344 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6345 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6347 if (arm_is_imm12 (inst->inst_offset + 4)) {
6348 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6350 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6351 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6355 if (arm_is_imm12 (inst->inst_offset)) {
6356 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6358 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6359 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6365 int imm8, rot_amount;
6367 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6368 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6369 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6371 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6373 if (ainfo->size == 8)
6374 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6376 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6379 case RegTypeStructByVal: {
6380 int doffset = inst->inst_offset;
6384 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6385 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6386 if (arm_is_imm12 (doffset)) {
6387 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6389 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6390 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6392 soffset += sizeof (gpointer);
6393 doffset += sizeof (gpointer);
6395 if (ainfo->vtsize) {
6396 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6397 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6398 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6403 g_assert_not_reached ();
6410 if (method->save_lmf)
6411 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6414 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6416 if (cfg->arch.seq_point_info_var) {
6417 MonoInst *ins = cfg->arch.seq_point_info_var;
6419 /* Initialize the variable from a GOT slot */
6420 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6421 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6423 *(gpointer*)code = NULL;
6425 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6427 g_assert (ins->opcode == OP_REGOFFSET);
6429 if (arm_is_imm12 (ins->inst_offset)) {
6430 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6432 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6433 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6437 /* Initialize ss_trigger_page_var */
6438 if (!cfg->soft_breakpoints) {
6439 MonoInst *info_var = cfg->arch.seq_point_info_var;
6440 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6441 int dreg = ARMREG_LR;
6444 g_assert (info_var->opcode == OP_REGOFFSET);
6445 g_assert (arm_is_imm12 (info_var->inst_offset));
6447 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6448 /* Load the trigger page addr */
6449 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6450 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6454 if (cfg->arch.seq_point_ss_method_var) {
6455 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6456 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6458 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6459 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6461 if (cfg->compile_aot) {
6462 MonoInst *info_var = cfg->arch.seq_point_info_var;
6463 int dreg = ARMREG_LR;
6465 g_assert (info_var->opcode == OP_REGOFFSET);
6466 g_assert (arm_is_imm12 (info_var->inst_offset));
6468 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6469 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6470 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6472 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6473 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6475 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6477 *(gpointer*)code = &single_step_tramp;
6479 *(gpointer*)code = breakpoint_tramp;
6482 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6483 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6484 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6485 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6489 cfg->code_len = code - cfg->native_code;
6490 g_assert (cfg->code_len < cfg->code_size);
6497 mono_arch_emit_epilog (MonoCompile *cfg)
6499 MonoMethod *method = cfg->method;
6500 int pos, i, rot_amount;
6501 int max_epilog_size = 16 + 20*4;
6505 if (cfg->method->save_lmf)
6506 max_epilog_size += 128;
6508 if (mono_jit_trace_calls != NULL)
6509 max_epilog_size += 50;
6511 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6512 max_epilog_size += 50;
6514 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6515 cfg->code_size *= 2;
6516 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6517 cfg->stat_code_reallocs++;
6521 * Keep in sync with OP_JMP
6523 code = cfg->native_code + cfg->code_len;
6525 /* Save the uwind state which is needed by the out-of-line code */
6526 mono_emit_unwind_op_remember_state (cfg, code);
6528 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6529 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6533 /* Load returned vtypes into registers if needed */
6534 cinfo = cfg->arch.cinfo;
6535 switch (cinfo->ret.storage) {
6536 case RegTypeStructByVal: {
6537 MonoInst *ins = cfg->ret;
6539 if (cinfo->ret.nregs == 1) {
6540 if (arm_is_imm12 (ins->inst_offset)) {
6541 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6543 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6544 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6547 for (i = 0; i < cinfo->ret.nregs; ++i) {
6548 int offset = ins->inst_offset + (i * 4);
6549 if (arm_is_imm12 (offset)) {
6550 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6552 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6553 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6560 MonoInst *ins = cfg->ret;
6562 for (i = 0; i < cinfo->ret.nregs; ++i) {
6563 if (cinfo->ret.esize == 4)
6564 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6566 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6574 if (method->save_lmf) {
6575 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6576 /* all but r0-r3, sp and pc */
6577 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6580 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6582 /* This points to r4 inside MonoLMF->iregs */
6583 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6585 regmask = 0x9ff0; /* restore lr to pc */
6586 /* Skip caller saved registers not used by the method */
6587 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6588 regmask &= ~(1 << reg);
6593 /* Restored later */
6594 regmask &= ~(1 << ARMREG_PC);
6595 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6596 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6597 for (i = 0; i < 16; i++) {
6598 if (regmask & (1 << i))
6601 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6603 ARM_POP (code, regmask);
6605 for (i = 0; i < 16; i++) {
6606 if (regmask & (1 << i))
6607 mono_emit_unwind_op_same_value (cfg, code, i);
6609 /* Restore saved r7, restore LR to PC */
6610 /* Skip lr from the lmf */
6611 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6612 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6613 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6614 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6617 int i, nused_int_regs = 0;
6619 for (i = 0; i < 16; i++) {
6620 if (cfg->used_int_regs & (1 << i))
6624 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6625 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6627 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6628 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6631 if (cfg->frame_reg != ARMREG_SP) {
6632 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6636 /* Restore saved gregs */
6637 if (cfg->used_int_regs) {
6638 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6639 ARM_POP (code, cfg->used_int_regs);
6640 for (i = 0; i < 16; i++) {
6641 if (cfg->used_int_regs & (1 << i))
6642 mono_emit_unwind_op_same_value (cfg, code, i);
6645 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6646 /* Restore saved r7, restore LR to PC */
6647 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6649 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6650 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6654 /* Restore the unwind state to be the same as before the epilog */
6655 mono_emit_unwind_op_restore_state (cfg, code);
6657 cfg->code_len = code - cfg->native_code;
6659 g_assert (cfg->code_len < cfg->code_size);
6664 mono_arch_emit_exceptions (MonoCompile *cfg)
6666 MonoJumpInfo *patch_info;
6669 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6670 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6671 int max_epilog_size = 50;
6673 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6674 exc_throw_pos [i] = NULL;
6675 exc_throw_found [i] = 0;
6678 /* count the number of exception infos */
6681 * make sure we have enough space for exceptions
6683 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6684 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6685 i = mini_exception_id_by_name (patch_info->data.target);
6686 if (!exc_throw_found [i]) {
6687 max_epilog_size += 32;
6688 exc_throw_found [i] = TRUE;
6693 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6694 cfg->code_size *= 2;
6695 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6696 cfg->stat_code_reallocs++;
6699 code = cfg->native_code + cfg->code_len;
6701 /* add code to raise exceptions */
6702 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6703 switch (patch_info->type) {
6704 case MONO_PATCH_INFO_EXC: {
6705 MonoClass *exc_class;
6706 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6708 i = mini_exception_id_by_name (patch_info->data.target);
6709 if (exc_throw_pos [i]) {
6710 arm_patch (ip, exc_throw_pos [i]);
6711 patch_info->type = MONO_PATCH_INFO_NONE;
6714 exc_throw_pos [i] = code;
6716 arm_patch (ip, code);
6718 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6720 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6721 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6722 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6723 patch_info->data.name = "mono_arch_throw_corlib_exception";
6724 patch_info->ip.i = code - cfg->native_code;
6726 cfg->thunk_area += THUNK_SIZE;
6727 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6737 cfg->code_len = code - cfg->native_code;
6739 g_assert (cfg->code_len < cfg->code_size);
6743 #endif /* #ifndef DISABLE_JIT */
6746 mono_arch_finish_init (void)
6751 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6756 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6763 mono_arch_print_tree (MonoInst *tree, int arity)
6773 mono_arch_get_patch_offset (guint8 *code)
6780 mono_arch_flush_register_windows (void)
6785 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6787 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6791 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6793 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6797 mono_arch_get_cie_program (void)
6801 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6806 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6807 #define BASE_SIZE (6 * 4)
6808 #define BSEARCH_ENTRY_SIZE (4 * 4)
6809 #define CMP_SIZE (3 * 4)
6810 #define BRANCH_SIZE (1 * 4)
6811 #define CALL_SIZE (2 * 4)
6812 #define WMC_SIZE (8 * 4)
6813 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6816 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6818 guint32 delta = DISTANCE (target, code);
6820 g_assert (delta >= 0 && delta <= 0xFFF);
6821 *target = *target | delta;
6826 #ifdef ENABLE_WRONG_METHOD_CHECK
6828 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6830 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6836 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6837 gpointer fail_tramp)
6840 arminstr_t *code, *start;
6841 gboolean large_offsets = FALSE;
6842 guint32 **constant_pool_starts;
6843 arminstr_t *vtable_target = NULL;
6844 int extra_space = 0;
6845 #ifdef ENABLE_WRONG_METHOD_CHECK
6851 constant_pool_starts = g_new0 (guint32*, count);
6853 for (i = 0; i < count; ++i) {
6854 MonoIMTCheckItem *item = imt_entries [i];
6855 if (item->is_equals) {
6856 gboolean fail_case = !item->check_target_idx && fail_tramp;
6858 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6859 item->chunk_size += 32;
6860 large_offsets = TRUE;
6863 if (item->check_target_idx || fail_case) {
6864 if (!item->compare_done || fail_case)
6865 item->chunk_size += CMP_SIZE;
6866 item->chunk_size += BRANCH_SIZE;
6868 #ifdef ENABLE_WRONG_METHOD_CHECK
6869 item->chunk_size += WMC_SIZE;
6873 item->chunk_size += 16;
6874 large_offsets = TRUE;
6876 item->chunk_size += CALL_SIZE;
6878 item->chunk_size += BSEARCH_ENTRY_SIZE;
6879 imt_entries [item->check_target_idx]->compare_done = TRUE;
6881 size += item->chunk_size;
6885 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6888 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6890 code = mono_domain_code_reserve (domain, size);
6893 unwind_ops = mono_arch_get_cie_program ();
6896 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6897 for (i = 0; i < count; ++i) {
6898 MonoIMTCheckItem *item = imt_entries [i];
6899 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6903 if (large_offsets) {
6904 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6905 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6907 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6908 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6910 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6911 vtable_target = code;
6912 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6913 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6915 for (i = 0; i < count; ++i) {
6916 MonoIMTCheckItem *item = imt_entries [i];
6917 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6918 gint32 vtable_offset;
6920 item->code_target = (guint8*)code;
6922 if (item->is_equals) {
6923 gboolean fail_case = !item->check_target_idx && fail_tramp;
6925 if (item->check_target_idx || fail_case) {
6926 if (!item->compare_done || fail_case) {
6928 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6929 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6931 item->jmp_code = (guint8*)code;
6932 ARM_B_COND (code, ARMCOND_NE, 0);
6934 /*Enable the commented code to assert on wrong method*/
6935 #ifdef ENABLE_WRONG_METHOD_CHECK
6937 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6938 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6940 ARM_B_COND (code, ARMCOND_EQ, 0);
6942 /* Define this if your system is so bad that gdb is failing. */
6943 #ifdef BROKEN_DEV_ENV
6944 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6946 arm_patch (code - 1, mini_dump_bad_imt);
6950 arm_patch (cond, code);
6954 if (item->has_target_code) {
6955 /* Load target address */
6956 target_code_ins = code;
6957 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6958 /* Save it to the fourth slot */
6959 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6960 /* Restore registers and branch */
6961 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6963 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6965 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6966 if (!arm_is_imm12 (vtable_offset)) {
6968 * We need to branch to a computed address but we don't have
6969 * a free register to store it, since IP must contain the
6970 * vtable address. So we push the two values to the stack, and
6971 * load them both using LDM.
6973 /* Compute target address */
6974 vtable_offset_ins = code;
6975 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6976 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6977 /* Save it to the fourth slot */
6978 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6979 /* Restore registers and branch */
6980 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6982 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6984 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6985 if (large_offsets) {
6986 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6987 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6989 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6990 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6995 arm_patch (item->jmp_code, (guchar*)code);
6997 target_code_ins = code;
6998 /* Load target address */
6999 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7000 /* Save it to the fourth slot */
7001 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7002 /* Restore registers and branch */
7003 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7005 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7006 item->jmp_code = NULL;
7010 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7012 /*must emit after unconditional branch*/
7013 if (vtable_target) {
7014 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7015 item->chunk_size += 4;
7016 vtable_target = NULL;
7019 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7020 constant_pool_starts [i] = code;
7022 code += extra_space;
7026 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7027 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7029 item->jmp_code = (guint8*)code;
7030 ARM_B_COND (code, ARMCOND_HS, 0);
7035 for (i = 0; i < count; ++i) {
7036 MonoIMTCheckItem *item = imt_entries [i];
7037 if (item->jmp_code) {
7038 if (item->check_target_idx)
7039 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7041 if (i > 0 && item->is_equals) {
7043 arminstr_t *space_start = constant_pool_starts [i];
7044 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7045 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7052 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7053 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7058 g_free (constant_pool_starts);
7060 mono_arch_flush_icache ((guint8*)start, size);
7061 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7062 mono_stats.imt_trampolines_size += code - start;
7064 g_assert (DISTANCE (start, code) <= size);
7066 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7072 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7074 return ctx->regs [reg];
7078 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7080 ctx->regs [reg] = val;
7084 * mono_arch_get_trampolines:
7086 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7090 mono_arch_get_trampolines (gboolean aot)
7092 return mono_arm_get_exception_trampolines (aot);
7096 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7103 bp = MONO_CONTEXT_GET_BP (ctx);
7104 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7106 old_value = *lr_loc;
7107 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7110 *lr_loc = new_value;
7115 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7117 * mono_arch_set_breakpoint:
7119 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7120 * The location should contain code emitted by OP_SEQ_POINT.
7123 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7126 guint32 native_offset = ip - (guint8*)ji->code_start;
7127 MonoDebugOptions *opt = mini_get_debug_options ();
7130 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7132 if (!breakpoint_tramp)
7133 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7135 g_assert (native_offset % 4 == 0);
7136 g_assert (info->bp_addrs [native_offset / 4] == 0);
7137 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7138 } else if (opt->soft_breakpoints) {
7140 ARM_BLX_REG (code, ARMREG_LR);
7141 mono_arch_flush_icache (code - 4, 4);
7143 int dreg = ARMREG_LR;
7145 /* Read from another trigger page */
7146 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7148 *(int*)code = (int)bp_trigger_page;
7150 ARM_LDR_IMM (code, dreg, dreg, 0);
7152 mono_arch_flush_icache (code - 16, 16);
7155 /* This is currently implemented by emitting an SWI instruction, which
7156 * qemu/linux seems to convert to a SIGILL.
7158 *(int*)code = (0xef << 24) | 8;
7160 mono_arch_flush_icache (code - 4, 4);
7166 * mono_arch_clear_breakpoint:
7168 * Clear the breakpoint at IP.
7171 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7173 MonoDebugOptions *opt = mini_get_debug_options ();
7178 guint32 native_offset = ip - (guint8*)ji->code_start;
7179 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7181 if (!breakpoint_tramp)
7182 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7184 g_assert (native_offset % 4 == 0);
7185 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7186 info->bp_addrs [native_offset / 4] = 0;
7187 } else if (opt->soft_breakpoints) {
7190 mono_arch_flush_icache (code - 4, 4);
7192 for (i = 0; i < 4; ++i)
7195 mono_arch_flush_icache (ip, code - ip);
7200 * mono_arch_start_single_stepping:
7202 * Start single stepping.
7205 mono_arch_start_single_stepping (void)
7207 if (ss_trigger_page)
7208 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7210 single_step_tramp = mini_get_single_step_trampoline ();
7214 * mono_arch_stop_single_stepping:
7216 * Stop single stepping.
7219 mono_arch_stop_single_stepping (void)
7221 if (ss_trigger_page)
7222 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7224 single_step_tramp = NULL;
7228 #define DBG_SIGNAL SIGBUS
7230 #define DBG_SIGNAL SIGSEGV
7234 * mono_arch_is_single_step_event:
7236 * Return whenever the machine state in SIGCTX corresponds to a single
7240 mono_arch_is_single_step_event (void *info, void *sigctx)
7242 siginfo_t *sinfo = info;
7244 if (!ss_trigger_page)
7247 /* Sometimes the address is off by 4 */
7248 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7255 * mono_arch_is_breakpoint_event:
7257 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7260 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7262 siginfo_t *sinfo = info;
7264 if (!ss_trigger_page)
7267 if (sinfo->si_signo == DBG_SIGNAL) {
7268 /* Sometimes the address is off by 4 */
7269 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7279 * mono_arch_skip_breakpoint:
7281 * See mini-amd64.c for docs.
7284 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7286 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7290 * mono_arch_skip_single_step:
7292 * See mini-amd64.c for docs.
7295 mono_arch_skip_single_step (MonoContext *ctx)
7297 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7300 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7303 * mono_arch_get_seq_point_info:
7305 * See mini-amd64.c for docs.
7308 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7313 // FIXME: Add a free function
7315 mono_domain_lock (domain);
7316 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7318 mono_domain_unlock (domain);
7321 ji = mono_jit_info_table_find (domain, (char*)code);
7324 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7326 info->ss_trigger_page = ss_trigger_page;
7327 info->bp_trigger_page = bp_trigger_page;
7328 info->ss_tramp_addr = &single_step_tramp;
7330 mono_domain_lock (domain);
7331 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7333 mono_domain_unlock (domain);
7340 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7342 ext->lmf.previous_lmf = prev_lmf;
7343 /* Mark that this is a MonoLMFExt */
7344 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7345 ext->lmf.sp = (gssize)ext;
7349 * mono_arch_set_target:
7351 * Set the target architecture the JIT backend should generate code for, in the form
7352 * of a GNU target triplet. Only used in AOT mode.
7355 mono_arch_set_target (char *mtriple)
7357 /* The GNU target triple format is not very well documented */
7358 if (strstr (mtriple, "armv7")) {
7359 v5_supported = TRUE;
7360 v6_supported = TRUE;
7361 v7_supported = TRUE;
7363 if (strstr (mtriple, "armv6")) {
7364 v5_supported = TRUE;
7365 v6_supported = TRUE;
7367 if (strstr (mtriple, "armv7s")) {
7368 v7s_supported = TRUE;
7370 if (strstr (mtriple, "armv7k")) {
7371 v7k_supported = TRUE;
7373 if (strstr (mtriple, "thumbv7s")) {
7374 v5_supported = TRUE;
7375 v6_supported = TRUE;
7376 v7_supported = TRUE;
7377 v7s_supported = TRUE;
7378 thumb_supported = TRUE;
7379 thumb2_supported = TRUE;
7381 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7382 v5_supported = TRUE;
7383 v6_supported = TRUE;
7384 thumb_supported = TRUE;
7387 if (strstr (mtriple, "gnueabi"))
7388 eabi_supported = TRUE;
7392 mono_arch_opcode_supported (int opcode)
7395 case OP_ATOMIC_ADD_I4:
7396 case OP_ATOMIC_EXCHANGE_I4:
7397 case OP_ATOMIC_CAS_I4:
7398 case OP_ATOMIC_LOAD_I1:
7399 case OP_ATOMIC_LOAD_I2:
7400 case OP_ATOMIC_LOAD_I4:
7401 case OP_ATOMIC_LOAD_U1:
7402 case OP_ATOMIC_LOAD_U2:
7403 case OP_ATOMIC_LOAD_U4:
7404 case OP_ATOMIC_STORE_I1:
7405 case OP_ATOMIC_STORE_I2:
7406 case OP_ATOMIC_STORE_I4:
7407 case OP_ATOMIC_STORE_U1:
7408 case OP_ATOMIC_STORE_U2:
7409 case OP_ATOMIC_STORE_U4:
7410 return v7_supported;
7411 case OP_ATOMIC_LOAD_R4:
7412 case OP_ATOMIC_LOAD_R8:
7413 case OP_ATOMIC_STORE_R4:
7414 case OP_ATOMIC_STORE_R8:
7415 return v7_supported && IS_VFP;
7422 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7424 return get_call_info (mp, sig);
7428 mono_arch_get_get_tls_tramp (void)
7434 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7437 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7438 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7440 *(gpointer*)code = NULL;
7442 /* Load the value from the GOT */
7443 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);
7448 mono_arm_emit_aotconst (gpointer ji_list, guint8 *code, guint8 *buf, int dreg, int patch_type, gconstpointer data)
7450 MonoJumpInfo **ji = (MonoJumpInfo**)ji_list;
7452 *ji = mono_patch_info_list_prepend (*ji, code - buf, patch_type, data);
7453 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7455 *(gpointer*)code = NULL;
7457 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);