mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  16  */
  17 #include "mini.h"
  18 #include <string.h>
  19 #include <math.h>
  20 #ifdef HAVE_UNISTD_H
  21 #include <unistd.h>
  22 #endif
  23
  24 #include <mono/metadata/abi-details.h>
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/metadata/threads.h>
  28 #include <mono/metadata/profiler-private.h>
  29 #include <mono/metadata/mono-debug.h>
  30 #include <mono/metadata/gc-internals.h>
  31 #include <mono/utils/mono-math.h>
  32 #include <mono/utils/mono-mmap.h>
  33 #include <mono/utils/mono-memory-model.h>
  34 #include <mono/utils/mono-tls.h>
  35 #include <mono/utils/mono-hwcap-x86.h>
  36 #include <mono/utils/mono-threads.h>
  37
  38 #include "trace.h"
  39 #include "ir-emit.h"
  40 #include "mini-amd64.h"
  41 #include "cpu-amd64.h"
  42 #include "debugger-agent.h"
  43 #include "mini-gc.h"
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef TARGET_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  67 static mono_mutex_t mini_arch_mutex;
  68
  69 /* The single step trampoline */
  70 static gpointer ss_trampoline;
  71
  72 /* The breakpoint trampoline */
  73 static gpointer bp_trampoline;
  74
  75 /* Offset between fp and the first argument in the callee */
  76 #define ARGS_OFFSET 16
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return mono_debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline gboolean
 169 amd64_use_imm32 (gint64 val)
 170 {
 171         if (mini_get_debug_options()->single_imm_size)
 172                 return FALSE;
 173
 174         return amd64_is_imm32 (val);
 175 }
 176
 177 static void
 178 amd64_patch (unsigned char* code, gpointer target)
 179 {
 180         guint8 rex = 0;
 181
 182         /* Skip REX */
 183         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 184                 rex = code [0];
 185                 code += 1;
 186         }
 187
 188         if ((code [0] & 0xf8) == 0xb8) {
 189                 /* amd64_set_reg_template */
 190                 *(guint64*)(code + 1) = (guint64)target;
 191         }
 192         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 193                 /* mov 0(%rip), %dreg */
 194                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 195         }
 196         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 197                 /* call *<OFFSET>(%rip) */
 198                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 199         }
 200         else if (code [0] == 0xe8) {
 201                 /* call <DISP> */
 202                 gint64 disp = (guint8*)target - (guint8*)code;
 203                 g_assert (amd64_is_imm32 (disp));
 204                 x86_patch (code, (unsigned char*)target);
 205         }
 206         else
 207                 x86_patch (code, (unsigned char*)target);
 208 }
 209
 210 void
 211 mono_amd64_patch (unsigned char* code, gpointer target)
 212 {
 213         amd64_patch (code, target);
 214 }
 215
 216 #define DEBUG(a) if (cfg->verbose_level > 1) a
 217
 218 static void inline
 219 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 ainfo->arg_size = sizeof (mgreg_t);
 226                 /* Since the same stack slot size is used for all arg */
 227                 /*  types, it needs to be big enough to hold them all */
 228                 (*stack_size) += sizeof(mgreg_t);
 229     }
 230     else {
 231                 ainfo->storage = ArgInIReg;
 232                 ainfo->reg = param_regs [*gr];
 233                 (*gr) ++;
 234     }
 235 }
 236
 237 static void inline
 238 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 239 {
 240     ainfo->offset = *stack_size;
 241
 242     if (*gr >= FLOAT_PARAM_REGS) {
 243                 ainfo->storage = ArgOnStack;
 244                 ainfo->arg_size = sizeof (mgreg_t);
 245                 /* Since the same stack slot size is used for both float */
 246                 /*  types, it needs to be big enough to hold them both */
 247                 (*stack_size) += sizeof(mgreg_t);
 248     }
 249     else {
 250                 /* A double register */
 251                 if (is_double)
 252                         ainfo->storage = ArgInDoubleSSEReg;
 253                 else
 254                         ainfo->storage = ArgInFloatSSEReg;
 255                 ainfo->reg = *gr;
 256                 (*gr) += 1;
 257     }
 258 }
 259
 260 typedef enum ArgumentClass {
 261         ARG_CLASS_NO_CLASS,
 262         ARG_CLASS_MEMORY,
 263         ARG_CLASS_INTEGER,
 264         ARG_CLASS_SSE
 265 } ArgumentClass;
 266
 267 static ArgumentClass
 268 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 269 {
 270         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 271         MonoType *ptype;
 272
 273         ptype = mini_get_underlying_type (type);
 274         switch (ptype->type) {
 275         case MONO_TYPE_I1:
 276         case MONO_TYPE_U1:
 277         case MONO_TYPE_I2:
 278         case MONO_TYPE_U2:
 279         case MONO_TYPE_I4:
 280         case MONO_TYPE_U4:
 281         case MONO_TYPE_I:
 282         case MONO_TYPE_U:
 283         case MONO_TYPE_STRING:
 284         case MONO_TYPE_OBJECT:
 285         case MONO_TYPE_CLASS:
 286         case MONO_TYPE_SZARRAY:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_ARRAY:
 290         case MONO_TYPE_I8:
 291         case MONO_TYPE_U8:
 292                 class2 = ARG_CLASS_INTEGER;
 293                 break;
 294         case MONO_TYPE_R4:
 295         case MONO_TYPE_R8:
 296 #ifdef TARGET_WIN32
 297                 class2 = ARG_CLASS_INTEGER;
 298 #else
 299                 class2 = ARG_CLASS_SSE;
 300 #endif
 301                 break;
 302
 303         case MONO_TYPE_TYPEDBYREF:
 304                 g_assert_not_reached ();
 305
 306         case MONO_TYPE_GENERICINST:
 307                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 308                         class2 = ARG_CLASS_INTEGER;
 309                         break;
 310                 }
 311                 /* fall through */
 312         case MONO_TYPE_VALUETYPE: {
 313                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 314                 int i;
 315
 316                 for (i = 0; i < info->num_fields; ++i) {
 317                         class2 = class1;
 318                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 319                 }
 320                 break;
 321         }
 322         default:
 323                 g_assert_not_reached ();
 324         }
 325
 326         /* Merge */
 327         if (class1 == class2)
 328                 ;
 329         else if (class1 == ARG_CLASS_NO_CLASS)
 330                 class1 = class2;
 331         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 332                 class1 = ARG_CLASS_MEMORY;
 333         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 334                 class1 = ARG_CLASS_INTEGER;
 335         else
 336                 class1 = ARG_CLASS_SSE;
 337
 338         return class1;
 339 }
 340
 341 static int
 342 count_fields_nested (MonoClass *klass)
 343 {
 344         MonoMarshalType *info;
 345         int i, count;
 346
 347         info = mono_marshal_load_type_info (klass);
 348         g_assert(info);
 349         count = 0;
 350         for (i = 0; i < info->num_fields; ++i) {
 351                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 352                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 353                 else
 354                         count ++;
 355         }
 356         return count;
 357 }
 358
 359 static int
 360 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 361 {
 362         MonoMarshalType *info;
 363         int i;
 364
 365         info = mono_marshal_load_type_info (klass);
 366         g_assert(info);
 367         for (i = 0; i < info->num_fields; ++i) {
 368                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 369                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 370                 } else {
 371                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 372                         fields [index].offset += offset;
 373                         index ++;
 374                 }
 375         }
 376         return index;
 377 }
 378
 379 #ifdef TARGET_WIN32
 380 static void
 381 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 382                                          gboolean is_return,
 383                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 384 {
 385         guint32 size, i, nfields;
 386         guint32 argsize = 8;
 387         ArgumentClass arg_class;
 388         MonoMarshalType *info = NULL;
 389         MonoMarshalField *fields = NULL;
 390         MonoClass *klass;
 391         gboolean pass_on_stack = FALSE;
 392
 393         klass = mono_class_from_mono_type (type);
 394         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 395
 396         /*
 397         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 398         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 399         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 400         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 401         * it must be represented in call and cannot be dropped.
 402         */
 403         if (0 == size && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke)
 404                 ainfo->pass_empty_struct = TRUE;
 405
 406         if (!sig->pinvoke)
 407                 pass_on_stack = TRUE;
 408
 409         /* If this struct can't be split up naturally into 8-byte */
 410         /* chunks (registers), pass it on the stack.              */
 411         if (sig->pinvoke && !pass_on_stack) {
 412                 guint32 align;
 413                 guint32 field_size;
 414
 415                 info = mono_marshal_load_type_info (klass);
 416                 g_assert (info);
 417
 418                 /*
 419                  * Collect field information recursively to be able to
 420                  * handle nested structures.
 421                  */
 422                 nfields = count_fields_nested (klass);
 423                 fields = g_new0 (MonoMarshalField, nfields);
 424                 collect_field_info_nested (klass, fields, 0, 0);
 425
 426                 for (i = 0; i < nfields; ++i) {
 427                         field_size = mono_marshal_type_size (fields [i].field->type,
 428                                                            fields [i].mspec,
 429                                                            &align, TRUE, klass->unicode);
 430                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 431                                 pass_on_stack = TRUE;
 432                                 break;
 433                         }
 434                 }
 435         }
 436
 437         if (pass_on_stack) {
 438                 /* Allways pass in memory */
 439                 ainfo->offset = *stack_size;
 440                 *stack_size += ALIGN_TO (size, 8);
 441                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 442                 if (!is_return)
 443                         ainfo->arg_size = ALIGN_TO (size, 8);
 444
 445                 g_free (fields);
 446                 return;
 447         }
 448
 449         if (!sig->pinvoke) {
 450                 int n = mono_class_value_size (klass, NULL);
 451
 452                 argsize = n;
 453
 454                 if (n > 8)
 455                         arg_class = ARG_CLASS_MEMORY;
 456                 else
 457                         /* Always pass in 1 integer register */
 458                         arg_class = ARG_CLASS_INTEGER;
 459         } else {
 460                 g_assert (info);
 461
 462                 /*Only drop value type if its not an empty struct as input that must be represented in call*/
 463                 if ((!fields && !ainfo->pass_empty_struct) || (!fields && ainfo->pass_empty_struct && is_return)) {
 464                         ainfo->storage = ArgValuetypeInReg;
 465                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 466                         return;
 467                 }
 468
 469                 switch (info->native_size) {
 470                 case 0:
 471                         g_assert (!fields && MONO_TYPE_ISSTRUCT (type) && !is_return);
 472                         break;
 473                 case 1: case 2: case 4: case 8:
 474                         break;
 475                 default:
 476                         if (is_return) {
 477                                 ainfo->storage = ArgValuetypeAddrInIReg;
 478                                 ainfo->offset = *stack_size;
 479                                 *stack_size += ALIGN_TO (info->native_size, 8);
 480                         }
 481                         else {
 482                                 ainfo->storage = ArgValuetypeAddrInIReg;
 483
 484                                 if (*gr < PARAM_REGS) {
 485                                         ainfo->pair_storage [0] = ArgInIReg;
 486                                         ainfo->pair_regs [0] = param_regs [*gr];
 487                                         (*gr) ++;
 488                                 }
 489                                 else {
 490                                         ainfo->pair_storage [0] = ArgOnStack;
 491                                         ainfo->offset = *stack_size;
 492                                         ainfo->arg_size = sizeof (mgreg_t);
 493                                         *stack_size += 8;
 494                                 }
 495                         }
 496
 497                         g_free (fields);
 498                         return;
 499                 }
 500
 501                 int size;
 502                 guint32 align;
 503                 ArgumentClass class1;
 504
 505                 if (nfields == 0 && ainfo->pass_empty_struct) {
 506                         g_assert (!fields && !is_return);
 507                         class1 = ARG_CLASS_INTEGER;
 508                 }
 509                 else if (nfields == 0)
 510                         class1 = ARG_CLASS_MEMORY;
 511                 else
 512                         class1 = ARG_CLASS_NO_CLASS;
 513                 for (i = 0; i < nfields; ++i) {
 514                         size = mono_marshal_type_size (fields [i].field->type,
 515                                                                                    fields [i].mspec,
 516                                                                                    &align, TRUE, klass->unicode);
 517                         /* How far into this quad this data extends.*/
 518                         /* (8 is size of quad) */
 519                         argsize = fields [i].offset + size;
 520
 521                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 522                 }
 523                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 524                 arg_class = class1;
 525         }
 526
 527         g_free (fields);
 528
 529         /* Allocate registers */
 530         {
 531                 int orig_gr = *gr;
 532                 int orig_fr = *fr;
 533
 534                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 535                         argsize ++;
 536
 537                 ainfo->storage = ArgValuetypeInReg;
 538                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 539                 ainfo->pair_size [0] = argsize;
 540                 ainfo->pair_size [1] = 0;
 541                 ainfo->nregs = 1;
 542                 switch (arg_class) {
 543                 case ARG_CLASS_INTEGER:
 544                         if (*gr >= PARAM_REGS)
 545                                 arg_class = ARG_CLASS_MEMORY;
 546                         else {
 547                                 ainfo->pair_storage [0] = ArgInIReg;
 548                                 if (is_return)
 549                                         ainfo->pair_regs [0] = return_regs [*gr];
 550                                 else
 551                                         ainfo->pair_regs [0] = param_regs [*gr];
 552                                 (*gr) ++;
 553                         }
 554                         break;
 555                 case ARG_CLASS_SSE:
 556                         if (*fr >= FLOAT_PARAM_REGS)
 557                                 arg_class = ARG_CLASS_MEMORY;
 558                         else {
 559                                 if (argsize <= 4)
 560                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 561                                 else
 562                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 563                                 ainfo->pair_regs [0] = *fr;
 564                                 (*fr) ++;
 565                         }
 566                         break;
 567                 case ARG_CLASS_MEMORY:
 568                         break;
 569                 default:
 570                         g_assert_not_reached ();
 571                 }
 572
 573                 if (arg_class == ARG_CLASS_MEMORY) {
 574                         /* Revert possible register assignments */
 575                         *gr = orig_gr;
 576                         *fr = orig_fr;
 577
 578                         ainfo->offset = *stack_size;
 579                         *stack_size += sizeof (mgreg_t);
 580                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 581                         if (!is_return)
 582                                 ainfo->arg_size = sizeof (mgreg_t);
 583                 }
 584         }
 585 }
 586 #endif /* TARGET_WIN32 */
 587
 588 static void
 589 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 590                            gboolean is_return,
 591                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 592 {
 593 #ifdef TARGET_WIN32
 594         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 595 #else
 596         guint32 size, quad, nquads, i, nfields;
 597         /* Keep track of the size used in each quad so we can */
 598         /* use the right size when copying args/return vars.  */
 599         guint32 quadsize [2] = {8, 8};
 600         ArgumentClass args [2];
 601         MonoMarshalType *info = NULL;
 602         MonoMarshalField *fields = NULL;
 603         MonoClass *klass;
 604         gboolean pass_on_stack = FALSE;
 605
 606         klass = mono_class_from_mono_type (type);
 607         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 608
 609         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 610                 /* We pass and return vtypes of size 8 in a register */
 611         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 612                 pass_on_stack = TRUE;
 613         }
 614
 615         /* If this struct can't be split up naturally into 8-byte */
 616         /* chunks (registers), pass it on the stack.              */
 617         if (sig->pinvoke && !pass_on_stack) {
 618                 guint32 align;
 619                 guint32 field_size;
 620
 621                 info = mono_marshal_load_type_info (klass);
 622                 g_assert (info);
 623
 624                 /*
 625                  * Collect field information recursively to be able to
 626                  * handle nested structures.
 627                  */
 628                 nfields = count_fields_nested (klass);
 629                 fields = g_new0 (MonoMarshalField, nfields);
 630                 collect_field_info_nested (klass, fields, 0, 0);
 631
 632                 for (i = 0; i < nfields; ++i) {
 633                         field_size = mono_marshal_type_size (fields [i].field->type,
 634                                                            fields [i].mspec,
 635                                                            &align, TRUE, klass->unicode);
 636                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 637                                 pass_on_stack = TRUE;
 638                                 break;
 639                         }
 640                 }
 641         }
 642
 643         if (size == 0) {
 644                 ainfo->storage = ArgValuetypeInReg;
 645                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 646                 return;
 647         }
 648
 649         if (pass_on_stack) {
 650                 /* Allways pass in memory */
 651                 ainfo->offset = *stack_size;
 652                 *stack_size += ALIGN_TO (size, 8);
 653                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 654                 if (!is_return)
 655                         ainfo->arg_size = ALIGN_TO (size, 8);
 656
 657                 g_free (fields);
 658                 return;
 659         }
 660
 661         if (size > 8)
 662                 nquads = 2;
 663         else
 664                 nquads = 1;
 665
 666         if (!sig->pinvoke) {
 667                 int n = mono_class_value_size (klass, NULL);
 668
 669                 quadsize [0] = n >= 8 ? 8 : n;
 670                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 671
 672                 /* Always pass in 1 or 2 integer registers */
 673                 args [0] = ARG_CLASS_INTEGER;
 674                 args [1] = ARG_CLASS_INTEGER;
 675                 /* Only the simplest cases are supported */
 676                 if (is_return && nquads != 1) {
 677                         args [0] = ARG_CLASS_MEMORY;
 678                         args [1] = ARG_CLASS_MEMORY;
 679                 }
 680         } else {
 681                 /*
 682                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 683                  * The X87 and SSEUP stuff is left out since there are no such types in
 684                  * the CLR.
 685                  */
 686                 g_assert (info);
 687
 688                 if (!fields) {
 689                         ainfo->storage = ArgValuetypeInReg;
 690                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 691                         return;
 692                 }
 693
 694                 if (info->native_size > 16) {
 695                         ainfo->offset = *stack_size;
 696                         *stack_size += ALIGN_TO (info->native_size, 8);
 697                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 698                         if (!is_return)
 699                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
 700
 701                         g_free (fields);
 702                         return;
 703                 }
 704
 705                 args [0] = ARG_CLASS_NO_CLASS;
 706                 args [1] = ARG_CLASS_NO_CLASS;
 707                 for (quad = 0; quad < nquads; ++quad) {
 708                         int size;
 709                         guint32 align;
 710                         ArgumentClass class1;
 711
 712                         if (nfields == 0)
 713                                 class1 = ARG_CLASS_MEMORY;
 714                         else
 715                                 class1 = ARG_CLASS_NO_CLASS;
 716                         for (i = 0; i < nfields; ++i) {
 717                                 size = mono_marshal_type_size (fields [i].field->type,
 718                                                                                            fields [i].mspec,
 719                                                                                            &align, TRUE, klass->unicode);
 720                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 721                                         /* Unaligned field */
 722                                         NOT_IMPLEMENTED;
 723                                 }
 724
 725                                 /* Skip fields in other quad */
 726                                 if ((quad == 0) && (fields [i].offset >= 8))
 727                                         continue;
 728                                 if ((quad == 1) && (fields [i].offset < 8))
 729                                         continue;
 730
 731                                 /* How far into this quad this data extends.*/
 732                                 /* (8 is size of quad) */
 733                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 734
 735                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 736                         }
 737                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 738                         args [quad] = class1;
 739                 }
 740         }
 741
 742         g_free (fields);
 743
 744         /* Post merger cleanup */
 745         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 746                 args [0] = args [1] = ARG_CLASS_MEMORY;
 747
 748         /* Allocate registers */
 749         {
 750                 int orig_gr = *gr;
 751                 int orig_fr = *fr;
 752
 753                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 754                         quadsize [0] ++;
 755                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 756                         quadsize [1] ++;
 757
 758                 ainfo->storage = ArgValuetypeInReg;
 759                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 760                 g_assert (quadsize [0] <= 8);
 761                 g_assert (quadsize [1] <= 8);
 762                 ainfo->pair_size [0] = quadsize [0];
 763                 ainfo->pair_size [1] = quadsize [1];
 764                 ainfo->nregs = nquads;
 765                 for (quad = 0; quad < nquads; ++quad) {
 766                         switch (args [quad]) {
 767                         case ARG_CLASS_INTEGER:
 768                                 if (*gr >= PARAM_REGS)
 769                                         args [quad] = ARG_CLASS_MEMORY;
 770                                 else {
 771                                         ainfo->pair_storage [quad] = ArgInIReg;
 772                                         if (is_return)
 773                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 774                                         else
 775                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 776                                         (*gr) ++;
 777                                 }
 778                                 break;
 779                         case ARG_CLASS_SSE:
 780                                 if (*fr >= FLOAT_PARAM_REGS)
 781                                         args [quad] = ARG_CLASS_MEMORY;
 782                                 else {
 783                                         if (quadsize[quad] <= 4)
 784                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 785                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 786                                         ainfo->pair_regs [quad] = *fr;
 787                                         (*fr) ++;
 788                                 }
 789                                 break;
 790                         case ARG_CLASS_MEMORY:
 791                                 break;
 792                         default:
 793                                 g_assert_not_reached ();
 794                         }
 795                 }
 796
 797                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 798                         int arg_size;
 799                         /* Revert possible register assignments */
 800                         *gr = orig_gr;
 801                         *fr = orig_fr;
 802
 803                         ainfo->offset = *stack_size;
 804                         if (sig->pinvoke)
 805                                 arg_size = ALIGN_TO (info->native_size, 8);
 806                         else
 807                                 arg_size = nquads * sizeof(mgreg_t);
 808                         *stack_size += arg_size;
 809                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 810                         if (!is_return)
 811                                 ainfo->arg_size = arg_size;
 812                 }
 813         }
 814 #endif /* !TARGET_WIN32 */
 815 }
 816
 817 /*
 818  * get_call_info:
 819  *
 820  * Obtain information about a call according to the calling convention.
 821  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 822  * Draft Version 0.23" document for more information.
 823  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 824  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 825  */
 826 static CallInfo*
 827 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 828 {
 829         guint32 i, gr, fr, pstart;
 830         MonoType *ret_type;
 831         int n = sig->hasthis + sig->param_count;
 832         guint32 stack_size = 0;
 833         CallInfo *cinfo;
 834         gboolean is_pinvoke = sig->pinvoke;
 835
 836         if (mp)
 837                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 838         else
 839                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 840
 841         cinfo->nargs = n;
 842         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 843
 844         gr = 0;
 845         fr = 0;
 846
 847 #ifdef TARGET_WIN32
 848         /* Reserve space where the callee can save the argument registers */
 849         stack_size = 4 * sizeof (mgreg_t);
 850 #endif
 851
 852         /* return value */
 853         ret_type = mini_get_underlying_type (sig->ret);
 854         switch (ret_type->type) {
 855         case MONO_TYPE_I1:
 856         case MONO_TYPE_U1:
 857         case MONO_TYPE_I2:
 858         case MONO_TYPE_U2:
 859         case MONO_TYPE_I4:
 860         case MONO_TYPE_U4:
 861         case MONO_TYPE_I:
 862         case MONO_TYPE_U:
 863         case MONO_TYPE_PTR:
 864         case MONO_TYPE_FNPTR:
 865         case MONO_TYPE_CLASS:
 866         case MONO_TYPE_OBJECT:
 867         case MONO_TYPE_SZARRAY:
 868         case MONO_TYPE_ARRAY:
 869         case MONO_TYPE_STRING:
 870                 cinfo->ret.storage = ArgInIReg;
 871                 cinfo->ret.reg = AMD64_RAX;
 872                 break;
 873         case MONO_TYPE_U8:
 874         case MONO_TYPE_I8:
 875                 cinfo->ret.storage = ArgInIReg;
 876                 cinfo->ret.reg = AMD64_RAX;
 877                 break;
 878         case MONO_TYPE_R4:
 879                 cinfo->ret.storage = ArgInFloatSSEReg;
 880                 cinfo->ret.reg = AMD64_XMM0;
 881                 break;
 882         case MONO_TYPE_R8:
 883                 cinfo->ret.storage = ArgInDoubleSSEReg;
 884                 cinfo->ret.reg = AMD64_XMM0;
 885                 break;
 886         case MONO_TYPE_GENERICINST:
 887                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 888                         cinfo->ret.storage = ArgInIReg;
 889                         cinfo->ret.reg = AMD64_RAX;
 890                         break;
 891                 }
 892                 if (mini_is_gsharedvt_type (ret_type)) {
 893                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 894                         break;
 895                 }
 896                 /* fall through */
 897         case MONO_TYPE_VALUETYPE:
 898         case MONO_TYPE_TYPEDBYREF: {
 899                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 900
 901                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 902                 g_assert (cinfo->ret.storage != ArgInIReg);
 903                 break;
 904         }
 905         case MONO_TYPE_VAR:
 906         case MONO_TYPE_MVAR:
 907                 g_assert (mini_is_gsharedvt_type (ret_type));
 908                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 909                 break;
 910         case MONO_TYPE_VOID:
 911                 break;
 912         default:
 913                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 914         }
 915
 916         pstart = 0;
 917         /*
 918          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 919          * the first argument, allowing 'this' to be always passed in the first arg reg.
 920          * Also do this if the first argument is a reference type, since virtual calls
 921          * are sometimes made using calli without sig->hasthis set, like in the delegate
 922          * invoke wrappers.
 923          */
 924         ArgStorage ret_storage = cinfo->ret.storage;
 925         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 926                 if (sig->hasthis) {
 927                         add_general (&gr, &stack_size, cinfo->args + 0);
 928                 } else {
 929                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 930                         pstart = 1;
 931                 }
 932                 add_general (&gr, &stack_size, &cinfo->ret);
 933                 cinfo->ret.storage = ret_storage;
 934                 cinfo->vret_arg_index = 1;
 935         } else {
 936                 /* this */
 937                 if (sig->hasthis)
 938                         add_general (&gr, &stack_size, cinfo->args + 0);
 939
 940                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 941                         add_general (&gr, &stack_size, &cinfo->ret);
 942                         cinfo->ret.storage = ret_storage;
 943                 }
 944         }
 945
 946         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 947                 gr = PARAM_REGS;
 948                 fr = FLOAT_PARAM_REGS;
 949
 950                 /* Emit the signature cookie just before the implicit arguments */
 951                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 952         }
 953
 954         for (i = pstart; i < sig->param_count; ++i) {
 955                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 956                 MonoType *ptype;
 957
 958 #ifdef TARGET_WIN32
 959                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 960                 if (gr > fr)
 961                         fr = gr;
 962                 else if (fr > gr)
 963                         gr = fr;
 964 #endif
 965
 966                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 967                         /* We allways pass the sig cookie on the stack for simplicity */
 968                         /*
 969                          * Prevent implicit arguments + the sig cookie from being passed
 970                          * in registers.
 971                          */
 972                         gr = PARAM_REGS;
 973                         fr = FLOAT_PARAM_REGS;
 974
 975                         /* Emit the signature cookie just before the implicit arguments */
 976                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 977                 }
 978
 979                 ptype = mini_get_underlying_type (sig->params [i]);
 980                 switch (ptype->type) {
 981                 case MONO_TYPE_I1:
 982                 case MONO_TYPE_U1:
 983                         add_general (&gr, &stack_size, ainfo);
 984                         break;
 985                 case MONO_TYPE_I2:
 986                 case MONO_TYPE_U2:
 987                         add_general (&gr, &stack_size, ainfo);
 988                         break;
 989                 case MONO_TYPE_I4:
 990                 case MONO_TYPE_U4:
 991                         add_general (&gr, &stack_size, ainfo);
 992                         break;
 993                 case MONO_TYPE_I:
 994                 case MONO_TYPE_U:
 995                 case MONO_TYPE_PTR:
 996                 case MONO_TYPE_FNPTR:
 997                 case MONO_TYPE_CLASS:
 998                 case MONO_TYPE_OBJECT:
 999                 case MONO_TYPE_STRING:
1000                 case MONO_TYPE_SZARRAY:
1001                 case MONO_TYPE_ARRAY:
1002                         add_general (&gr, &stack_size, ainfo);
1003                         break;
1004                 case MONO_TYPE_GENERICINST:
1005                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1006                                 add_general (&gr, &stack_size, ainfo);
1007                                 break;
1008                         }
1009                         if (mini_is_gsharedvt_variable_type (ptype)) {
1010                                 /* gsharedvt arguments are passed by ref */
1011                                 add_general (&gr, &stack_size, ainfo);
1012                                 if (ainfo->storage == ArgInIReg)
1013                                         ainfo->storage = ArgGSharedVtInReg;
1014                                 else
1015                                         ainfo->storage = ArgGSharedVtOnStack;
1016                                 break;
1017                         }
1018                         /* fall through */
1019                 case MONO_TYPE_VALUETYPE:
1020                 case MONO_TYPE_TYPEDBYREF:
1021                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1022                         break;
1023                 case MONO_TYPE_U8:
1024
1025                 case MONO_TYPE_I8:
1026                         add_general (&gr, &stack_size, ainfo);
1027                         break;
1028                 case MONO_TYPE_R4:
1029                         add_float (&fr, &stack_size, ainfo, FALSE);
1030                         break;
1031                 case MONO_TYPE_R8:
1032                         add_float (&fr, &stack_size, ainfo, TRUE);
1033                         break;
1034                 case MONO_TYPE_VAR:
1035                 case MONO_TYPE_MVAR:
1036                         /* gsharedvt arguments are passed by ref */
1037                         g_assert (mini_is_gsharedvt_type (ptype));
1038                         add_general (&gr, &stack_size, ainfo);
1039                         if (ainfo->storage == ArgInIReg)
1040                                 ainfo->storage = ArgGSharedVtInReg;
1041                         else
1042                                 ainfo->storage = ArgGSharedVtOnStack;
1043                         break;
1044                 default:
1045                         g_assert_not_reached ();
1046                 }
1047         }
1048
1049         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1050                 gr = PARAM_REGS;
1051                 fr = FLOAT_PARAM_REGS;
1052
1053                 /* Emit the signature cookie just before the implicit arguments */
1054                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1055         }
1056
1057         cinfo->stack_usage = stack_size;
1058         cinfo->reg_usage = gr;
1059         cinfo->freg_usage = fr;
1060         return cinfo;
1061 }
1062
1063 /*
1064  * mono_arch_get_argument_info:
1065  * @csig:  a method signature
1066  * @param_count: the number of parameters to consider
1067  * @arg_info: an array to store the result infos
1068  *
1069  * Gathers information on parameters such as size, alignment and
1070  * padding. arg_info should be large enought to hold param_count + 1 entries.
1071  *
1072  * Returns the size of the argument area on the stack.
1073  */
1074 int
1075 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1076 {
1077         int k;
1078         CallInfo *cinfo = get_call_info (NULL, csig);
1079         guint32 args_size = cinfo->stack_usage;
1080
1081         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1082         if (csig->hasthis) {
1083                 arg_info [0].offset = 0;
1084         }
1085
1086         for (k = 0; k < param_count; k++) {
1087                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1088                 /* FIXME: */
1089                 arg_info [k + 1].size = 0;
1090         }
1091
1092         g_free (cinfo);
1093
1094         return args_size;
1095 }
1096
1097 gboolean
1098 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1099 {
1100         CallInfo *c1, *c2;
1101         gboolean res;
1102         MonoType *callee_ret;
1103
1104         c1 = get_call_info (NULL, caller_sig);
1105         c2 = get_call_info (NULL, callee_sig);
1106         res = c1->stack_usage >= c2->stack_usage;
1107         callee_ret = mini_get_underlying_type (callee_sig->ret);
1108         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1109                 /* An address on the callee's stack is passed as the first argument */
1110                 res = FALSE;
1111
1112         g_free (c1);
1113         g_free (c2);
1114
1115         return res;
1116 }
1117
1118 /*
1119  * Initialize the cpu to execute managed code.
1120  */
1121 void
1122 mono_arch_cpu_init (void)
1123 {
1124 #ifndef _MSC_VER
1125         guint16 fpcw;
1126
1127         /* spec compliance requires running with double precision */
1128         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1129         fpcw &= ~X86_FPCW_PRECC_MASK;
1130         fpcw |= X86_FPCW_PREC_DOUBLE;
1131         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1132         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1133 #else
1134         /* TODO: This is crashing on Win64 right now.
1135         * _control87 (_PC_53, MCW_PC);
1136         */
1137 #endif
1138 }
1139
1140 /*
1141  * Initialize architecture specific code.
1142  */
1143 void
1144 mono_arch_init (void)
1145 {
1146         mono_os_mutex_init_recursive (&mini_arch_mutex);
1147
1148         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1149         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1150         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1151         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1152 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1153         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1154 #endif
1155
1156         if (!mono_aot_only)
1157                 bp_trampoline = mini_get_breakpoint_trampoline ();
1158 }
1159
1160 /*
1161  * Cleanup architecture specific code.
1162  */
1163 void
1164 mono_arch_cleanup (void)
1165 {
1166         mono_os_mutex_destroy (&mini_arch_mutex);
1167 }
1168
1169 /*
1170  * This function returns the optimizations supported on this cpu.
1171  */
1172 guint32
1173 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1174 {
1175         guint32 opts = 0;
1176
1177         *exclude_mask = 0;
1178
1179         if (mono_hwcap_x86_has_cmov) {
1180                 opts |= MONO_OPT_CMOV;
1181
1182                 if (mono_hwcap_x86_has_fcmov)
1183                         opts |= MONO_OPT_FCMOV;
1184                 else
1185                         *exclude_mask |= MONO_OPT_FCMOV;
1186         } else {
1187                 *exclude_mask |= MONO_OPT_CMOV;
1188         }
1189
1190         return opts;
1191 }
1192
1193 /*
1194  * This function test for all SSE functions supported.
1195  *
1196  * Returns a bitmask corresponding to all supported versions.
1197  *
1198  */
1199 guint32
1200 mono_arch_cpu_enumerate_simd_versions (void)
1201 {
1202         guint32 sse_opts = 0;
1203
1204         if (mono_hwcap_x86_has_sse1)
1205                 sse_opts |= SIMD_VERSION_SSE1;
1206
1207         if (mono_hwcap_x86_has_sse2)
1208                 sse_opts |= SIMD_VERSION_SSE2;
1209
1210         if (mono_hwcap_x86_has_sse3)
1211                 sse_opts |= SIMD_VERSION_SSE3;
1212
1213         if (mono_hwcap_x86_has_ssse3)
1214                 sse_opts |= SIMD_VERSION_SSSE3;
1215
1216         if (mono_hwcap_x86_has_sse41)
1217                 sse_opts |= SIMD_VERSION_SSE41;
1218
1219         if (mono_hwcap_x86_has_sse42)
1220                 sse_opts |= SIMD_VERSION_SSE42;
1221
1222         if (mono_hwcap_x86_has_sse4a)
1223                 sse_opts |= SIMD_VERSION_SSE4a;
1224
1225         return sse_opts;
1226 }
1227
1228 #ifndef DISABLE_JIT
1229
1230 GList *
1231 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1232 {
1233         GList *vars = NULL;
1234         int i;
1235
1236         for (i = 0; i < cfg->num_varinfo; i++) {
1237                 MonoInst *ins = cfg->varinfo [i];
1238                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1239
1240                 /* unused vars */
1241                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1242                         continue;
1243
1244                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1245                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1246                         continue;
1247
1248                 if (mono_is_regsize_var (ins->inst_vtype)) {
1249                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1250                         g_assert (i == vmv->idx);
1251                         vars = g_list_prepend (vars, vmv);
1252                 }
1253         }
1254
1255         vars = mono_varlist_sort (cfg, vars, 0);
1256
1257         return vars;
1258 }
1259
1260 /**
1261  * mono_arch_compute_omit_fp:
1262  *
1263  *   Determine whenever the frame pointer can be eliminated.
1264  */
1265 static void
1266 mono_arch_compute_omit_fp (MonoCompile *cfg)
1267 {
1268         MonoMethodSignature *sig;
1269         MonoMethodHeader *header;
1270         int i, locals_size;
1271         CallInfo *cinfo;
1272
1273         if (cfg->arch.omit_fp_computed)
1274                 return;
1275
1276         header = cfg->header;
1277
1278         sig = mono_method_signature (cfg->method);
1279
1280         if (!cfg->arch.cinfo)
1281                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1282         cinfo = (CallInfo *)cfg->arch.cinfo;
1283
1284         /*
1285          * FIXME: Remove some of the restrictions.
1286          */
1287         cfg->arch.omit_fp = TRUE;
1288         cfg->arch.omit_fp_computed = TRUE;
1289
1290         if (cfg->disable_omit_fp)
1291                 cfg->arch.omit_fp = FALSE;
1292
1293         if (!debug_omit_fp ())
1294                 cfg->arch.omit_fp = FALSE;
1295         /*
1296         if (cfg->method->save_lmf)
1297                 cfg->arch.omit_fp = FALSE;
1298         */
1299         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1300                 cfg->arch.omit_fp = FALSE;
1301         if (header->num_clauses)
1302                 cfg->arch.omit_fp = FALSE;
1303         if (cfg->param_area)
1304                 cfg->arch.omit_fp = FALSE;
1305         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1306                 cfg->arch.omit_fp = FALSE;
1307         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1308                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1309                 cfg->arch.omit_fp = FALSE;
1310         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1311                 ArgInfo *ainfo = &cinfo->args [i];
1312
1313                 if (ainfo->storage == ArgOnStack) {
1314                         /*
1315                          * The stack offset can only be determined when the frame
1316                          * size is known.
1317                          */
1318                         cfg->arch.omit_fp = FALSE;
1319                 }
1320         }
1321
1322         locals_size = 0;
1323         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1324                 MonoInst *ins = cfg->varinfo [i];
1325                 int ialign;
1326
1327                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1328         }
1329 }
1330
1331 GList *
1332 mono_arch_get_global_int_regs (MonoCompile *cfg)
1333 {
1334         GList *regs = NULL;
1335
1336         mono_arch_compute_omit_fp (cfg);
1337
1338         if (cfg->arch.omit_fp)
1339                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1340
1341         /* We use the callee saved registers for global allocation */
1342         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1343         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1344         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1345         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1346         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1347 #ifdef TARGET_WIN32
1348         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1349         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1350 #endif
1351
1352         return regs;
1353 }
1354
1355 GList*
1356 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1357 {
1358         GList *regs = NULL;
1359         int i;
1360
1361         /* All XMM registers */
1362         for (i = 0; i < 16; ++i)
1363                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1364
1365         return regs;
1366 }
1367
1368 GList*
1369 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1370 {
1371         static GList *r = NULL;
1372
1373         if (r == NULL) {
1374                 GList *regs = NULL;
1375
1376                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1377                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1378                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1379                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1380                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1381                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1382
1383                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1384                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1385                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1386                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1387                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1388                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1389                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1390                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1391
1392                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1393         }
1394
1395         return r;
1396 }
1397
1398 GList*
1399 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1400 {
1401         int i;
1402         static GList *r = NULL;
1403
1404         if (r == NULL) {
1405                 GList *regs = NULL;
1406
1407                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1408                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1409
1410                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1411         }
1412
1413         return r;
1414 }
1415
1416 /*
1417  * mono_arch_regalloc_cost:
1418  *
1419  *  Return the cost, in number of memory references, of the action of
1420  * allocating the variable VMV into a register during global register
1421  * allocation.
1422  */
1423 guint32
1424 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1425 {
1426         MonoInst *ins = cfg->varinfo [vmv->idx];
1427
1428         if (cfg->method->save_lmf)
1429                 /* The register is already saved */
1430                 /* substract 1 for the invisible store in the prolog */
1431                 return (ins->opcode == OP_ARG) ? 0 : 1;
1432         else
1433                 /* push+pop */
1434                 return (ins->opcode == OP_ARG) ? 1 : 2;
1435 }
1436
1437 /*
1438  * mono_arch_fill_argument_info:
1439  *
1440  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1441  * of the method.
1442  */
1443 void
1444 mono_arch_fill_argument_info (MonoCompile *cfg)
1445 {
1446         MonoType *sig_ret;
1447         MonoMethodSignature *sig;
1448         MonoInst *ins;
1449         int i;
1450         CallInfo *cinfo;
1451
1452         sig = mono_method_signature (cfg->method);
1453
1454         cinfo = (CallInfo *)cfg->arch.cinfo;
1455         sig_ret = mini_get_underlying_type (sig->ret);
1456
1457         /*
1458          * Contrary to mono_arch_allocate_vars (), the information should describe
1459          * where the arguments are at the beginning of the method, not where they can be
1460          * accessed during the execution of the method. The later makes no sense for the
1461          * global register allocator, since a variable can be in more than one location.
1462          */
1463         switch (cinfo->ret.storage) {
1464         case ArgInIReg:
1465         case ArgInFloatSSEReg:
1466         case ArgInDoubleSSEReg:
1467                 cfg->ret->opcode = OP_REGVAR;
1468                 cfg->ret->inst_c0 = cinfo->ret.reg;
1469                 break;
1470         case ArgValuetypeInReg:
1471                 cfg->ret->opcode = OP_REGOFFSET;
1472                 cfg->ret->inst_basereg = -1;
1473                 cfg->ret->inst_offset = -1;
1474                 break;
1475         case ArgNone:
1476                 break;
1477         default:
1478                 g_assert_not_reached ();
1479         }
1480
1481         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1482                 ArgInfo *ainfo = &cinfo->args [i];
1483
1484                 ins = cfg->args [i];
1485
1486                 switch (ainfo->storage) {
1487                 case ArgInIReg:
1488                 case ArgInFloatSSEReg:
1489                 case ArgInDoubleSSEReg:
1490                         ins->opcode = OP_REGVAR;
1491                         ins->inst_c0 = ainfo->reg;
1492                         break;
1493                 case ArgOnStack:
1494                         ins->opcode = OP_REGOFFSET;
1495                         ins->inst_basereg = -1;
1496                         ins->inst_offset = -1;
1497                         break;
1498                 case ArgValuetypeInReg:
1499                         /* Dummy */
1500                         ins->opcode = OP_NOP;
1501                         break;
1502                 default:
1503                         g_assert_not_reached ();
1504                 }
1505         }
1506 }
1507
1508 void
1509 mono_arch_allocate_vars (MonoCompile *cfg)
1510 {
1511         MonoType *sig_ret;
1512         MonoMethodSignature *sig;
1513         MonoInst *ins;
1514         int i, offset;
1515         guint32 locals_stack_size, locals_stack_align;
1516         gint32 *offsets;
1517         CallInfo *cinfo;
1518
1519         sig = mono_method_signature (cfg->method);
1520
1521         cinfo = (CallInfo *)cfg->arch.cinfo;
1522         sig_ret = mini_get_underlying_type (sig->ret);
1523
1524         mono_arch_compute_omit_fp (cfg);
1525
1526         /*
1527          * We use the ABI calling conventions for managed code as well.
1528          * Exception: valuetypes are only sometimes passed or returned in registers.
1529          */
1530
1531         /*
1532          * The stack looks like this:
1533          * <incoming arguments passed on the stack>
1534          * <return value>
1535          * <lmf/caller saved registers>
1536          * <locals>
1537          * <spill area>
1538          * <localloc area>  -> grows dynamically
1539          * <params area>
1540          */
1541
1542         if (cfg->arch.omit_fp) {
1543                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1544                 cfg->frame_reg = AMD64_RSP;
1545                 offset = 0;
1546         } else {
1547                 /* Locals are allocated backwards from %fp */
1548                 cfg->frame_reg = AMD64_RBP;
1549                 offset = 0;
1550         }
1551
1552         cfg->arch.saved_iregs = cfg->used_int_regs;
1553         if (cfg->method->save_lmf)
1554                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1555                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1556
1557         if (cfg->arch.omit_fp)
1558                 cfg->arch.reg_save_area_offset = offset;
1559         /* Reserve space for callee saved registers */
1560         for (i = 0; i < AMD64_NREG; ++i)
1561                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1562                         offset += sizeof(mgreg_t);
1563                 }
1564         if (!cfg->arch.omit_fp)
1565                 cfg->arch.reg_save_area_offset = -offset;
1566
1567         if (sig_ret->type != MONO_TYPE_VOID) {
1568                 switch (cinfo->ret.storage) {
1569                 case ArgInIReg:
1570                 case ArgInFloatSSEReg:
1571                 case ArgInDoubleSSEReg:
1572                         cfg->ret->opcode = OP_REGVAR;
1573                         cfg->ret->inst_c0 = cinfo->ret.reg;
1574                         cfg->ret->dreg = cinfo->ret.reg;
1575                         break;
1576                 case ArgValuetypeAddrInIReg:
1577                 case ArgGsharedvtVariableInReg:
1578                         /* The register is volatile */
1579                         cfg->vret_addr->opcode = OP_REGOFFSET;
1580                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1581                         if (cfg->arch.omit_fp) {
1582                                 cfg->vret_addr->inst_offset = offset;
1583                                 offset += 8;
1584                         } else {
1585                                 offset += 8;
1586                                 cfg->vret_addr->inst_offset = -offset;
1587                         }
1588                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1589                                 printf ("vret_addr =");
1590                                 mono_print_ins (cfg->vret_addr);
1591                         }
1592                         break;
1593                 case ArgValuetypeInReg:
1594                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1595                         cfg->ret->opcode = OP_REGOFFSET;
1596                         cfg->ret->inst_basereg = cfg->frame_reg;
1597                         if (cfg->arch.omit_fp) {
1598                                 cfg->ret->inst_offset = offset;
1599                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1600                         } else {
1601                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1602                                 cfg->ret->inst_offset = - offset;
1603                         }
1604                         break;
1605                 default:
1606                         g_assert_not_reached ();
1607                 }
1608         }
1609
1610         /* Allocate locals */
1611         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1612         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1613                 char *mname = mono_method_full_name (cfg->method, TRUE);
1614                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1615                 g_free (mname);
1616                 return;
1617         }
1618
1619         if (locals_stack_align) {
1620                 offset += (locals_stack_align - 1);
1621                 offset &= ~(locals_stack_align - 1);
1622         }
1623         if (cfg->arch.omit_fp) {
1624                 cfg->locals_min_stack_offset = offset;
1625                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1626         } else {
1627                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1628                 cfg->locals_max_stack_offset = - offset;
1629         }
1630
1631         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1632                 if (offsets [i] != -1) {
1633                         MonoInst *ins = cfg->varinfo [i];
1634                         ins->opcode = OP_REGOFFSET;
1635                         ins->inst_basereg = cfg->frame_reg;
1636                         if (cfg->arch.omit_fp)
1637                                 ins->inst_offset = (offset + offsets [i]);
1638                         else
1639                                 ins->inst_offset = - (offset + offsets [i]);
1640                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1641                 }
1642         }
1643         offset += locals_stack_size;
1644
1645         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1646                 g_assert (!cfg->arch.omit_fp);
1647                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1648                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1649         }
1650
1651         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1652                 ins = cfg->args [i];
1653                 if (ins->opcode != OP_REGVAR) {
1654                         ArgInfo *ainfo = &cinfo->args [i];
1655                         gboolean inreg = TRUE;
1656
1657                         /* FIXME: Allocate volatile arguments to registers */
1658                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1659                                 inreg = FALSE;
1660
1661                         /*
1662                          * Under AMD64, all registers used to pass arguments to functions
1663                          * are volatile across calls.
1664                          * FIXME: Optimize this.
1665                          */
1666                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1667                                 inreg = FALSE;
1668
1669                         ins->opcode = OP_REGOFFSET;
1670
1671                         switch (ainfo->storage) {
1672                         case ArgInIReg:
1673                         case ArgInFloatSSEReg:
1674                         case ArgInDoubleSSEReg:
1675                         case ArgGSharedVtInReg:
1676                                 if (inreg) {
1677                                         ins->opcode = OP_REGVAR;
1678                                         ins->dreg = ainfo->reg;
1679                                 }
1680                                 break;
1681                         case ArgOnStack:
1682                         case ArgGSharedVtOnStack:
1683                                 g_assert (!cfg->arch.omit_fp);
1684                                 ins->opcode = OP_REGOFFSET;
1685                                 ins->inst_basereg = cfg->frame_reg;
1686                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1687                                 break;
1688                         case ArgValuetypeInReg:
1689                                 break;
1690                         case ArgValuetypeAddrInIReg: {
1691                                 MonoInst *indir;
1692                                 g_assert (!cfg->arch.omit_fp);
1693
1694                                 MONO_INST_NEW (cfg, indir, 0);
1695                                 indir->opcode = OP_REGOFFSET;
1696                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1697                                         indir->inst_basereg = cfg->frame_reg;
1698                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1699                                         offset += (sizeof (gpointer));
1700                                         indir->inst_offset = - offset;
1701                                 }
1702                                 else {
1703                                         indir->inst_basereg = cfg->frame_reg;
1704                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1705                                 }
1706
1707                                 ins->opcode = OP_VTARG_ADDR;
1708                                 ins->inst_left = indir;
1709
1710                                 break;
1711                         }
1712                         default:
1713                                 NOT_IMPLEMENTED;
1714                         }
1715
1716                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
1717                                 ins->opcode = OP_REGOFFSET;
1718                                 ins->inst_basereg = cfg->frame_reg;
1719                                 /* These arguments are saved to the stack in the prolog */
1720                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1721                                 if (cfg->arch.omit_fp) {
1722                                         ins->inst_offset = offset;
1723                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1724                                         // Arguments are yet supported by the stack map creation code
1725                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1726                                 } else {
1727                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1728                                         ins->inst_offset = - offset;
1729                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1730                                 }
1731                         }
1732                 }
1733         }
1734
1735         cfg->stack_offset = offset;
1736 }
1737
1738 void
1739 mono_arch_create_vars (MonoCompile *cfg)
1740 {
1741         MonoMethodSignature *sig;
1742         CallInfo *cinfo;
1743         MonoType *sig_ret;
1744
1745         sig = mono_method_signature (cfg->method);
1746
1747         if (!cfg->arch.cinfo)
1748                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1749         cinfo = (CallInfo *)cfg->arch.cinfo;
1750
1751         if (cinfo->ret.storage == ArgValuetypeInReg)
1752                 cfg->ret_var_is_local = TRUE;
1753
1754         sig_ret = mini_get_underlying_type (sig->ret);
1755         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1756                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1757                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1758                         printf ("vret_addr = ");
1759                         mono_print_ins (cfg->vret_addr);
1760                 }
1761         }
1762
1763         if (cfg->gen_sdb_seq_points) {
1764                 MonoInst *ins;
1765
1766                 if (cfg->compile_aot) {
1767                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1768                         ins->flags |= MONO_INST_VOLATILE;
1769                         cfg->arch.seq_point_info_var = ins;
1770                 }
1771                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1772                 ins->flags |= MONO_INST_VOLATILE;
1773                 cfg->arch.ss_tramp_var = ins;
1774
1775                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1776                 ins->flags |= MONO_INST_VOLATILE;
1777                 cfg->arch.bp_tramp_var = ins;
1778         }
1779
1780         if (cfg->method->save_lmf)
1781                 cfg->create_lmf_var = TRUE;
1782
1783         if (cfg->method->save_lmf) {
1784                 cfg->lmf_ir = TRUE;
1785 #if !defined(TARGET_WIN32)
1786                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1787                         cfg->lmf_ir_mono_lmf = TRUE;
1788 #endif
1789         }
1790 }
1791
1792 static void
1793 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1794 {
1795         MonoInst *ins;
1796
1797         switch (storage) {
1798         case ArgInIReg:
1799                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1800                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1801                 ins->sreg1 = tree->dreg;
1802                 MONO_ADD_INS (cfg->cbb, ins);
1803                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1804                 break;
1805         case ArgInFloatSSEReg:
1806                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1807                 ins->dreg = mono_alloc_freg (cfg);
1808                 ins->sreg1 = tree->dreg;
1809                 MONO_ADD_INS (cfg->cbb, ins);
1810
1811                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1812                 break;
1813         case ArgInDoubleSSEReg:
1814                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1815                 ins->dreg = mono_alloc_freg (cfg);
1816                 ins->sreg1 = tree->dreg;
1817                 MONO_ADD_INS (cfg->cbb, ins);
1818
1819                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1820
1821                 break;
1822         default:
1823                 g_assert_not_reached ();
1824         }
1825 }
1826
1827 static int
1828 arg_storage_to_load_membase (ArgStorage storage)
1829 {
1830         switch (storage) {
1831         case ArgInIReg:
1832 #if defined(__mono_ilp32__)
1833                 return OP_LOADI8_MEMBASE;
1834 #else
1835                 return OP_LOAD_MEMBASE;
1836 #endif
1837         case ArgInDoubleSSEReg:
1838                 return OP_LOADR8_MEMBASE;
1839         case ArgInFloatSSEReg:
1840                 return OP_LOADR4_MEMBASE;
1841         default:
1842                 g_assert_not_reached ();
1843         }
1844
1845         return -1;
1846 }
1847
1848 static void
1849 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1850 {
1851         MonoMethodSignature *tmp_sig;
1852         int sig_reg;
1853
1854         if (call->tail_call)
1855                 NOT_IMPLEMENTED;
1856
1857         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1858
1859         /*
1860          * mono_ArgIterator_Setup assumes the signature cookie is
1861          * passed first and all the arguments which were before it are
1862          * passed on the stack after the signature. So compensate by
1863          * passing a different signature.
1864          */
1865         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1866         tmp_sig->param_count -= call->signature->sentinelpos;
1867         tmp_sig->sentinelpos = 0;
1868         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1869
1870         sig_reg = mono_alloc_ireg (cfg);
1871         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1872
1873         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1874 }
1875
1876 #ifdef ENABLE_LLVM
1877 static inline LLVMArgStorage
1878 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1879 {
1880         switch (storage) {
1881         case ArgInIReg:
1882                 return LLVMArgInIReg;
1883         case ArgNone:
1884                 return LLVMArgNone;
1885         case ArgGSharedVtInReg:
1886         case ArgGSharedVtOnStack:
1887                 return LLVMArgGSharedVt;
1888         default:
1889                 g_assert_not_reached ();
1890                 return LLVMArgNone;
1891         }
1892 }
1893
1894 LLVMCallInfo*
1895 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1896 {
1897         int i, n;
1898         CallInfo *cinfo;
1899         ArgInfo *ainfo;
1900         int j;
1901         LLVMCallInfo *linfo;
1902         MonoType *t, *sig_ret;
1903
1904         n = sig->param_count + sig->hasthis;
1905         sig_ret = mini_get_underlying_type (sig->ret);
1906
1907         cinfo = get_call_info (cfg->mempool, sig);
1908
1909         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1910
1911         /*
1912          * LLVM always uses the native ABI while we use our own ABI, the
1913          * only difference is the handling of vtypes:
1914          * - we only pass/receive them in registers in some cases, and only
1915          *   in 1 or 2 integer registers.
1916          */
1917         switch (cinfo->ret.storage) {
1918         case ArgNone:
1919                 linfo->ret.storage = LLVMArgNone;
1920                 break;
1921         case ArgInIReg:
1922         case ArgInFloatSSEReg:
1923         case ArgInDoubleSSEReg:
1924                 linfo->ret.storage = LLVMArgNormal;
1925                 break;
1926         case ArgValuetypeInReg: {
1927                 ainfo = &cinfo->ret;
1928
1929                 if (sig->pinvoke &&
1930                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1931                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1932                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1933                         cfg->disable_llvm = TRUE;
1934                         return linfo;
1935                 }
1936
1937                 linfo->ret.storage = LLVMArgVtypeInReg;
1938                 for (j = 0; j < 2; ++j)
1939                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1940                 break;
1941         }
1942         case ArgValuetypeAddrInIReg:
1943         case ArgGsharedvtVariableInReg:
1944                 /* Vtype returned using a hidden argument */
1945                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1946                 linfo->vret_arg_index = cinfo->vret_arg_index;
1947                 break;
1948         default:
1949                 g_assert_not_reached ();
1950                 break;
1951         }
1952
1953         for (i = 0; i < n; ++i) {
1954                 ainfo = cinfo->args + i;
1955
1956                 if (i >= sig->hasthis)
1957                         t = sig->params [i - sig->hasthis];
1958                 else
1959                         t = &mono_defaults.int_class->byval_arg;
1960                 t = mini_type_get_underlying_type (t);
1961
1962                 linfo->args [i].storage = LLVMArgNone;
1963
1964                 switch (ainfo->storage) {
1965                 case ArgInIReg:
1966                         linfo->args [i].storage = LLVMArgNormal;
1967                         break;
1968                 case ArgInDoubleSSEReg:
1969                 case ArgInFloatSSEReg:
1970                         linfo->args [i].storage = LLVMArgNormal;
1971                         break;
1972                 case ArgOnStack:
1973                         if (MONO_TYPE_ISSTRUCT (t))
1974                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1975                         else
1976                                 linfo->args [i].storage = LLVMArgNormal;
1977                         break;
1978                 case ArgValuetypeInReg:
1979                         if (sig->pinvoke &&
1980                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1981                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1982                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1983                                 cfg->disable_llvm = TRUE;
1984                                 return linfo;
1985                         }
1986
1987                         linfo->args [i].storage = LLVMArgVtypeInReg;
1988                         for (j = 0; j < 2; ++j)
1989                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1990                         break;
1991                 case ArgGSharedVtInReg:
1992                 case ArgGSharedVtOnStack:
1993                         linfo->args [i].storage = LLVMArgGSharedVt;
1994                         break;
1995                 default:
1996                         cfg->exception_message = g_strdup ("ainfo->storage");
1997                         cfg->disable_llvm = TRUE;
1998                         break;
1999                 }
2000         }
2001
2002         return linfo;
2003 }
2004 #endif
2005
2006 void
2007 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2008 {
2009         MonoInst *arg, *in;
2010         MonoMethodSignature *sig;
2011         MonoType *sig_ret;
2012         int i, n;
2013         CallInfo *cinfo;
2014         ArgInfo *ainfo;
2015
2016         sig = call->signature;
2017         n = sig->param_count + sig->hasthis;
2018
2019         cinfo = get_call_info (cfg->mempool, sig);
2020
2021         sig_ret = sig->ret;
2022
2023         if (COMPILE_LLVM (cfg)) {
2024                 /* We shouldn't be called in the llvm case */
2025                 cfg->disable_llvm = TRUE;
2026                 return;
2027         }
2028
2029         /*
2030          * Emit all arguments which are passed on the stack to prevent register
2031          * allocation problems.
2032          */
2033         for (i = 0; i < n; ++i) {
2034                 MonoType *t;
2035                 ainfo = cinfo->args + i;
2036
2037                 in = call->args [i];
2038
2039                 if (sig->hasthis && i == 0)
2040                         t = &mono_defaults.object_class->byval_arg;
2041                 else
2042                         t = sig->params [i - sig->hasthis];
2043
2044                 t = mini_get_underlying_type (t);
2045                 //XXX what about ArgGSharedVtOnStack here?
2046                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2047                         if (!t->byref) {
2048                                 if (t->type == MONO_TYPE_R4)
2049                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2050                                 else if (t->type == MONO_TYPE_R8)
2051                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2052                                 else
2053                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2054                         } else {
2055                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2056                         }
2057                         if (cfg->compute_gc_maps) {
2058                                 MonoInst *def;
2059
2060                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2061                         }
2062                 }
2063         }
2064
2065         /*
2066          * Emit all parameters passed in registers in non-reverse order for better readability
2067          * and to help the optimization in emit_prolog ().
2068          */
2069         for (i = 0; i < n; ++i) {
2070                 ainfo = cinfo->args + i;
2071
2072                 in = call->args [i];
2073
2074                 if (ainfo->storage == ArgInIReg)
2075                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2076         }
2077
2078         for (i = n - 1; i >= 0; --i) {
2079                 MonoType *t;
2080
2081                 ainfo = cinfo->args + i;
2082
2083                 in = call->args [i];
2084
2085                 if (sig->hasthis && i == 0)
2086                         t = &mono_defaults.object_class->byval_arg;
2087                 else
2088                         t = sig->params [i - sig->hasthis];
2089                 t = mini_get_underlying_type (t);
2090
2091                 switch (ainfo->storage) {
2092                 case ArgInIReg:
2093                         /* Already done */
2094                         break;
2095                 case ArgInFloatSSEReg:
2096                 case ArgInDoubleSSEReg:
2097                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2098                         break;
2099                 case ArgOnStack:
2100                 case ArgValuetypeInReg:
2101                 case ArgValuetypeAddrInIReg:
2102                 case ArgGSharedVtInReg:
2103                 case ArgGSharedVtOnStack: {
2104                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2105                                 /* Already emitted above */
2106                                 break;
2107                         //FIXME what about ArgGSharedVtOnStack ?
2108                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2109                                 MonoInst *call_inst = (MonoInst*)call;
2110                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2111                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2112                                 break;
2113                         }
2114
2115                         guint32 align;
2116                         guint32 size;
2117
2118                         if (sig->pinvoke)
2119                                 size = mono_type_native_stack_size (t, &align);
2120                         else {
2121                                 /*
2122                                  * Other backends use mono_type_stack_size (), but that
2123                                  * aligns the size to 8, which is larger than the size of
2124                                  * the source, leading to reads of invalid memory if the
2125                                  * source is at the end of address space.
2126                                  */
2127                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2128                         }
2129
2130                         if (size >= 10000) {
2131                                 /* Avoid asserts in emit_memcpy () */
2132                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2133                                 /* Continue normally */
2134                         }
2135
2136                         if (size > 0 || ainfo->pass_empty_struct) {
2137                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2138                                 arg->sreg1 = in->dreg;
2139                                 arg->klass = mono_class_from_mono_type (t);
2140                                 arg->backend.size = size;
2141                                 arg->inst_p0 = call;
2142                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2143                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2144
2145                                 MONO_ADD_INS (cfg->cbb, arg);
2146                         }
2147                         break;
2148                 }
2149                 default:
2150                         g_assert_not_reached ();
2151                 }
2152
2153                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2154                         /* Emit the signature cookie just before the implicit arguments */
2155                         emit_sig_cookie (cfg, call, cinfo);
2156         }
2157
2158         /* Handle the case where there are no implicit arguments */
2159         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2160                 emit_sig_cookie (cfg, call, cinfo);
2161
2162         switch (cinfo->ret.storage) {
2163         case ArgValuetypeInReg:
2164                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2165                         /*
2166                          * Tell the JIT to use a more efficient calling convention: call using
2167                          * OP_CALL, compute the result location after the call, and save the
2168                          * result there.
2169                          */
2170                         call->vret_in_reg = TRUE;
2171                         /*
2172                          * Nullify the instruction computing the vret addr to enable
2173                          * future optimizations.
2174                          */
2175                         if (call->vret_var)
2176                                 NULLIFY_INS (call->vret_var);
2177                 } else {
2178                         if (call->tail_call)
2179                                 NOT_IMPLEMENTED;
2180                         /*
2181                          * The valuetype is in RAX:RDX after the call, need to be copied to
2182                          * the stack. Push the address here, so the call instruction can
2183                          * access it.
2184                          */
2185                         if (!cfg->arch.vret_addr_loc) {
2186                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2187                                 /* Prevent it from being register allocated or optimized away */
2188                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2189                         }
2190
2191                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2192                 }
2193                 break;
2194         case ArgValuetypeAddrInIReg:
2195         case ArgGsharedvtVariableInReg: {
2196                 MonoInst *vtarg;
2197                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2198                 vtarg->sreg1 = call->vret_var->dreg;
2199                 vtarg->dreg = mono_alloc_preg (cfg);
2200                 MONO_ADD_INS (cfg->cbb, vtarg);
2201
2202                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2203                 break;
2204         }
2205         default:
2206                 break;
2207         }
2208
2209         if (cfg->method->save_lmf) {
2210                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2211                 MONO_ADD_INS (cfg->cbb, arg);
2212         }
2213
2214         call->stack_usage = cinfo->stack_usage;
2215 }
2216
2217 void
2218 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2219 {
2220         MonoInst *arg;
2221         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2222         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2223         int size = ins->backend.size;
2224
2225         switch (ainfo->storage) {
2226         case ArgValuetypeInReg: {
2227                 MonoInst *load;
2228                 int part;
2229
2230                 for (part = 0; part < 2; ++part) {
2231                         if (ainfo->pair_storage [part] == ArgNone)
2232                                 continue;
2233
2234                         if (ainfo->pass_empty_struct) {
2235                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2236                                 NEW_ICONST (cfg, load, 0);
2237                         }
2238                         else {
2239                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2240                                 load->inst_basereg = src->dreg;
2241                                 load->inst_offset = part * sizeof(mgreg_t);
2242
2243                                 switch (ainfo->pair_storage [part]) {
2244                                 case ArgInIReg:
2245                                         load->dreg = mono_alloc_ireg (cfg);
2246                                         break;
2247                                 case ArgInDoubleSSEReg:
2248                                 case ArgInFloatSSEReg:
2249                                         load->dreg = mono_alloc_freg (cfg);
2250                                         break;
2251                                 default:
2252                                         g_assert_not_reached ();
2253                                 }
2254                         }
2255
2256                         MONO_ADD_INS (cfg->cbb, load);
2257
2258                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2259                 }
2260                 break;
2261         }
2262         case ArgValuetypeAddrInIReg: {
2263                 MonoInst *vtaddr, *load;
2264                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2265
2266                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2267                 cfg->has_indirection = TRUE;
2268                 load->inst_p0 = vtaddr;
2269                 vtaddr->flags |= MONO_INST_INDIRECT;
2270                 load->type = STACK_MP;
2271                 load->klass = vtaddr->klass;
2272                 load->dreg = mono_alloc_ireg (cfg);
2273                 MONO_ADD_INS (cfg->cbb, load);
2274                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2275
2276                 if (ainfo->pair_storage [0] == ArgInIReg) {
2277                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2278                         arg->dreg = mono_alloc_ireg (cfg);
2279                         arg->sreg1 = load->dreg;
2280                         arg->inst_imm = 0;
2281                         MONO_ADD_INS (cfg->cbb, arg);
2282                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2283                 } else {
2284                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2285                 }
2286                 break;
2287         }
2288         case ArgGSharedVtInReg:
2289                 /* Pass by addr */
2290                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2291                 break;
2292         case ArgGSharedVtOnStack:
2293                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2294                 break;
2295         default:
2296                 if (size == 8) {
2297                         int dreg = mono_alloc_ireg (cfg);
2298
2299                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2300                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2301                 } else if (size <= 40) {
2302                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2303                 } else {
2304                         // FIXME: Code growth
2305                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2306                 }
2307
2308                 if (cfg->compute_gc_maps) {
2309                         MonoInst *def;
2310                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2311                 }
2312         }
2313 }
2314
2315 void
2316 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2317 {
2318         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2319
2320         if (ret->type == MONO_TYPE_R4) {
2321                 if (COMPILE_LLVM (cfg))
2322                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2323                 else
2324                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2325                 return;
2326         } else if (ret->type == MONO_TYPE_R8) {
2327                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2328                 return;
2329         }
2330
2331         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2332 }
2333
2334 #endif /* DISABLE_JIT */
2335
2336 #define EMIT_COND_BRANCH(ins,cond,sign) \
2337         if (ins->inst_true_bb->native_offset) { \
2338                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2339         } else { \
2340                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2341                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2342             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2343                         x86_branch8 (code, cond, 0, sign); \
2344                 else \
2345                         x86_branch32 (code, cond, 0, sign); \
2346 }
2347
2348 typedef struct {
2349         MonoMethodSignature *sig;
2350         CallInfo *cinfo;
2351 } ArchDynCallInfo;
2352
2353 static gboolean
2354 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2355 {
2356         int i;
2357
2358         switch (cinfo->ret.storage) {
2359         case ArgNone:
2360         case ArgInIReg:
2361         case ArgInFloatSSEReg:
2362         case ArgInDoubleSSEReg:
2363         case ArgValuetypeAddrInIReg:
2364                 break;
2365         case ArgValuetypeInReg: {
2366                 ArgInfo *ainfo = &cinfo->ret;
2367
2368                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2369                         return FALSE;
2370                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2371                         return FALSE;
2372                 break;
2373         }
2374         default:
2375                 return FALSE;
2376         }
2377
2378         for (i = 0; i < cinfo->nargs; ++i) {
2379                 ArgInfo *ainfo = &cinfo->args [i];
2380                 switch (ainfo->storage) {
2381                 case ArgInIReg:
2382                 case ArgInFloatSSEReg:
2383                 case ArgInDoubleSSEReg:
2384                         break;
2385                 case ArgValuetypeInReg:
2386                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2387                                 return FALSE;
2388                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2389                                 return FALSE;
2390                         break;
2391                 case ArgOnStack:
2392                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2393                                 return FALSE;
2394                         break;
2395                 default:
2396                         return FALSE;
2397                 }
2398         }
2399
2400         return TRUE;
2401 }
2402
2403 /*
2404  * mono_arch_dyn_call_prepare:
2405  *
2406  *   Return a pointer to an arch-specific structure which contains information
2407  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2408  * supported for SIG.
2409  * This function is equivalent to ffi_prep_cif in libffi.
2410  */
2411 MonoDynCallInfo*
2412 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2413 {
2414         ArchDynCallInfo *info;
2415         CallInfo *cinfo;
2416
2417         cinfo = get_call_info (NULL, sig);
2418
2419         if (!dyn_call_supported (sig, cinfo)) {
2420                 g_free (cinfo);
2421                 return NULL;
2422         }
2423
2424         info = g_new0 (ArchDynCallInfo, 1);
2425         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2426         info->sig = sig;
2427         info->cinfo = cinfo;
2428
2429         return (MonoDynCallInfo*)info;
2430 }
2431
2432 /*
2433  * mono_arch_dyn_call_free:
2434  *
2435  *   Free a MonoDynCallInfo structure.
2436  */
2437 void
2438 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2439 {
2440         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2441
2442         g_free (ainfo->cinfo);
2443         g_free (ainfo);
2444 }
2445
2446 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2447 #define GREG_TO_PTR(greg) (gpointer)(greg)
2448
2449 /*
2450  * mono_arch_get_start_dyn_call:
2451  *
2452  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2453  * store the result into BUF.
2454  * ARGS should be an array of pointers pointing to the arguments.
2455  * RET should point to a memory buffer large enought to hold the result of the
2456  * call.
2457  * This function should be as fast as possible, any work which does not depend
2458  * on the actual values of the arguments should be done in
2459  * mono_arch_dyn_call_prepare ().
2460  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2461  * libffi.
2462  */
2463 void
2464 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2465 {
2466         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2467         DynCallArgs *p = (DynCallArgs*)buf;
2468         int arg_index, greg, freg, i, pindex;
2469         MonoMethodSignature *sig = dinfo->sig;
2470         int buffer_offset = 0;
2471         static int param_reg_to_index [16];
2472         static gboolean param_reg_to_index_inited;
2473
2474         if (!param_reg_to_index_inited) {
2475                 for (i = 0; i < PARAM_REGS; ++i)
2476                         param_reg_to_index [param_regs [i]] = i;
2477                 mono_memory_barrier ();
2478                 param_reg_to_index_inited = 1;
2479         }
2480
2481         g_assert (buf_len >= sizeof (DynCallArgs));
2482
2483         p->res = 0;
2484         p->ret = ret;
2485
2486         arg_index = 0;
2487         greg = 0;
2488         freg = 0;
2489         pindex = 0;
2490
2491         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2492                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2493                 if (!sig->hasthis)
2494                         pindex = 1;
2495         }
2496
2497         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2498                 p->regs [greg ++] = PTR_TO_GREG(ret);
2499
2500         for (; pindex < sig->param_count; pindex++) {
2501                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2502                 gpointer *arg = args [arg_index ++];
2503                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2504                 int slot;
2505
2506                 if (ainfo->storage == ArgOnStack) {
2507                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2508                 } else {
2509                         slot = param_reg_to_index [ainfo->reg];
2510                 }
2511
2512                 if (t->byref) {
2513                         p->regs [slot] = PTR_TO_GREG(*(arg));
2514                         greg ++;
2515                         continue;
2516                 }
2517
2518                 switch (t->type) {
2519                 case MONO_TYPE_STRING:
2520                 case MONO_TYPE_CLASS:
2521                 case MONO_TYPE_ARRAY:
2522                 case MONO_TYPE_SZARRAY:
2523                 case MONO_TYPE_OBJECT:
2524                 case MONO_TYPE_PTR:
2525                 case MONO_TYPE_I:
2526                 case MONO_TYPE_U:
2527 #if !defined(__mono_ilp32__)
2528                 case MONO_TYPE_I8:
2529                 case MONO_TYPE_U8:
2530 #endif
2531                         p->regs [slot] = PTR_TO_GREG(*(arg));
2532                         break;
2533 #if defined(__mono_ilp32__)
2534                 case MONO_TYPE_I8:
2535                 case MONO_TYPE_U8:
2536                         p->regs [slot] = *(guint64*)(arg);
2537                         break;
2538 #endif
2539                 case MONO_TYPE_U1:
2540                         p->regs [slot] = *(guint8*)(arg);
2541                         break;
2542                 case MONO_TYPE_I1:
2543                         p->regs [slot] = *(gint8*)(arg);
2544                         break;
2545                 case MONO_TYPE_I2:
2546                         p->regs [slot] = *(gint16*)(arg);
2547                         break;
2548                 case MONO_TYPE_U2:
2549                         p->regs [slot] = *(guint16*)(arg);
2550                         break;
2551                 case MONO_TYPE_I4:
2552                         p->regs [slot] = *(gint32*)(arg);
2553                         break;
2554                 case MONO_TYPE_U4:
2555                         p->regs [slot] = *(guint32*)(arg);
2556                         break;
2557                 case MONO_TYPE_R4: {
2558                         double d;
2559
2560                         *(float*)&d = *(float*)(arg);
2561                         p->has_fp = 1;
2562                         p->fregs [freg ++] = d;
2563                         break;
2564                 }
2565                 case MONO_TYPE_R8:
2566                         p->has_fp = 1;
2567                         p->fregs [freg ++] = *(double*)(arg);
2568                         break;
2569                 case MONO_TYPE_GENERICINST:
2570                     if (MONO_TYPE_IS_REFERENCE (t)) {
2571                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2572                                 break;
2573                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2574                                         MonoClass *klass = mono_class_from_mono_type (t);
2575                                         guint8 *nullable_buf;
2576                                         int size;
2577
2578                                         size = mono_class_value_size (klass, NULL);
2579                                         nullable_buf = p->buffer + buffer_offset;
2580                                         buffer_offset += size;
2581                                         g_assert (buffer_offset <= 256);
2582
2583                                         /* The argument pointed to by arg is either a boxed vtype or null */
2584                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2585
2586                                         arg = (gpointer*)nullable_buf;
2587                                         /* Fall though */
2588
2589                         } else {
2590                                 /* Fall through */
2591                         }
2592                 case MONO_TYPE_VALUETYPE: {
2593                         switch (ainfo->storage) {
2594                         case ArgValuetypeInReg:
2595                                 if (ainfo->pair_storage [0] != ArgNone) {
2596                                         slot = param_reg_to_index [ainfo->pair_regs [0]];
2597                                         g_assert (ainfo->pair_storage [0] == ArgInIReg);
2598                                         p->regs [slot] = ((mgreg_t*)(arg))[0];
2599                                 }
2600                                 if (ainfo->pair_storage [1] != ArgNone) {
2601                                         slot = param_reg_to_index [ainfo->pair_regs [1]];
2602                                         g_assert (ainfo->pair_storage [1] == ArgInIReg);
2603                                         p->regs [slot] = ((mgreg_t*)(arg))[1];
2604                                 }
2605                                 break;
2606                         case ArgOnStack:
2607                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2608                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2609                                 break;
2610                         default:
2611                                 g_assert_not_reached ();
2612                                 break;
2613                         }
2614                         break;
2615                 }
2616                 default:
2617                         g_assert_not_reached ();
2618                 }
2619         }
2620 }
2621
2622 /*
2623  * mono_arch_finish_dyn_call:
2624  *
2625  *   Store the result of a dyn call into the return value buffer passed to
2626  * start_dyn_call ().
2627  * This function should be as fast as possible, any work which does not depend
2628  * on the actual values of the arguments should be done in
2629  * mono_arch_dyn_call_prepare ().
2630  */
2631 void
2632 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2633 {
2634         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2635         MonoMethodSignature *sig = dinfo->sig;
2636         DynCallArgs *dargs = (DynCallArgs*)buf;
2637         guint8 *ret = dargs->ret;
2638         mgreg_t res = dargs->res;
2639         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2640
2641         switch (sig_ret->type) {
2642         case MONO_TYPE_VOID:
2643                 *(gpointer*)ret = NULL;
2644                 break;
2645         case MONO_TYPE_STRING:
2646         case MONO_TYPE_CLASS:
2647         case MONO_TYPE_ARRAY:
2648         case MONO_TYPE_SZARRAY:
2649         case MONO_TYPE_OBJECT:
2650         case MONO_TYPE_I:
2651         case MONO_TYPE_U:
2652         case MONO_TYPE_PTR:
2653                 *(gpointer*)ret = GREG_TO_PTR(res);
2654                 break;
2655         case MONO_TYPE_I1:
2656                 *(gint8*)ret = res;
2657                 break;
2658         case MONO_TYPE_U1:
2659                 *(guint8*)ret = res;
2660                 break;
2661         case MONO_TYPE_I2:
2662                 *(gint16*)ret = res;
2663                 break;
2664         case MONO_TYPE_U2:
2665                 *(guint16*)ret = res;
2666                 break;
2667         case MONO_TYPE_I4:
2668                 *(gint32*)ret = res;
2669                 break;
2670         case MONO_TYPE_U4:
2671                 *(guint32*)ret = res;
2672                 break;
2673         case MONO_TYPE_I8:
2674                 *(gint64*)ret = res;
2675                 break;
2676         case MONO_TYPE_U8:
2677                 *(guint64*)ret = res;
2678                 break;
2679         case MONO_TYPE_R4:
2680                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2681                 break;
2682         case MONO_TYPE_R8:
2683                 *(double*)ret = dargs->fregs [0];
2684                 break;
2685         case MONO_TYPE_GENERICINST:
2686                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2687                         *(gpointer*)ret = GREG_TO_PTR(res);
2688                         break;
2689                 } else {
2690                         /* Fall through */
2691                 }
2692         case MONO_TYPE_VALUETYPE:
2693                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2694                         /* Nothing to do */
2695                 } else {
2696                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2697
2698                         g_assert (ainfo->storage == ArgValuetypeInReg);
2699
2700                         if (ainfo->pair_storage [0] != ArgNone) {
2701                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2702                                 ((mgreg_t*)ret)[0] = res;
2703                         }
2704
2705                         g_assert (ainfo->pair_storage [1] == ArgNone);
2706                 }
2707                 break;
2708         default:
2709                 g_assert_not_reached ();
2710         }
2711 }
2712
2713 /* emit an exception if condition is fail */
2714 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2715         do {                                                        \
2716                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2717                 if (tins == NULL) {                                                                             \
2718                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2719                                         MONO_PATCH_INFO_EXC, exc_name);  \
2720                         x86_branch32 (code, cond, 0, signed);               \
2721                 } else {        \
2722                         EMIT_COND_BRANCH (tins, cond, signed);  \
2723                 }                       \
2724         } while (0);
2725
2726 #define EMIT_FPCOMPARE(code) do { \
2727         amd64_fcompp (code); \
2728         amd64_fnstsw (code); \
2729 } while (0);
2730
2731 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2732     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2733         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2734         amd64_ ##op (code); \
2735         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2736         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2737 } while (0);
2738
2739 static guint8*
2740 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2741 {
2742         gboolean no_patch = FALSE;
2743
2744         /*
2745          * FIXME: Add support for thunks
2746          */
2747         {
2748                 gboolean near_call = FALSE;
2749
2750                 /*
2751                  * Indirect calls are expensive so try to make a near call if possible.
2752                  * The caller memory is allocated by the code manager so it is
2753                  * guaranteed to be at a 32 bit offset.
2754                  */
2755
2756                 if (patch_type != MONO_PATCH_INFO_ABS) {
2757                         /* The target is in memory allocated using the code manager */
2758                         near_call = TRUE;
2759
2760                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2761                                 if (((MonoMethod*)data)->klass->image->aot_module)
2762                                         /* The callee might be an AOT method */
2763                                         near_call = FALSE;
2764                                 if (((MonoMethod*)data)->dynamic)
2765                                         /* The target is in malloc-ed memory */
2766                                         near_call = FALSE;
2767                         }
2768
2769                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2770                                 /*
2771                                  * The call might go directly to a native function without
2772                                  * the wrapper.
2773                                  */
2774                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2775                                 if (mi) {
2776                                         gconstpointer target = mono_icall_get_wrapper (mi);
2777                                         if ((((guint64)target) >> 32) != 0)
2778                                                 near_call = FALSE;
2779                                 }
2780                         }
2781                 }
2782                 else {
2783                         MonoJumpInfo *jinfo = NULL;
2784
2785                         if (cfg->abs_patches)
2786                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2787                         if (jinfo) {
2788                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2789                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2790                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2791                                                 near_call = TRUE;
2792                                         no_patch = TRUE;
2793                                 } else {
2794                                         /*
2795                                          * This is not really an optimization, but required because the
2796                                          * generic class init trampolines use R11 to pass the vtable.
2797                                          */
2798                                         near_call = TRUE;
2799                                 }
2800                         } else {
2801                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2802                                 if (info) {
2803                                         if (info->func == info->wrapper) {
2804                                                 /* No wrapper */
2805                                                 if ((((guint64)info->func) >> 32) == 0)
2806                                                         near_call = TRUE;
2807                                         }
2808                                         else {
2809                                                 /* See the comment in mono_codegen () */
2810                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2811                                                         near_call = TRUE;
2812                                         }
2813                                 }
2814                                 else if ((((guint64)data) >> 32) == 0) {
2815                                         near_call = TRUE;
2816                                         no_patch = TRUE;
2817                                 }
2818                         }
2819                 }
2820
2821                 if (cfg->method->dynamic)
2822                         /* These methods are allocated using malloc */
2823                         near_call = FALSE;
2824
2825 #ifdef MONO_ARCH_NOMAP32BIT
2826                 near_call = FALSE;
2827 #endif
2828                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2829                 if (optimize_for_xen)
2830                         near_call = FALSE;
2831
2832                 if (cfg->compile_aot) {
2833                         near_call = TRUE;
2834                         no_patch = TRUE;
2835                 }
2836
2837                 if (near_call) {
2838                         /*
2839                          * Align the call displacement to an address divisible by 4 so it does
2840                          * not span cache lines. This is required for code patching to work on SMP
2841                          * systems.
2842                          */
2843                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2844                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2845                                 amd64_padding (code, pad_size);
2846                         }
2847                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2848                         amd64_call_code (code, 0);
2849                 }
2850                 else {
2851                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2852                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2853                         amd64_call_reg (code, GP_SCRATCH_REG);
2854                 }
2855         }
2856
2857         return code;
2858 }
2859
2860 static inline guint8*
2861 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2862 {
2863 #ifdef TARGET_WIN32
2864         if (win64_adjust_stack)
2865                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2866 #endif
2867         code = emit_call_body (cfg, code, patch_type, data);
2868 #ifdef TARGET_WIN32
2869         if (win64_adjust_stack)
2870                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2871 #endif
2872
2873         return code;
2874 }
2875
2876 static inline int
2877 store_membase_imm_to_store_membase_reg (int opcode)
2878 {
2879         switch (opcode) {
2880         case OP_STORE_MEMBASE_IMM:
2881                 return OP_STORE_MEMBASE_REG;
2882         case OP_STOREI4_MEMBASE_IMM:
2883                 return OP_STOREI4_MEMBASE_REG;
2884         case OP_STOREI8_MEMBASE_IMM:
2885                 return OP_STOREI8_MEMBASE_REG;
2886         }
2887
2888         return -1;
2889 }
2890
2891 #ifndef DISABLE_JIT
2892
2893 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2894
2895 /*
2896  * mono_arch_peephole_pass_1:
2897  *
2898  *   Perform peephole opts which should/can be performed before local regalloc
2899  */
2900 void
2901 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2902 {
2903         MonoInst *ins, *n;
2904
2905         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2906                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2907
2908                 switch (ins->opcode) {
2909                 case OP_ADD_IMM:
2910                 case OP_IADD_IMM:
2911                 case OP_LADD_IMM:
2912                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2913                                 /*
2914                                  * X86_LEA is like ADD, but doesn't have the
2915                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2916                                  * its operand to 64 bit.
2917                                  */
2918                                 ins->opcode = OP_X86_LEA_MEMBASE;
2919                                 ins->inst_basereg = ins->sreg1;
2920                         }
2921                         break;
2922                 case OP_LXOR:
2923                 case OP_IXOR:
2924                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2925                                 MonoInst *ins2;
2926
2927                                 /*
2928                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2929                                  * the latter has length 2-3 instead of 6 (reverse constant
2930                                  * propagation). These instruction sequences are very common
2931                                  * in the initlocals bblock.
2932                                  */
2933                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2934                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2935                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2936                                                 ins2->sreg1 = ins->dreg;
2937                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2938                                                 /* Continue */
2939                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2940                                                 NULLIFY_INS (ins2);
2941                                                 /* Continue */
2942                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2943                                                 /* Continue */
2944                                         } else {
2945                                                 break;
2946                                         }
2947                                 }
2948                         }
2949                         break;
2950                 case OP_COMPARE_IMM:
2951                 case OP_LCOMPARE_IMM:
2952                         /* OP_COMPARE_IMM (reg, 0)
2953                          * -->
2954                          * OP_AMD64_TEST_NULL (reg)
2955                          */
2956                         if (!ins->inst_imm)
2957                                 ins->opcode = OP_AMD64_TEST_NULL;
2958                         break;
2959                 case OP_ICOMPARE_IMM:
2960                         if (!ins->inst_imm)
2961                                 ins->opcode = OP_X86_TEST_NULL;
2962                         break;
2963                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2964                         /*
2965                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2966                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2967                          * -->
2968                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2969                          * OP_COMPARE_IMM reg, imm
2970                          *
2971                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2972                          */
2973                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2974                             ins->inst_basereg == last_ins->inst_destbasereg &&
2975                             ins->inst_offset == last_ins->inst_offset) {
2976                                         ins->opcode = OP_ICOMPARE_IMM;
2977                                         ins->sreg1 = last_ins->sreg1;
2978
2979                                         /* check if we can remove cmp reg,0 with test null */
2980                                         if (!ins->inst_imm)
2981                                                 ins->opcode = OP_X86_TEST_NULL;
2982                                 }
2983
2984                         break;
2985                 }
2986
2987                 mono_peephole_ins (bb, ins);
2988         }
2989 }
2990
2991 void
2992 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2993 {
2994         MonoInst *ins, *n;
2995
2996         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2997                 switch (ins->opcode) {
2998                 case OP_ICONST:
2999                 case OP_I8CONST: {
3000                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3001                         /* reg = 0 -> XOR (reg, reg) */
3002                         /* XOR sets cflags on x86, so we cant do it always */
3003                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3004                                 ins->opcode = OP_LXOR;
3005                                 ins->sreg1 = ins->dreg;
3006                                 ins->sreg2 = ins->dreg;
3007                                 /* Fall through */
3008                         } else {
3009                                 break;
3010                         }
3011                 }
3012                 case OP_LXOR:
3013                         /*
3014                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3015                          * 0 result into 64 bits.
3016                          */
3017                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3018                                 ins->opcode = OP_IXOR;
3019                         }
3020                         /* Fall through */
3021                 case OP_IXOR:
3022                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3023                                 MonoInst *ins2;
3024
3025                                 /*
3026                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3027                                  * the latter has length 2-3 instead of 6 (reverse constant
3028                                  * propagation). These instruction sequences are very common
3029                                  * in the initlocals bblock.
3030                                  */
3031                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3032                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3033                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3034                                                 ins2->sreg1 = ins->dreg;
3035                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3036                                                 /* Continue */
3037                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3038                                                 NULLIFY_INS (ins2);
3039                                                 /* Continue */
3040                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3041                                                 /* Continue */
3042                                         } else {
3043                                                 break;
3044                                         }
3045                                 }
3046                         }
3047                         break;
3048                 case OP_IADD_IMM:
3049                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3050                                 ins->opcode = OP_X86_INC_REG;
3051                         break;
3052                 case OP_ISUB_IMM:
3053                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3054                                 ins->opcode = OP_X86_DEC_REG;
3055                         break;
3056                 }
3057
3058                 mono_peephole_ins (bb, ins);
3059         }
3060 }
3061
3062 #define NEW_INS(cfg,ins,dest,op) do {   \
3063                 MONO_INST_NEW ((cfg), (dest), (op)); \
3064         (dest)->cil_code = (ins)->cil_code; \
3065         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3066         } while (0)
3067
3068 /*
3069  * mono_arch_lowering_pass:
3070  *
3071  *  Converts complex opcodes into simpler ones so that each IR instruction
3072  * corresponds to one machine instruction.
3073  */
3074 void
3075 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3076 {
3077         MonoInst *ins, *n, *temp;
3078
3079         /*
3080          * FIXME: Need to add more instructions, but the current machine
3081          * description can't model some parts of the composite instructions like
3082          * cdq.
3083          */
3084         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3085                 switch (ins->opcode) {
3086                 case OP_DIV_IMM:
3087                 case OP_REM_IMM:
3088                 case OP_IDIV_IMM:
3089                 case OP_IDIV_UN_IMM:
3090                 case OP_IREM_UN_IMM:
3091                 case OP_LREM_IMM:
3092                 case OP_IREM_IMM:
3093                         mono_decompose_op_imm (cfg, bb, ins);
3094                         break;
3095                 case OP_COMPARE_IMM:
3096                 case OP_LCOMPARE_IMM:
3097                         if (!amd64_use_imm32 (ins->inst_imm)) {
3098                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3099                                 temp->inst_c0 = ins->inst_imm;
3100                                 temp->dreg = mono_alloc_ireg (cfg);
3101                                 ins->opcode = OP_COMPARE;
3102                                 ins->sreg2 = temp->dreg;
3103                         }
3104                         break;
3105 #ifndef __mono_ilp32__
3106                 case OP_LOAD_MEMBASE:
3107 #endif
3108                 case OP_LOADI8_MEMBASE:
3109                 /*  Don't generate memindex opcodes (to simplify */
3110                 /*  read sandboxing) */
3111                         if (!amd64_use_imm32 (ins->inst_offset)) {
3112                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3113                                 temp->inst_c0 = ins->inst_offset;
3114                                 temp->dreg = mono_alloc_ireg (cfg);
3115                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3116                                 ins->inst_indexreg = temp->dreg;
3117                         }
3118                         break;
3119 #ifndef __mono_ilp32__
3120                 case OP_STORE_MEMBASE_IMM:
3121 #endif
3122                 case OP_STOREI8_MEMBASE_IMM:
3123                         if (!amd64_use_imm32 (ins->inst_imm)) {
3124                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3125                                 temp->inst_c0 = ins->inst_imm;
3126                                 temp->dreg = mono_alloc_ireg (cfg);
3127                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3128                                 ins->sreg1 = temp->dreg;
3129                         }
3130                         break;
3131 #ifdef MONO_ARCH_SIMD_INTRINSICS
3132                 case OP_EXPAND_I1: {
3133                                 int temp_reg1 = mono_alloc_ireg (cfg);
3134                                 int temp_reg2 = mono_alloc_ireg (cfg);
3135                                 int original_reg = ins->sreg1;
3136
3137                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3138                                 temp->sreg1 = original_reg;
3139                                 temp->dreg = temp_reg1;
3140
3141                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3142                                 temp->sreg1 = temp_reg1;
3143                                 temp->dreg = temp_reg2;
3144                                 temp->inst_imm = 8;
3145
3146                                 NEW_INS (cfg, ins, temp, OP_LOR);
3147                                 temp->sreg1 = temp->dreg = temp_reg2;
3148                                 temp->sreg2 = temp_reg1;
3149
3150                                 ins->opcode = OP_EXPAND_I2;
3151                                 ins->sreg1 = temp_reg2;
3152                         }
3153                         break;
3154 #endif
3155                 default:
3156                         break;
3157                 }
3158         }
3159
3160         bb->max_vreg = cfg->next_vreg;
3161 }
3162
3163 static const int
3164 branch_cc_table [] = {
3165         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3166         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3167         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3168 };
3169
3170 /* Maps CMP_... constants to X86_CC_... constants */
3171 static const int
3172 cc_table [] = {
3173         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3174         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3175 };
3176
3177 static const int
3178 cc_signed_table [] = {
3179         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3180         FALSE, FALSE, FALSE, FALSE
3181 };
3182
3183 /*#include "cprop.c"*/
3184
3185 static unsigned char*
3186 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3187 {
3188         if (size == 8)
3189                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3190         else
3191                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3192
3193         if (size == 1)
3194                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3195         else if (size == 2)
3196                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3197         return code;
3198 }
3199
3200 static unsigned char*
3201 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3202 {
3203         int sreg = tree->sreg1;
3204         int need_touch = FALSE;
3205
3206 #if defined(TARGET_WIN32)
3207         need_touch = TRUE;
3208 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3209         if (!tree->flags & MONO_INST_INIT)
3210                 need_touch = TRUE;
3211 #endif
3212
3213         if (need_touch) {
3214                 guint8* br[5];
3215
3216                 /*
3217                  * Under Windows:
3218                  * If requested stack size is larger than one page,
3219                  * perform stack-touch operation
3220                  */
3221                 /*
3222                  * Generate stack probe code.
3223                  * Under Windows, it is necessary to allocate one page at a time,
3224                  * "touching" stack after each successful sub-allocation. This is
3225                  * because of the way stack growth is implemented - there is a
3226                  * guard page before the lowest stack page that is currently commited.
3227                  * Stack normally grows sequentially so OS traps access to the
3228                  * guard page and commits more pages when needed.
3229                  */
3230                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3231                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3232
3233                 br[2] = code; /* loop */
3234                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3235                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3236                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3237                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3238                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3239                 amd64_patch (br[3], br[2]);
3240                 amd64_test_reg_reg (code, sreg, sreg);
3241                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3242                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3243
3244                 br[1] = code; x86_jump8 (code, 0);
3245
3246                 amd64_patch (br[0], code);
3247                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3248                 amd64_patch (br[1], code);
3249                 amd64_patch (br[4], code);
3250         }
3251         else
3252                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3253
3254         if (tree->flags & MONO_INST_INIT) {
3255                 int offset = 0;
3256                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3257                         amd64_push_reg (code, AMD64_RAX);
3258                         offset += 8;
3259                 }
3260                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3261                         amd64_push_reg (code, AMD64_RCX);
3262                         offset += 8;
3263                 }
3264                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3265                         amd64_push_reg (code, AMD64_RDI);
3266                         offset += 8;
3267                 }
3268
3269                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3270                 if (sreg != AMD64_RCX)
3271                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3272                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3273
3274                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3275                 if (cfg->param_area)
3276                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3277                 amd64_cld (code);
3278                 amd64_prefix (code, X86_REP_PREFIX);
3279                 amd64_stosl (code);
3280
3281                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3282                         amd64_pop_reg (code, AMD64_RDI);
3283                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3284                         amd64_pop_reg (code, AMD64_RCX);
3285                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3286                         amd64_pop_reg (code, AMD64_RAX);
3287         }
3288         return code;
3289 }
3290
3291 static guint8*
3292 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3293 {
3294         CallInfo *cinfo;
3295         guint32 quad;
3296
3297         /* Move return value to the target register */
3298         /* FIXME: do this in the local reg allocator */
3299         switch (ins->opcode) {
3300         case OP_CALL:
3301         case OP_CALL_REG:
3302         case OP_CALL_MEMBASE:
3303         case OP_LCALL:
3304         case OP_LCALL_REG:
3305         case OP_LCALL_MEMBASE:
3306                 g_assert (ins->dreg == AMD64_RAX);
3307                 break;
3308         case OP_FCALL:
3309         case OP_FCALL_REG:
3310         case OP_FCALL_MEMBASE: {
3311                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3312                 if (rtype->type == MONO_TYPE_R4) {
3313                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3314                 }
3315                 else {
3316                         if (ins->dreg != AMD64_XMM0)
3317                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3318                 }
3319                 break;
3320         }
3321         case OP_RCALL:
3322         case OP_RCALL_REG:
3323         case OP_RCALL_MEMBASE:
3324                 if (ins->dreg != AMD64_XMM0)
3325                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3326                 break;
3327         case OP_VCALL:
3328         case OP_VCALL_REG:
3329         case OP_VCALL_MEMBASE:
3330         case OP_VCALL2:
3331         case OP_VCALL2_REG:
3332         case OP_VCALL2_MEMBASE:
3333                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3334                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3335                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3336
3337                         /* Load the destination address */
3338                         g_assert (loc->opcode == OP_REGOFFSET);
3339                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3340
3341                         for (quad = 0; quad < 2; quad ++) {
3342                                 switch (cinfo->ret.pair_storage [quad]) {
3343                                 case ArgInIReg:
3344                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3345                                         break;
3346                                 case ArgInFloatSSEReg:
3347                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3348                                         break;
3349                                 case ArgInDoubleSSEReg:
3350                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3351                                         break;
3352                                 case ArgNone:
3353                                         break;
3354                                 default:
3355                                         NOT_IMPLEMENTED;
3356                                 }
3357                         }
3358                 }
3359                 break;
3360         }
3361
3362         return code;
3363 }
3364
3365 #endif /* DISABLE_JIT */
3366
3367 #ifdef __APPLE__
3368 static int tls_gs_offset;
3369 #endif
3370
3371 gboolean
3372 mono_amd64_have_tls_get (void)
3373 {
3374 #ifdef TARGET_MACH
3375         static gboolean have_tls_get = FALSE;
3376         static gboolean inited = FALSE;
3377
3378         if (inited)
3379                 return have_tls_get;
3380
3381 #if MONO_HAVE_FAST_TLS
3382         guint8 *ins = (guint8*)pthread_getspecific;
3383
3384         /*
3385          * We're looking for these two instructions:
3386          *
3387          * mov    %gs:[offset](,%rdi,8),%rax
3388          * retq
3389          */
3390         have_tls_get = ins [0] == 0x65 &&
3391                        ins [1] == 0x48 &&
3392                        ins [2] == 0x8b &&
3393                        ins [3] == 0x04 &&
3394                        ins [4] == 0xfd &&
3395                        ins [6] == 0x00 &&
3396                        ins [7] == 0x00 &&
3397                        ins [8] == 0x00 &&
3398                        ins [9] == 0xc3;
3399
3400         tls_gs_offset = ins[5];
3401
3402         /*
3403          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3404          * For that version we're looking for these instructions:
3405          *
3406          * pushq  %rbp
3407          * movq   %rsp, %rbp
3408          * mov    %gs:[offset](,%rdi,8),%rax
3409          * popq   %rbp
3410          * retq
3411          */
3412         if (!have_tls_get) {
3413                 have_tls_get = ins [0] == 0x55 &&
3414                                ins [1] == 0x48 &&
3415                                ins [2] == 0x89 &&
3416                                ins [3] == 0xe5 &&
3417                                ins [4] == 0x65 &&
3418                                ins [5] == 0x48 &&
3419                                ins [6] == 0x8b &&
3420                                ins [7] == 0x04 &&
3421                                ins [8] == 0xfd &&
3422                                ins [10] == 0x00 &&
3423                                ins [11] == 0x00 &&
3424                                ins [12] == 0x00 &&
3425                                ins [13] == 0x5d &&
3426                                ins [14] == 0xc3;
3427
3428                 tls_gs_offset = ins[9];
3429         }
3430 #endif
3431
3432         inited = TRUE;
3433
3434         return have_tls_get;
3435 #elif defined(TARGET_ANDROID)
3436         return FALSE;
3437 #else
3438         return TRUE;
3439 #endif
3440 }
3441
3442 int
3443 mono_amd64_get_tls_gs_offset (void)
3444 {
3445 #ifdef TARGET_OSX
3446         return tls_gs_offset;
3447 #else
3448         g_assert_not_reached ();
3449         return -1;
3450 #endif
3451 }
3452
3453 /*
3454  * mono_amd64_emit_tls_get:
3455  * @code: buffer to store code to
3456  * @dreg: hard register where to place the result
3457  * @tls_offset: offset info
3458  *
3459  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3460  * the dreg register the item in the thread local storage identified
3461  * by tls_offset.
3462  *
3463  * Returns: a pointer to the end of the stored code
3464  */
3465 guint8*
3466 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3467 {
3468 #ifdef TARGET_WIN32
3469         if (tls_offset < 64) {
3470                 x86_prefix (code, X86_GS_PREFIX);
3471                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3472         } else {
3473                 guint8 *buf [16];
3474
3475                 g_assert (tls_offset < 0x440);
3476                 /* Load TEB->TlsExpansionSlots */
3477                 x86_prefix (code, X86_GS_PREFIX);
3478                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3479                 amd64_test_reg_reg (code, dreg, dreg);
3480                 buf [0] = code;
3481                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3482                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3483                 amd64_patch (buf [0], code);
3484         }
3485 #elif defined(__APPLE__)
3486         x86_prefix (code, X86_GS_PREFIX);
3487         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3488 #else
3489         if (optimize_for_xen) {
3490                 x86_prefix (code, X86_FS_PREFIX);
3491                 amd64_mov_reg_mem (code, dreg, 0, 8);
3492                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3493         } else {
3494                 x86_prefix (code, X86_FS_PREFIX);
3495                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3496         }
3497 #endif
3498         return code;
3499 }
3500
3501 #ifdef TARGET_WIN32
3502
3503 #define MAX_TEB_TLS_SLOTS 64
3504 #define TEB_TLS_SLOTS_OFFSET 0x1480
3505 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3506
3507 static guint8*
3508 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3509 {
3510         int tmp_reg = -1;
3511         guint8 * more_than_64_slots = NULL;
3512         guint8 * empty_slot = NULL;
3513         guint8 * tls_get_reg_done = NULL;
3514
3515         //Use temporary register for offset calculation?
3516         if (dreg == offset_reg) {
3517                 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3518                 amd64_push_reg (code, tmp_reg);
3519                 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3520                 offset_reg = tmp_reg;
3521         }
3522
3523         //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3524         amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3525         more_than_64_slots = code;
3526         amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3527
3528         //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3529         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3530         amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3531
3532         //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3533         x86_prefix (code, X86_GS_PREFIX);
3534         amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3535
3536         tls_get_reg_done = code;
3537         amd64_jump8 (code, 0);
3538
3539         amd64_patch (more_than_64_slots, code);
3540
3541         //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3542         x86_prefix (code, X86_GS_PREFIX);
3543         amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3544
3545         //Check for NULL in _TEB.TlsExpansionSlots.
3546         amd64_test_reg_reg (code, dreg, dreg);
3547         empty_slot = code;
3548         amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3549
3550         //TLS expansion slots are at index offset into the expansion array.
3551         //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3552         amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3553         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3554
3555         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3556
3557         amd64_patch (empty_slot, code);
3558         amd64_patch (tls_get_reg_done, code);
3559
3560         if (tmp_reg != -1)
3561                 amd64_pop_reg (code, tmp_reg);
3562
3563         return code;
3564 }
3565
3566 #endif
3567
3568 static guint8*
3569 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3570 {
3571         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3572 #ifdef TARGET_OSX
3573         if (dreg != offset_reg)
3574                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3575         amd64_prefix (code, X86_GS_PREFIX);
3576         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3577 #elif defined(__linux__)
3578         int tmpreg = -1;
3579
3580         if (dreg == offset_reg) {
3581                 /* Use a temporary reg by saving it to the redzone */
3582                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3583                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3584                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3585                 offset_reg = tmpreg;
3586         }
3587         x86_prefix (code, X86_FS_PREFIX);
3588         amd64_mov_reg_mem (code, dreg, 0, 8);
3589         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3590         if (tmpreg != -1)
3591                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3592 #elif defined(TARGET_WIN32)
3593         code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3594 #else
3595         g_assert_not_reached ();
3596 #endif
3597         return code;
3598 }
3599
3600 static guint8*
3601 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3602 {
3603 #ifdef TARGET_WIN32
3604         g_assert_not_reached ();
3605 #elif defined(__APPLE__)
3606         x86_prefix (code, X86_GS_PREFIX);
3607         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3608 #else
3609         g_assert (!optimize_for_xen);
3610         x86_prefix (code, X86_FS_PREFIX);
3611         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3612 #endif
3613         return code;
3614 }
3615
3616 static guint8*
3617 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3618 {
3619         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3620 #ifdef TARGET_WIN32
3621         g_assert_not_reached ();
3622 #elif defined(__APPLE__)
3623         x86_prefix (code, X86_GS_PREFIX);
3624         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3625 #else
3626         x86_prefix (code, X86_FS_PREFIX);
3627         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3628 #endif
3629         return code;
3630 }
3631
3632  /*
3633  * mono_arch_translate_tls_offset:
3634  *
3635  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3636  */
3637 int
3638 mono_arch_translate_tls_offset (int offset)
3639 {
3640 #ifdef __APPLE__
3641         return tls_gs_offset + (offset * 8);
3642 #else
3643         return offset;
3644 #endif
3645 }
3646
3647 /*
3648  * emit_setup_lmf:
3649  *
3650  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3651  */
3652 static guint8*
3653 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3654 {
3655         /*
3656          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3657          */
3658         /*
3659          * sp is saved right before calls but we need to save it here too so
3660          * async stack walks would work.
3661          */
3662         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3663         /* Save rbp */
3664         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3665         if (cfg->arch.omit_fp && cfa_offset != -1)
3666                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3667
3668         /* These can't contain refs */
3669         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3670         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3671         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3672         /* These are handled automatically by the stack marking code */
3673         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3674
3675         return code;
3676 }
3677
3678 /* benchmark and set based on cpu */
3679 #define LOOP_ALIGNMENT 8
3680 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3681
3682 #ifndef DISABLE_JIT
3683 void
3684 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3685 {
3686         MonoInst *ins;
3687         MonoCallInst *call;
3688         guint offset;
3689         guint8 *code = cfg->native_code + cfg->code_len;
3690         int max_len;
3691
3692         /* Fix max_offset estimate for each successor bb */
3693         if (cfg->opt & MONO_OPT_BRANCH) {
3694                 int current_offset = cfg->code_len;
3695                 MonoBasicBlock *current_bb;
3696                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3697                         current_bb->max_offset = current_offset;
3698                         current_offset += current_bb->max_length;
3699                 }
3700         }
3701
3702         if (cfg->opt & MONO_OPT_LOOP) {
3703                 int pad, align = LOOP_ALIGNMENT;
3704                 /* set alignment depending on cpu */
3705                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3706                         pad = align - pad;
3707                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3708                         amd64_padding (code, pad);
3709                         cfg->code_len += pad;
3710                         bb->native_offset = cfg->code_len;
3711                 }
3712         }
3713
3714         if (cfg->verbose_level > 2)
3715                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3716
3717         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3718                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3719                 g_assert (!cfg->compile_aot);
3720
3721                 cov->data [bb->dfn].cil_code = bb->cil_code;
3722                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3723                 /* this is not thread save, but good enough */
3724                 amd64_inc_membase (code, AMD64_R11, 0);
3725         }
3726
3727         offset = code - cfg->native_code;
3728
3729         mono_debug_open_block (cfg, bb, offset);
3730
3731     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3732                 x86_breakpoint (code);
3733
3734         MONO_BB_FOR_EACH_INS (bb, ins) {
3735                 offset = code - cfg->native_code;
3736
3737                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3738
3739 #define EXTRA_CODE_SPACE (16)
3740
3741                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3742                         cfg->code_size *= 2;
3743                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3744                         code = cfg->native_code + offset;
3745                         cfg->stat_code_reallocs++;
3746                 }
3747
3748                 if (cfg->debug_info)
3749                         mono_debug_record_line_number (cfg, ins, offset);
3750
3751                 switch (ins->opcode) {
3752                 case OP_BIGMUL:
3753                         amd64_mul_reg (code, ins->sreg2, TRUE);
3754                         break;
3755                 case OP_BIGMUL_UN:
3756                         amd64_mul_reg (code, ins->sreg2, FALSE);
3757                         break;
3758                 case OP_X86_SETEQ_MEMBASE:
3759                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3760                         break;
3761                 case OP_STOREI1_MEMBASE_IMM:
3762                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3763                         break;
3764                 case OP_STOREI2_MEMBASE_IMM:
3765                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3766                         break;
3767                 case OP_STOREI4_MEMBASE_IMM:
3768                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3769                         break;
3770                 case OP_STOREI1_MEMBASE_REG:
3771                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3772                         break;
3773                 case OP_STOREI2_MEMBASE_REG:
3774                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3775                         break;
3776                 /* In AMD64 NaCl, pointers are 4 bytes, */
3777                 /*  so STORE_* != STOREI8_*. Likewise below. */
3778                 case OP_STORE_MEMBASE_REG:
3779                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3780                         break;
3781                 case OP_STOREI8_MEMBASE_REG:
3782                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3783                         break;
3784                 case OP_STOREI4_MEMBASE_REG:
3785                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3786                         break;
3787                 case OP_STORE_MEMBASE_IMM:
3788                         /* In NaCl, this could be a PCONST type, which could */
3789                         /* mean a pointer type was copied directly into the  */
3790                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3791                         /* the value would be 0x00000000FFFFFFFF which is    */
3792                         /* not proper for an imm32 unless you cast it.       */
3793                         g_assert (amd64_is_imm32 (ins->inst_imm));
3794                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3795                         break;
3796                 case OP_STOREI8_MEMBASE_IMM:
3797                         g_assert (amd64_is_imm32 (ins->inst_imm));
3798                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3799                         break;
3800                 case OP_LOAD_MEM:
3801 #ifdef __mono_ilp32__
3802                         /* In ILP32, pointers are 4 bytes, so separate these */
3803                         /* cases, use literal 8 below where we really want 8 */
3804                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3805                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3806                         break;
3807 #endif
3808                 case OP_LOADI8_MEM:
3809                         // FIXME: Decompose this earlier
3810                         if (amd64_use_imm32 (ins->inst_imm))
3811                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3812                         else {
3813                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3814                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3815                         }
3816                         break;
3817                 case OP_LOADI4_MEM:
3818                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3819                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3820                         break;
3821                 case OP_LOADU4_MEM:
3822                         // FIXME: Decompose this earlier
3823                         if (amd64_use_imm32 (ins->inst_imm))
3824                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3825                         else {
3826                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3827                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3828                         }
3829                         break;
3830                 case OP_LOADU1_MEM:
3831                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3832                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3833                         break;
3834                 case OP_LOADU2_MEM:
3835                         /* For NaCl, pointers are 4 bytes, so separate these */
3836                         /* cases, use literal 8 below where we really want 8 */
3837                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3838                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3839                         break;
3840                 case OP_LOAD_MEMBASE:
3841                         g_assert (amd64_is_imm32 (ins->inst_offset));
3842                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3843                         break;
3844                 case OP_LOADI8_MEMBASE:
3845                         /* Use literal 8 instead of sizeof pointer or */
3846                         /* register, we really want 8 for this opcode */
3847                         g_assert (amd64_is_imm32 (ins->inst_offset));
3848                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3849                         break;
3850                 case OP_LOADI4_MEMBASE:
3851                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3852                         break;
3853                 case OP_LOADU4_MEMBASE:
3854                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3855                         break;
3856                 case OP_LOADU1_MEMBASE:
3857                         /* The cpu zero extends the result into 64 bits */
3858                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3859                         break;
3860                 case OP_LOADI1_MEMBASE:
3861                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3862                         break;
3863                 case OP_LOADU2_MEMBASE:
3864                         /* The cpu zero extends the result into 64 bits */
3865                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3866                         break;
3867                 case OP_LOADI2_MEMBASE:
3868                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3869                         break;
3870                 case OP_AMD64_LOADI8_MEMINDEX:
3871                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3872                         break;
3873                 case OP_LCONV_TO_I1:
3874                 case OP_ICONV_TO_I1:
3875                 case OP_SEXT_I1:
3876                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3877                         break;
3878                 case OP_LCONV_TO_I2:
3879                 case OP_ICONV_TO_I2:
3880                 case OP_SEXT_I2:
3881                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3882                         break;
3883                 case OP_LCONV_TO_U1:
3884                 case OP_ICONV_TO_U1:
3885                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3886                         break;
3887                 case OP_LCONV_TO_U2:
3888                 case OP_ICONV_TO_U2:
3889                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3890                         break;
3891                 case OP_ZEXT_I4:
3892                         /* Clean out the upper word */
3893                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3894                         break;
3895                 case OP_SEXT_I4:
3896                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3897                         break;
3898                 case OP_COMPARE:
3899                 case OP_LCOMPARE:
3900                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3901                         break;
3902                 case OP_COMPARE_IMM:
3903 #if defined(__mono_ilp32__)
3904                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3905                         g_assert (amd64_is_imm32 (ins->inst_imm));
3906                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3907                         break;
3908 #endif
3909                 case OP_LCOMPARE_IMM:
3910                         g_assert (amd64_is_imm32 (ins->inst_imm));
3911                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3912                         break;
3913                 case OP_X86_COMPARE_REG_MEMBASE:
3914                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3915                         break;
3916                 case OP_X86_TEST_NULL:
3917                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3918                         break;
3919                 case OP_AMD64_TEST_NULL:
3920                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3921                         break;
3922
3923                 case OP_X86_ADD_REG_MEMBASE:
3924                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3925                         break;
3926                 case OP_X86_SUB_REG_MEMBASE:
3927                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3928                         break;
3929                 case OP_X86_AND_REG_MEMBASE:
3930                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3931                         break;
3932                 case OP_X86_OR_REG_MEMBASE:
3933                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3934                         break;
3935                 case OP_X86_XOR_REG_MEMBASE:
3936                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3937                         break;
3938
3939                 case OP_X86_ADD_MEMBASE_IMM:
3940                         /* FIXME: Make a 64 version too */
3941                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3942                         break;
3943                 case OP_X86_SUB_MEMBASE_IMM:
3944                         g_assert (amd64_is_imm32 (ins->inst_imm));
3945                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3946                         break;
3947                 case OP_X86_AND_MEMBASE_IMM:
3948                         g_assert (amd64_is_imm32 (ins->inst_imm));
3949                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3950                         break;
3951                 case OP_X86_OR_MEMBASE_IMM:
3952                         g_assert (amd64_is_imm32 (ins->inst_imm));
3953                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3954                         break;
3955                 case OP_X86_XOR_MEMBASE_IMM:
3956                         g_assert (amd64_is_imm32 (ins->inst_imm));
3957                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3958                         break;
3959                 case OP_X86_ADD_MEMBASE_REG:
3960                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3961                         break;
3962                 case OP_X86_SUB_MEMBASE_REG:
3963                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3964                         break;
3965                 case OP_X86_AND_MEMBASE_REG:
3966                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3967                         break;
3968                 case OP_X86_OR_MEMBASE_REG:
3969                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3970                         break;
3971                 case OP_X86_XOR_MEMBASE_REG:
3972                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3973                         break;
3974                 case OP_X86_INC_MEMBASE:
3975                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3976                         break;
3977                 case OP_X86_INC_REG:
3978                         amd64_inc_reg_size (code, ins->dreg, 4);
3979                         break;
3980                 case OP_X86_DEC_MEMBASE:
3981                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3982                         break;
3983                 case OP_X86_DEC_REG:
3984                         amd64_dec_reg_size (code, ins->dreg, 4);
3985                         break;
3986                 case OP_X86_MUL_REG_MEMBASE:
3987                 case OP_X86_MUL_MEMBASE_REG:
3988                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3989                         break;
3990                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3991                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3992                         break;
3993                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3994                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3995                         break;
3996                 case OP_AMD64_COMPARE_MEMBASE_REG:
3997                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3998                         break;
3999                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4000                         g_assert (amd64_is_imm32 (ins->inst_imm));
4001                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4002                         break;
4003                 case OP_X86_COMPARE_MEMBASE8_IMM:
4004                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4005                         break;
4006                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4007                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4008                         break;
4009                 case OP_AMD64_COMPARE_REG_MEMBASE:
4010                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4011                         break;
4012
4013                 case OP_AMD64_ADD_REG_MEMBASE:
4014                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4015                         break;
4016                 case OP_AMD64_SUB_REG_MEMBASE:
4017                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4018                         break;
4019                 case OP_AMD64_AND_REG_MEMBASE:
4020                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4021                         break;
4022                 case OP_AMD64_OR_REG_MEMBASE:
4023                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4024                         break;
4025                 case OP_AMD64_XOR_REG_MEMBASE:
4026                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4027                         break;
4028
4029                 case OP_AMD64_ADD_MEMBASE_REG:
4030                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4031                         break;
4032                 case OP_AMD64_SUB_MEMBASE_REG:
4033                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4034                         break;
4035                 case OP_AMD64_AND_MEMBASE_REG:
4036                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4037                         break;
4038                 case OP_AMD64_OR_MEMBASE_REG:
4039                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4040                         break;
4041                 case OP_AMD64_XOR_MEMBASE_REG:
4042                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4043                         break;
4044
4045                 case OP_AMD64_ADD_MEMBASE_IMM:
4046                         g_assert (amd64_is_imm32 (ins->inst_imm));
4047                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4048                         break;
4049                 case OP_AMD64_SUB_MEMBASE_IMM:
4050                         g_assert (amd64_is_imm32 (ins->inst_imm));
4051                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4052                         break;
4053                 case OP_AMD64_AND_MEMBASE_IMM:
4054                         g_assert (amd64_is_imm32 (ins->inst_imm));
4055                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4056                         break;
4057                 case OP_AMD64_OR_MEMBASE_IMM:
4058                         g_assert (amd64_is_imm32 (ins->inst_imm));
4059                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4060                         break;
4061                 case OP_AMD64_XOR_MEMBASE_IMM:
4062                         g_assert (amd64_is_imm32 (ins->inst_imm));
4063                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4064                         break;
4065
4066                 case OP_BREAK:
4067                         amd64_breakpoint (code);
4068                         break;
4069                 case OP_RELAXED_NOP:
4070                         x86_prefix (code, X86_REP_PREFIX);
4071                         x86_nop (code);
4072                         break;
4073                 case OP_HARD_NOP:
4074                         x86_nop (code);
4075                         break;
4076                 case OP_NOP:
4077                 case OP_DUMMY_USE:
4078                 case OP_DUMMY_STORE:
4079                 case OP_DUMMY_ICONST:
4080                 case OP_DUMMY_R8CONST:
4081                 case OP_NOT_REACHED:
4082                 case OP_NOT_NULL:
4083                         break;
4084                 case OP_IL_SEQ_POINT:
4085                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4086                         break;
4087                 case OP_SEQ_POINT: {
4088                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4089                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4090                                 guint8 *label;
4091
4092                                 /* Load ss_tramp_var */
4093                                 /* This is equal to &ss_trampoline */
4094                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4095                                 /* Load the trampoline address */
4096                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4097                                 /* Call it if it is non-null */
4098                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4099                                 label = code;
4100                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4101                                 amd64_call_reg (code, AMD64_R11);
4102                                 amd64_patch (label, code);
4103                         }
4104
4105                         /*
4106                          * This is the address which is saved in seq points,
4107                          */
4108                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4109
4110                         if (cfg->compile_aot) {
4111                                 guint32 offset = code - cfg->native_code;
4112                                 guint32 val;
4113                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4114                                 guint8 *label;
4115
4116                                 /* Load info var */
4117                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4118                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4119                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4120                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4121                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4122                                 label = code;
4123                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4124                                 /* Call the trampoline */
4125                                 amd64_call_reg (code, AMD64_R11);
4126                                 amd64_patch (label, code);
4127                         } else {
4128                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4129                                 guint8 *label;
4130
4131                                 /*
4132                                  * Emit a test+branch against a constant, the constant will be overwritten
4133                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4134                                  */
4135                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4136                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4137                                 label = code;
4138                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4139
4140                                 g_assert (var);
4141                                 g_assert (var->opcode == OP_REGOFFSET);
4142                                 /* Load bp_tramp_var */
4143                                 /* This is equal to &bp_trampoline */
4144                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4145                                 /* Call the trampoline */
4146                                 amd64_call_membase (code, AMD64_R11, 0);
4147                                 amd64_patch (label, code);
4148                         }
4149                         /*
4150                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4151                          * to another IL offset.
4152                          */
4153                         x86_nop (code);
4154                         break;
4155                 }
4156                 case OP_ADDCC:
4157                 case OP_LADDCC:
4158                 case OP_LADD:
4159                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4160                         break;
4161                 case OP_ADC:
4162                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4163                         break;
4164                 case OP_ADD_IMM:
4165                 case OP_LADD_IMM:
4166                         g_assert (amd64_is_imm32 (ins->inst_imm));
4167                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4168                         break;
4169                 case OP_ADC_IMM:
4170                         g_assert (amd64_is_imm32 (ins->inst_imm));
4171                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4172                         break;
4173                 case OP_SUBCC:
4174                 case OP_LSUBCC:
4175                 case OP_LSUB:
4176                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4177                         break;
4178                 case OP_SBB:
4179                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4180                         break;
4181                 case OP_SUB_IMM:
4182                 case OP_LSUB_IMM:
4183                         g_assert (amd64_is_imm32 (ins->inst_imm));
4184                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4185                         break;
4186                 case OP_SBB_IMM:
4187                         g_assert (amd64_is_imm32 (ins->inst_imm));
4188                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4189                         break;
4190                 case OP_LAND:
4191                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4192                         break;
4193                 case OP_AND_IMM:
4194                 case OP_LAND_IMM:
4195                         g_assert (amd64_is_imm32 (ins->inst_imm));
4196                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4197                         break;
4198                 case OP_LMUL:
4199                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4200                         break;
4201                 case OP_MUL_IMM:
4202                 case OP_LMUL_IMM:
4203                 case OP_IMUL_IMM: {
4204                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4205
4206                         switch (ins->inst_imm) {
4207                         case 2:
4208                                 /* MOV r1, r2 */
4209                                 /* ADD r1, r1 */
4210                                 if (ins->dreg != ins->sreg1)
4211                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4212                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4213                                 break;
4214                         case 3:
4215                                 /* LEA r1, [r2 + r2*2] */
4216                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4217                                 break;
4218                         case 5:
4219                                 /* LEA r1, [r2 + r2*4] */
4220                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4221                                 break;
4222                         case 6:
4223                                 /* LEA r1, [r2 + r2*2] */
4224                                 /* ADD r1, r1          */
4225                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4226                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4227                                 break;
4228                         case 9:
4229                                 /* LEA r1, [r2 + r2*8] */
4230                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4231                                 break;
4232                         case 10:
4233                                 /* LEA r1, [r2 + r2*4] */
4234                                 /* ADD r1, r1          */
4235                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4236                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4237                                 break;
4238                         case 12:
4239                                 /* LEA r1, [r2 + r2*2] */
4240                                 /* SHL r1, 2           */
4241                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4242                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4243                                 break;
4244                         case 25:
4245                                 /* LEA r1, [r2 + r2*4] */
4246                                 /* LEA r1, [r1 + r1*4] */
4247                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4248                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4249                                 break;
4250                         case 100:
4251                                 /* LEA r1, [r2 + r2*4] */
4252                                 /* SHL r1, 2           */
4253                                 /* LEA r1, [r1 + r1*4] */
4254                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4255                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4256                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4257                                 break;
4258                         default:
4259                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4260                                 break;
4261                         }
4262                         break;
4263                 }
4264                 case OP_LDIV:
4265                 case OP_LREM:
4266                         /* Regalloc magic makes the div/rem cases the same */
4267                         if (ins->sreg2 == AMD64_RDX) {
4268                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4269                                 amd64_cdq (code);
4270                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4271                         } else {
4272                                 amd64_cdq (code);
4273                                 amd64_div_reg (code, ins->sreg2, TRUE);
4274                         }
4275                         break;
4276                 case OP_LDIV_UN:
4277                 case OP_LREM_UN:
4278                         if (ins->sreg2 == AMD64_RDX) {
4279                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4280                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4281                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4282                         } else {
4283                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4284                                 amd64_div_reg (code, ins->sreg2, FALSE);
4285                         }
4286                         break;
4287                 case OP_IDIV:
4288                 case OP_IREM:
4289                         if (ins->sreg2 == AMD64_RDX) {
4290                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4291                                 amd64_cdq_size (code, 4);
4292                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4293                         } else {
4294                                 amd64_cdq_size (code, 4);
4295                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4296                         }
4297                         break;
4298                 case OP_IDIV_UN:
4299                 case OP_IREM_UN:
4300                         if (ins->sreg2 == AMD64_RDX) {
4301                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4302                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4303                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4304                         } else {
4305                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4306                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4307                         }
4308                         break;
4309                 case OP_LMUL_OVF:
4310                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4311                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4312                         break;
4313                 case OP_LOR:
4314                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4315                         break;
4316                 case OP_OR_IMM:
4317                 case OP_LOR_IMM:
4318                         g_assert (amd64_is_imm32 (ins->inst_imm));
4319                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4320                         break;
4321                 case OP_LXOR:
4322                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4323                         break;
4324                 case OP_XOR_IMM:
4325                 case OP_LXOR_IMM:
4326                         g_assert (amd64_is_imm32 (ins->inst_imm));
4327                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4328                         break;
4329                 case OP_LSHL:
4330                         g_assert (ins->sreg2 == AMD64_RCX);
4331                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4332                         break;
4333                 case OP_LSHR:
4334                         g_assert (ins->sreg2 == AMD64_RCX);
4335                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4336                         break;
4337                 case OP_SHR_IMM:
4338                 case OP_LSHR_IMM:
4339                         g_assert (amd64_is_imm32 (ins->inst_imm));
4340                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4341                         break;
4342                 case OP_SHR_UN_IMM:
4343                         g_assert (amd64_is_imm32 (ins->inst_imm));
4344                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4345                         break;
4346                 case OP_LSHR_UN_IMM:
4347                         g_assert (amd64_is_imm32 (ins->inst_imm));
4348                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4349                         break;
4350                 case OP_LSHR_UN:
4351                         g_assert (ins->sreg2 == AMD64_RCX);
4352                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4353                         break;
4354                 case OP_SHL_IMM:
4355                 case OP_LSHL_IMM:
4356                         g_assert (amd64_is_imm32 (ins->inst_imm));
4357                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4358                         break;
4359
4360                 case OP_IADDCC:
4361                 case OP_IADD:
4362                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4363                         break;
4364                 case OP_IADC:
4365                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4366                         break;
4367                 case OP_IADD_IMM:
4368                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4369                         break;
4370                 case OP_IADC_IMM:
4371                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4372                         break;
4373                 case OP_ISUBCC:
4374                 case OP_ISUB:
4375                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4376                         break;
4377                 case OP_ISBB:
4378                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4379                         break;
4380                 case OP_ISUB_IMM:
4381                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4382                         break;
4383                 case OP_ISBB_IMM:
4384                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4385                         break;
4386                 case OP_IAND:
4387                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4388                         break;
4389                 case OP_IAND_IMM:
4390                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4391                         break;
4392                 case OP_IOR:
4393                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4394                         break;
4395                 case OP_IOR_IMM:
4396                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4397                         break;
4398                 case OP_IXOR:
4399                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4400                         break;
4401                 case OP_IXOR_IMM:
4402                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4403                         break;
4404                 case OP_INEG:
4405                         amd64_neg_reg_size (code, ins->sreg1, 4);
4406                         break;
4407                 case OP_INOT:
4408                         amd64_not_reg_size (code, ins->sreg1, 4);
4409                         break;
4410                 case OP_ISHL:
4411                         g_assert (ins->sreg2 == AMD64_RCX);
4412                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4413                         break;
4414                 case OP_ISHR:
4415                         g_assert (ins->sreg2 == AMD64_RCX);
4416                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4417                         break;
4418                 case OP_ISHR_IMM:
4419                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4420                         break;
4421                 case OP_ISHR_UN_IMM:
4422                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4423                         break;
4424                 case OP_ISHR_UN:
4425                         g_assert (ins->sreg2 == AMD64_RCX);
4426                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4427                         break;
4428                 case OP_ISHL_IMM:
4429                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4430                         break;
4431                 case OP_IMUL:
4432                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4433                         break;
4434                 case OP_IMUL_OVF:
4435                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4436                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4437                         break;
4438                 case OP_IMUL_OVF_UN:
4439                 case OP_LMUL_OVF_UN: {
4440                         /* the mul operation and the exception check should most likely be split */
4441                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4442                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4443                         /*g_assert (ins->sreg2 == X86_EAX);
4444                         g_assert (ins->dreg == X86_EAX);*/
4445                         if (ins->sreg2 == X86_EAX) {
4446                                 non_eax_reg = ins->sreg1;
4447                         } else if (ins->sreg1 == X86_EAX) {
4448                                 non_eax_reg = ins->sreg2;
4449                         } else {
4450                                 /* no need to save since we're going to store to it anyway */
4451                                 if (ins->dreg != X86_EAX) {
4452                                         saved_eax = TRUE;
4453                                         amd64_push_reg (code, X86_EAX);
4454                                 }
4455                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4456                                 non_eax_reg = ins->sreg2;
4457                         }
4458                         if (ins->dreg == X86_EDX) {
4459                                 if (!saved_eax) {
4460                                         saved_eax = TRUE;
4461                                         amd64_push_reg (code, X86_EAX);
4462                                 }
4463                         } else {
4464                                 saved_edx = TRUE;
4465                                 amd64_push_reg (code, X86_EDX);
4466                         }
4467                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4468                         /* save before the check since pop and mov don't change the flags */
4469                         if (ins->dreg != X86_EAX)
4470                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4471                         if (saved_edx)
4472                                 amd64_pop_reg (code, X86_EDX);
4473                         if (saved_eax)
4474                                 amd64_pop_reg (code, X86_EAX);
4475                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4476                         break;
4477                 }
4478                 case OP_ICOMPARE:
4479                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4480                         break;
4481                 case OP_ICOMPARE_IMM:
4482                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4483                         break;
4484                 case OP_IBEQ:
4485                 case OP_IBLT:
4486                 case OP_IBGT:
4487                 case OP_IBGE:
4488                 case OP_IBLE:
4489                 case OP_LBEQ:
4490                 case OP_LBLT:
4491                 case OP_LBGT:
4492                 case OP_LBGE:
4493                 case OP_LBLE:
4494                 case OP_IBNE_UN:
4495                 case OP_IBLT_UN:
4496                 case OP_IBGT_UN:
4497                 case OP_IBGE_UN:
4498                 case OP_IBLE_UN:
4499                 case OP_LBNE_UN:
4500                 case OP_LBLT_UN:
4501                 case OP_LBGT_UN:
4502                 case OP_LBGE_UN:
4503                 case OP_LBLE_UN:
4504                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4505                         break;
4506
4507                 case OP_CMOV_IEQ:
4508                 case OP_CMOV_IGE:
4509                 case OP_CMOV_IGT:
4510                 case OP_CMOV_ILE:
4511                 case OP_CMOV_ILT:
4512                 case OP_CMOV_INE_UN:
4513                 case OP_CMOV_IGE_UN:
4514                 case OP_CMOV_IGT_UN:
4515                 case OP_CMOV_ILE_UN:
4516                 case OP_CMOV_ILT_UN:
4517                 case OP_CMOV_LEQ:
4518                 case OP_CMOV_LGE:
4519                 case OP_CMOV_LGT:
4520                 case OP_CMOV_LLE:
4521                 case OP_CMOV_LLT:
4522                 case OP_CMOV_LNE_UN:
4523                 case OP_CMOV_LGE_UN:
4524                 case OP_CMOV_LGT_UN:
4525                 case OP_CMOV_LLE_UN:
4526                 case OP_CMOV_LLT_UN:
4527                         g_assert (ins->dreg == ins->sreg1);
4528                         /* This needs to operate on 64 bit values */
4529                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4530                         break;
4531
4532                 case OP_LNOT:
4533                         amd64_not_reg (code, ins->sreg1);
4534                         break;
4535                 case OP_LNEG:
4536                         amd64_neg_reg (code, ins->sreg1);
4537                         break;
4538
4539                 case OP_ICONST:
4540                 case OP_I8CONST:
4541                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4542                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4543                         else
4544                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4545                         break;
4546                 case OP_AOTCONST:
4547                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4548                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4549                         break;
4550                 case OP_JUMP_TABLE:
4551                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4552                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4553                         break;
4554                 case OP_MOVE:
4555                         if (ins->dreg != ins->sreg1)
4556                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4557                         break;
4558                 case OP_AMD64_SET_XMMREG_R4: {
4559                         if (cfg->r4fp) {
4560                                 if (ins->dreg != ins->sreg1)
4561                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4562                         } else {
4563                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4564                         }
4565                         break;
4566                 }
4567                 case OP_AMD64_SET_XMMREG_R8: {
4568                         if (ins->dreg != ins->sreg1)
4569                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4570                         break;
4571                 }
4572                 case OP_TAILCALL: {
4573                         MonoCallInst *call = (MonoCallInst*)ins;
4574                         int i, save_area_offset;
4575
4576                         g_assert (!cfg->method->save_lmf);
4577
4578                         /* Restore callee saved registers */
4579                         save_area_offset = cfg->arch.reg_save_area_offset;
4580                         for (i = 0; i < AMD64_NREG; ++i)
4581                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4582                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4583                                         save_area_offset += 8;
4584                                 }
4585
4586                         if (cfg->arch.omit_fp) {
4587                                 if (cfg->arch.stack_alloc_size)
4588                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4589                                 // FIXME:
4590                                 if (call->stack_usage)
4591                                         NOT_IMPLEMENTED;
4592                         } else {
4593                                 /* Copy arguments on the stack to our argument area */
4594                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4595                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4596                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4597                                 }
4598
4599                                 amd64_leave (code);
4600                         }
4601
4602                         offset = code - cfg->native_code;
4603                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4604                         if (cfg->compile_aot)
4605                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4606                         else
4607                                 amd64_set_reg_template (code, AMD64_R11);
4608                         amd64_jump_reg (code, AMD64_R11);
4609                         ins->flags |= MONO_INST_GC_CALLSITE;
4610                         ins->backend.pc_offset = code - cfg->native_code;
4611                         break;
4612                 }
4613                 case OP_CHECK_THIS:
4614                         /* ensure ins->sreg1 is not NULL */
4615                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4616                         break;
4617                 case OP_ARGLIST: {
4618                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4619                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4620                         break;
4621                 }
4622                 case OP_CALL:
4623                 case OP_FCALL:
4624                 case OP_RCALL:
4625                 case OP_LCALL:
4626                 case OP_VCALL:
4627                 case OP_VCALL2:
4628                 case OP_VOIDCALL:
4629                         call = (MonoCallInst*)ins;
4630                         /*
4631                          * The AMD64 ABI forces callers to know about varargs.
4632                          */
4633                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4634                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4635                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4636                                 /*
4637                                  * Since the unmanaged calling convention doesn't contain a
4638                                  * 'vararg' entry, we have to treat every pinvoke call as a
4639                                  * potential vararg call.
4640                                  */
4641                                 guint32 nregs, i;
4642                                 nregs = 0;
4643                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4644                                         if (call->used_fregs & (1 << i))
4645                                                 nregs ++;
4646                                 if (!nregs)
4647                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4648                                 else
4649                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4650                         }
4651
4652                         if (ins->flags & MONO_INST_HAS_METHOD)
4653                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4654                         else
4655                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4656                         ins->flags |= MONO_INST_GC_CALLSITE;
4657                         ins->backend.pc_offset = code - cfg->native_code;
4658                         code = emit_move_return_value (cfg, ins, code);
4659                         break;
4660                 case OP_FCALL_REG:
4661                 case OP_RCALL_REG:
4662                 case OP_LCALL_REG:
4663                 case OP_VCALL_REG:
4664                 case OP_VCALL2_REG:
4665                 case OP_VOIDCALL_REG:
4666                 case OP_CALL_REG:
4667                         call = (MonoCallInst*)ins;
4668
4669                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4670                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4671                                 ins->sreg1 = AMD64_R11;
4672                         }
4673
4674                         /*
4675                          * The AMD64 ABI forces callers to know about varargs.
4676                          */
4677                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4678                                 if (ins->sreg1 == AMD64_RAX) {
4679                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4680                                         ins->sreg1 = AMD64_R11;
4681                                 }
4682                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4683                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4684                                 /*
4685                                  * Since the unmanaged calling convention doesn't contain a
4686                                  * 'vararg' entry, we have to treat every pinvoke call as a
4687                                  * potential vararg call.
4688                                  */
4689                                 guint32 nregs, i;
4690                                 nregs = 0;
4691                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4692                                         if (call->used_fregs & (1 << i))
4693                                                 nregs ++;
4694                                 if (ins->sreg1 == AMD64_RAX) {
4695                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4696                                         ins->sreg1 = AMD64_R11;
4697                                 }
4698                                 if (!nregs)
4699                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4700                                 else
4701                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4702                         }
4703
4704                         amd64_call_reg (code, ins->sreg1);
4705                         ins->flags |= MONO_INST_GC_CALLSITE;
4706                         ins->backend.pc_offset = code - cfg->native_code;
4707                         code = emit_move_return_value (cfg, ins, code);
4708                         break;
4709                 case OP_FCALL_MEMBASE:
4710                 case OP_RCALL_MEMBASE:
4711                 case OP_LCALL_MEMBASE:
4712                 case OP_VCALL_MEMBASE:
4713                 case OP_VCALL2_MEMBASE:
4714                 case OP_VOIDCALL_MEMBASE:
4715                 case OP_CALL_MEMBASE:
4716                         call = (MonoCallInst*)ins;
4717
4718                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4719                         ins->flags |= MONO_INST_GC_CALLSITE;
4720                         ins->backend.pc_offset = code - cfg->native_code;
4721                         code = emit_move_return_value (cfg, ins, code);
4722                         break;
4723                 case OP_DYN_CALL: {
4724                         int i;
4725                         MonoInst *var = cfg->dyn_call_var;
4726                         guint8 *label;
4727
4728                         g_assert (var->opcode == OP_REGOFFSET);
4729
4730                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4731                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4732                         /* r10 = ftn */
4733                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4734
4735                         /* Save args buffer */
4736                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4737
4738                         /* Set fp arg regs */
4739                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4740                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4741                         label = code;
4742                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4743                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4744                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4745                         amd64_patch (label, code);
4746
4747                         /* Set stack args */
4748                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4749                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4750                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4751                         }
4752
4753                         /* Set argument registers */
4754                         for (i = 0; i < PARAM_REGS; ++i)
4755                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4756
4757                         /* Make the call */
4758                         amd64_call_reg (code, AMD64_R10);
4759
4760                         ins->flags |= MONO_INST_GC_CALLSITE;
4761                         ins->backend.pc_offset = code - cfg->native_code;
4762
4763                         /* Save result */
4764                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4765                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4766                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4767                         break;
4768                 }
4769                 case OP_AMD64_SAVE_SP_TO_LMF: {
4770                         MonoInst *lmf_var = cfg->lmf_var;
4771                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4772                         break;
4773                 }
4774                 case OP_X86_PUSH:
4775                         g_assert_not_reached ();
4776                         amd64_push_reg (code, ins->sreg1);
4777                         break;
4778                 case OP_X86_PUSH_IMM:
4779                         g_assert_not_reached ();
4780                         g_assert (amd64_is_imm32 (ins->inst_imm));
4781                         amd64_push_imm (code, ins->inst_imm);
4782                         break;
4783                 case OP_X86_PUSH_MEMBASE:
4784                         g_assert_not_reached ();
4785                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4786                         break;
4787                 case OP_X86_PUSH_OBJ: {
4788                         int size = ALIGN_TO (ins->inst_imm, 8);
4789
4790                         g_assert_not_reached ();
4791
4792                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4793                         amd64_push_reg (code, AMD64_RDI);
4794                         amd64_push_reg (code, AMD64_RSI);
4795                         amd64_push_reg (code, AMD64_RCX);
4796                         if (ins->inst_offset)
4797                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4798                         else
4799                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4800                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4801                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4802                         amd64_cld (code);
4803                         amd64_prefix (code, X86_REP_PREFIX);
4804                         amd64_movsd (code);
4805                         amd64_pop_reg (code, AMD64_RCX);
4806                         amd64_pop_reg (code, AMD64_RSI);
4807                         amd64_pop_reg (code, AMD64_RDI);
4808                         break;
4809                 }
4810                 case OP_GENERIC_CLASS_INIT: {
4811                         static int byte_offset = -1;
4812                         static guint8 bitmask;
4813                         guint8 *jump;
4814
4815                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4816
4817                         if (byte_offset < 0)
4818                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4819
4820                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4821                         jump = code;
4822                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4823
4824                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4825                         ins->flags |= MONO_INST_GC_CALLSITE;
4826                         ins->backend.pc_offset = code - cfg->native_code;
4827
4828                         x86_patch (jump, code);
4829                         break;
4830                 }
4831
4832                 case OP_X86_LEA:
4833                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4834                         break;
4835                 case OP_X86_LEA_MEMBASE:
4836                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4837                         break;
4838                 case OP_X86_XCHG:
4839                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4840                         break;
4841                 case OP_LOCALLOC:
4842                         /* keep alignment */
4843                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4844                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4845                         code = mono_emit_stack_alloc (cfg, code, ins);
4846                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4847                         if (cfg->param_area)
4848                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4849                         break;
4850                 case OP_LOCALLOC_IMM: {
4851                         guint32 size = ins->inst_imm;
4852                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4853
4854                         if (ins->flags & MONO_INST_INIT) {
4855                                 if (size < 64) {
4856                                         int i;
4857
4858                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4859                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4860
4861                                         for (i = 0; i < size; i += 8)
4862                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4863                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4864                                 } else {
4865                                         amd64_mov_reg_imm (code, ins->dreg, size);
4866                                         ins->sreg1 = ins->dreg;
4867
4868                                         code = mono_emit_stack_alloc (cfg, code, ins);
4869                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4870                                 }
4871                         } else {
4872                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4873                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4874                         }
4875                         if (cfg->param_area)
4876                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4877                         break;
4878                 }
4879                 case OP_THROW: {
4880                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4881                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4882                                              (gpointer)"mono_arch_throw_exception", FALSE);
4883                         ins->flags |= MONO_INST_GC_CALLSITE;
4884                         ins->backend.pc_offset = code - cfg->native_code;
4885                         break;
4886                 }
4887                 case OP_RETHROW: {
4888                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4889                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4890                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4891                         ins->flags |= MONO_INST_GC_CALLSITE;
4892                         ins->backend.pc_offset = code - cfg->native_code;
4893                         break;
4894                 }
4895                 case OP_CALL_HANDLER:
4896                         /* Align stack */
4897                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4898                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4899                         amd64_call_imm (code, 0);
4900                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4901                         /* Restore stack alignment */
4902                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4903                         break;
4904                 case OP_START_HANDLER: {
4905                         /* Even though we're saving RSP, use sizeof */
4906                         /* gpointer because spvar is of type IntPtr */
4907                         /* see: mono_create_spvar_for_region */
4908                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4909                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4910
4911                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4912                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4913                                 cfg->param_area) {
4914                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4915                         }
4916                         break;
4917                 }
4918                 case OP_ENDFINALLY: {
4919                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4920                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4921                         amd64_ret (code);
4922                         break;
4923                 }
4924                 case OP_ENDFILTER: {
4925                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4926                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4927                         /* The local allocator will put the result into RAX */
4928                         amd64_ret (code);
4929                         break;
4930                 }
4931                 case OP_GET_EX_OBJ:
4932                         if (ins->dreg != AMD64_RAX)
4933                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4934                         break;
4935                 case OP_LABEL:
4936                         ins->inst_c0 = code - cfg->native_code;
4937                         break;
4938                 case OP_BR:
4939                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4940                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4941                         //break;
4942                                 if (ins->inst_target_bb->native_offset) {
4943                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4944                                 } else {
4945                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4946                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4947                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4948                                                 x86_jump8 (code, 0);
4949                                         else
4950                                                 x86_jump32 (code, 0);
4951                         }
4952                         break;
4953                 case OP_BR_REG:
4954                         amd64_jump_reg (code, ins->sreg1);
4955                         break;
4956                 case OP_ICNEQ:
4957                 case OP_ICGE:
4958                 case OP_ICLE:
4959                 case OP_ICGE_UN:
4960                 case OP_ICLE_UN:
4961
4962                 case OP_CEQ:
4963                 case OP_LCEQ:
4964                 case OP_ICEQ:
4965                 case OP_CLT:
4966                 case OP_LCLT:
4967                 case OP_ICLT:
4968                 case OP_CGT:
4969                 case OP_ICGT:
4970                 case OP_LCGT:
4971                 case OP_CLT_UN:
4972                 case OP_LCLT_UN:
4973                 case OP_ICLT_UN:
4974                 case OP_CGT_UN:
4975                 case OP_LCGT_UN:
4976                 case OP_ICGT_UN:
4977                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4978                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4979                         break;
4980                 case OP_COND_EXC_EQ:
4981                 case OP_COND_EXC_NE_UN:
4982                 case OP_COND_EXC_LT:
4983                 case OP_COND_EXC_LT_UN:
4984                 case OP_COND_EXC_GT:
4985                 case OP_COND_EXC_GT_UN:
4986                 case OP_COND_EXC_GE:
4987                 case OP_COND_EXC_GE_UN:
4988                 case OP_COND_EXC_LE:
4989                 case OP_COND_EXC_LE_UN:
4990                 case OP_COND_EXC_IEQ:
4991                 case OP_COND_EXC_INE_UN:
4992                 case OP_COND_EXC_ILT:
4993                 case OP_COND_EXC_ILT_UN:
4994                 case OP_COND_EXC_IGT:
4995                 case OP_COND_EXC_IGT_UN:
4996                 case OP_COND_EXC_IGE:
4997                 case OP_COND_EXC_IGE_UN:
4998                 case OP_COND_EXC_ILE:
4999                 case OP_COND_EXC_ILE_UN:
5000                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5001                         break;
5002                 case OP_COND_EXC_OV:
5003                 case OP_COND_EXC_NO:
5004                 case OP_COND_EXC_C:
5005                 case OP_COND_EXC_NC:
5006                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5007                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5008                         break;
5009                 case OP_COND_EXC_IOV:
5010                 case OP_COND_EXC_INO:
5011                 case OP_COND_EXC_IC:
5012                 case OP_COND_EXC_INC:
5013                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5014                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5015                         break;
5016
5017                 /* floating point opcodes */
5018                 case OP_R8CONST: {
5019                         double d = *(double *)ins->inst_p0;
5020
5021                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5022                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5023                         }
5024                         else {
5025                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5026                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5027                         }
5028                         break;
5029                 }
5030                 case OP_R4CONST: {
5031                         float f = *(float *)ins->inst_p0;
5032
5033                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5034                                 if (cfg->r4fp)
5035                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5036                                 else
5037                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5038                         }
5039                         else {
5040                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5041                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5042                                 if (!cfg->r4fp)
5043                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5044                         }
5045                         break;
5046                 }
5047                 case OP_STORER8_MEMBASE_REG:
5048                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5049                         break;
5050                 case OP_LOADR8_MEMBASE:
5051                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5052                         break;
5053                 case OP_STORER4_MEMBASE_REG:
5054                         if (cfg->r4fp) {
5055                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5056                         } else {
5057                                 /* This requires a double->single conversion */
5058                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5059                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5060                         }
5061                         break;
5062                 case OP_LOADR4_MEMBASE:
5063                         if (cfg->r4fp) {
5064                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5065                         } else {
5066                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5067                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5068                         }
5069                         break;
5070                 case OP_ICONV_TO_R4:
5071                         if (cfg->r4fp) {
5072                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5073                         } else {
5074                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5075                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5076                         }
5077                         break;
5078                 case OP_ICONV_TO_R8:
5079                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5080                         break;
5081                 case OP_LCONV_TO_R4:
5082                         if (cfg->r4fp) {
5083                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5084                         } else {
5085                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5086                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5087                         }
5088                         break;
5089                 case OP_LCONV_TO_R8:
5090                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5091                         break;
5092                 case OP_FCONV_TO_R4:
5093                         if (cfg->r4fp) {
5094                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5095                         } else {
5096                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5097                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5098                         }
5099                         break;
5100                 case OP_FCONV_TO_I1:
5101                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5102                         break;
5103                 case OP_FCONV_TO_U1:
5104                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5105                         break;
5106                 case OP_FCONV_TO_I2:
5107                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5108                         break;
5109                 case OP_FCONV_TO_U2:
5110                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5111                         break;
5112                 case OP_FCONV_TO_U4:
5113                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5114                         break;
5115                 case OP_FCONV_TO_I4:
5116                 case OP_FCONV_TO_I:
5117                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5118                         break;
5119                 case OP_FCONV_TO_I8:
5120                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5121                         break;
5122
5123                 case OP_RCONV_TO_I1:
5124                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5125                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5126                         break;
5127                 case OP_RCONV_TO_U1:
5128                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5129                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5130                         break;
5131                 case OP_RCONV_TO_I2:
5132                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5133                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5134                         break;
5135                 case OP_RCONV_TO_U2:
5136                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5137                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5138                         break;
5139                 case OP_RCONV_TO_I4:
5140                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5141                         break;
5142                 case OP_RCONV_TO_U4:
5143                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5144                         break;
5145                 case OP_RCONV_TO_I8:
5146                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5147                         break;
5148                 case OP_RCONV_TO_R8:
5149                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5150                         break;
5151                 case OP_RCONV_TO_R4:
5152                         if (ins->dreg != ins->sreg1)
5153                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5154                         break;
5155
5156                 case OP_LCONV_TO_R_UN: {
5157                         guint8 *br [2];
5158
5159                         /* Based on gcc code */
5160                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5161                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5162
5163                         /* Positive case */
5164                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5165                         br [1] = code; x86_jump8 (code, 0);
5166                         amd64_patch (br [0], code);
5167
5168                         /* Negative case */
5169                         /* Save to the red zone */
5170                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5171                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5172                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5173                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5174                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5175                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5176                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5177                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5178                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5179                         /* Restore */
5180                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5181                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5182                         amd64_patch (br [1], code);
5183                         break;
5184                 }
5185                 case OP_LCONV_TO_OVF_U4:
5186                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5187                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5188                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5189                         break;
5190                 case OP_LCONV_TO_OVF_I4_UN:
5191                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5192                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5193                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5194                         break;
5195                 case OP_FMOVE:
5196                         if (ins->dreg != ins->sreg1)
5197                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5198                         break;
5199                 case OP_RMOVE:
5200                         if (ins->dreg != ins->sreg1)
5201                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5202                         break;
5203                 case OP_MOVE_F_TO_I4:
5204                         if (cfg->r4fp) {
5205                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5206                         } else {
5207                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5208                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5209                         }
5210                         break;
5211                 case OP_MOVE_I4_TO_F:
5212                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5213                         if (!cfg->r4fp)
5214                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5215                         break;
5216                 case OP_MOVE_F_TO_I8:
5217                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5218                         break;
5219                 case OP_MOVE_I8_TO_F:
5220                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5221                         break;
5222                 case OP_FADD:
5223                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5224                         break;
5225                 case OP_FSUB:
5226                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5227                         break;
5228                 case OP_FMUL:
5229                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5230                         break;
5231                 case OP_FDIV:
5232                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5233                         break;
5234                 case OP_FNEG: {
5235                         static double r8_0 = -0.0;
5236
5237                         g_assert (ins->sreg1 == ins->dreg);
5238
5239                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5240                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5241                         break;
5242                 }
5243                 case OP_SIN:
5244                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5245                         break;
5246                 case OP_COS:
5247                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5248                         break;
5249                 case OP_ABS: {
5250                         static guint64 d = 0x7fffffffffffffffUL;
5251
5252                         g_assert (ins->sreg1 == ins->dreg);
5253
5254                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5255                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5256                         break;
5257                 }
5258                 case OP_SQRT:
5259                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5260                         break;
5261
5262                 case OP_RADD:
5263                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5264                         break;
5265                 case OP_RSUB:
5266                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5267                         break;
5268                 case OP_RMUL:
5269                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5270                         break;
5271                 case OP_RDIV:
5272                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5273                         break;
5274                 case OP_RNEG: {
5275                         static float r4_0 = -0.0;
5276
5277                         g_assert (ins->sreg1 == ins->dreg);
5278
5279                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5280                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5281                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5282                         break;
5283                 }
5284
5285                 case OP_IMIN:
5286                         g_assert (cfg->opt & MONO_OPT_CMOV);
5287                         g_assert (ins->dreg == ins->sreg1);
5288                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5289                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5290                         break;
5291                 case OP_IMIN_UN:
5292                         g_assert (cfg->opt & MONO_OPT_CMOV);
5293                         g_assert (ins->dreg == ins->sreg1);
5294                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5295                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5296                         break;
5297                 case OP_IMAX:
5298                         g_assert (cfg->opt & MONO_OPT_CMOV);
5299                         g_assert (ins->dreg == ins->sreg1);
5300                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5301                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5302                         break;
5303                 case OP_IMAX_UN:
5304                         g_assert (cfg->opt & MONO_OPT_CMOV);
5305                         g_assert (ins->dreg == ins->sreg1);
5306                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5307                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5308                         break;
5309                 case OP_LMIN:
5310                         g_assert (cfg->opt & MONO_OPT_CMOV);
5311                         g_assert (ins->dreg == ins->sreg1);
5312                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5313                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5314                         break;
5315                 case OP_LMIN_UN:
5316                         g_assert (cfg->opt & MONO_OPT_CMOV);
5317                         g_assert (ins->dreg == ins->sreg1);
5318                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5319                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5320                         break;
5321                 case OP_LMAX:
5322                         g_assert (cfg->opt & MONO_OPT_CMOV);
5323                         g_assert (ins->dreg == ins->sreg1);
5324                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5325                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5326                         break;
5327                 case OP_LMAX_UN:
5328                         g_assert (cfg->opt & MONO_OPT_CMOV);
5329                         g_assert (ins->dreg == ins->sreg1);
5330                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5331                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5332                         break;
5333                 case OP_X86_FPOP:
5334                         break;
5335                 case OP_FCOMPARE:
5336                         /*
5337                          * The two arguments are swapped because the fbranch instructions
5338                          * depend on this for the non-sse case to work.
5339                          */
5340                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5341                         break;
5342                 case OP_RCOMPARE:
5343                         /*
5344                          * FIXME: Get rid of this.
5345                          * The two arguments are swapped because the fbranch instructions
5346                          * depend on this for the non-sse case to work.
5347                          */
5348                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5349                         break;
5350                 case OP_FCNEQ:
5351                 case OP_FCEQ: {
5352                         /* zeroing the register at the start results in
5353                          * shorter and faster code (we can also remove the widening op)
5354                          */
5355                         guchar *unordered_check;
5356
5357                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5358                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5359                         unordered_check = code;
5360                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5361
5362                         if (ins->opcode == OP_FCEQ) {
5363                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5364                                 amd64_patch (unordered_check, code);
5365                         } else {
5366                                 guchar *jump_to_end;
5367                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5368                                 jump_to_end = code;
5369                                 x86_jump8 (code, 0);
5370                                 amd64_patch (unordered_check, code);
5371                                 amd64_inc_reg (code, ins->dreg);
5372                                 amd64_patch (jump_to_end, code);
5373                         }
5374                         break;
5375                 }
5376                 case OP_FCLT:
5377                 case OP_FCLT_UN: {
5378                         /* zeroing the register at the start results in
5379                          * shorter and faster code (we can also remove the widening op)
5380                          */
5381                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5382                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5383                         if (ins->opcode == OP_FCLT_UN) {
5384                                 guchar *unordered_check = code;
5385                                 guchar *jump_to_end;
5386                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5387                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5388                                 jump_to_end = code;
5389                                 x86_jump8 (code, 0);
5390                                 amd64_patch (unordered_check, code);
5391                                 amd64_inc_reg (code, ins->dreg);
5392                                 amd64_patch (jump_to_end, code);
5393                         } else {
5394                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5395                         }
5396                         break;
5397                 }
5398                 case OP_FCLE: {
5399                         guchar *unordered_check;
5400                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5401                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5402                         unordered_check = code;
5403                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5404                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5405                         amd64_patch (unordered_check, code);
5406                         break;
5407                 }
5408                 case OP_FCGT:
5409                 case OP_FCGT_UN: {
5410                         /* zeroing the register at the start results in
5411                          * shorter and faster code (we can also remove the widening op)
5412                          */
5413                         guchar *unordered_check;
5414
5415                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5416                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5417                         if (ins->opcode == OP_FCGT) {
5418                                 unordered_check = code;
5419                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5420                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5421                                 amd64_patch (unordered_check, code);
5422                         } else {
5423                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5424                         }
5425                         break;
5426                 }
5427                 case OP_FCGE: {
5428                         guchar *unordered_check;
5429                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5430                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5431                         unordered_check = code;
5432                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5433                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5434                         amd64_patch (unordered_check, code);
5435                         break;
5436                 }
5437
5438                 case OP_RCEQ:
5439                 case OP_RCGT:
5440                 case OP_RCLT:
5441                 case OP_RCLT_UN:
5442                 case OP_RCGT_UN: {
5443                         int x86_cond;
5444                         gboolean unordered = FALSE;
5445
5446                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5447                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5448
5449                         switch (ins->opcode) {
5450                         case OP_RCEQ:
5451                                 x86_cond = X86_CC_EQ;
5452                                 break;
5453                         case OP_RCGT:
5454                                 x86_cond = X86_CC_LT;
5455                                 break;
5456                         case OP_RCLT:
5457                                 x86_cond = X86_CC_GT;
5458                                 break;
5459                         case OP_RCLT_UN:
5460                                 x86_cond = X86_CC_GT;
5461                                 unordered = TRUE;
5462                                 break;
5463                         case OP_RCGT_UN:
5464                                 x86_cond = X86_CC_LT;
5465                                 unordered = TRUE;
5466                                 break;
5467                         default:
5468                                 g_assert_not_reached ();
5469                                 break;
5470                         }
5471
5472                         if (unordered) {
5473                                 guchar *unordered_check;
5474                                 guchar *jump_to_end;
5475
5476                                 unordered_check = code;
5477                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5478                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5479                                 jump_to_end = code;
5480                                 x86_jump8 (code, 0);
5481                                 amd64_patch (unordered_check, code);
5482                                 amd64_inc_reg (code, ins->dreg);
5483                                 amd64_patch (jump_to_end, code);
5484                         } else {
5485                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5486                         }
5487                         break;
5488                 }
5489                 case OP_FCLT_MEMBASE:
5490                 case OP_FCGT_MEMBASE:
5491                 case OP_FCLT_UN_MEMBASE:
5492                 case OP_FCGT_UN_MEMBASE:
5493                 case OP_FCEQ_MEMBASE: {
5494                         guchar *unordered_check, *jump_to_end;
5495                         int x86_cond;
5496
5497                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5498                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5499
5500                         switch (ins->opcode) {
5501                         case OP_FCEQ_MEMBASE:
5502                                 x86_cond = X86_CC_EQ;
5503                                 break;
5504                         case OP_FCLT_MEMBASE:
5505                         case OP_FCLT_UN_MEMBASE:
5506                                 x86_cond = X86_CC_LT;
5507                                 break;
5508                         case OP_FCGT_MEMBASE:
5509                         case OP_FCGT_UN_MEMBASE:
5510                                 x86_cond = X86_CC_GT;
5511                                 break;
5512                         default:
5513                                 g_assert_not_reached ();
5514                         }
5515
5516                         unordered_check = code;
5517                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5518                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5519
5520                         switch (ins->opcode) {
5521                         case OP_FCEQ_MEMBASE:
5522                         case OP_FCLT_MEMBASE:
5523                         case OP_FCGT_MEMBASE:
5524                                 amd64_patch (unordered_check, code);
5525                                 break;
5526                         case OP_FCLT_UN_MEMBASE:
5527                         case OP_FCGT_UN_MEMBASE:
5528                                 jump_to_end = code;
5529                                 x86_jump8 (code, 0);
5530                                 amd64_patch (unordered_check, code);
5531                                 amd64_inc_reg (code, ins->dreg);
5532                                 amd64_patch (jump_to_end, code);
5533                                 break;
5534                         default:
5535                                 break;
5536                         }
5537                         break;
5538                 }
5539                 case OP_FBEQ: {
5540                         guchar *jump = code;
5541                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5542                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5543                         amd64_patch (jump, code);
5544                         break;
5545                 }
5546                 case OP_FBNE_UN:
5547                         /* Branch if C013 != 100 */
5548                         /* branch if !ZF or (PF|CF) */
5549                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5550                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5551                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5552                         break;
5553                 case OP_FBLT:
5554                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5555                         break;
5556                 case OP_FBLT_UN:
5557                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5558                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5559                         break;
5560                 case OP_FBGT:
5561                 case OP_FBGT_UN:
5562                         if (ins->opcode == OP_FBGT) {
5563                                 guchar *br1;
5564
5565                                 /* skip branch if C1=1 */
5566                                 br1 = code;
5567                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5568                                 /* branch if (C0 | C3) = 1 */
5569                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5570                                 amd64_patch (br1, code);
5571                                 break;
5572                         } else {
5573                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5574                         }
5575                         break;
5576                 case OP_FBGE: {
5577                         /* Branch if C013 == 100 or 001 */
5578                         guchar *br1;
5579
5580                         /* skip branch if C1=1 */
5581                         br1 = code;
5582                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5583                         /* branch if (C0 | C3) = 1 */
5584                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5585                         amd64_patch (br1, code);
5586                         break;
5587                 }
5588                 case OP_FBGE_UN:
5589                         /* Branch if C013 == 000 */
5590                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5591                         break;
5592                 case OP_FBLE: {
5593                         /* Branch if C013=000 or 100 */
5594                         guchar *br1;
5595
5596                         /* skip branch if C1=1 */
5597                         br1 = code;
5598                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5599                         /* branch if C0=0 */
5600                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5601                         amd64_patch (br1, code);
5602                         break;
5603                 }
5604                 case OP_FBLE_UN:
5605                         /* Branch if C013 != 001 */
5606                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5607                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5608                         break;
5609                 case OP_CKFINITE:
5610                         /* Transfer value to the fp stack */
5611                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5612                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5613                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5614
5615                         amd64_push_reg (code, AMD64_RAX);
5616                         amd64_fxam (code);
5617                         amd64_fnstsw (code);
5618                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5619                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5620                         amd64_pop_reg (code, AMD64_RAX);
5621                         amd64_fstp (code, 0);
5622                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5623                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5624                         break;
5625                 case OP_TLS_GET: {
5626                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5627                         break;
5628                 }
5629                 case OP_TLS_GET_REG:
5630                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5631                         break;
5632                 case OP_TLS_SET: {
5633                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5634                         break;
5635                 }
5636                 case OP_TLS_SET_REG: {
5637                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5638                         break;
5639                 }
5640                 case OP_MEMORY_BARRIER: {
5641                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5642                                 x86_mfence (code);
5643                         break;
5644                 }
5645                 case OP_ATOMIC_ADD_I4:
5646                 case OP_ATOMIC_ADD_I8: {
5647                         int dreg = ins->dreg;
5648                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5649
5650                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5651                                 dreg = AMD64_R11;
5652
5653                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5654                         amd64_prefix (code, X86_LOCK_PREFIX);
5655                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5656                         /* dreg contains the old value, add with sreg2 value */
5657                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5658
5659                         if (ins->dreg != dreg)
5660                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5661
5662                         break;
5663                 }
5664                 case OP_ATOMIC_EXCHANGE_I4:
5665                 case OP_ATOMIC_EXCHANGE_I8: {
5666                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5667
5668                         /* LOCK prefix is implied. */
5669                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5670                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5671                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5672                         break;
5673                 }
5674                 case OP_ATOMIC_CAS_I4:
5675                 case OP_ATOMIC_CAS_I8: {
5676                         guint32 size;
5677
5678                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5679                                 size = 8;
5680                         else
5681                                 size = 4;
5682
5683                         /*
5684                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5685                          * an explanation of how this works.
5686                          */
5687                         g_assert (ins->sreg3 == AMD64_RAX);
5688                         g_assert (ins->sreg1 != AMD64_RAX);
5689                         g_assert (ins->sreg1 != ins->sreg2);
5690
5691                         amd64_prefix (code, X86_LOCK_PREFIX);
5692                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5693
5694                         if (ins->dreg != AMD64_RAX)
5695                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5696                         break;
5697                 }
5698                 case OP_ATOMIC_LOAD_I1: {
5699                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5700                         break;
5701                 }
5702                 case OP_ATOMIC_LOAD_U1: {
5703                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5704                         break;
5705                 }
5706                 case OP_ATOMIC_LOAD_I2: {
5707                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5708                         break;
5709                 }
5710                 case OP_ATOMIC_LOAD_U2: {
5711                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5712                         break;
5713                 }
5714                 case OP_ATOMIC_LOAD_I4: {
5715                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5716                         break;
5717                 }
5718                 case OP_ATOMIC_LOAD_U4:
5719                 case OP_ATOMIC_LOAD_I8:
5720                 case OP_ATOMIC_LOAD_U8: {
5721                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5722                         break;
5723                 }
5724                 case OP_ATOMIC_LOAD_R4: {
5725                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5726                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5727                         break;
5728                 }
5729                 case OP_ATOMIC_LOAD_R8: {
5730                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5731                         break;
5732                 }
5733                 case OP_ATOMIC_STORE_I1:
5734                 case OP_ATOMIC_STORE_U1:
5735                 case OP_ATOMIC_STORE_I2:
5736                 case OP_ATOMIC_STORE_U2:
5737                 case OP_ATOMIC_STORE_I4:
5738                 case OP_ATOMIC_STORE_U4:
5739                 case OP_ATOMIC_STORE_I8:
5740                 case OP_ATOMIC_STORE_U8: {
5741                         int size;
5742
5743                         switch (ins->opcode) {
5744                         case OP_ATOMIC_STORE_I1:
5745                         case OP_ATOMIC_STORE_U1:
5746                                 size = 1;
5747                                 break;
5748                         case OP_ATOMIC_STORE_I2:
5749                         case OP_ATOMIC_STORE_U2:
5750                                 size = 2;
5751                                 break;
5752                         case OP_ATOMIC_STORE_I4:
5753                         case OP_ATOMIC_STORE_U4:
5754                                 size = 4;
5755                                 break;
5756                         case OP_ATOMIC_STORE_I8:
5757                         case OP_ATOMIC_STORE_U8:
5758                                 size = 8;
5759                                 break;
5760                         }
5761
5762                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5763
5764                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5765                                 x86_mfence (code);
5766                         break;
5767                 }
5768                 case OP_ATOMIC_STORE_R4: {
5769                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5770                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5771
5772                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5773                                 x86_mfence (code);
5774                         break;
5775                 }
5776                 case OP_ATOMIC_STORE_R8: {
5777                         x86_nop (code);
5778                         x86_nop (code);
5779                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5780                         x86_nop (code);
5781                         x86_nop (code);
5782
5783                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5784                                 x86_mfence (code);
5785                         break;
5786                 }
5787                 case OP_CARD_TABLE_WBARRIER: {
5788                         int ptr = ins->sreg1;
5789                         int value = ins->sreg2;
5790                         guchar *br = 0;
5791                         int nursery_shift, card_table_shift;
5792                         gpointer card_table_mask;
5793                         size_t nursery_size;
5794
5795                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5796                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5797                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5798
5799                         /*If either point to the stack we can simply avoid the WB. This happens due to
5800                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5801                          */
5802                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5803                                 continue;
5804
5805                         /*
5806                          * We need one register we can clobber, we choose EDX and make sreg1
5807                          * fixed EAX to work around limitations in the local register allocator.
5808                          * sreg2 might get allocated to EDX, but that is not a problem since
5809                          * we use it before clobbering EDX.
5810                          */
5811                         g_assert (ins->sreg1 == AMD64_RAX);
5812
5813                         /*
5814                          * This is the code we produce:
5815                          *
5816                          *   edx = value
5817                          *   edx >>= nursery_shift
5818                          *   cmp edx, (nursery_start >> nursery_shift)
5819                          *   jne done
5820                          *   edx = ptr
5821                          *   edx >>= card_table_shift
5822                          *   edx += cardtable
5823                          *   [edx] = 1
5824                          * done:
5825                          */
5826
5827                         if (mono_gc_card_table_nursery_check ()) {
5828                                 if (value != AMD64_RDX)
5829                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5830                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5831                                 if (shifted_nursery_start >> 31) {
5832                                         /*
5833                                          * The value we need to compare against is 64 bits, so we need
5834                                          * another spare register.  We use RBX, which we save and
5835                                          * restore.
5836                                          */
5837                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5838                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5839                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5840                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5841                                 } else {
5842                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5843                                 }
5844                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5845                         }
5846                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5847                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5848                         if (card_table_mask)
5849                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5850
5851                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5852                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5853
5854                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5855
5856                         if (mono_gc_card_table_nursery_check ())
5857                                 x86_patch (br, code);
5858                         break;
5859                 }
5860 #ifdef MONO_ARCH_SIMD_INTRINSICS
5861                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5862                 case OP_ADDPS:
5863                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5864                         break;
5865                 case OP_DIVPS:
5866                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868                 case OP_MULPS:
5869                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5870                         break;
5871                 case OP_SUBPS:
5872                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5873                         break;
5874                 case OP_MAXPS:
5875                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5876                         break;
5877                 case OP_MINPS:
5878                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5879                         break;
5880                 case OP_COMPPS:
5881                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5882                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5883                         break;
5884                 case OP_ANDPS:
5885                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_ANDNPS:
5888                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_ORPS:
5891                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_XORPS:
5894                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5895                         break;
5896                 case OP_SQRTPS:
5897                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5898                         break;
5899                 case OP_RSQRTPS:
5900                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5901                         break;
5902                 case OP_RCPPS:
5903                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5904                         break;
5905                 case OP_ADDSUBPS:
5906                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5907                         break;
5908                 case OP_HADDPS:
5909                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5910                         break;
5911                 case OP_HSUBPS:
5912                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_DUPPS_HIGH:
5915                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5916                         break;
5917                 case OP_DUPPS_LOW:
5918                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5919                         break;
5920
5921                 case OP_PSHUFLEW_HIGH:
5922                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5923                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5924                         break;
5925                 case OP_PSHUFLEW_LOW:
5926                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5927                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5928                         break;
5929                 case OP_PSHUFLED:
5930                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5931                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5932                         break;
5933                 case OP_SHUFPS:
5934                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5935                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5936                         break;
5937                 case OP_SHUFPD:
5938                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5939                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5940                         break;
5941
5942                 case OP_ADDPD:
5943                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_DIVPD:
5946                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_MULPD:
5949                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_SUBPD:
5952                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954                 case OP_MAXPD:
5955                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5956                         break;
5957                 case OP_MINPD:
5958                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_COMPPD:
5961                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5962                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5963                         break;
5964                 case OP_ANDPD:
5965                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5966                         break;
5967                 case OP_ANDNPD:
5968                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5969                         break;
5970                 case OP_ORPD:
5971                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5972                         break;
5973                 case OP_XORPD:
5974                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5975                         break;
5976                 case OP_SQRTPD:
5977                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5978                         break;
5979                 case OP_ADDSUBPD:
5980                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_HADDPD:
5983                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_HSUBPD:
5986                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_DUPPD:
5989                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5990                         break;
5991
5992                 case OP_EXTRACT_MASK:
5993                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5994                         break;
5995
5996                 case OP_PAND:
5997                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_POR:
6000                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_PXOR:
6003                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005
6006                 case OP_PADDB:
6007                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_PADDW:
6010                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_PADDD:
6013                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_PADDQ:
6016                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018
6019                 case OP_PSUBB:
6020                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_PSUBW:
6023                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_PSUBD:
6026                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_PSUBQ:
6029                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031
6032                 case OP_PMAXB_UN:
6033                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_PMAXW_UN:
6036                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_PMAXD_UN:
6039                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041
6042                 case OP_PMAXB:
6043                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045                 case OP_PMAXW:
6046                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_PMAXD:
6049                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051
6052                 case OP_PAVGB_UN:
6053                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_PAVGW_UN:
6056                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058
6059                 case OP_PMINB_UN:
6060                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_PMINW_UN:
6063                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065                 case OP_PMIND_UN:
6066                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068
6069                 case OP_PMINB:
6070                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072                 case OP_PMINW:
6073                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075                 case OP_PMIND:
6076                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6077                         break;
6078
6079                 case OP_PCMPEQB:
6080                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PCMPEQW:
6083                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085                 case OP_PCMPEQD:
6086                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088                 case OP_PCMPEQQ:
6089                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6090                         break;
6091
6092                 case OP_PCMPGTB:
6093                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PCMPGTW:
6096                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098                 case OP_PCMPGTD:
6099                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101                 case OP_PCMPGTQ:
6102                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104
6105                 case OP_PSUM_ABS_DIFF:
6106                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108
6109                 case OP_UNPACK_LOWB:
6110                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_UNPACK_LOWW:
6113                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_UNPACK_LOWD:
6116                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_UNPACK_LOWQ:
6119                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121                 case OP_UNPACK_LOWPS:
6122                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124                 case OP_UNPACK_LOWPD:
6125                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6126                         break;
6127
6128                 case OP_UNPACK_HIGHB:
6129                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_UNPACK_HIGHW:
6132                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_UNPACK_HIGHD:
6135                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137                 case OP_UNPACK_HIGHQ:
6138                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6139                         break;
6140                 case OP_UNPACK_HIGHPS:
6141                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6142                         break;
6143                 case OP_UNPACK_HIGHPD:
6144                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6145                         break;
6146
6147                 case OP_PACKW:
6148                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6149                         break;
6150                 case OP_PACKD:
6151                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6152                         break;
6153                 case OP_PACKW_UN:
6154                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156                 case OP_PACKD_UN:
6157                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159
6160                 case OP_PADDB_SAT_UN:
6161                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6162                         break;
6163                 case OP_PSUBB_SAT_UN:
6164                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6165                         break;
6166                 case OP_PADDW_SAT_UN:
6167                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6168                         break;
6169                 case OP_PSUBW_SAT_UN:
6170                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6171                         break;
6172
6173                 case OP_PADDB_SAT:
6174                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6175                         break;
6176                 case OP_PSUBB_SAT:
6177                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179                 case OP_PADDW_SAT:
6180                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6181                         break;
6182                 case OP_PSUBW_SAT:
6183                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6184                         break;
6185
6186                 case OP_PMULW:
6187                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_PMULD:
6190                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192                 case OP_PMULQ:
6193                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6194                         break;
6195                 case OP_PMULW_HIGH_UN:
6196                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198                 case OP_PMULW_HIGH:
6199                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201
6202                 case OP_PSHRW:
6203                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6204                         break;
6205                 case OP_PSHRW_REG:
6206                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6207                         break;
6208
6209                 case OP_PSARW:
6210                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6211                         break;
6212                 case OP_PSARW_REG:
6213                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6214                         break;
6215
6216                 case OP_PSHLW:
6217                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6218                         break;
6219                 case OP_PSHLW_REG:
6220                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6221                         break;
6222
6223                 case OP_PSHRD:
6224                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6225                         break;
6226                 case OP_PSHRD_REG:
6227                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6228                         break;
6229
6230                 case OP_PSARD:
6231                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6232                         break;
6233                 case OP_PSARD_REG:
6234                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6235                         break;
6236
6237                 case OP_PSHLD:
6238                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6239                         break;
6240                 case OP_PSHLD_REG:
6241                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6242                         break;
6243
6244                 case OP_PSHRQ:
6245                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6246                         break;
6247                 case OP_PSHRQ_REG:
6248                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6249                         break;
6250
6251                 /*TODO: This is appart of the sse spec but not added
6252                 case OP_PSARQ:
6253                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6254                         break;
6255                 case OP_PSARQ_REG:
6256                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6257                         break;
6258                 */
6259
6260                 case OP_PSHLQ:
6261                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6262                         break;
6263                 case OP_PSHLQ_REG:
6264                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6265                         break;
6266                 case OP_CVTDQ2PD:
6267                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6268                         break;
6269                 case OP_CVTDQ2PS:
6270                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6271                         break;
6272                 case OP_CVTPD2DQ:
6273                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6274                         break;
6275                 case OP_CVTPD2PS:
6276                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6277                         break;
6278                 case OP_CVTPS2DQ:
6279                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6280                         break;
6281                 case OP_CVTPS2PD:
6282                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6283                         break;
6284                 case OP_CVTTPD2DQ:
6285                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6286                         break;
6287                 case OP_CVTTPS2DQ:
6288                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6289                         break;
6290
6291                 case OP_ICONV_TO_X:
6292                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6293                         break;
6294                 case OP_EXTRACT_I4:
6295                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6296                         break;
6297                 case OP_EXTRACT_I8:
6298                         if (ins->inst_c0) {
6299                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6300                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6301                         } else {
6302                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6303                         }
6304                         break;
6305                 case OP_EXTRACT_I1:
6306                 case OP_EXTRACT_U1:
6307                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6308                         if (ins->inst_c0)
6309                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6310                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6311                         break;
6312                 case OP_EXTRACT_I2:
6313                 case OP_EXTRACT_U2:
6314                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6315                         if (ins->inst_c0)
6316                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6317                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6318                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6319                         break;
6320                 case OP_EXTRACT_R8:
6321                         if (ins->inst_c0)
6322                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6323                         else
6324                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6325                         break;
6326                 case OP_INSERT_I2:
6327                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6328                         break;
6329                 case OP_EXTRACTX_U2:
6330                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6331                         break;
6332                 case OP_INSERTX_U1_SLOW:
6333                         /*sreg1 is the extracted ireg (scratch)
6334                         /sreg2 is the to be inserted ireg (scratch)
6335                         /dreg is the xreg to receive the value*/
6336
6337                         /*clear the bits from the extracted word*/
6338                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6339                         /*shift the value to insert if needed*/
6340                         if (ins->inst_c0 & 1)
6341                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6342                         /*join them together*/
6343                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6344                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6345                         break;
6346                 case OP_INSERTX_I4_SLOW:
6347                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6348                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6349                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6350                         break;
6351                 case OP_INSERTX_I8_SLOW:
6352                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6353                         if (ins->inst_c0)
6354                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6355                         else
6356                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6357                         break;
6358
6359                 case OP_INSERTX_R4_SLOW:
6360                         switch (ins->inst_c0) {
6361                         case 0:
6362                                 if (cfg->r4fp)
6363                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6364                                 else
6365                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6366                                 break;
6367                         case 1:
6368                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6369                                 if (cfg->r4fp)
6370                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6371                                 else
6372                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6373                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6374                                 break;
6375                         case 2:
6376                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6377                                 if (cfg->r4fp)
6378                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6379                                 else
6380                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6381                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6382                                 break;
6383                         case 3:
6384                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6385                                 if (cfg->r4fp)
6386                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6387                                 else
6388                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6389                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6390                                 break;
6391                         }
6392                         break;
6393                 case OP_INSERTX_R8_SLOW:
6394                         if (ins->inst_c0)
6395                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6396                         else
6397                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6398                         break;
6399                 case OP_STOREX_MEMBASE_REG:
6400                 case OP_STOREX_MEMBASE:
6401                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6402                         break;
6403                 case OP_LOADX_MEMBASE:
6404                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6405                         break;
6406                 case OP_LOADX_ALIGNED_MEMBASE:
6407                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6408                         break;
6409                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6410                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6411                         break;
6412                 case OP_STOREX_NTA_MEMBASE_REG:
6413                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6414                         break;
6415                 case OP_PREFETCH_MEMBASE:
6416                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6417                         break;
6418
6419                 case OP_XMOVE:
6420                         /*FIXME the peephole pass should have killed this*/
6421                         if (ins->dreg != ins->sreg1)
6422                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6423                         break;
6424                 case OP_XZERO:
6425                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6426                         break;
6427                 case OP_ICONV_TO_R4_RAW:
6428                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6429                         break;
6430
6431                 case OP_FCONV_TO_R8_X:
6432                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6433                         break;
6434
6435                 case OP_XCONV_R8_TO_I4:
6436                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6437                         switch (ins->backend.source_opcode) {
6438                         case OP_FCONV_TO_I1:
6439                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6440                                 break;
6441                         case OP_FCONV_TO_U1:
6442                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6443                                 break;
6444                         case OP_FCONV_TO_I2:
6445                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6446                                 break;
6447                         case OP_FCONV_TO_U2:
6448                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6449                                 break;
6450                         }
6451                         break;
6452
6453                 case OP_EXPAND_I2:
6454                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6455                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6456                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6457                         break;
6458                 case OP_EXPAND_I4:
6459                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6460                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6461                         break;
6462                 case OP_EXPAND_I8:
6463                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6464                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6465                         break;
6466                 case OP_EXPAND_R4:
6467                         if (cfg->r4fp) {
6468                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6469                         } else {
6470                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6471                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6472                         }
6473                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6474                         break;
6475                 case OP_EXPAND_R8:
6476                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6477                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6478                         break;
6479 #endif
6480                 case OP_LIVERANGE_START: {
6481                         if (cfg->verbose_level > 1)
6482                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6483                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6484                         break;
6485                 }
6486                 case OP_LIVERANGE_END: {
6487                         if (cfg->verbose_level > 1)
6488                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6489                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6490                         break;
6491                 }
6492                 case OP_GC_SAFE_POINT: {
6493                         guint8 *br [1];
6494
6495                         g_assert (mono_threads_is_coop_enabled ());
6496
6497                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6498                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6499                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6500                         amd64_patch (br[0], code);
6501                         break;
6502                 }
6503
6504                 case OP_GC_LIVENESS_DEF:
6505                 case OP_GC_LIVENESS_USE:
6506                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6507                         ins->backend.pc_offset = code - cfg->native_code;
6508                         break;
6509                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6510                         ins->backend.pc_offset = code - cfg->native_code;
6511                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6512                         break;
6513                 default:
6514                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6515                         g_assert_not_reached ();
6516                 }
6517
6518                 if ((code - cfg->native_code - offset) > max_len) {
6519                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6520                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6521                         g_assert_not_reached ();
6522                 }
6523         }
6524
6525         cfg->code_len = code - cfg->native_code;
6526 }
6527
6528 #endif /* DISABLE_JIT */
6529
6530 void
6531 mono_arch_register_lowlevel_calls (void)
6532 {
6533         /* The signature doesn't matter */
6534         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6535 }
6536
6537 void
6538 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6539 {
6540         unsigned char *ip = ji->ip.i + code;
6541
6542         /*
6543          * Debug code to help track down problems where the target of a near call is
6544          * is not valid.
6545          */
6546         if (amd64_is_near_call (ip)) {
6547                 gint64 disp = (guint8*)target - (guint8*)ip;
6548
6549                 if (!amd64_is_imm32 (disp)) {
6550                         printf ("TYPE: %d\n", ji->type);
6551                         switch (ji->type) {
6552                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6553                                 printf ("V: %s\n", ji->data.name);
6554                                 break;
6555                         case MONO_PATCH_INFO_METHOD_JUMP:
6556                         case MONO_PATCH_INFO_METHOD:
6557                                 printf ("V: %s\n", ji->data.method->name);
6558                                 break;
6559                         default:
6560                                 break;
6561                         }
6562                 }
6563         }
6564
6565         amd64_patch (ip, (gpointer)target);
6566 }
6567
6568 #ifndef DISABLE_JIT
6569
6570 static int
6571 get_max_epilog_size (MonoCompile *cfg)
6572 {
6573         int max_epilog_size = 16;
6574
6575         if (cfg->method->save_lmf)
6576                 max_epilog_size += 256;
6577
6578         if (mono_jit_trace_calls != NULL)
6579                 max_epilog_size += 50;
6580
6581         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6582                 max_epilog_size += 50;
6583
6584         max_epilog_size += (AMD64_NREG * 2);
6585
6586         return max_epilog_size;
6587 }
6588
6589 /*
6590  * This macro is used for testing whenever the unwinder works correctly at every point
6591  * where an async exception can happen.
6592  */
6593 /* This will generate a SIGSEGV at the given point in the code */
6594 #define async_exc_point(code) do { \
6595     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6596          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6597              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6598          cfg->arch.async_point_count ++; \
6599     } \
6600 } while (0)
6601
6602 guint8 *
6603 mono_arch_emit_prolog (MonoCompile *cfg)
6604 {
6605         MonoMethod *method = cfg->method;
6606         MonoBasicBlock *bb;
6607         MonoMethodSignature *sig;
6608         MonoInst *ins;
6609         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6610         guint8 *code;
6611         CallInfo *cinfo;
6612         MonoInst *lmf_var = cfg->lmf_var;
6613         gboolean args_clobbered = FALSE;
6614         gboolean trace = FALSE;
6615
6616         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6617
6618         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6619
6620         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6621                 trace = TRUE;
6622
6623         /* Amount of stack space allocated by register saving code */
6624         pos = 0;
6625
6626         /* Offset between RSP and the CFA */
6627         cfa_offset = 0;
6628
6629         /*
6630          * The prolog consists of the following parts:
6631          * FP present:
6632          * - push rbp, mov rbp, rsp
6633          * - save callee saved regs using pushes
6634          * - allocate frame
6635          * - save rgctx if needed
6636          * - save lmf if needed
6637          * FP not present:
6638          * - allocate frame
6639          * - save rgctx if needed
6640          * - save lmf if needed
6641          * - save callee saved regs using moves
6642          */
6643
6644         // CFA = sp + 8
6645         cfa_offset = 8;
6646         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6647         // IP saved at CFA - 8
6648         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6649         async_exc_point (code);
6650         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6651
6652         if (!cfg->arch.omit_fp) {
6653                 amd64_push_reg (code, AMD64_RBP);
6654                 cfa_offset += 8;
6655                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6656                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6657                 async_exc_point (code);
6658 #ifdef TARGET_WIN32
6659                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6660 #endif
6661                 /* These are handled automatically by the stack marking code */
6662                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6663
6664                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6665                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6666                 async_exc_point (code);
6667 #ifdef TARGET_WIN32
6668                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6669 #endif
6670         }
6671
6672         /* The param area is always at offset 0 from sp */
6673         /* This needs to be allocated here, since it has to come after the spill area */
6674         if (cfg->param_area) {
6675                 if (cfg->arch.omit_fp)
6676                         // FIXME:
6677                         g_assert_not_reached ();
6678                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6679         }
6680
6681         if (cfg->arch.omit_fp) {
6682                 /*
6683                  * On enter, the stack is misaligned by the pushing of the return
6684                  * address. It is either made aligned by the pushing of %rbp, or by
6685                  * this.
6686                  */
6687                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6688                 if ((alloc_size % 16) == 0) {
6689                         alloc_size += 8;
6690                         /* Mark the padding slot as NOREF */
6691                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6692                 }
6693         } else {
6694                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6695                 if (cfg->stack_offset != alloc_size) {
6696                         /* Mark the padding slot as NOREF */
6697                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6698                 }
6699                 cfg->arch.sp_fp_offset = alloc_size;
6700                 alloc_size -= pos;
6701         }
6702
6703         cfg->arch.stack_alloc_size = alloc_size;
6704
6705         /* Allocate stack frame */
6706         if (alloc_size) {
6707                 /* See mono_emit_stack_alloc */
6708 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6709                 guint32 remaining_size = alloc_size;
6710                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6711                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6712                 guint32 offset = code - cfg->native_code;
6713                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6714                         while (required_code_size >= (cfg->code_size - offset))
6715                                 cfg->code_size *= 2;
6716                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6717                         code = cfg->native_code + offset;
6718                         cfg->stat_code_reallocs++;
6719                 }
6720
6721                 while (remaining_size >= 0x1000) {
6722                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6723                         if (cfg->arch.omit_fp) {
6724                                 cfa_offset += 0x1000;
6725                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6726                         }
6727                         async_exc_point (code);
6728 #ifdef TARGET_WIN32
6729                         if (cfg->arch.omit_fp)
6730                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6731 #endif
6732
6733                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6734                         remaining_size -= 0x1000;
6735                 }
6736                 if (remaining_size) {
6737                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6738                         if (cfg->arch.omit_fp) {
6739                                 cfa_offset += remaining_size;
6740                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6741                                 async_exc_point (code);
6742                         }
6743 #ifdef TARGET_WIN32
6744                         if (cfg->arch.omit_fp)
6745                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6746 #endif
6747                 }
6748 #else
6749                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6750                 if (cfg->arch.omit_fp) {
6751                         cfa_offset += alloc_size;
6752                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6753                         async_exc_point (code);
6754                 }
6755 #endif
6756         }
6757
6758         /* Stack alignment check */
6759 #if 0
6760         {
6761                 guint8 *buf;
6762
6763                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6764                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6765                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6766                 buf = code;
6767                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6768                 amd64_breakpoint (code);
6769                 amd64_patch (buf, code);
6770         }
6771 #endif
6772
6773         if (mini_get_debug_options ()->init_stacks) {
6774                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6775
6776                 /* Save registers to the red zone */
6777                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6778                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6779
6780                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6781                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6782                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6783
6784                 amd64_cld (code);
6785                 amd64_prefix (code, X86_REP_PREFIX);
6786                 amd64_stosl (code);
6787
6788                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6789                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6790         }
6791
6792         /* Save LMF */
6793         if (method->save_lmf)
6794                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6795
6796         /* Save callee saved registers */
6797         if (cfg->arch.omit_fp) {
6798                 save_area_offset = cfg->arch.reg_save_area_offset;
6799                 /* Save caller saved registers after sp is adjusted */
6800                 /* The registers are saved at the bottom of the frame */
6801                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6802         } else {
6803                 /* The registers are saved just below the saved rbp */
6804                 save_area_offset = cfg->arch.reg_save_area_offset;
6805         }
6806
6807         for (i = 0; i < AMD64_NREG; ++i) {
6808                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6809                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6810
6811                         if (cfg->arch.omit_fp) {
6812                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6813                                 /* These are handled automatically by the stack marking code */
6814                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6815                         } else {
6816                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6817                                 // FIXME: GC
6818                         }
6819
6820                         save_area_offset += 8;
6821                         async_exc_point (code);
6822                 }
6823         }
6824
6825         /* store runtime generic context */
6826         if (cfg->rgctx_var) {
6827                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6828                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6829
6830                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6831
6832                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6833                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6834         }
6835
6836         /* compute max_length in order to use short forward jumps */
6837         max_epilog_size = get_max_epilog_size (cfg);
6838         if (cfg->opt & MONO_OPT_BRANCH) {
6839                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6840                         MonoInst *ins;
6841                         int max_length = 0;
6842
6843                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6844                                 max_length += 6;
6845                         /* max alignment for loops */
6846                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6847                                 max_length += LOOP_ALIGNMENT;
6848
6849                         MONO_BB_FOR_EACH_INS (bb, ins) {
6850                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6851                         }
6852
6853                         /* Take prolog and epilog instrumentation into account */
6854                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6855                                 max_length += max_epilog_size;
6856
6857                         bb->max_length = max_length;
6858                 }
6859         }
6860
6861         sig = mono_method_signature (method);
6862         pos = 0;
6863
6864         cinfo = (CallInfo *)cfg->arch.cinfo;
6865
6866         if (sig->ret->type != MONO_TYPE_VOID) {
6867                 /* Save volatile arguments to the stack */
6868                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6869                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6870         }
6871
6872         /* Keep this in sync with emit_load_volatile_arguments */
6873         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6874                 ArgInfo *ainfo = cinfo->args + i;
6875
6876                 ins = cfg->args [i];
6877
6878                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6879                         /* Unused arguments */
6880                         continue;
6881
6882                 /* Save volatile arguments to the stack */
6883                 if (ins->opcode != OP_REGVAR) {
6884                         switch (ainfo->storage) {
6885                         case ArgInIReg: {
6886                                 guint32 size = 8;
6887
6888                                 /* FIXME: I1 etc */
6889                                 /*
6890                                 if (stack_offset & 0x1)
6891                                         size = 1;
6892                                 else if (stack_offset & 0x2)
6893                                         size = 2;
6894                                 else if (stack_offset & 0x4)
6895                                         size = 4;
6896                                 else
6897                                         size = 8;
6898                                 */
6899                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6900
6901                                 /*
6902                                  * Save the original location of 'this',
6903                                  * get_generic_info_from_stack_frame () needs this to properly look up
6904                                  * the argument value during the handling of async exceptions.
6905                                  */
6906                                 if (ins == cfg->args [0]) {
6907                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6908                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6909                                 }
6910                                 break;
6911                         }
6912                         case ArgInFloatSSEReg:
6913                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6914                                 break;
6915                         case ArgInDoubleSSEReg:
6916                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6917                                 break;
6918                         case ArgValuetypeInReg:
6919                                 for (quad = 0; quad < 2; quad ++) {
6920                                         switch (ainfo->pair_storage [quad]) {
6921                                         case ArgInIReg:
6922                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6923                                                 break;
6924                                         case ArgInFloatSSEReg:
6925                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6926                                                 break;
6927                                         case ArgInDoubleSSEReg:
6928                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6929                                                 break;
6930                                         case ArgNone:
6931                                                 break;
6932                                         default:
6933                                                 g_assert_not_reached ();
6934                                         }
6935                                 }
6936                                 break;
6937                         case ArgValuetypeAddrInIReg:
6938                                 if (ainfo->pair_storage [0] == ArgInIReg)
6939                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6940                                 break;
6941                         case ArgGSharedVtInReg:
6942                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6943                                 break;
6944                         default:
6945                                 break;
6946                         }
6947                 } else {
6948                         /* Argument allocated to (non-volatile) register */
6949                         switch (ainfo->storage) {
6950                         case ArgInIReg:
6951                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6952                                 break;
6953                         case ArgOnStack:
6954                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6955                                 break;
6956                         default:
6957                                 g_assert_not_reached ();
6958                         }
6959
6960                         if (ins == cfg->args [0]) {
6961                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6962                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6963                         }
6964                 }
6965         }
6966
6967         if (cfg->method->save_lmf)
6968                 args_clobbered = TRUE;
6969
6970         if (trace) {
6971                 args_clobbered = TRUE;
6972                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6973         }
6974
6975         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6976                 args_clobbered = TRUE;
6977
6978         /*
6979          * Optimize the common case of the first bblock making a call with the same
6980          * arguments as the method. This works because the arguments are still in their
6981          * original argument registers.
6982          * FIXME: Generalize this
6983          */
6984         if (!args_clobbered) {
6985                 MonoBasicBlock *first_bb = cfg->bb_entry;
6986                 MonoInst *next;
6987                 int filter = FILTER_IL_SEQ_POINT;
6988
6989                 next = mono_bb_first_inst (first_bb, filter);
6990                 if (!next && first_bb->next_bb) {
6991                         first_bb = first_bb->next_bb;
6992                         next = mono_bb_first_inst (first_bb, filter);
6993                 }
6994
6995                 if (first_bb->in_count > 1)
6996                         next = NULL;
6997
6998                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6999                         ArgInfo *ainfo = cinfo->args + i;
7000                         gboolean match = FALSE;
7001
7002                         ins = cfg->args [i];
7003                         if (ins->opcode != OP_REGVAR) {
7004                                 switch (ainfo->storage) {
7005                                 case ArgInIReg: {
7006                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7007                                                 if (next->dreg == ainfo->reg) {
7008                                                         NULLIFY_INS (next);
7009                                                         match = TRUE;
7010                                                 } else {
7011                                                         next->opcode = OP_MOVE;
7012                                                         next->sreg1 = ainfo->reg;
7013                                                         /* Only continue if the instruction doesn't change argument regs */
7014                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7015                                                                 match = TRUE;
7016                                                 }
7017                                         }
7018                                         break;
7019                                 }
7020                                 default:
7021                                         break;
7022                                 }
7023                         } else {
7024                                 /* Argument allocated to (non-volatile) register */
7025                                 switch (ainfo->storage) {
7026                                 case ArgInIReg:
7027                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7028                                                 NULLIFY_INS (next);
7029                                                 match = TRUE;
7030                                         }
7031                                         break;
7032                                 default:
7033                                         break;
7034                                 }
7035                         }
7036
7037                         if (match) {
7038                                 next = mono_inst_next (next, filter);
7039                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7040                                 if (!next)
7041                                         break;
7042                         }
7043                 }
7044         }
7045
7046         if (cfg->gen_sdb_seq_points) {
7047                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7048
7049                 /* Initialize seq_point_info_var */
7050                 if (cfg->compile_aot) {
7051                         /* Initialize the variable from a GOT slot */
7052                         /* Same as OP_AOTCONST */
7053                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7054                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7055                         g_assert (info_var->opcode == OP_REGOFFSET);
7056                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7057                 }
7058
7059                 if (cfg->compile_aot) {
7060                         /* Initialize ss_tramp_var */
7061                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7062                         g_assert (ins->opcode == OP_REGOFFSET);
7063
7064                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7065                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7066                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7067                 } else {
7068                         /* Initialize ss_tramp_var */
7069                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7070                         g_assert (ins->opcode == OP_REGOFFSET);
7071
7072                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7073                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7074
7075                         /* Initialize bp_tramp_var */
7076                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7077                         g_assert (ins->opcode == OP_REGOFFSET);
7078
7079                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7080                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7081                 }
7082         }
7083
7084         cfg->code_len = code - cfg->native_code;
7085
7086         g_assert (cfg->code_len < cfg->code_size);
7087
7088         return code;
7089 }
7090
7091 void
7092 mono_arch_emit_epilog (MonoCompile *cfg)
7093 {
7094         MonoMethod *method = cfg->method;
7095         int quad, i;
7096         guint8 *code;
7097         int max_epilog_size;
7098         CallInfo *cinfo;
7099         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7100         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7101
7102         max_epilog_size = get_max_epilog_size (cfg);
7103
7104         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7105                 cfg->code_size *= 2;
7106                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7107                 cfg->stat_code_reallocs++;
7108         }
7109         code = cfg->native_code + cfg->code_len;
7110
7111         cfg->has_unwind_info_for_epilog = TRUE;
7112
7113         /* Mark the start of the epilog */
7114         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7115
7116         /* Save the uwind state which is needed by the out-of-line code */
7117         mono_emit_unwind_op_remember_state (cfg, code);
7118
7119         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7120                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7121
7122         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7123
7124         if (method->save_lmf) {
7125                 /* check if we need to restore protection of the stack after a stack overflow */
7126                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7127                         guint8 *patch;
7128                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7129                         /* we load the value in a separate instruction: this mechanism may be
7130                          * used later as a safer way to do thread interruption
7131                          */
7132                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7133                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7134                         patch = code;
7135                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7136                         /* note that the call trampoline will preserve eax/edx */
7137                         x86_call_reg (code, X86_ECX);
7138                         x86_patch (patch, code);
7139                 } else {
7140                         /* FIXME: maybe save the jit tls in the prolog */
7141                 }
7142                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7143                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7144                 }
7145         }
7146
7147         /* Restore callee saved regs */
7148         for (i = 0; i < AMD64_NREG; ++i) {
7149                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7150                         /* Restore only used_int_regs, not arch.saved_iregs */
7151 #if defined(MONO_SUPPORT_TASKLETS)
7152                         int restore_reg=1;
7153 #else
7154                         int restore_reg=(cfg->used_int_regs & (1 << i));
7155 #endif
7156                         if (restore_reg) {
7157                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7158                                 mono_emit_unwind_op_same_value (cfg, code, i);
7159                                 async_exc_point (code);
7160                         }
7161                         save_area_offset += 8;
7162                 }
7163         }
7164
7165         /* Load returned vtypes into registers if needed */
7166         cinfo = (CallInfo *)cfg->arch.cinfo;
7167         if (cinfo->ret.storage == ArgValuetypeInReg) {
7168                 ArgInfo *ainfo = &cinfo->ret;
7169                 MonoInst *inst = cfg->ret;
7170
7171                 for (quad = 0; quad < 2; quad ++) {
7172                         switch (ainfo->pair_storage [quad]) {
7173                         case ArgInIReg:
7174                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7175                                 break;
7176                         case ArgInFloatSSEReg:
7177                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7178                                 break;
7179                         case ArgInDoubleSSEReg:
7180                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7181                                 break;
7182                         case ArgNone:
7183                                 break;
7184                         default:
7185                                 g_assert_not_reached ();
7186                         }
7187                 }
7188         }
7189
7190         if (cfg->arch.omit_fp) {
7191                 if (cfg->arch.stack_alloc_size) {
7192                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7193                 }
7194         } else {
7195                 amd64_leave (code);
7196                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7197         }
7198         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7199         async_exc_point (code);
7200         amd64_ret (code);
7201
7202         /* Restore the unwind state to be the same as before the epilog */
7203         mono_emit_unwind_op_restore_state (cfg, code);
7204
7205         cfg->code_len = code - cfg->native_code;
7206
7207         g_assert (cfg->code_len < cfg->code_size);
7208 }
7209
7210 void
7211 mono_arch_emit_exceptions (MonoCompile *cfg)
7212 {
7213         MonoJumpInfo *patch_info;
7214         int nthrows, i;
7215         guint8 *code;
7216         MonoClass *exc_classes [16];
7217         guint8 *exc_throw_start [16], *exc_throw_end [16];
7218         guint32 code_size = 0;
7219
7220         /* Compute needed space */
7221         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7222                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7223                         code_size += 40;
7224                 if (patch_info->type == MONO_PATCH_INFO_R8)
7225                         code_size += 8 + 15; /* sizeof (double) + alignment */
7226                 if (patch_info->type == MONO_PATCH_INFO_R4)
7227                         code_size += 4 + 15; /* sizeof (float) + alignment */
7228                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7229                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7230         }
7231
7232         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7233                 cfg->code_size *= 2;
7234                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7235                 cfg->stat_code_reallocs++;
7236         }
7237
7238         code = cfg->native_code + cfg->code_len;
7239
7240         /* add code to raise exceptions */
7241         nthrows = 0;
7242         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7243                 switch (patch_info->type) {
7244                 case MONO_PATCH_INFO_EXC: {
7245                         MonoClass *exc_class;
7246                         guint8 *buf, *buf2;
7247                         guint32 throw_ip;
7248
7249                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7250
7251                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7252                         throw_ip = patch_info->ip.i;
7253
7254                         //x86_breakpoint (code);
7255                         /* Find a throw sequence for the same exception class */
7256                         for (i = 0; i < nthrows; ++i)
7257                                 if (exc_classes [i] == exc_class)
7258                                         break;
7259                         if (i < nthrows) {
7260                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7261                                 x86_jump_code (code, exc_throw_start [i]);
7262                                 patch_info->type = MONO_PATCH_INFO_NONE;
7263                         }
7264                         else {
7265                                 buf = code;
7266                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7267                                 buf2 = code;
7268
7269                                 if (nthrows < 16) {
7270                                         exc_classes [nthrows] = exc_class;
7271                                         exc_throw_start [nthrows] = code;
7272                                 }
7273                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7274
7275                                 patch_info->type = MONO_PATCH_INFO_NONE;
7276
7277                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7278
7279                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7280                                 while (buf < buf2)
7281                                         x86_nop (buf);
7282
7283                                 if (nthrows < 16) {
7284                                         exc_throw_end [nthrows] = code;
7285                                         nthrows ++;
7286                                 }
7287                         }
7288                         break;
7289                 }
7290                 default:
7291                         /* do nothing */
7292                         break;
7293                 }
7294                 g_assert(code < cfg->native_code + cfg->code_size);
7295         }
7296
7297         /* Handle relocations with RIP relative addressing */
7298         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7299                 gboolean remove = FALSE;
7300                 guint8 *orig_code = code;
7301
7302                 switch (patch_info->type) {
7303                 case MONO_PATCH_INFO_R8:
7304                 case MONO_PATCH_INFO_R4: {
7305                         guint8 *pos, *patch_pos;
7306                         guint32 target_pos;
7307
7308                         /* The SSE opcodes require a 16 byte alignment */
7309                         code = (guint8*)ALIGN_TO (code, 16);
7310
7311                         pos = cfg->native_code + patch_info->ip.i;
7312                         if (IS_REX (pos [1])) {
7313                                 patch_pos = pos + 5;
7314                                 target_pos = code - pos - 9;
7315                         }
7316                         else {
7317                                 patch_pos = pos + 4;
7318                                 target_pos = code - pos - 8;
7319                         }
7320
7321                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7322                                 *(double*)code = *(double*)patch_info->data.target;
7323                                 code += sizeof (double);
7324                         } else {
7325                                 *(float*)code = *(float*)patch_info->data.target;
7326                                 code += sizeof (float);
7327                         }
7328
7329                         *(guint32*)(patch_pos) = target_pos;
7330
7331                         remove = TRUE;
7332                         break;
7333                 }
7334                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7335                         guint8 *pos;
7336
7337                         if (cfg->compile_aot)
7338                                 continue;
7339
7340                         /*loading is faster against aligned addresses.*/
7341                         code = (guint8*)ALIGN_TO (code, 8);
7342                         memset (orig_code, 0, code - orig_code);
7343
7344                         pos = cfg->native_code + patch_info->ip.i;
7345
7346                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7347                         if (IS_REX (pos [1]))
7348                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7349                         else
7350                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7351
7352                         *(gpointer*)code = (gpointer)patch_info->data.target;
7353                         code += sizeof (gpointer);
7354
7355                         remove = TRUE;
7356                         break;
7357                 }
7358                 default:
7359                         break;
7360                 }
7361
7362                 if (remove) {
7363                         if (patch_info == cfg->patch_info)
7364                                 cfg->patch_info = patch_info->next;
7365                         else {
7366                                 MonoJumpInfo *tmp;
7367
7368                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7369                                         ;
7370                                 tmp->next = patch_info->next;
7371                         }
7372                 }
7373                 g_assert (code < cfg->native_code + cfg->code_size);
7374         }
7375
7376         cfg->code_len = code - cfg->native_code;
7377
7378         g_assert (cfg->code_len < cfg->code_size);
7379
7380 }
7381
7382 #endif /* DISABLE_JIT */
7383
7384 void*
7385 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7386 {
7387         guchar *code = (guchar *)p;
7388         MonoMethodSignature *sig;
7389         MonoInst *inst;
7390         int i, n, stack_area = 0;
7391
7392         /* Keep this in sync with mono_arch_get_argument_info */
7393
7394         if (enable_arguments) {
7395                 /* Allocate a new area on the stack and save arguments there */
7396                 sig = mono_method_signature (cfg->method);
7397
7398                 n = sig->param_count + sig->hasthis;
7399
7400                 stack_area = ALIGN_TO (n * 8, 16);
7401
7402                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7403
7404                 for (i = 0; i < n; ++i) {
7405                         inst = cfg->args [i];
7406
7407                         if (inst->opcode == OP_REGVAR)
7408                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7409                         else {
7410                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7411                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7412                         }
7413                 }
7414         }
7415
7416         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7417         amd64_set_reg_template (code, AMD64_ARG_REG1);
7418         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7419         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7420
7421         if (enable_arguments)
7422                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7423
7424         return code;
7425 }
7426
7427 enum {
7428         SAVE_NONE,
7429         SAVE_STRUCT,
7430         SAVE_EAX,
7431         SAVE_EAX_EDX,
7432         SAVE_XMM
7433 };
7434
7435 void*
7436 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7437 {
7438         guchar *code = (guchar *)p;
7439         int save_mode = SAVE_NONE;
7440         MonoMethod *method = cfg->method;
7441         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7442         int i;
7443
7444         switch (ret_type->type) {
7445         case MONO_TYPE_VOID:
7446                 /* special case string .ctor icall */
7447                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7448                         save_mode = SAVE_EAX;
7449                 else
7450                         save_mode = SAVE_NONE;
7451                 break;
7452         case MONO_TYPE_I8:
7453         case MONO_TYPE_U8:
7454                 save_mode = SAVE_EAX;
7455                 break;
7456         case MONO_TYPE_R4:
7457         case MONO_TYPE_R8:
7458                 save_mode = SAVE_XMM;
7459                 break;
7460         case MONO_TYPE_GENERICINST:
7461                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7462                         save_mode = SAVE_EAX;
7463                         break;
7464                 }
7465                 /* Fall through */
7466         case MONO_TYPE_VALUETYPE:
7467                 save_mode = SAVE_STRUCT;
7468                 break;
7469         default:
7470                 save_mode = SAVE_EAX;
7471                 break;
7472         }
7473
7474         /* Save the result and copy it into the proper argument register */
7475         switch (save_mode) {
7476         case SAVE_EAX:
7477                 amd64_push_reg (code, AMD64_RAX);
7478                 /* Align stack */
7479                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7480                 if (enable_arguments)
7481                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7482                 break;
7483         case SAVE_STRUCT:
7484                 /* FIXME: */
7485                 if (enable_arguments)
7486                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7487                 break;
7488         case SAVE_XMM:
7489                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7490                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7491                 /* Align stack */
7492                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7493                 /*
7494                  * The result is already in the proper argument register so no copying
7495                  * needed.
7496                  */
7497                 break;
7498         case SAVE_NONE:
7499                 break;
7500         default:
7501                 g_assert_not_reached ();
7502         }
7503
7504         /* Set %al since this is a varargs call */
7505         if (save_mode == SAVE_XMM)
7506                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7507         else
7508                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7509
7510         if (preserve_argument_registers) {
7511                 for (i = 0; i < PARAM_REGS; ++i)
7512                         amd64_push_reg (code, param_regs [i]);
7513         }
7514
7515         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7516         amd64_set_reg_template (code, AMD64_ARG_REG1);
7517         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7518
7519         if (preserve_argument_registers) {
7520                 for (i = PARAM_REGS - 1; i >= 0; --i)
7521                         amd64_pop_reg (code, param_regs [i]);
7522         }
7523
7524         /* Restore result */
7525         switch (save_mode) {
7526         case SAVE_EAX:
7527                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7528                 amd64_pop_reg (code, AMD64_RAX);
7529                 break;
7530         case SAVE_STRUCT:
7531                 /* FIXME: */
7532                 break;
7533         case SAVE_XMM:
7534                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7535                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7536                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7537                 break;
7538         case SAVE_NONE:
7539                 break;
7540         default:
7541                 g_assert_not_reached ();
7542         }
7543
7544         return code;
7545 }
7546
7547 void
7548 mono_arch_flush_icache (guint8 *code, gint size)
7549 {
7550         /* Not needed */
7551 }
7552
7553 void
7554 mono_arch_flush_register_windows (void)
7555 {
7556 }
7557
7558 gboolean
7559 mono_arch_is_inst_imm (gint64 imm)
7560 {
7561         return amd64_use_imm32 (imm);
7562 }
7563
7564 /*
7565  * Determine whenever the trap whose info is in SIGINFO is caused by
7566  * integer overflow.
7567  */
7568 gboolean
7569 mono_arch_is_int_overflow (void *sigctx, void *info)
7570 {
7571         MonoContext ctx;
7572         guint8* rip;
7573         int reg;
7574         gint64 value;
7575
7576         mono_sigctx_to_monoctx (sigctx, &ctx);
7577
7578         rip = (guint8*)ctx.gregs [AMD64_RIP];
7579
7580         if (IS_REX (rip [0])) {
7581                 reg = amd64_rex_b (rip [0]);
7582                 rip ++;
7583         }
7584         else
7585                 reg = 0;
7586
7587         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7588                 /* idiv REG */
7589                 reg += x86_modrm_rm (rip [1]);
7590
7591                 value = ctx.gregs [reg];
7592
7593                 if (value == -1)
7594                         return TRUE;
7595         }
7596
7597         return FALSE;
7598 }
7599
7600 guint32
7601 mono_arch_get_patch_offset (guint8 *code)
7602 {
7603         return 3;
7604 }
7605
7606 /**
7607  * mono_breakpoint_clean_code:
7608  *
7609  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7610  * breakpoints in the original code, they are removed in the copy.
7611  *
7612  * Returns TRUE if no sw breakpoint was present.
7613  */
7614 gboolean
7615 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7616 {
7617         /*
7618          * If method_start is non-NULL we need to perform bound checks, since we access memory
7619          * at code - offset we could go before the start of the method and end up in a different
7620          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7621          * instead.
7622          */
7623         if (!method_start || code - offset >= method_start) {
7624                 memcpy (buf, code - offset, size);
7625         } else {
7626                 int diff = code - method_start;
7627                 memset (buf, 0, size);
7628                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7629         }
7630         return TRUE;
7631 }
7632
7633 int
7634 mono_arch_get_this_arg_reg (guint8 *code)
7635 {
7636         return AMD64_ARG_REG1;
7637 }
7638
7639 gpointer
7640 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7641 {
7642         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7643 }
7644
7645 #define MAX_ARCH_DELEGATE_PARAMS 10
7646
7647 static gpointer
7648 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7649 {
7650         guint8 *code, *start;
7651         GSList *unwind_ops = NULL;
7652         int i;
7653
7654         unwind_ops = mono_arch_get_cie_program ();
7655
7656         if (has_target) {
7657                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7658
7659                 /* Replace the this argument with the target */
7660                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7661                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7662                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7663
7664                 g_assert ((code - start) < 64);
7665         } else {
7666                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7667
7668                 if (param_count == 0) {
7669                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7670                 } else {
7671                         /* We have to shift the arguments left */
7672                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7673                         for (i = 0; i < param_count; ++i) {
7674 #ifdef TARGET_WIN32
7675                                 if (i < 3)
7676                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7677                                 else
7678                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7679 #else
7680                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7681 #endif
7682                         }
7683
7684                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7685                 }
7686                 g_assert ((code - start) < 64);
7687         }
7688
7689         mono_arch_flush_icache (start, code - start);
7690
7691         if (has_target) {
7692                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7693         } else {
7694                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7695                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7696                 g_free (name);
7697         }
7698
7699         if (mono_jit_map_is_enabled ()) {
7700                 char *buff;
7701                 if (has_target)
7702                         buff = (char*)"delegate_invoke_has_target";
7703                 else
7704                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7705                 mono_emit_jit_tramp (start, code - start, buff);
7706                 if (!has_target)
7707                         g_free (buff);
7708         }
7709         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7710
7711         return start;
7712 }
7713
7714 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7715
7716 static gpointer
7717 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7718 {
7719         guint8 *code, *start;
7720         int size = 20;
7721         char *tramp_name;
7722         GSList *unwind_ops;
7723
7724         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7725                 return NULL;
7726
7727         start = code = (guint8 *)mono_global_codeman_reserve (size);
7728
7729         unwind_ops = mono_arch_get_cie_program ();
7730
7731         /* Replace the this argument with the target */
7732         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7733         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7734
7735         if (load_imt_reg) {
7736                 /* Load the IMT reg */
7737                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7738         }
7739
7740         /* Load the vtable */
7741         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7742         amd64_jump_membase (code, AMD64_RAX, offset);
7743         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7744
7745         if (load_imt_reg)
7746                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7747         else
7748                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7749         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7750         g_free (tramp_name);
7751
7752         return start;
7753 }
7754
7755 /*
7756  * mono_arch_get_delegate_invoke_impls:
7757  *
7758  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7759  * trampolines.
7760  */
7761 GSList*
7762 mono_arch_get_delegate_invoke_impls (void)
7763 {
7764         GSList *res = NULL;
7765         MonoTrampInfo *info;
7766         int i;
7767
7768         get_delegate_invoke_impl (&info, TRUE, 0);
7769         res = g_slist_prepend (res, info);
7770
7771         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7772                 get_delegate_invoke_impl (&info, FALSE, i);
7773                 res = g_slist_prepend (res, info);
7774         }
7775
7776         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7777                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7778                 res = g_slist_prepend (res, info);
7779
7780                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7781                 res = g_slist_prepend (res, info);
7782         }
7783
7784         return res;
7785 }
7786
7787 gpointer
7788 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7789 {
7790         guint8 *code, *start;
7791         int i;
7792
7793         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7794                 return NULL;
7795
7796         /* FIXME: Support more cases */
7797         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7798                 return NULL;
7799
7800         if (has_target) {
7801                 static guint8* cached = NULL;
7802
7803                 if (cached)
7804                         return cached;
7805
7806                 if (mono_aot_only) {
7807                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7808                 } else {
7809                         MonoTrampInfo *info;
7810                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7811                         mono_tramp_info_register (info, NULL);
7812                 }
7813
7814                 mono_memory_barrier ();
7815
7816                 cached = start;
7817         } else {
7818                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7819                 for (i = 0; i < sig->param_count; ++i)
7820                         if (!mono_is_regsize_var (sig->params [i]))
7821                                 return NULL;
7822                 if (sig->param_count > 4)
7823                         return NULL;
7824
7825                 code = cache [sig->param_count];
7826                 if (code)
7827                         return code;
7828
7829                 if (mono_aot_only) {
7830                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7831                         start = (guint8 *)mono_aot_get_trampoline (name);
7832                         g_free (name);
7833                 } else {
7834                         MonoTrampInfo *info;
7835                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7836                         mono_tramp_info_register (info, NULL);
7837                 }
7838
7839                 mono_memory_barrier ();
7840
7841                 cache [sig->param_count] = start;
7842         }
7843
7844         return start;
7845 }
7846
7847 gpointer
7848 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7849 {
7850         MonoTrampInfo *info;
7851         gpointer code;
7852
7853         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7854         if (code)
7855                 mono_tramp_info_register (info, NULL);
7856         return code;
7857 }
7858
7859 void
7860 mono_arch_finish_init (void)
7861 {
7862 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7863         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7864 #endif
7865 }
7866
7867 void
7868 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7869 {
7870 }
7871
7872 #define CMP_SIZE (6 + 1)
7873 #define CMP_REG_REG_SIZE (4 + 1)
7874 #define BR_SMALL_SIZE 2
7875 #define BR_LARGE_SIZE 6
7876 #define MOV_REG_IMM_SIZE 10
7877 #define MOV_REG_IMM_32BIT_SIZE 6
7878 #define JUMP_REG_SIZE (2 + 1)
7879
7880 static int
7881 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7882 {
7883         int i, distance = 0;
7884         for (i = start; i < target; ++i)
7885                 distance += imt_entries [i]->chunk_size;
7886         return distance;
7887 }
7888
7889 /*
7890  * LOCKING: called with the domain lock held
7891  */
7892 gpointer
7893 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7894         gpointer fail_tramp)
7895 {
7896         int i;
7897         int size = 0;
7898         guint8 *code, *start;
7899         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7900         GSList *unwind_ops;
7901
7902         for (i = 0; i < count; ++i) {
7903                 MonoIMTCheckItem *item = imt_entries [i];
7904                 if (item->is_equals) {
7905                         if (item->check_target_idx) {
7906                                 if (!item->compare_done) {
7907                                         if (amd64_use_imm32 ((gint64)item->key))
7908                                                 item->chunk_size += CMP_SIZE;
7909                                         else
7910                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7911                                 }
7912                                 if (item->has_target_code) {
7913                                         item->chunk_size += MOV_REG_IMM_SIZE;
7914                                 } else {
7915                                         if (vtable_is_32bit)
7916                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7917                                         else
7918                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7919                                 }
7920                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7921                         } else {
7922                                 if (fail_tramp) {
7923                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7924                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7925                                 } else {
7926                                         if (vtable_is_32bit)
7927                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7928                                         else
7929                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7930                                         item->chunk_size += JUMP_REG_SIZE;
7931                                         /* with assert below:
7932                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7933                                          */
7934                                 }
7935                         }
7936                 } else {
7937                         if (amd64_use_imm32 ((gint64)item->key))
7938                                 item->chunk_size += CMP_SIZE;
7939                         else
7940                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7941                         item->chunk_size += BR_LARGE_SIZE;
7942                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7943                 }
7944                 size += item->chunk_size;
7945         }
7946         if (fail_tramp)
7947                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
7948         else
7949                 code = (guint8 *)mono_domain_code_reserve (domain, size);
7950         start = code;
7951
7952         unwind_ops = mono_arch_get_cie_program ();
7953
7954         for (i = 0; i < count; ++i) {
7955                 MonoIMTCheckItem *item = imt_entries [i];
7956                 item->code_target = code;
7957                 if (item->is_equals) {
7958                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7959
7960                         if (item->check_target_idx || fail_case) {
7961                                 if (!item->compare_done || fail_case) {
7962                                         if (amd64_use_imm32 ((gint64)item->key))
7963                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7964                                         else {
7965                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7966                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7967                                         }
7968                                 }
7969                                 item->jmp_code = code;
7970                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7971                                 if (item->has_target_code) {
7972                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7973                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7974                                 } else {
7975                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7976                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7977                                 }
7978
7979                                 if (fail_case) {
7980                                         amd64_patch (item->jmp_code, code);
7981                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7982                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7983                                         item->jmp_code = NULL;
7984                                 }
7985                         } else {
7986                                 /* enable the commented code to assert on wrong method */
7987 #if 0
7988                                 if (amd64_is_imm32 (item->key))
7989                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7990                                 else {
7991                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7992                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7993                                 }
7994                                 item->jmp_code = code;
7995                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7996                                 /* See the comment below about R10 */
7997                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7998                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7999                                 amd64_patch (item->jmp_code, code);
8000                                 amd64_breakpoint (code);
8001                                 item->jmp_code = NULL;
8002 #else
8003                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8004                                    needs to be preserved.  R10 needs
8005                                    to be preserved for calls which
8006                                    require a runtime generic context,
8007                                    but interface calls don't. */
8008                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8009                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8010 #endif
8011                         }
8012                 } else {
8013                         if (amd64_use_imm32 ((gint64)item->key))
8014                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8015                         else {
8016                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8017                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8018                         }
8019                         item->jmp_code = code;
8020                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8021                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8022                         else
8023                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8024                 }
8025                 g_assert (code - item->code_target <= item->chunk_size);
8026         }
8027         /* patch the branches to get to the target items */
8028         for (i = 0; i < count; ++i) {
8029                 MonoIMTCheckItem *item = imt_entries [i];
8030                 if (item->jmp_code) {
8031                         if (item->check_target_idx) {
8032                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8033                         }
8034                 }
8035         }
8036
8037         if (!fail_tramp)
8038                 mono_stats.imt_thunks_size += code - start;
8039         g_assert (code - start <= size);
8040
8041         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8042
8043         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8044
8045         return start;
8046 }
8047
8048 MonoMethod*
8049 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8050 {
8051         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8052 }
8053
8054 MonoVTable*
8055 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8056 {
8057         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8058 }
8059
8060 GSList*
8061 mono_arch_get_cie_program (void)
8062 {
8063         GSList *l = NULL;
8064
8065         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8066         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8067
8068         return l;
8069 }
8070
8071 #ifndef DISABLE_JIT
8072
8073 MonoInst*
8074 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8075 {
8076         MonoInst *ins = NULL;
8077         int opcode = 0;
8078
8079         if (cmethod->klass == mono_defaults.math_class) {
8080                 if (strcmp (cmethod->name, "Sin") == 0) {
8081                         opcode = OP_SIN;
8082                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8083                         opcode = OP_COS;
8084                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8085                         opcode = OP_SQRT;
8086                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8087                         opcode = OP_ABS;
8088                 }
8089
8090                 if (opcode && fsig->param_count == 1) {
8091                         MONO_INST_NEW (cfg, ins, opcode);
8092                         ins->type = STACK_R8;
8093                         ins->dreg = mono_alloc_freg (cfg);
8094                         ins->sreg1 = args [0]->dreg;
8095                         MONO_ADD_INS (cfg->cbb, ins);
8096                 }
8097
8098                 opcode = 0;
8099                 if (cfg->opt & MONO_OPT_CMOV) {
8100                         if (strcmp (cmethod->name, "Min") == 0) {
8101                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8102                                         opcode = OP_IMIN;
8103                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8104                                         opcode = OP_IMIN_UN;
8105                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8106                                         opcode = OP_LMIN;
8107                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8108                                         opcode = OP_LMIN_UN;
8109                         } else if (strcmp (cmethod->name, "Max") == 0) {
8110                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8111                                         opcode = OP_IMAX;
8112                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8113                                         opcode = OP_IMAX_UN;
8114                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8115                                         opcode = OP_LMAX;
8116                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8117                                         opcode = OP_LMAX_UN;
8118                         }
8119                 }
8120
8121                 if (opcode && fsig->param_count == 2) {
8122                         MONO_INST_NEW (cfg, ins, opcode);
8123                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8124                         ins->dreg = mono_alloc_ireg (cfg);
8125                         ins->sreg1 = args [0]->dreg;
8126                         ins->sreg2 = args [1]->dreg;
8127                         MONO_ADD_INS (cfg->cbb, ins);
8128                 }
8129
8130 #if 0
8131                 /* OP_FREM is not IEEE compatible */
8132                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8133                         MONO_INST_NEW (cfg, ins, OP_FREM);
8134                         ins->inst_i0 = args [0];
8135                         ins->inst_i1 = args [1];
8136                 }
8137 #endif
8138         }
8139
8140         return ins;
8141 }
8142 #endif
8143
8144 gboolean
8145 mono_arch_print_tree (MonoInst *tree, int arity)
8146 {
8147         return 0;
8148 }
8149
8150 mgreg_t
8151 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8152 {
8153         return ctx->gregs [reg];
8154 }
8155
8156 void
8157 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8158 {
8159         ctx->gregs [reg] = val;
8160 }
8161
8162 gpointer
8163 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8164 {
8165         gpointer *sp, old_value;
8166         char *bp;
8167
8168         /*Load the spvar*/
8169         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8170         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8171
8172         old_value = *sp;
8173         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8174                 return old_value;
8175
8176         *sp = new_value;
8177
8178         return old_value;
8179 }
8180
8181 /*
8182  * mono_arch_emit_load_aotconst:
8183  *
8184  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8185  * TARGET from the mscorlib GOT in full-aot code.
8186  * On AMD64, the result is placed into R11.
8187  */
8188 guint8*
8189 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8190 {
8191         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8192         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8193
8194         return code;
8195 }
8196
8197 /*
8198  * mono_arch_get_trampolines:
8199  *
8200  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8201  * for AOT.
8202  */
8203 GSList *
8204 mono_arch_get_trampolines (gboolean aot)
8205 {
8206         return mono_amd64_get_exception_trampolines (aot);
8207 }
8208
8209 /* Soft Debug support */
8210 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8211
8212 /*
8213  * mono_arch_set_breakpoint:
8214  *
8215  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8216  * The location should contain code emitted by OP_SEQ_POINT.
8217  */
8218 void
8219 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8220 {
8221         guint8 *code = ip;
8222
8223         if (ji->from_aot) {
8224                 guint32 native_offset = ip - (guint8*)ji->code_start;
8225                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8226
8227                 g_assert (info->bp_addrs [native_offset] == 0);
8228                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8229         } else {
8230                 /* ip points to a mov r11, 0 */
8231                 g_assert (code [0] == 0x41);
8232                 g_assert (code [1] == 0xbb);
8233                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8234         }
8235 }
8236
8237 /*
8238  * mono_arch_clear_breakpoint:
8239  *
8240  *   Clear the breakpoint at IP.
8241  */
8242 void
8243 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8244 {
8245         guint8 *code = ip;
8246
8247         if (ji->from_aot) {
8248                 guint32 native_offset = ip - (guint8*)ji->code_start;
8249                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8250
8251                 info->bp_addrs [native_offset] = NULL;
8252         } else {
8253                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8254         }
8255 }
8256
8257 gboolean
8258 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8259 {
8260         /* We use soft breakpoints on amd64 */
8261         return FALSE;
8262 }
8263
8264 /*
8265  * mono_arch_skip_breakpoint:
8266  *
8267  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8268  * we resume, the instruction is not executed again.
8269  */
8270 void
8271 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8272 {
8273         g_assert_not_reached ();
8274 }
8275
8276 /*
8277  * mono_arch_start_single_stepping:
8278  *
8279  *   Start single stepping.
8280  */
8281 void
8282 mono_arch_start_single_stepping (void)
8283 {
8284         ss_trampoline = mini_get_single_step_trampoline ();
8285 }
8286
8287 /*
8288  * mono_arch_stop_single_stepping:
8289  *
8290  *   Stop single stepping.
8291  */
8292 void
8293 mono_arch_stop_single_stepping (void)
8294 {
8295         ss_trampoline = NULL;
8296 }
8297
8298 /*
8299  * mono_arch_is_single_step_event:
8300  *
8301  *   Return whenever the machine state in SIGCTX corresponds to a single
8302  * step event.
8303  */
8304 gboolean
8305 mono_arch_is_single_step_event (void *info, void *sigctx)
8306 {
8307         /* We use soft breakpoints on amd64 */
8308         return FALSE;
8309 }
8310
8311 /*
8312  * mono_arch_skip_single_step:
8313  *
8314  *   Modify CTX so the ip is placed after the single step trigger instruction,
8315  * we resume, the instruction is not executed again.
8316  */
8317 void
8318 mono_arch_skip_single_step (MonoContext *ctx)
8319 {
8320         g_assert_not_reached ();
8321 }
8322
8323 /*
8324  * mono_arch_create_seq_point_info:
8325  *
8326  *   Return a pointer to a data structure which is used by the sequence
8327  * point implementation in AOTed code.
8328  */
8329 gpointer
8330 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8331 {
8332         SeqPointInfo *info;
8333         MonoJitInfo *ji;
8334
8335         // FIXME: Add a free function
8336
8337         mono_domain_lock (domain);
8338         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8339                                                                 code);
8340         mono_domain_unlock (domain);
8341
8342         if (!info) {
8343                 ji = mono_jit_info_table_find (domain, (char*)code);
8344                 g_assert (ji);
8345
8346                 // FIXME: Optimize the size
8347                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8348
8349                 info->ss_tramp_addr = &ss_trampoline;
8350
8351                 mono_domain_lock (domain);
8352                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8353                                                          code, info);
8354                 mono_domain_unlock (domain);
8355         }
8356
8357         return info;
8358 }
8359
8360 void
8361 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8362 {
8363         ext->lmf.previous_lmf = prev_lmf;
8364         /* Mark that this is a MonoLMFExt */
8365         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8366         ext->lmf.rsp = (gssize)ext;
8367 }
8368
8369 #endif
8370
8371 gboolean
8372 mono_arch_opcode_supported (int opcode)
8373 {
8374         switch (opcode) {
8375         case OP_ATOMIC_ADD_I4:
8376         case OP_ATOMIC_ADD_I8:
8377         case OP_ATOMIC_EXCHANGE_I4:
8378         case OP_ATOMIC_EXCHANGE_I8:
8379         case OP_ATOMIC_CAS_I4:
8380         case OP_ATOMIC_CAS_I8:
8381         case OP_ATOMIC_LOAD_I1:
8382         case OP_ATOMIC_LOAD_I2:
8383         case OP_ATOMIC_LOAD_I4:
8384         case OP_ATOMIC_LOAD_I8:
8385         case OP_ATOMIC_LOAD_U1:
8386         case OP_ATOMIC_LOAD_U2:
8387         case OP_ATOMIC_LOAD_U4:
8388         case OP_ATOMIC_LOAD_U8:
8389         case OP_ATOMIC_LOAD_R4:
8390         case OP_ATOMIC_LOAD_R8:
8391         case OP_ATOMIC_STORE_I1:
8392         case OP_ATOMIC_STORE_I2:
8393         case OP_ATOMIC_STORE_I4:
8394         case OP_ATOMIC_STORE_I8:
8395         case OP_ATOMIC_STORE_U1:
8396         case OP_ATOMIC_STORE_U2:
8397         case OP_ATOMIC_STORE_U4:
8398         case OP_ATOMIC_STORE_U8:
8399         case OP_ATOMIC_STORE_R4:
8400         case OP_ATOMIC_STORE_R8:
8401                 return TRUE;
8402         default:
8403                 return FALSE;
8404         }
8405 }
8406
8407 CallInfo*
8408 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8409 {
8410         return get_call_info (mp, sig);
8411 }