2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
11 * Johan Lorensson (lateralusx.github@gmail.com)
13 * (C) 2003 Ximian, Inc.
14 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
15 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
16 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
25 #include <mono/metadata/abi-details.h>
26 #include <mono/metadata/appdomain.h>
27 #include <mono/metadata/debug-helpers.h>
28 #include <mono/metadata/threads.h>
29 #include <mono/metadata/profiler-private.h>
30 #include <mono/metadata/mono-debug.h>
31 #include <mono/metadata/gc-internals.h>
32 #include <mono/utils/mono-math.h>
33 #include <mono/utils/mono-mmap.h>
34 #include <mono/utils/mono-memory-model.h>
35 #include <mono/utils/mono-tls.h>
36 #include <mono/utils/mono-hwcap-x86.h>
37 #include <mono/utils/mono-threads.h>
41 #include "mini-amd64.h"
42 #include "cpu-amd64.h"
43 #include "debugger-agent.h"
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
59 /* Under windows, the calling convention is never stdcall */
60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
65 /* This mutex protects architecture specific caches */
66 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
67 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
68 static mono_mutex_t mini_arch_mutex;
70 /* The single step trampoline */
71 static gpointer ss_trampoline;
73 /* The breakpoint trampoline */
74 static gpointer bp_trampoline;
76 /* Offset between fp and the first argument in the callee */
77 #define ARGS_OFFSET 16
78 #define GP_SCRATCH_REG AMD64_R11
81 * AMD64 register usage:
82 * - callee saved registers are used for global register allocation
83 * - %r11 is used for materializing 64 bit constants in opcodes
84 * - the rest is used for local allocation
88 * Floating point comparison results:
98 mono_arch_regname (int reg)
101 case AMD64_RAX: return "%rax";
102 case AMD64_RBX: return "%rbx";
103 case AMD64_RCX: return "%rcx";
104 case AMD64_RDX: return "%rdx";
105 case AMD64_RSP: return "%rsp";
106 case AMD64_RBP: return "%rbp";
107 case AMD64_RDI: return "%rdi";
108 case AMD64_RSI: return "%rsi";
109 case AMD64_R8: return "%r8";
110 case AMD64_R9: return "%r9";
111 case AMD64_R10: return "%r10";
112 case AMD64_R11: return "%r11";
113 case AMD64_R12: return "%r12";
114 case AMD64_R13: return "%r13";
115 case AMD64_R14: return "%r14";
116 case AMD64_R15: return "%r15";
121 static const char * packed_xmmregs [] = {
122 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
123 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
126 static const char * single_xmmregs [] = {
127 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
128 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
132 mono_arch_fregname (int reg)
134 if (reg < AMD64_XMM_NREG)
135 return single_xmmregs [reg];
141 mono_arch_xregname (int reg)
143 if (reg < AMD64_XMM_NREG)
144 return packed_xmmregs [reg];
153 return mono_debug_count ();
159 static inline gboolean
160 amd64_is_near_call (guint8 *code)
163 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
166 return code [0] == 0xe8;
169 static inline gboolean
170 amd64_use_imm32 (gint64 val)
172 if (mini_get_debug_options()->single_imm_size)
175 return amd64_is_imm32 (val);
179 amd64_patch (unsigned char* code, gpointer target)
184 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
189 if ((code [0] & 0xf8) == 0xb8) {
190 /* amd64_set_reg_template */
191 *(guint64*)(code + 1) = (guint64)target;
193 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
194 /* mov 0(%rip), %dreg */
195 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
197 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
198 /* call *<OFFSET>(%rip) */
199 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
201 else if (code [0] == 0xe8) {
203 gint64 disp = (guint8*)target - (guint8*)code;
204 g_assert (amd64_is_imm32 (disp));
205 x86_patch (code, (unsigned char*)target);
208 x86_patch (code, (unsigned char*)target);
212 mono_amd64_patch (unsigned char* code, gpointer target)
214 amd64_patch (code, target);
217 #define DEBUG(a) if (cfg->verbose_level > 1) a
220 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
222 ainfo->offset = *stack_size;
224 if (*gr >= PARAM_REGS) {
225 ainfo->storage = ArgOnStack;
226 ainfo->arg_size = sizeof (mgreg_t);
227 /* Since the same stack slot size is used for all arg */
228 /* types, it needs to be big enough to hold them all */
229 (*stack_size) += sizeof(mgreg_t);
232 ainfo->storage = ArgInIReg;
233 ainfo->reg = param_regs [*gr];
239 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
241 ainfo->offset = *stack_size;
243 if (*gr >= FLOAT_PARAM_REGS) {
244 ainfo->storage = ArgOnStack;
245 ainfo->arg_size = sizeof (mgreg_t);
246 /* Since the same stack slot size is used for both float */
247 /* types, it needs to be big enough to hold them both */
248 (*stack_size) += sizeof(mgreg_t);
251 /* A double register */
253 ainfo->storage = ArgInDoubleSSEReg;
255 ainfo->storage = ArgInFloatSSEReg;
261 typedef enum ArgumentClass {
269 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
271 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
274 ptype = mini_get_underlying_type (type);
275 switch (ptype->type) {
284 case MONO_TYPE_STRING:
285 case MONO_TYPE_OBJECT:
286 case MONO_TYPE_CLASS:
287 case MONO_TYPE_SZARRAY:
289 case MONO_TYPE_FNPTR:
290 case MONO_TYPE_ARRAY:
293 class2 = ARG_CLASS_INTEGER;
298 class2 = ARG_CLASS_INTEGER;
300 class2 = ARG_CLASS_SSE;
304 case MONO_TYPE_TYPEDBYREF:
305 g_assert_not_reached ();
307 case MONO_TYPE_GENERICINST:
308 if (!mono_type_generic_inst_is_valuetype (ptype)) {
309 class2 = ARG_CLASS_INTEGER;
313 case MONO_TYPE_VALUETYPE: {
314 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
317 for (i = 0; i < info->num_fields; ++i) {
319 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
324 g_assert_not_reached ();
328 if (class1 == class2)
330 else if (class1 == ARG_CLASS_NO_CLASS)
332 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
333 class1 = ARG_CLASS_MEMORY;
334 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
335 class1 = ARG_CLASS_INTEGER;
337 class1 = ARG_CLASS_SSE;
343 count_fields_nested (MonoClass *klass, gboolean pinvoke)
345 MonoMarshalType *info;
350 info = mono_marshal_load_type_info (klass);
352 for (i = 0; i < info->num_fields; ++i) {
353 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
354 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type), pinvoke);
360 MonoClassField *field;
363 while ((field = mono_class_get_fields (klass, &iter))) {
364 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
366 if (MONO_TYPE_ISSTRUCT (field->type))
367 count += count_fields_nested (mono_class_from_mono_type (field->type), pinvoke);
381 * collect_field_info_nested:
383 * Collect field info from KLASS recursively into FIELDS.
386 collect_field_info_nested (MonoClass *klass, StructFieldInfo *fields, int index, int offset, gboolean pinvoke, gboolean unicode)
388 MonoMarshalType *info;
392 info = mono_marshal_load_type_info (klass);
394 for (i = 0; i < info->num_fields; ++i) {
395 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
396 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset, pinvoke, unicode);
400 fields [index].type = info->fields [i].field->type;
401 fields [index].size = mono_marshal_type_size (info->fields [i].field->type,
402 info->fields [i].mspec,
403 &align, TRUE, unicode);
404 fields [index].offset = offset + info->fields [i].offset;
410 MonoClassField *field;
413 while ((field = mono_class_get_fields (klass, &iter))) {
414 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
416 if (MONO_TYPE_ISSTRUCT (field->type)) {
417 index = collect_field_info_nested (mono_class_from_mono_type (field->type), fields, index, field->offset - sizeof (MonoObject), pinvoke, unicode);
421 fields [index].type = field->type;
422 fields [index].size = mono_type_size (field->type, &align);
423 fields [index].offset = field->offset - sizeof (MonoObject) + offset;
433 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
434 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
437 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
439 gboolean result = FALSE;
441 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
442 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
444 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
445 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
446 arg_info->pair_size [0] = 0;
447 arg_info->pair_size [1] = 0;
450 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
451 /* Pass parameter in integer register. */
452 arg_info->pair_storage [0] = ArgInIReg;
453 arg_info->pair_regs [0] = int_regs [*current_int_reg];
454 (*current_int_reg) ++;
456 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
457 /* Pass parameter in float register. */
458 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
459 arg_info->pair_regs [0] = float_regs [*current_float_reg];
460 (*current_float_reg) ++;
464 if (result == TRUE) {
465 arg_info->pair_size [0] = arg_size;
473 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
475 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
479 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
481 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
485 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
486 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
488 /* Windows x64 value type ABI.
490 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
492 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
493 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
494 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
495 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
497 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
499 * Integers/Float types smaller than or equal to 8 bytes
500 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
501 * Properly sized struct/unions (1,2,4,8)
502 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
503 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
504 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
507 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
511 /* Parameter cases. */
512 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
513 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
515 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
516 arg_info->storage = ArgValuetypeInReg;
517 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
518 /* No more registers, fallback passing parameter on stack as value. */
519 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
521 /* Passing value directly on stack, so use size of value. */
522 arg_info->storage = ArgOnStack;
523 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
524 arg_info->offset = *stack_size;
525 arg_info->arg_size = arg_size;
526 *stack_size += arg_size;
529 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
530 arg_info->storage = ArgValuetypeAddrInIReg;
531 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
532 /* No more registers, fallback passing address to parameter on stack. */
533 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
535 /* Passing an address to value on stack, so use size of register as argument size. */
536 arg_info->storage = ArgValuetypeAddrOnStack;
537 arg_size = sizeof (mgreg_t);
538 arg_info->offset = *stack_size;
539 arg_info->arg_size = arg_size;
540 *stack_size += arg_size;
544 /* Return value cases. */
545 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
546 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
548 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
549 arg_info->storage = ArgValuetypeInReg;
550 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
552 /* Only RAX/XMM0 should be used to return valuetype. */
553 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
555 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
556 arg_info->storage = ArgValuetypeAddrInIReg;
557 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
559 /* Only RAX should be used to return valuetype address. */
560 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
562 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
563 arg_info->offset = *stack_size;
564 *stack_size += arg_size;
570 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
573 *arg_class = ARG_CLASS_NO_CLASS;
575 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
578 /* Calculate argument class type and size of marshalled type. */
579 MonoMarshalType *info = mono_marshal_load_type_info (klass);
580 *arg_size = info->native_size;
582 /* Calculate argument class type and size of managed type. */
583 *arg_size = mono_class_value_size (klass, NULL);
586 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
587 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
589 if (*arg_class == ARG_CLASS_MEMORY) {
590 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
591 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
595 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
596 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
597 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
598 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
599 * it must be represented in call and cannot be dropped.
601 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
602 arg_info->pass_empty_struct = TRUE;
603 *arg_size = SIZEOF_REGISTER;
604 *arg_class = ARG_CLASS_INTEGER;
607 assert (*arg_class != ARG_CLASS_NO_CLASS);
611 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
612 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
614 guint32 arg_size = SIZEOF_REGISTER;
615 MonoClass *klass = NULL;
616 ArgumentClass arg_class;
618 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
620 klass = mono_class_from_mono_type (type);
621 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
623 /* Only drop value type if its not an empty struct as input that must be represented in call */
624 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
625 arg_info->storage = ArgValuetypeInReg;
626 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
628 /* Alocate storage for value type. */
629 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
633 #endif /* TARGET_WIN32 */
636 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
638 guint32 *gr, guint32 *fr, guint32 *stack_size)
641 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
643 guint32 size, quad, nquads, i, nfields;
644 /* Keep track of the size used in each quad so we can */
645 /* use the right size when copying args/return vars. */
646 guint32 quadsize [2] = {8, 8};
647 ArgumentClass args [2];
648 StructFieldInfo *fields = NULL;
650 gboolean pass_on_stack = FALSE;
653 klass = mono_class_from_mono_type (type);
654 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
656 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
657 /* We pass and return vtypes of size 8 in a register */
658 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
659 pass_on_stack = TRUE;
662 /* If this struct can't be split up naturally into 8-byte */
663 /* chunks (registers), pass it on the stack. */
665 MonoMarshalType *info = mono_marshal_load_type_info (klass);
667 struct_size = info->native_size;
669 struct_size = mono_class_value_size (klass, NULL);
672 * Collect field information recursively to be able to
673 * handle nested structures.
675 nfields = count_fields_nested (klass, sig->pinvoke);
676 fields = g_new0 (StructFieldInfo, nfields);
677 collect_field_info_nested (klass, fields, 0, 0, sig->pinvoke, klass->unicode);
679 for (i = 0; i < nfields; ++i) {
680 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
681 pass_on_stack = TRUE;
687 ainfo->storage = ArgValuetypeInReg;
688 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
693 /* Allways pass in memory */
694 ainfo->offset = *stack_size;
695 *stack_size += ALIGN_TO (size, 8);
696 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
698 ainfo->arg_size = ALIGN_TO (size, 8);
710 int n = mono_class_value_size (klass, NULL);
712 quadsize [0] = n >= 8 ? 8 : n;
713 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
715 /* Always pass in 1 or 2 integer registers */
716 args [0] = ARG_CLASS_INTEGER;
717 args [1] = ARG_CLASS_INTEGER;
718 /* Only the simplest cases are supported */
719 if (is_return && nquads != 1) {
720 args [0] = ARG_CLASS_MEMORY;
721 args [1] = ARG_CLASS_MEMORY;
725 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
726 * The X87 and SSEUP stuff is left out since there are no such types in
730 ainfo->storage = ArgValuetypeInReg;
731 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
735 if (struct_size > 16) {
736 ainfo->offset = *stack_size;
737 *stack_size += ALIGN_TO (struct_size, 8);
738 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
740 ainfo->arg_size = ALIGN_TO (struct_size, 8);
746 args [0] = ARG_CLASS_NO_CLASS;
747 args [1] = ARG_CLASS_NO_CLASS;
748 for (quad = 0; quad < nquads; ++quad) {
749 ArgumentClass class1;
752 class1 = ARG_CLASS_MEMORY;
754 class1 = ARG_CLASS_NO_CLASS;
755 for (i = 0; i < nfields; ++i) {
756 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
757 /* Unaligned field */
761 /* Skip fields in other quad */
762 if ((quad == 0) && (fields [i].offset >= 8))
764 if ((quad == 1) && (fields [i].offset < 8))
767 /* How far into this quad this data extends.*/
768 /* (8 is size of quad) */
769 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
771 class1 = merge_argument_class_from_type (fields [i].type, class1);
773 /* Empty structs have a nonzero size, causing this assert to be hit */
775 g_assert (class1 != ARG_CLASS_NO_CLASS);
776 args [quad] = class1;
782 /* Post merger cleanup */
783 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
784 args [0] = args [1] = ARG_CLASS_MEMORY;
786 /* Allocate registers */
791 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
793 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
796 ainfo->storage = ArgValuetypeInReg;
797 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
798 g_assert (quadsize [0] <= 8);
799 g_assert (quadsize [1] <= 8);
800 ainfo->pair_size [0] = quadsize [0];
801 ainfo->pair_size [1] = quadsize [1];
802 ainfo->nregs = nquads;
803 for (quad = 0; quad < nquads; ++quad) {
804 switch (args [quad]) {
805 case ARG_CLASS_INTEGER:
806 if (*gr >= PARAM_REGS)
807 args [quad] = ARG_CLASS_MEMORY;
809 ainfo->pair_storage [quad] = ArgInIReg;
811 ainfo->pair_regs [quad] = return_regs [*gr];
813 ainfo->pair_regs [quad] = param_regs [*gr];
818 if (*fr >= FLOAT_PARAM_REGS)
819 args [quad] = ARG_CLASS_MEMORY;
821 if (quadsize[quad] <= 4)
822 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
823 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
824 ainfo->pair_regs [quad] = *fr;
828 case ARG_CLASS_MEMORY:
830 case ARG_CLASS_NO_CLASS:
833 g_assert_not_reached ();
837 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
839 /* Revert possible register assignments */
843 ainfo->offset = *stack_size;
845 arg_size = ALIGN_TO (struct_size, 8);
847 arg_size = nquads * sizeof(mgreg_t);
848 *stack_size += arg_size;
849 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
851 ainfo->arg_size = arg_size;
854 #endif /* !TARGET_WIN32 */
860 * Obtain information about a call according to the calling convention.
861 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
862 * Draft Version 0.23" document for more information.
863 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
864 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
867 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
869 guint32 i, gr, fr, pstart;
871 int n = sig->hasthis + sig->param_count;
872 guint32 stack_size = 0;
874 gboolean is_pinvoke = sig->pinvoke;
877 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
879 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
882 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
888 /* Reserve space where the callee can save the argument registers */
889 stack_size = 4 * sizeof (mgreg_t);
893 ret_type = mini_get_underlying_type (sig->ret);
894 switch (ret_type->type) {
904 case MONO_TYPE_FNPTR:
905 case MONO_TYPE_CLASS:
906 case MONO_TYPE_OBJECT:
907 case MONO_TYPE_SZARRAY:
908 case MONO_TYPE_ARRAY:
909 case MONO_TYPE_STRING:
910 cinfo->ret.storage = ArgInIReg;
911 cinfo->ret.reg = AMD64_RAX;
915 cinfo->ret.storage = ArgInIReg;
916 cinfo->ret.reg = AMD64_RAX;
919 cinfo->ret.storage = ArgInFloatSSEReg;
920 cinfo->ret.reg = AMD64_XMM0;
923 cinfo->ret.storage = ArgInDoubleSSEReg;
924 cinfo->ret.reg = AMD64_XMM0;
926 case MONO_TYPE_GENERICINST:
927 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
928 cinfo->ret.storage = ArgInIReg;
929 cinfo->ret.reg = AMD64_RAX;
932 if (mini_is_gsharedvt_type (ret_type)) {
933 cinfo->ret.storage = ArgGsharedvtVariableInReg;
937 case MONO_TYPE_VALUETYPE:
938 case MONO_TYPE_TYPEDBYREF: {
939 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
941 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
942 g_assert (cinfo->ret.storage != ArgInIReg);
947 g_assert (mini_is_gsharedvt_type (ret_type));
948 cinfo->ret.storage = ArgGsharedvtVariableInReg;
953 g_error ("Can't handle as return value 0x%x", ret_type->type);
958 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
959 * the first argument, allowing 'this' to be always passed in the first arg reg.
960 * Also do this if the first argument is a reference type, since virtual calls
961 * are sometimes made using calli without sig->hasthis set, like in the delegate
964 ArgStorage ret_storage = cinfo->ret.storage;
965 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
967 add_general (&gr, &stack_size, cinfo->args + 0);
969 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
972 add_general (&gr, &stack_size, &cinfo->ret);
973 cinfo->ret.storage = ret_storage;
974 cinfo->vret_arg_index = 1;
978 add_general (&gr, &stack_size, cinfo->args + 0);
980 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
981 add_general (&gr, &stack_size, &cinfo->ret);
982 cinfo->ret.storage = ret_storage;
986 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
988 fr = FLOAT_PARAM_REGS;
990 /* Emit the signature cookie just before the implicit arguments */
991 add_general (&gr, &stack_size, &cinfo->sig_cookie);
994 for (i = pstart; i < sig->param_count; ++i) {
995 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
999 /* The float param registers and other param registers must be the same index on Windows x64.*/
1006 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1007 /* We allways pass the sig cookie on the stack for simplicity */
1009 * Prevent implicit arguments + the sig cookie from being passed
1013 fr = FLOAT_PARAM_REGS;
1015 /* Emit the signature cookie just before the implicit arguments */
1016 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1019 ptype = mini_get_underlying_type (sig->params [i]);
1020 switch (ptype->type) {
1023 add_general (&gr, &stack_size, ainfo);
1027 add_general (&gr, &stack_size, ainfo);
1031 add_general (&gr, &stack_size, ainfo);
1036 case MONO_TYPE_FNPTR:
1037 case MONO_TYPE_CLASS:
1038 case MONO_TYPE_OBJECT:
1039 case MONO_TYPE_STRING:
1040 case MONO_TYPE_SZARRAY:
1041 case MONO_TYPE_ARRAY:
1042 add_general (&gr, &stack_size, ainfo);
1044 case MONO_TYPE_GENERICINST:
1045 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1046 add_general (&gr, &stack_size, ainfo);
1049 if (mini_is_gsharedvt_variable_type (ptype)) {
1050 /* gsharedvt arguments are passed by ref */
1051 add_general (&gr, &stack_size, ainfo);
1052 if (ainfo->storage == ArgInIReg)
1053 ainfo->storage = ArgGSharedVtInReg;
1055 ainfo->storage = ArgGSharedVtOnStack;
1059 case MONO_TYPE_VALUETYPE:
1060 case MONO_TYPE_TYPEDBYREF:
1061 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1066 add_general (&gr, &stack_size, ainfo);
1069 add_float (&fr, &stack_size, ainfo, FALSE);
1072 add_float (&fr, &stack_size, ainfo, TRUE);
1075 case MONO_TYPE_MVAR:
1076 /* gsharedvt arguments are passed by ref */
1077 g_assert (mini_is_gsharedvt_type (ptype));
1078 add_general (&gr, &stack_size, ainfo);
1079 if (ainfo->storage == ArgInIReg)
1080 ainfo->storage = ArgGSharedVtInReg;
1082 ainfo->storage = ArgGSharedVtOnStack;
1085 g_assert_not_reached ();
1089 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1091 fr = FLOAT_PARAM_REGS;
1093 /* Emit the signature cookie just before the implicit arguments */
1094 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1097 cinfo->stack_usage = stack_size;
1098 cinfo->reg_usage = gr;
1099 cinfo->freg_usage = fr;
1104 * mono_arch_get_argument_info:
1105 * @csig: a method signature
1106 * @param_count: the number of parameters to consider
1107 * @arg_info: an array to store the result infos
1109 * Gathers information on parameters such as size, alignment and
1110 * padding. arg_info should be large enought to hold param_count + 1 entries.
1112 * Returns the size of the argument area on the stack.
1115 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1118 CallInfo *cinfo = get_call_info (NULL, csig);
1119 guint32 args_size = cinfo->stack_usage;
1121 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1122 if (csig->hasthis) {
1123 arg_info [0].offset = 0;
1126 for (k = 0; k < param_count; k++) {
1127 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1129 arg_info [k + 1].size = 0;
1138 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1142 MonoType *callee_ret;
1144 c1 = get_call_info (NULL, caller_sig);
1145 c2 = get_call_info (NULL, callee_sig);
1146 res = c1->stack_usage >= c2->stack_usage;
1147 callee_ret = mini_get_underlying_type (callee_sig->ret);
1148 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1149 /* An address on the callee's stack is passed as the first argument */
1159 * Initialize the cpu to execute managed code.
1162 mono_arch_cpu_init (void)
1167 /* spec compliance requires running with double precision */
1168 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1169 fpcw &= ~X86_FPCW_PRECC_MASK;
1170 fpcw |= X86_FPCW_PREC_DOUBLE;
1171 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1172 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1174 /* TODO: This is crashing on Win64 right now.
1175 * _control87 (_PC_53, MCW_PC);
1181 * Initialize architecture specific code.
1184 mono_arch_init (void)
1186 mono_os_mutex_init_recursive (&mini_arch_mutex);
1188 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1189 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1190 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1191 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1192 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1193 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1197 bp_trampoline = mini_get_breakpoint_trampoline ();
1201 * Cleanup architecture specific code.
1204 mono_arch_cleanup (void)
1206 mono_os_mutex_destroy (&mini_arch_mutex);
1210 * This function returns the optimizations supported on this cpu.
1213 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1219 if (mono_hwcap_x86_has_cmov) {
1220 opts |= MONO_OPT_CMOV;
1222 if (mono_hwcap_x86_has_fcmov)
1223 opts |= MONO_OPT_FCMOV;
1225 *exclude_mask |= MONO_OPT_FCMOV;
1227 *exclude_mask |= MONO_OPT_CMOV;
1231 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1232 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1233 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1234 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1235 /* will now have a reference to an argument that won't be fully decomposed. */
1236 *exclude_mask |= MONO_OPT_SIMD;
1243 * This function test for all SSE functions supported.
1245 * Returns a bitmask corresponding to all supported versions.
1249 mono_arch_cpu_enumerate_simd_versions (void)
1251 guint32 sse_opts = 0;
1253 if (mono_hwcap_x86_has_sse1)
1254 sse_opts |= SIMD_VERSION_SSE1;
1256 if (mono_hwcap_x86_has_sse2)
1257 sse_opts |= SIMD_VERSION_SSE2;
1259 if (mono_hwcap_x86_has_sse3)
1260 sse_opts |= SIMD_VERSION_SSE3;
1262 if (mono_hwcap_x86_has_ssse3)
1263 sse_opts |= SIMD_VERSION_SSSE3;
1265 if (mono_hwcap_x86_has_sse41)
1266 sse_opts |= SIMD_VERSION_SSE41;
1268 if (mono_hwcap_x86_has_sse42)
1269 sse_opts |= SIMD_VERSION_SSE42;
1271 if (mono_hwcap_x86_has_sse4a)
1272 sse_opts |= SIMD_VERSION_SSE4a;
1280 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1285 for (i = 0; i < cfg->num_varinfo; i++) {
1286 MonoInst *ins = cfg->varinfo [i];
1287 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1290 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1293 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1294 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1297 if (mono_is_regsize_var (ins->inst_vtype)) {
1298 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1299 g_assert (i == vmv->idx);
1300 vars = g_list_prepend (vars, vmv);
1304 vars = mono_varlist_sort (cfg, vars, 0);
1310 * mono_arch_compute_omit_fp:
1312 * Determine whenever the frame pointer can be eliminated.
1315 mono_arch_compute_omit_fp (MonoCompile *cfg)
1317 MonoMethodSignature *sig;
1318 MonoMethodHeader *header;
1322 if (cfg->arch.omit_fp_computed)
1325 header = cfg->header;
1327 sig = mono_method_signature (cfg->method);
1329 if (!cfg->arch.cinfo)
1330 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1331 cinfo = (CallInfo *)cfg->arch.cinfo;
1334 * FIXME: Remove some of the restrictions.
1336 cfg->arch.omit_fp = TRUE;
1337 cfg->arch.omit_fp_computed = TRUE;
1339 if (cfg->disable_omit_fp)
1340 cfg->arch.omit_fp = FALSE;
1342 if (!debug_omit_fp ())
1343 cfg->arch.omit_fp = FALSE;
1345 if (cfg->method->save_lmf)
1346 cfg->arch.omit_fp = FALSE;
1348 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1349 cfg->arch.omit_fp = FALSE;
1350 if (header->num_clauses)
1351 cfg->arch.omit_fp = FALSE;
1352 if (cfg->param_area)
1353 cfg->arch.omit_fp = FALSE;
1354 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1355 cfg->arch.omit_fp = FALSE;
1356 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1357 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1358 cfg->arch.omit_fp = FALSE;
1359 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1360 ArgInfo *ainfo = &cinfo->args [i];
1362 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1364 * The stack offset can only be determined when the frame
1367 cfg->arch.omit_fp = FALSE;
1372 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1373 MonoInst *ins = cfg->varinfo [i];
1376 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1381 mono_arch_get_global_int_regs (MonoCompile *cfg)
1385 mono_arch_compute_omit_fp (cfg);
1387 if (cfg->arch.omit_fp)
1388 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1390 /* We use the callee saved registers for global allocation */
1391 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1392 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1393 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1394 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1395 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1397 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1398 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1405 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1410 /* All XMM registers */
1411 for (i = 0; i < 16; ++i)
1412 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1418 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1420 static GList *r = NULL;
1425 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1426 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1427 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1428 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1429 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1430 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1432 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1433 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1434 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1435 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1436 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1437 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1438 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1439 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1441 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1448 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1451 static GList *r = NULL;
1456 for (i = 0; i < AMD64_XMM_NREG; ++i)
1457 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1459 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1466 * mono_arch_regalloc_cost:
1468 * Return the cost, in number of memory references, of the action of
1469 * allocating the variable VMV into a register during global register
1473 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1475 MonoInst *ins = cfg->varinfo [vmv->idx];
1477 if (cfg->method->save_lmf)
1478 /* The register is already saved */
1479 /* substract 1 for the invisible store in the prolog */
1480 return (ins->opcode == OP_ARG) ? 0 : 1;
1483 return (ins->opcode == OP_ARG) ? 1 : 2;
1487 * mono_arch_fill_argument_info:
1489 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1493 mono_arch_fill_argument_info (MonoCompile *cfg)
1496 MonoMethodSignature *sig;
1501 sig = mono_method_signature (cfg->method);
1503 cinfo = (CallInfo *)cfg->arch.cinfo;
1504 sig_ret = mini_get_underlying_type (sig->ret);
1507 * Contrary to mono_arch_allocate_vars (), the information should describe
1508 * where the arguments are at the beginning of the method, not where they can be
1509 * accessed during the execution of the method. The later makes no sense for the
1510 * global register allocator, since a variable can be in more than one location.
1512 switch (cinfo->ret.storage) {
1514 case ArgInFloatSSEReg:
1515 case ArgInDoubleSSEReg:
1516 cfg->ret->opcode = OP_REGVAR;
1517 cfg->ret->inst_c0 = cinfo->ret.reg;
1519 case ArgValuetypeInReg:
1520 cfg->ret->opcode = OP_REGOFFSET;
1521 cfg->ret->inst_basereg = -1;
1522 cfg->ret->inst_offset = -1;
1527 g_assert_not_reached ();
1530 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1531 ArgInfo *ainfo = &cinfo->args [i];
1533 ins = cfg->args [i];
1535 switch (ainfo->storage) {
1537 case ArgInFloatSSEReg:
1538 case ArgInDoubleSSEReg:
1539 ins->opcode = OP_REGVAR;
1540 ins->inst_c0 = ainfo->reg;
1543 ins->opcode = OP_REGOFFSET;
1544 ins->inst_basereg = -1;
1545 ins->inst_offset = -1;
1547 case ArgValuetypeInReg:
1549 ins->opcode = OP_NOP;
1552 g_assert_not_reached ();
1558 mono_arch_allocate_vars (MonoCompile *cfg)
1561 MonoMethodSignature *sig;
1564 guint32 locals_stack_size, locals_stack_align;
1568 sig = mono_method_signature (cfg->method);
1570 cinfo = (CallInfo *)cfg->arch.cinfo;
1571 sig_ret = mini_get_underlying_type (sig->ret);
1573 mono_arch_compute_omit_fp (cfg);
1576 * We use the ABI calling conventions for managed code as well.
1577 * Exception: valuetypes are only sometimes passed or returned in registers.
1581 * The stack looks like this:
1582 * <incoming arguments passed on the stack>
1584 * <lmf/caller saved registers>
1587 * <localloc area> -> grows dynamically
1591 if (cfg->arch.omit_fp) {
1592 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1593 cfg->frame_reg = AMD64_RSP;
1596 /* Locals are allocated backwards from %fp */
1597 cfg->frame_reg = AMD64_RBP;
1601 cfg->arch.saved_iregs = cfg->used_int_regs;
1602 if (cfg->method->save_lmf) {
1603 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1604 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1605 cfg->arch.saved_iregs |= iregs_to_save;
1608 if (cfg->arch.omit_fp)
1609 cfg->arch.reg_save_area_offset = offset;
1610 /* Reserve space for callee saved registers */
1611 for (i = 0; i < AMD64_NREG; ++i)
1612 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1613 offset += sizeof(mgreg_t);
1615 if (!cfg->arch.omit_fp)
1616 cfg->arch.reg_save_area_offset = -offset;
1618 if (sig_ret->type != MONO_TYPE_VOID) {
1619 switch (cinfo->ret.storage) {
1621 case ArgInFloatSSEReg:
1622 case ArgInDoubleSSEReg:
1623 cfg->ret->opcode = OP_REGVAR;
1624 cfg->ret->inst_c0 = cinfo->ret.reg;
1625 cfg->ret->dreg = cinfo->ret.reg;
1627 case ArgValuetypeAddrInIReg:
1628 case ArgGsharedvtVariableInReg:
1629 /* The register is volatile */
1630 cfg->vret_addr->opcode = OP_REGOFFSET;
1631 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1632 if (cfg->arch.omit_fp) {
1633 cfg->vret_addr->inst_offset = offset;
1637 cfg->vret_addr->inst_offset = -offset;
1639 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1640 printf ("vret_addr =");
1641 mono_print_ins (cfg->vret_addr);
1644 case ArgValuetypeInReg:
1645 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1646 cfg->ret->opcode = OP_REGOFFSET;
1647 cfg->ret->inst_basereg = cfg->frame_reg;
1648 if (cfg->arch.omit_fp) {
1649 cfg->ret->inst_offset = offset;
1650 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1652 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1653 cfg->ret->inst_offset = - offset;
1657 g_assert_not_reached ();
1661 /* Allocate locals */
1662 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1663 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1664 char *mname = mono_method_full_name (cfg->method, TRUE);
1665 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1670 if (locals_stack_align) {
1671 offset += (locals_stack_align - 1);
1672 offset &= ~(locals_stack_align - 1);
1674 if (cfg->arch.omit_fp) {
1675 cfg->locals_min_stack_offset = offset;
1676 cfg->locals_max_stack_offset = offset + locals_stack_size;
1678 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1679 cfg->locals_max_stack_offset = - offset;
1682 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1683 if (offsets [i] != -1) {
1684 MonoInst *ins = cfg->varinfo [i];
1685 ins->opcode = OP_REGOFFSET;
1686 ins->inst_basereg = cfg->frame_reg;
1687 if (cfg->arch.omit_fp)
1688 ins->inst_offset = (offset + offsets [i]);
1690 ins->inst_offset = - (offset + offsets [i]);
1691 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1694 offset += locals_stack_size;
1696 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1697 g_assert (!cfg->arch.omit_fp);
1698 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1699 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1702 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1703 ins = cfg->args [i];
1704 if (ins->opcode != OP_REGVAR) {
1705 ArgInfo *ainfo = &cinfo->args [i];
1706 gboolean inreg = TRUE;
1708 /* FIXME: Allocate volatile arguments to registers */
1709 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1713 * Under AMD64, all registers used to pass arguments to functions
1714 * are volatile across calls.
1715 * FIXME: Optimize this.
1717 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1720 ins->opcode = OP_REGOFFSET;
1722 switch (ainfo->storage) {
1724 case ArgInFloatSSEReg:
1725 case ArgInDoubleSSEReg:
1726 case ArgGSharedVtInReg:
1728 ins->opcode = OP_REGVAR;
1729 ins->dreg = ainfo->reg;
1733 case ArgGSharedVtOnStack:
1734 g_assert (!cfg->arch.omit_fp);
1735 ins->opcode = OP_REGOFFSET;
1736 ins->inst_basereg = cfg->frame_reg;
1737 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1739 case ArgValuetypeInReg:
1741 case ArgValuetypeAddrInIReg:
1742 case ArgValuetypeAddrOnStack: {
1744 g_assert (!cfg->arch.omit_fp);
1745 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1746 MONO_INST_NEW (cfg, indir, 0);
1748 indir->opcode = OP_REGOFFSET;
1749 if (ainfo->pair_storage [0] == ArgInIReg) {
1750 indir->inst_basereg = cfg->frame_reg;
1751 offset = ALIGN_TO (offset, sizeof (gpointer));
1752 offset += (sizeof (gpointer));
1753 indir->inst_offset = - offset;
1756 indir->inst_basereg = cfg->frame_reg;
1757 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1760 ins->opcode = OP_VTARG_ADDR;
1761 ins->inst_left = indir;
1769 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1770 ins->opcode = OP_REGOFFSET;
1771 ins->inst_basereg = cfg->frame_reg;
1772 /* These arguments are saved to the stack in the prolog */
1773 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1774 if (cfg->arch.omit_fp) {
1775 ins->inst_offset = offset;
1776 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1777 // Arguments are yet supported by the stack map creation code
1778 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1780 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1781 ins->inst_offset = - offset;
1782 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1788 cfg->stack_offset = offset;
1792 mono_arch_create_vars (MonoCompile *cfg)
1794 MonoMethodSignature *sig;
1798 sig = mono_method_signature (cfg->method);
1800 if (!cfg->arch.cinfo)
1801 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1802 cinfo = (CallInfo *)cfg->arch.cinfo;
1804 if (cinfo->ret.storage == ArgValuetypeInReg)
1805 cfg->ret_var_is_local = TRUE;
1807 sig_ret = mini_get_underlying_type (sig->ret);
1808 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1809 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1810 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1811 printf ("vret_addr = ");
1812 mono_print_ins (cfg->vret_addr);
1816 if (cfg->gen_sdb_seq_points) {
1819 if (cfg->compile_aot) {
1820 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1821 ins->flags |= MONO_INST_VOLATILE;
1822 cfg->arch.seq_point_info_var = ins;
1824 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1825 ins->flags |= MONO_INST_VOLATILE;
1826 cfg->arch.ss_tramp_var = ins;
1828 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1829 ins->flags |= MONO_INST_VOLATILE;
1830 cfg->arch.bp_tramp_var = ins;
1833 if (cfg->method->save_lmf)
1834 cfg->create_lmf_var = TRUE;
1836 if (cfg->method->save_lmf) {
1838 #if !defined(TARGET_WIN32)
1839 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1840 cfg->lmf_ir_mono_lmf = TRUE;
1846 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1852 MONO_INST_NEW (cfg, ins, OP_MOVE);
1853 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1854 ins->sreg1 = tree->dreg;
1855 MONO_ADD_INS (cfg->cbb, ins);
1856 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1858 case ArgInFloatSSEReg:
1859 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1860 ins->dreg = mono_alloc_freg (cfg);
1861 ins->sreg1 = tree->dreg;
1862 MONO_ADD_INS (cfg->cbb, ins);
1864 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1866 case ArgInDoubleSSEReg:
1867 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1868 ins->dreg = mono_alloc_freg (cfg);
1869 ins->sreg1 = tree->dreg;
1870 MONO_ADD_INS (cfg->cbb, ins);
1872 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1876 g_assert_not_reached ();
1881 arg_storage_to_load_membase (ArgStorage storage)
1885 #if defined(__mono_ilp32__)
1886 return OP_LOADI8_MEMBASE;
1888 return OP_LOAD_MEMBASE;
1890 case ArgInDoubleSSEReg:
1891 return OP_LOADR8_MEMBASE;
1892 case ArgInFloatSSEReg:
1893 return OP_LOADR4_MEMBASE;
1895 g_assert_not_reached ();
1902 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1904 MonoMethodSignature *tmp_sig;
1907 if (call->tail_call)
1910 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1913 * mono_ArgIterator_Setup assumes the signature cookie is
1914 * passed first and all the arguments which were before it are
1915 * passed on the stack after the signature. So compensate by
1916 * passing a different signature.
1918 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1919 tmp_sig->param_count -= call->signature->sentinelpos;
1920 tmp_sig->sentinelpos = 0;
1921 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1923 sig_reg = mono_alloc_ireg (cfg);
1924 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1926 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1930 static inline LLVMArgStorage
1931 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1935 return LLVMArgInIReg;
1938 case ArgGSharedVtInReg:
1939 case ArgGSharedVtOnStack:
1940 return LLVMArgGSharedVt;
1942 g_assert_not_reached ();
1948 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1954 LLVMCallInfo *linfo;
1955 MonoType *t, *sig_ret;
1957 n = sig->param_count + sig->hasthis;
1958 sig_ret = mini_get_underlying_type (sig->ret);
1960 cinfo = get_call_info (cfg->mempool, sig);
1962 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1965 * LLVM always uses the native ABI while we use our own ABI, the
1966 * only difference is the handling of vtypes:
1967 * - we only pass/receive them in registers in some cases, and only
1968 * in 1 or 2 integer registers.
1970 switch (cinfo->ret.storage) {
1972 linfo->ret.storage = LLVMArgNone;
1975 case ArgInFloatSSEReg:
1976 case ArgInDoubleSSEReg:
1977 linfo->ret.storage = LLVMArgNormal;
1979 case ArgValuetypeInReg: {
1980 ainfo = &cinfo->ret;
1983 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1984 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1985 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1986 cfg->disable_llvm = TRUE;
1990 linfo->ret.storage = LLVMArgVtypeInReg;
1991 for (j = 0; j < 2; ++j)
1992 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1995 case ArgValuetypeAddrInIReg:
1996 case ArgGsharedvtVariableInReg:
1997 /* Vtype returned using a hidden argument */
1998 linfo->ret.storage = LLVMArgVtypeRetAddr;
1999 linfo->vret_arg_index = cinfo->vret_arg_index;
2002 g_assert_not_reached ();
2006 for (i = 0; i < n; ++i) {
2007 ainfo = cinfo->args + i;
2009 if (i >= sig->hasthis)
2010 t = sig->params [i - sig->hasthis];
2012 t = &mono_defaults.int_class->byval_arg;
2013 t = mini_type_get_underlying_type (t);
2015 linfo->args [i].storage = LLVMArgNone;
2017 switch (ainfo->storage) {
2019 linfo->args [i].storage = LLVMArgNormal;
2021 case ArgInDoubleSSEReg:
2022 case ArgInFloatSSEReg:
2023 linfo->args [i].storage = LLVMArgNormal;
2026 if (MONO_TYPE_ISSTRUCT (t))
2027 linfo->args [i].storage = LLVMArgVtypeByVal;
2029 linfo->args [i].storage = LLVMArgNormal;
2031 case ArgValuetypeInReg:
2033 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2034 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2035 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2036 cfg->disable_llvm = TRUE;
2040 linfo->args [i].storage = LLVMArgVtypeInReg;
2041 for (j = 0; j < 2; ++j)
2042 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2044 case ArgGSharedVtInReg:
2045 case ArgGSharedVtOnStack:
2046 linfo->args [i].storage = LLVMArgGSharedVt;
2049 cfg->exception_message = g_strdup ("ainfo->storage");
2050 cfg->disable_llvm = TRUE;
2060 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2063 MonoMethodSignature *sig;
2069 sig = call->signature;
2070 n = sig->param_count + sig->hasthis;
2072 cinfo = get_call_info (cfg->mempool, sig);
2076 if (COMPILE_LLVM (cfg)) {
2077 /* We shouldn't be called in the llvm case */
2078 cfg->disable_llvm = TRUE;
2083 * Emit all arguments which are passed on the stack to prevent register
2084 * allocation problems.
2086 for (i = 0; i < n; ++i) {
2088 ainfo = cinfo->args + i;
2090 in = call->args [i];
2092 if (sig->hasthis && i == 0)
2093 t = &mono_defaults.object_class->byval_arg;
2095 t = sig->params [i - sig->hasthis];
2097 t = mini_get_underlying_type (t);
2098 //XXX what about ArgGSharedVtOnStack here?
2099 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2101 if (t->type == MONO_TYPE_R4)
2102 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2103 else if (t->type == MONO_TYPE_R8)
2104 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2106 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2108 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2110 if (cfg->compute_gc_maps) {
2113 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2119 * Emit all parameters passed in registers in non-reverse order for better readability
2120 * and to help the optimization in emit_prolog ().
2122 for (i = 0; i < n; ++i) {
2123 ainfo = cinfo->args + i;
2125 in = call->args [i];
2127 if (ainfo->storage == ArgInIReg)
2128 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2131 for (i = n - 1; i >= 0; --i) {
2134 ainfo = cinfo->args + i;
2136 in = call->args [i];
2138 if (sig->hasthis && i == 0)
2139 t = &mono_defaults.object_class->byval_arg;
2141 t = sig->params [i - sig->hasthis];
2142 t = mini_get_underlying_type (t);
2144 switch (ainfo->storage) {
2148 case ArgInFloatSSEReg:
2149 case ArgInDoubleSSEReg:
2150 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2153 case ArgValuetypeInReg:
2154 case ArgValuetypeAddrInIReg:
2155 case ArgValuetypeAddrOnStack:
2156 case ArgGSharedVtInReg:
2157 case ArgGSharedVtOnStack: {
2158 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2159 /* Already emitted above */
2161 //FIXME what about ArgGSharedVtOnStack ?
2162 if (ainfo->storage == ArgOnStack && call->tail_call) {
2163 MonoInst *call_inst = (MonoInst*)call;
2164 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2165 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2173 size = mono_type_native_stack_size (t, &align);
2176 * Other backends use mono_type_stack_size (), but that
2177 * aligns the size to 8, which is larger than the size of
2178 * the source, leading to reads of invalid memory if the
2179 * source is at the end of address space.
2181 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2184 if (size >= 10000) {
2185 /* Avoid asserts in emit_memcpy () */
2186 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2187 /* Continue normally */
2190 if (size > 0 || ainfo->pass_empty_struct) {
2191 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2192 arg->sreg1 = in->dreg;
2193 arg->klass = mono_class_from_mono_type (t);
2194 arg->backend.size = size;
2195 arg->inst_p0 = call;
2196 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2197 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2199 MONO_ADD_INS (cfg->cbb, arg);
2204 g_assert_not_reached ();
2207 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2208 /* Emit the signature cookie just before the implicit arguments */
2209 emit_sig_cookie (cfg, call, cinfo);
2212 /* Handle the case where there are no implicit arguments */
2213 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2214 emit_sig_cookie (cfg, call, cinfo);
2216 switch (cinfo->ret.storage) {
2217 case ArgValuetypeInReg:
2218 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2220 * Tell the JIT to use a more efficient calling convention: call using
2221 * OP_CALL, compute the result location after the call, and save the
2224 call->vret_in_reg = TRUE;
2226 * Nullify the instruction computing the vret addr to enable
2227 * future optimizations.
2230 NULLIFY_INS (call->vret_var);
2232 if (call->tail_call)
2235 * The valuetype is in RAX:RDX after the call, need to be copied to
2236 * the stack. Push the address here, so the call instruction can
2239 if (!cfg->arch.vret_addr_loc) {
2240 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2241 /* Prevent it from being register allocated or optimized away */
2242 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2245 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2248 case ArgValuetypeAddrInIReg:
2249 case ArgGsharedvtVariableInReg: {
2251 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2252 vtarg->sreg1 = call->vret_var->dreg;
2253 vtarg->dreg = mono_alloc_preg (cfg);
2254 MONO_ADD_INS (cfg->cbb, vtarg);
2256 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2263 if (cfg->method->save_lmf) {
2264 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2265 MONO_ADD_INS (cfg->cbb, arg);
2268 call->stack_usage = cinfo->stack_usage;
2272 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2275 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2276 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2277 int size = ins->backend.size;
2279 switch (ainfo->storage) {
2280 case ArgValuetypeInReg: {
2284 for (part = 0; part < 2; ++part) {
2285 if (ainfo->pair_storage [part] == ArgNone)
2288 if (ainfo->pass_empty_struct) {
2289 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2290 NEW_ICONST (cfg, load, 0);
2293 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2294 load->inst_basereg = src->dreg;
2295 load->inst_offset = part * sizeof(mgreg_t);
2297 switch (ainfo->pair_storage [part]) {
2299 load->dreg = mono_alloc_ireg (cfg);
2301 case ArgInDoubleSSEReg:
2302 case ArgInFloatSSEReg:
2303 load->dreg = mono_alloc_freg (cfg);
2306 g_assert_not_reached ();
2310 MONO_ADD_INS (cfg->cbb, load);
2312 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2316 case ArgValuetypeAddrInIReg:
2317 case ArgValuetypeAddrOnStack: {
2318 MonoInst *vtaddr, *load;
2320 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2322 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2324 MONO_INST_NEW (cfg, load, OP_LDADDR);
2325 cfg->has_indirection = TRUE;
2326 load->inst_p0 = vtaddr;
2327 vtaddr->flags |= MONO_INST_INDIRECT;
2328 load->type = STACK_MP;
2329 load->klass = vtaddr->klass;
2330 load->dreg = mono_alloc_ireg (cfg);
2331 MONO_ADD_INS (cfg->cbb, load);
2332 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2334 if (ainfo->pair_storage [0] == ArgInIReg) {
2335 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2336 arg->dreg = mono_alloc_ireg (cfg);
2337 arg->sreg1 = load->dreg;
2339 MONO_ADD_INS (cfg->cbb, arg);
2340 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2342 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2346 case ArgGSharedVtInReg:
2348 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2350 case ArgGSharedVtOnStack:
2351 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2355 int dreg = mono_alloc_ireg (cfg);
2357 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2358 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2359 } else if (size <= 40) {
2360 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2362 // FIXME: Code growth
2363 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2366 if (cfg->compute_gc_maps) {
2368 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2374 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2376 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2378 if (ret->type == MONO_TYPE_R4) {
2379 if (COMPILE_LLVM (cfg))
2380 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2382 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2384 } else if (ret->type == MONO_TYPE_R8) {
2385 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2389 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2392 #endif /* DISABLE_JIT */
2394 #define EMIT_COND_BRANCH(ins,cond,sign) \
2395 if (ins->inst_true_bb->native_offset) { \
2396 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2398 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2399 if ((cfg->opt & MONO_OPT_BRANCH) && \
2400 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2401 x86_branch8 (code, cond, 0, sign); \
2403 x86_branch32 (code, cond, 0, sign); \
2407 MonoMethodSignature *sig;
2412 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2416 switch (cinfo->ret.storage) {
2419 case ArgInFloatSSEReg:
2420 case ArgInDoubleSSEReg:
2421 case ArgValuetypeAddrInIReg:
2422 case ArgValuetypeInReg:
2428 for (i = 0; i < cinfo->nargs; ++i) {
2429 ArgInfo *ainfo = &cinfo->args [i];
2430 switch (ainfo->storage) {
2432 case ArgInFloatSSEReg:
2433 case ArgInDoubleSSEReg:
2434 case ArgValuetypeInReg:
2437 if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2449 * mono_arch_dyn_call_prepare:
2451 * Return a pointer to an arch-specific structure which contains information
2452 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2453 * supported for SIG.
2454 * This function is equivalent to ffi_prep_cif in libffi.
2457 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2459 ArchDynCallInfo *info;
2462 cinfo = get_call_info (NULL, sig);
2464 if (!dyn_call_supported (sig, cinfo)) {
2469 info = g_new0 (ArchDynCallInfo, 1);
2470 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2472 info->cinfo = cinfo;
2474 return (MonoDynCallInfo*)info;
2478 * mono_arch_dyn_call_free:
2480 * Free a MonoDynCallInfo structure.
2483 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2485 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2487 g_free (ainfo->cinfo);
2491 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2492 #define GREG_TO_PTR(greg) (gpointer)(greg)
2495 * mono_arch_get_start_dyn_call:
2497 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2498 * store the result into BUF.
2499 * ARGS should be an array of pointers pointing to the arguments.
2500 * RET should point to a memory buffer large enought to hold the result of the
2502 * This function should be as fast as possible, any work which does not depend
2503 * on the actual values of the arguments should be done in
2504 * mono_arch_dyn_call_prepare ().
2505 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2509 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2511 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2512 DynCallArgs *p = (DynCallArgs*)buf;
2513 int arg_index, greg, freg, i, pindex;
2514 MonoMethodSignature *sig = dinfo->sig;
2515 int buffer_offset = 0;
2516 static int param_reg_to_index [16];
2517 static gboolean param_reg_to_index_inited;
2519 if (!param_reg_to_index_inited) {
2520 for (i = 0; i < PARAM_REGS; ++i)
2521 param_reg_to_index [param_regs [i]] = i;
2522 mono_memory_barrier ();
2523 param_reg_to_index_inited = 1;
2526 g_assert (buf_len >= sizeof (DynCallArgs));
2536 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2537 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2542 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2543 p->regs [greg ++] = PTR_TO_GREG(ret);
2545 for (; pindex < sig->param_count; pindex++) {
2546 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2547 gpointer *arg = args [arg_index ++];
2548 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2551 if (ainfo->storage == ArgOnStack) {
2552 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2554 slot = param_reg_to_index [ainfo->reg];
2558 p->regs [slot] = PTR_TO_GREG(*(arg));
2564 case MONO_TYPE_STRING:
2565 case MONO_TYPE_CLASS:
2566 case MONO_TYPE_ARRAY:
2567 case MONO_TYPE_SZARRAY:
2568 case MONO_TYPE_OBJECT:
2572 #if !defined(__mono_ilp32__)
2576 p->regs [slot] = PTR_TO_GREG(*(arg));
2578 #if defined(__mono_ilp32__)
2581 p->regs [slot] = *(guint64*)(arg);
2585 p->regs [slot] = *(guint8*)(arg);
2588 p->regs [slot] = *(gint8*)(arg);
2591 p->regs [slot] = *(gint16*)(arg);
2594 p->regs [slot] = *(guint16*)(arg);
2597 p->regs [slot] = *(gint32*)(arg);
2600 p->regs [slot] = *(guint32*)(arg);
2602 case MONO_TYPE_R4: {
2605 *(float*)&d = *(float*)(arg);
2607 p->fregs [freg ++] = d;
2612 p->fregs [freg ++] = *(double*)(arg);
2614 case MONO_TYPE_GENERICINST:
2615 if (MONO_TYPE_IS_REFERENCE (t)) {
2616 p->regs [slot] = PTR_TO_GREG(*(arg));
2618 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2619 MonoClass *klass = mono_class_from_mono_type (t);
2620 guint8 *nullable_buf;
2623 size = mono_class_value_size (klass, NULL);
2624 nullable_buf = p->buffer + buffer_offset;
2625 buffer_offset += size;
2626 g_assert (buffer_offset <= 256);
2628 /* The argument pointed to by arg is either a boxed vtype or null */
2629 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2631 arg = (gpointer*)nullable_buf;
2637 case MONO_TYPE_VALUETYPE: {
2638 switch (ainfo->storage) {
2639 case ArgValuetypeInReg:
2640 for (i = 0; i < 2; ++i) {
2641 switch (ainfo->pair_storage [i]) {
2645 slot = param_reg_to_index [ainfo->pair_regs [i]];
2646 p->regs [slot] = ((mgreg_t*)(arg))[i];
2648 case ArgInDoubleSSEReg:
2650 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2653 g_assert_not_reached ();
2659 for (i = 0; i < ainfo->arg_size / 8; ++i)
2660 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2663 g_assert_not_reached ();
2669 g_assert_not_reached ();
2675 * mono_arch_finish_dyn_call:
2677 * Store the result of a dyn call into the return value buffer passed to
2678 * start_dyn_call ().
2679 * This function should be as fast as possible, any work which does not depend
2680 * on the actual values of the arguments should be done in
2681 * mono_arch_dyn_call_prepare ().
2684 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2686 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2687 MonoMethodSignature *sig = dinfo->sig;
2688 DynCallArgs *dargs = (DynCallArgs*)buf;
2689 guint8 *ret = dargs->ret;
2690 mgreg_t res = dargs->res;
2691 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2694 switch (sig_ret->type) {
2695 case MONO_TYPE_VOID:
2696 *(gpointer*)ret = NULL;
2698 case MONO_TYPE_STRING:
2699 case MONO_TYPE_CLASS:
2700 case MONO_TYPE_ARRAY:
2701 case MONO_TYPE_SZARRAY:
2702 case MONO_TYPE_OBJECT:
2706 *(gpointer*)ret = GREG_TO_PTR(res);
2712 *(guint8*)ret = res;
2715 *(gint16*)ret = res;
2718 *(guint16*)ret = res;
2721 *(gint32*)ret = res;
2724 *(guint32*)ret = res;
2727 *(gint64*)ret = res;
2730 *(guint64*)ret = res;
2733 *(float*)ret = *(float*)&(dargs->fregs [0]);
2736 *(double*)ret = dargs->fregs [0];
2738 case MONO_TYPE_GENERICINST:
2739 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2740 *(gpointer*)ret = GREG_TO_PTR(res);
2745 case MONO_TYPE_VALUETYPE:
2746 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2749 ArgInfo *ainfo = &dinfo->cinfo->ret;
2751 g_assert (ainfo->storage == ArgValuetypeInReg);
2753 for (i = 0; i < 2; ++i) {
2754 switch (ainfo->pair_storage [0]) {
2756 ((mgreg_t*)ret)[i] = res;
2758 case ArgInDoubleSSEReg:
2759 ((double*)ret)[i] = dargs->fregs [i];
2764 g_assert_not_reached ();
2771 g_assert_not_reached ();
2775 /* emit an exception if condition is fail */
2776 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2778 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2779 if (tins == NULL) { \
2780 mono_add_patch_info (cfg, code - cfg->native_code, \
2781 MONO_PATCH_INFO_EXC, exc_name); \
2782 x86_branch32 (code, cond, 0, signed); \
2784 EMIT_COND_BRANCH (tins, cond, signed); \
2788 #define EMIT_FPCOMPARE(code) do { \
2789 amd64_fcompp (code); \
2790 amd64_fnstsw (code); \
2793 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2794 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2795 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2796 amd64_ ##op (code); \
2797 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2798 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2802 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2804 gboolean no_patch = FALSE;
2807 * FIXME: Add support for thunks
2810 gboolean near_call = FALSE;
2813 * Indirect calls are expensive so try to make a near call if possible.
2814 * The caller memory is allocated by the code manager so it is
2815 * guaranteed to be at a 32 bit offset.
2818 if (patch_type != MONO_PATCH_INFO_ABS) {
2819 /* The target is in memory allocated using the code manager */
2822 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2823 if (((MonoMethod*)data)->klass->image->aot_module)
2824 /* The callee might be an AOT method */
2826 if (((MonoMethod*)data)->dynamic)
2827 /* The target is in malloc-ed memory */
2831 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2833 * The call might go directly to a native function without
2836 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2838 gconstpointer target = mono_icall_get_wrapper (mi);
2839 if ((((guint64)target) >> 32) != 0)
2845 MonoJumpInfo *jinfo = NULL;
2847 if (cfg->abs_patches)
2848 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2850 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2851 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2852 if (mi && (((guint64)mi->func) >> 32) == 0)
2857 * This is not really an optimization, but required because the
2858 * generic class init trampolines use R11 to pass the vtable.
2863 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2865 if (info->func == info->wrapper) {
2867 if ((((guint64)info->func) >> 32) == 0)
2871 /* See the comment in mono_codegen () */
2872 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2876 else if ((((guint64)data) >> 32) == 0) {
2883 if (cfg->method->dynamic)
2884 /* These methods are allocated using malloc */
2887 #ifdef MONO_ARCH_NOMAP32BIT
2890 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2891 if (optimize_for_xen)
2894 if (cfg->compile_aot) {
2901 * Align the call displacement to an address divisible by 4 so it does
2902 * not span cache lines. This is required for code patching to work on SMP
2905 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2906 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2907 amd64_padding (code, pad_size);
2909 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2910 amd64_call_code (code, 0);
2913 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2914 amd64_set_reg_template (code, GP_SCRATCH_REG);
2915 amd64_call_reg (code, GP_SCRATCH_REG);
2922 static inline guint8*
2923 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2926 if (win64_adjust_stack)
2927 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2929 code = emit_call_body (cfg, code, patch_type, data);
2931 if (win64_adjust_stack)
2932 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2939 store_membase_imm_to_store_membase_reg (int opcode)
2942 case OP_STORE_MEMBASE_IMM:
2943 return OP_STORE_MEMBASE_REG;
2944 case OP_STOREI4_MEMBASE_IMM:
2945 return OP_STOREI4_MEMBASE_REG;
2946 case OP_STOREI8_MEMBASE_IMM:
2947 return OP_STOREI8_MEMBASE_REG;
2955 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2958 * mono_arch_peephole_pass_1:
2960 * Perform peephole opts which should/can be performed before local regalloc
2963 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2967 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2968 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2970 switch (ins->opcode) {
2974 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2976 * X86_LEA is like ADD, but doesn't have the
2977 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2978 * its operand to 64 bit.
2980 ins->opcode = OP_X86_LEA_MEMBASE;
2981 ins->inst_basereg = ins->sreg1;
2986 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2990 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2991 * the latter has length 2-3 instead of 6 (reverse constant
2992 * propagation). These instruction sequences are very common
2993 * in the initlocals bblock.
2995 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2996 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2997 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2998 ins2->sreg1 = ins->dreg;
2999 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3001 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3004 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3012 case OP_COMPARE_IMM:
3013 case OP_LCOMPARE_IMM:
3014 /* OP_COMPARE_IMM (reg, 0)
3016 * OP_AMD64_TEST_NULL (reg)
3019 ins->opcode = OP_AMD64_TEST_NULL;
3021 case OP_ICOMPARE_IMM:
3023 ins->opcode = OP_X86_TEST_NULL;
3025 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3027 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3028 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3030 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3031 * OP_COMPARE_IMM reg, imm
3033 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3035 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3036 ins->inst_basereg == last_ins->inst_destbasereg &&
3037 ins->inst_offset == last_ins->inst_offset) {
3038 ins->opcode = OP_ICOMPARE_IMM;
3039 ins->sreg1 = last_ins->sreg1;
3041 /* check if we can remove cmp reg,0 with test null */
3043 ins->opcode = OP_X86_TEST_NULL;
3049 mono_peephole_ins (bb, ins);
3054 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3058 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3059 switch (ins->opcode) {
3062 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3063 /* reg = 0 -> XOR (reg, reg) */
3064 /* XOR sets cflags on x86, so we cant do it always */
3065 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3066 ins->opcode = OP_LXOR;
3067 ins->sreg1 = ins->dreg;
3068 ins->sreg2 = ins->dreg;
3076 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3077 * 0 result into 64 bits.
3079 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3080 ins->opcode = OP_IXOR;
3084 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3088 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3089 * the latter has length 2-3 instead of 6 (reverse constant
3090 * propagation). These instruction sequences are very common
3091 * in the initlocals bblock.
3093 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3094 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3095 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3096 ins2->sreg1 = ins->dreg;
3097 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3099 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3102 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3111 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3112 ins->opcode = OP_X86_INC_REG;
3115 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3116 ins->opcode = OP_X86_DEC_REG;
3120 mono_peephole_ins (bb, ins);
3124 #define NEW_INS(cfg,ins,dest,op) do { \
3125 MONO_INST_NEW ((cfg), (dest), (op)); \
3126 (dest)->cil_code = (ins)->cil_code; \
3127 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3131 * mono_arch_lowering_pass:
3133 * Converts complex opcodes into simpler ones so that each IR instruction
3134 * corresponds to one machine instruction.
3137 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3139 MonoInst *ins, *n, *temp;
3142 * FIXME: Need to add more instructions, but the current machine
3143 * description can't model some parts of the composite instructions like
3146 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3147 switch (ins->opcode) {
3151 case OP_IDIV_UN_IMM:
3152 case OP_IREM_UN_IMM:
3155 mono_decompose_op_imm (cfg, bb, ins);
3157 case OP_COMPARE_IMM:
3158 case OP_LCOMPARE_IMM:
3159 if (!amd64_use_imm32 (ins->inst_imm)) {
3160 NEW_INS (cfg, ins, temp, OP_I8CONST);
3161 temp->inst_c0 = ins->inst_imm;
3162 temp->dreg = mono_alloc_ireg (cfg);
3163 ins->opcode = OP_COMPARE;
3164 ins->sreg2 = temp->dreg;
3167 #ifndef __mono_ilp32__
3168 case OP_LOAD_MEMBASE:
3170 case OP_LOADI8_MEMBASE:
3171 /* Don't generate memindex opcodes (to simplify */
3172 /* read sandboxing) */
3173 if (!amd64_use_imm32 (ins->inst_offset)) {
3174 NEW_INS (cfg, ins, temp, OP_I8CONST);
3175 temp->inst_c0 = ins->inst_offset;
3176 temp->dreg = mono_alloc_ireg (cfg);
3177 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3178 ins->inst_indexreg = temp->dreg;
3181 #ifndef __mono_ilp32__
3182 case OP_STORE_MEMBASE_IMM:
3184 case OP_STOREI8_MEMBASE_IMM:
3185 if (!amd64_use_imm32 (ins->inst_imm)) {
3186 NEW_INS (cfg, ins, temp, OP_I8CONST);
3187 temp->inst_c0 = ins->inst_imm;
3188 temp->dreg = mono_alloc_ireg (cfg);
3189 ins->opcode = OP_STOREI8_MEMBASE_REG;
3190 ins->sreg1 = temp->dreg;
3193 #ifdef MONO_ARCH_SIMD_INTRINSICS
3194 case OP_EXPAND_I1: {
3195 int temp_reg1 = mono_alloc_ireg (cfg);
3196 int temp_reg2 = mono_alloc_ireg (cfg);
3197 int original_reg = ins->sreg1;
3199 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3200 temp->sreg1 = original_reg;
3201 temp->dreg = temp_reg1;
3203 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3204 temp->sreg1 = temp_reg1;
3205 temp->dreg = temp_reg2;
3208 NEW_INS (cfg, ins, temp, OP_LOR);
3209 temp->sreg1 = temp->dreg = temp_reg2;
3210 temp->sreg2 = temp_reg1;
3212 ins->opcode = OP_EXPAND_I2;
3213 ins->sreg1 = temp_reg2;
3222 bb->max_vreg = cfg->next_vreg;
3226 branch_cc_table [] = {
3227 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3228 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3229 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3232 /* Maps CMP_... constants to X86_CC_... constants */
3235 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3236 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3240 cc_signed_table [] = {
3241 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3242 FALSE, FALSE, FALSE, FALSE
3245 /*#include "cprop.c"*/
3247 static unsigned char*
3248 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3251 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3253 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3256 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3258 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3262 static unsigned char*
3263 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3265 int sreg = tree->sreg1;
3266 int need_touch = FALSE;
3268 #if defined(TARGET_WIN32)
3270 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3271 if (!tree->flags & MONO_INST_INIT)
3280 * If requested stack size is larger than one page,
3281 * perform stack-touch operation
3284 * Generate stack probe code.
3285 * Under Windows, it is necessary to allocate one page at a time,
3286 * "touching" stack after each successful sub-allocation. This is
3287 * because of the way stack growth is implemented - there is a
3288 * guard page before the lowest stack page that is currently commited.
3289 * Stack normally grows sequentially so OS traps access to the
3290 * guard page and commits more pages when needed.
3292 amd64_test_reg_imm (code, sreg, ~0xFFF);
3293 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3295 br[2] = code; /* loop */
3296 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3297 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3298 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3299 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3300 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3301 amd64_patch (br[3], br[2]);
3302 amd64_test_reg_reg (code, sreg, sreg);
3303 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3304 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3306 br[1] = code; x86_jump8 (code, 0);
3308 amd64_patch (br[0], code);
3309 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3310 amd64_patch (br[1], code);
3311 amd64_patch (br[4], code);
3314 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3316 if (tree->flags & MONO_INST_INIT) {
3318 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3319 amd64_push_reg (code, AMD64_RAX);
3322 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3323 amd64_push_reg (code, AMD64_RCX);
3326 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3327 amd64_push_reg (code, AMD64_RDI);
3331 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3332 if (sreg != AMD64_RCX)
3333 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3334 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3336 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3337 if (cfg->param_area)
3338 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3340 amd64_prefix (code, X86_REP_PREFIX);
3343 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3344 amd64_pop_reg (code, AMD64_RDI);
3345 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3346 amd64_pop_reg (code, AMD64_RCX);
3347 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3348 amd64_pop_reg (code, AMD64_RAX);
3354 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3359 /* Move return value to the target register */
3360 /* FIXME: do this in the local reg allocator */
3361 switch (ins->opcode) {
3364 case OP_CALL_MEMBASE:
3367 case OP_LCALL_MEMBASE:
3368 g_assert (ins->dreg == AMD64_RAX);
3372 case OP_FCALL_MEMBASE: {
3373 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3374 if (rtype->type == MONO_TYPE_R4) {
3375 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3378 if (ins->dreg != AMD64_XMM0)
3379 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3385 case OP_RCALL_MEMBASE:
3386 if (ins->dreg != AMD64_XMM0)
3387 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3391 case OP_VCALL_MEMBASE:
3394 case OP_VCALL2_MEMBASE:
3395 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3396 if (cinfo->ret.storage == ArgValuetypeInReg) {
3397 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3399 /* Load the destination address */
3400 g_assert (loc->opcode == OP_REGOFFSET);
3401 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3403 for (quad = 0; quad < 2; quad ++) {
3404 switch (cinfo->ret.pair_storage [quad]) {
3406 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3408 case ArgInFloatSSEReg:
3409 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3411 case ArgInDoubleSSEReg:
3412 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3427 #endif /* DISABLE_JIT */
3430 static int tls_gs_offset;
3434 mono_amd64_have_tls_get (void)
3437 static gboolean have_tls_get = FALSE;
3438 static gboolean inited = FALSE;
3441 return have_tls_get;
3443 #if MONO_HAVE_FAST_TLS
3444 guint8 *ins = (guint8*)pthread_getspecific;
3447 * We're looking for these two instructions:
3449 * mov %gs:[offset](,%rdi,8),%rax
3452 have_tls_get = ins [0] == 0x65 &&
3462 tls_gs_offset = ins[5];
3465 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3466 * For that version we're looking for these instructions:
3470 * mov %gs:[offset](,%rdi,8),%rax
3474 if (!have_tls_get) {
3475 have_tls_get = ins [0] == 0x55 &&
3490 tls_gs_offset = ins[9];
3496 return have_tls_get;
3497 #elif defined(TARGET_ANDROID)
3505 mono_amd64_get_tls_gs_offset (void)
3508 return tls_gs_offset;
3510 g_assert_not_reached ();
3516 * mono_amd64_emit_tls_get:
3517 * @code: buffer to store code to
3518 * @dreg: hard register where to place the result
3519 * @tls_offset: offset info
3521 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3522 * the dreg register the item in the thread local storage identified
3525 * Returns: a pointer to the end of the stored code
3528 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3531 if (tls_offset < 64) {
3532 x86_prefix (code, X86_GS_PREFIX);
3533 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3537 g_assert (tls_offset < 0x440);
3538 /* Load TEB->TlsExpansionSlots */
3539 x86_prefix (code, X86_GS_PREFIX);
3540 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3541 amd64_test_reg_reg (code, dreg, dreg);
3543 amd64_branch (code, X86_CC_EQ, code, TRUE);
3544 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3545 amd64_patch (buf [0], code);
3547 #elif defined(__APPLE__)
3548 x86_prefix (code, X86_GS_PREFIX);
3549 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3551 if (optimize_for_xen) {
3552 x86_prefix (code, X86_FS_PREFIX);
3553 amd64_mov_reg_mem (code, dreg, 0, 8);
3554 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3556 x86_prefix (code, X86_FS_PREFIX);
3557 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3565 #define MAX_TEB_TLS_SLOTS 64
3566 #define TEB_TLS_SLOTS_OFFSET 0x1480
3567 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3570 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3573 guint8 * more_than_64_slots = NULL;
3574 guint8 * empty_slot = NULL;
3575 guint8 * tls_get_reg_done = NULL;
3577 //Use temporary register for offset calculation?
3578 if (dreg == offset_reg) {
3579 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3580 amd64_push_reg (code, tmp_reg);
3581 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3582 offset_reg = tmp_reg;
3585 //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3586 amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3587 more_than_64_slots = code;
3588 amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3590 //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3591 amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3592 amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3594 //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3595 x86_prefix (code, X86_GS_PREFIX);
3596 amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3598 tls_get_reg_done = code;
3599 amd64_jump8 (code, 0);
3601 amd64_patch (more_than_64_slots, code);
3603 //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3604 x86_prefix (code, X86_GS_PREFIX);
3605 amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3607 //Check for NULL in _TEB.TlsExpansionSlots.
3608 amd64_test_reg_reg (code, dreg, dreg);
3610 amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3612 //TLS expansion slots are at index offset into the expansion array.
3613 //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3614 amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3615 amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3617 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3619 amd64_patch (empty_slot, code);
3620 amd64_patch (tls_get_reg_done, code);
3623 amd64_pop_reg (code, tmp_reg);
3631 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3633 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3635 if (dreg != offset_reg)
3636 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3637 amd64_prefix (code, X86_GS_PREFIX);
3638 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3639 #elif defined(__linux__)
3642 if (dreg == offset_reg) {
3643 /* Use a temporary reg by saving it to the redzone */
3644 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3645 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3646 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3647 offset_reg = tmpreg;
3649 x86_prefix (code, X86_FS_PREFIX);
3650 amd64_mov_reg_mem (code, dreg, 0, 8);
3651 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3653 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3654 #elif defined(TARGET_WIN32)
3655 code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3657 g_assert_not_reached ();
3663 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3666 g_assert_not_reached ();
3667 #elif defined(__APPLE__)
3668 x86_prefix (code, X86_GS_PREFIX);
3669 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3671 g_assert (!optimize_for_xen);
3672 x86_prefix (code, X86_FS_PREFIX);
3673 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3679 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3681 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3683 g_assert_not_reached ();
3684 #elif defined(__APPLE__)
3685 x86_prefix (code, X86_GS_PREFIX);
3686 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3688 x86_prefix (code, X86_FS_PREFIX);
3689 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3695 * mono_arch_translate_tls_offset:
3697 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3700 mono_arch_translate_tls_offset (int offset)
3703 return tls_gs_offset + (offset * 8);
3712 * Emit code to initialize an LMF structure at LMF_OFFSET.
3715 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3718 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3721 * sp is saved right before calls but we need to save it here too so
3722 * async stack walks would work.
3724 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3726 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3727 if (cfg->arch.omit_fp && cfa_offset != -1)
3728 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3730 /* These can't contain refs */
3731 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3732 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3733 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3734 /* These are handled automatically by the stack marking code */
3735 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3742 #define TEB_LAST_ERROR_OFFSET 0x068
3745 emit_get_last_error (guint8* code, int dreg)
3747 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3748 x86_prefix (code, X86_GS_PREFIX);
3749 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3757 emit_get_last_error (guint8* code, int dreg)
3759 g_assert_not_reached ();
3764 /* benchmark and set based on cpu */
3765 #define LOOP_ALIGNMENT 8
3766 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3770 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3775 guint8 *code = cfg->native_code + cfg->code_len;
3778 /* Fix max_offset estimate for each successor bb */
3779 if (cfg->opt & MONO_OPT_BRANCH) {
3780 int current_offset = cfg->code_len;
3781 MonoBasicBlock *current_bb;
3782 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3783 current_bb->max_offset = current_offset;
3784 current_offset += current_bb->max_length;
3788 if (cfg->opt & MONO_OPT_LOOP) {
3789 int pad, align = LOOP_ALIGNMENT;
3790 /* set alignment depending on cpu */
3791 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3793 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3794 amd64_padding (code, pad);
3795 cfg->code_len += pad;
3796 bb->native_offset = cfg->code_len;
3800 if (cfg->verbose_level > 2)
3801 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3803 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3804 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3805 g_assert (!cfg->compile_aot);
3807 cov->data [bb->dfn].cil_code = bb->cil_code;
3808 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3809 /* this is not thread save, but good enough */
3810 amd64_inc_membase (code, AMD64_R11, 0);
3813 offset = code - cfg->native_code;
3815 mono_debug_open_block (cfg, bb, offset);
3817 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3818 x86_breakpoint (code);
3820 MONO_BB_FOR_EACH_INS (bb, ins) {
3821 offset = code - cfg->native_code;
3823 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3825 #define EXTRA_CODE_SPACE (16)
3827 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3828 cfg->code_size *= 2;
3829 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3830 code = cfg->native_code + offset;
3831 cfg->stat_code_reallocs++;
3834 if (cfg->debug_info)
3835 mono_debug_record_line_number (cfg, ins, offset);
3837 switch (ins->opcode) {
3839 amd64_mul_reg (code, ins->sreg2, TRUE);
3842 amd64_mul_reg (code, ins->sreg2, FALSE);
3844 case OP_X86_SETEQ_MEMBASE:
3845 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3847 case OP_STOREI1_MEMBASE_IMM:
3848 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3850 case OP_STOREI2_MEMBASE_IMM:
3851 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3853 case OP_STOREI4_MEMBASE_IMM:
3854 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3856 case OP_STOREI1_MEMBASE_REG:
3857 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3859 case OP_STOREI2_MEMBASE_REG:
3860 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3862 /* In AMD64 NaCl, pointers are 4 bytes, */
3863 /* so STORE_* != STOREI8_*. Likewise below. */
3864 case OP_STORE_MEMBASE_REG:
3865 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3867 case OP_STOREI8_MEMBASE_REG:
3868 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3870 case OP_STOREI4_MEMBASE_REG:
3871 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3873 case OP_STORE_MEMBASE_IMM:
3874 /* In NaCl, this could be a PCONST type, which could */
3875 /* mean a pointer type was copied directly into the */
3876 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3877 /* the value would be 0x00000000FFFFFFFF which is */
3878 /* not proper for an imm32 unless you cast it. */
3879 g_assert (amd64_is_imm32 (ins->inst_imm));
3880 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3882 case OP_STOREI8_MEMBASE_IMM:
3883 g_assert (amd64_is_imm32 (ins->inst_imm));
3884 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3887 #ifdef __mono_ilp32__
3888 /* In ILP32, pointers are 4 bytes, so separate these */
3889 /* cases, use literal 8 below where we really want 8 */
3890 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3891 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3895 // FIXME: Decompose this earlier
3896 if (amd64_use_imm32 (ins->inst_imm))
3897 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3899 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3900 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3904 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3905 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3908 // FIXME: Decompose this earlier
3909 if (amd64_use_imm32 (ins->inst_imm))
3910 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3912 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3913 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3917 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3918 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3921 /* For NaCl, pointers are 4 bytes, so separate these */
3922 /* cases, use literal 8 below where we really want 8 */
3923 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3924 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3926 case OP_LOAD_MEMBASE:
3927 g_assert (amd64_is_imm32 (ins->inst_offset));
3928 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3930 case OP_LOADI8_MEMBASE:
3931 /* Use literal 8 instead of sizeof pointer or */
3932 /* register, we really want 8 for this opcode */
3933 g_assert (amd64_is_imm32 (ins->inst_offset));
3934 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3936 case OP_LOADI4_MEMBASE:
3937 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3939 case OP_LOADU4_MEMBASE:
3940 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3942 case OP_LOADU1_MEMBASE:
3943 /* The cpu zero extends the result into 64 bits */
3944 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3946 case OP_LOADI1_MEMBASE:
3947 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3949 case OP_LOADU2_MEMBASE:
3950 /* The cpu zero extends the result into 64 bits */
3951 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3953 case OP_LOADI2_MEMBASE:
3954 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3956 case OP_AMD64_LOADI8_MEMINDEX:
3957 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3959 case OP_LCONV_TO_I1:
3960 case OP_ICONV_TO_I1:
3962 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3964 case OP_LCONV_TO_I2:
3965 case OP_ICONV_TO_I2:
3967 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3969 case OP_LCONV_TO_U1:
3970 case OP_ICONV_TO_U1:
3971 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3973 case OP_LCONV_TO_U2:
3974 case OP_ICONV_TO_U2:
3975 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3978 /* Clean out the upper word */
3979 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3982 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3986 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3988 case OP_COMPARE_IMM:
3989 #if defined(__mono_ilp32__)
3990 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3991 g_assert (amd64_is_imm32 (ins->inst_imm));
3992 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3995 case OP_LCOMPARE_IMM:
3996 g_assert (amd64_is_imm32 (ins->inst_imm));
3997 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3999 case OP_X86_COMPARE_REG_MEMBASE:
4000 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4002 case OP_X86_TEST_NULL:
4003 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4005 case OP_AMD64_TEST_NULL:
4006 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4009 case OP_X86_ADD_REG_MEMBASE:
4010 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4012 case OP_X86_SUB_REG_MEMBASE:
4013 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4015 case OP_X86_AND_REG_MEMBASE:
4016 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4018 case OP_X86_OR_REG_MEMBASE:
4019 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4021 case OP_X86_XOR_REG_MEMBASE:
4022 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4025 case OP_X86_ADD_MEMBASE_IMM:
4026 /* FIXME: Make a 64 version too */
4027 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4029 case OP_X86_SUB_MEMBASE_IMM:
4030 g_assert (amd64_is_imm32 (ins->inst_imm));
4031 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4033 case OP_X86_AND_MEMBASE_IMM:
4034 g_assert (amd64_is_imm32 (ins->inst_imm));
4035 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4037 case OP_X86_OR_MEMBASE_IMM:
4038 g_assert (amd64_is_imm32 (ins->inst_imm));
4039 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4041 case OP_X86_XOR_MEMBASE_IMM:
4042 g_assert (amd64_is_imm32 (ins->inst_imm));
4043 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4045 case OP_X86_ADD_MEMBASE_REG:
4046 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4048 case OP_X86_SUB_MEMBASE_REG:
4049 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4051 case OP_X86_AND_MEMBASE_REG:
4052 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4054 case OP_X86_OR_MEMBASE_REG:
4055 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4057 case OP_X86_XOR_MEMBASE_REG:
4058 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4060 case OP_X86_INC_MEMBASE:
4061 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4063 case OP_X86_INC_REG:
4064 amd64_inc_reg_size (code, ins->dreg, 4);
4066 case OP_X86_DEC_MEMBASE:
4067 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4069 case OP_X86_DEC_REG:
4070 amd64_dec_reg_size (code, ins->dreg, 4);
4072 case OP_X86_MUL_REG_MEMBASE:
4073 case OP_X86_MUL_MEMBASE_REG:
4074 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4076 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4077 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4079 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4080 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4082 case OP_AMD64_COMPARE_MEMBASE_REG:
4083 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4085 case OP_AMD64_COMPARE_MEMBASE_IMM:
4086 g_assert (amd64_is_imm32 (ins->inst_imm));
4087 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4089 case OP_X86_COMPARE_MEMBASE8_IMM:
4090 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4092 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4093 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4095 case OP_AMD64_COMPARE_REG_MEMBASE:
4096 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4099 case OP_AMD64_ADD_REG_MEMBASE:
4100 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4102 case OP_AMD64_SUB_REG_MEMBASE:
4103 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4105 case OP_AMD64_AND_REG_MEMBASE:
4106 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4108 case OP_AMD64_OR_REG_MEMBASE:
4109 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4111 case OP_AMD64_XOR_REG_MEMBASE:
4112 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4115 case OP_AMD64_ADD_MEMBASE_REG:
4116 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4118 case OP_AMD64_SUB_MEMBASE_REG:
4119 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4121 case OP_AMD64_AND_MEMBASE_REG:
4122 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4124 case OP_AMD64_OR_MEMBASE_REG:
4125 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4127 case OP_AMD64_XOR_MEMBASE_REG:
4128 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4131 case OP_AMD64_ADD_MEMBASE_IMM:
4132 g_assert (amd64_is_imm32 (ins->inst_imm));
4133 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4135 case OP_AMD64_SUB_MEMBASE_IMM:
4136 g_assert (amd64_is_imm32 (ins->inst_imm));
4137 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4139 case OP_AMD64_AND_MEMBASE_IMM:
4140 g_assert (amd64_is_imm32 (ins->inst_imm));
4141 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4143 case OP_AMD64_OR_MEMBASE_IMM:
4144 g_assert (amd64_is_imm32 (ins->inst_imm));
4145 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4147 case OP_AMD64_XOR_MEMBASE_IMM:
4148 g_assert (amd64_is_imm32 (ins->inst_imm));
4149 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4153 amd64_breakpoint (code);
4155 case OP_RELAXED_NOP:
4156 x86_prefix (code, X86_REP_PREFIX);
4164 case OP_DUMMY_STORE:
4165 case OP_DUMMY_ICONST:
4166 case OP_DUMMY_R8CONST:
4167 case OP_NOT_REACHED:
4170 case OP_IL_SEQ_POINT:
4171 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4173 case OP_SEQ_POINT: {
4174 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4175 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4178 /* Load ss_tramp_var */
4179 /* This is equal to &ss_trampoline */
4180 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4181 /* Load the trampoline address */
4182 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4183 /* Call it if it is non-null */
4184 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4186 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4187 amd64_call_reg (code, AMD64_R11);
4188 amd64_patch (label, code);
4192 * This is the address which is saved in seq points,
4194 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4196 if (cfg->compile_aot) {
4197 guint32 offset = code - cfg->native_code;
4199 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4203 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4204 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4205 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4206 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4207 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4209 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4210 /* Call the trampoline */
4211 amd64_call_reg (code, AMD64_R11);
4212 amd64_patch (label, code);
4214 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4218 * Emit a test+branch against a constant, the constant will be overwritten
4219 * by mono_arch_set_breakpoint () to cause the test to fail.
4221 amd64_mov_reg_imm (code, AMD64_R11, 0);
4222 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4224 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4227 g_assert (var->opcode == OP_REGOFFSET);
4228 /* Load bp_tramp_var */
4229 /* This is equal to &bp_trampoline */
4230 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4231 /* Call the trampoline */
4232 amd64_call_membase (code, AMD64_R11, 0);
4233 amd64_patch (label, code);
4236 * Add an additional nop so skipping the bp doesn't cause the ip to point
4237 * to another IL offset.
4245 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4248 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4252 g_assert (amd64_is_imm32 (ins->inst_imm));
4253 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4256 g_assert (amd64_is_imm32 (ins->inst_imm));
4257 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4262 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4265 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4269 g_assert (amd64_is_imm32 (ins->inst_imm));
4270 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4273 g_assert (amd64_is_imm32 (ins->inst_imm));
4274 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4277 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4281 g_assert (amd64_is_imm32 (ins->inst_imm));
4282 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4285 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4290 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4292 switch (ins->inst_imm) {
4296 if (ins->dreg != ins->sreg1)
4297 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4298 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4301 /* LEA r1, [r2 + r2*2] */
4302 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4305 /* LEA r1, [r2 + r2*4] */
4306 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4309 /* LEA r1, [r2 + r2*2] */
4311 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4312 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4315 /* LEA r1, [r2 + r2*8] */
4316 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4319 /* LEA r1, [r2 + r2*4] */
4321 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4322 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4325 /* LEA r1, [r2 + r2*2] */
4327 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4328 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4331 /* LEA r1, [r2 + r2*4] */
4332 /* LEA r1, [r1 + r1*4] */
4333 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4334 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4337 /* LEA r1, [r2 + r2*4] */
4339 /* LEA r1, [r1 + r1*4] */
4340 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4341 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4342 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4345 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4352 /* Regalloc magic makes the div/rem cases the same */
4353 if (ins->sreg2 == AMD64_RDX) {
4354 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4356 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4359 amd64_div_reg (code, ins->sreg2, TRUE);
4364 if (ins->sreg2 == AMD64_RDX) {
4365 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4366 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4367 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4369 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4370 amd64_div_reg (code, ins->sreg2, FALSE);
4375 if (ins->sreg2 == AMD64_RDX) {
4376 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4377 amd64_cdq_size (code, 4);
4378 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4380 amd64_cdq_size (code, 4);
4381 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4386 if (ins->sreg2 == AMD64_RDX) {
4387 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4388 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4389 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4391 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4392 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4396 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4397 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4400 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4404 g_assert (amd64_is_imm32 (ins->inst_imm));
4405 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4408 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4412 g_assert (amd64_is_imm32 (ins->inst_imm));
4413 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4416 g_assert (ins->sreg2 == AMD64_RCX);
4417 amd64_shift_reg (code, X86_SHL, ins->dreg);
4420 g_assert (ins->sreg2 == AMD64_RCX);
4421 amd64_shift_reg (code, X86_SAR, ins->dreg);
4425 g_assert (amd64_is_imm32 (ins->inst_imm));
4426 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4429 g_assert (amd64_is_imm32 (ins->inst_imm));
4430 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4432 case OP_LSHR_UN_IMM:
4433 g_assert (amd64_is_imm32 (ins->inst_imm));
4434 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4437 g_assert (ins->sreg2 == AMD64_RCX);
4438 amd64_shift_reg (code, X86_SHR, ins->dreg);
4442 g_assert (amd64_is_imm32 (ins->inst_imm));
4443 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4448 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4451 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4454 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4457 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4461 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4464 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4467 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4470 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4473 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4476 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4479 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4482 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4485 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4488 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4491 amd64_neg_reg_size (code, ins->sreg1, 4);
4494 amd64_not_reg_size (code, ins->sreg1, 4);
4497 g_assert (ins->sreg2 == AMD64_RCX);
4498 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4501 g_assert (ins->sreg2 == AMD64_RCX);
4502 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4505 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4507 case OP_ISHR_UN_IMM:
4508 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4511 g_assert (ins->sreg2 == AMD64_RCX);
4512 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4515 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4518 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4521 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4522 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4524 case OP_IMUL_OVF_UN:
4525 case OP_LMUL_OVF_UN: {
4526 /* the mul operation and the exception check should most likely be split */
4527 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4528 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4529 /*g_assert (ins->sreg2 == X86_EAX);
4530 g_assert (ins->dreg == X86_EAX);*/
4531 if (ins->sreg2 == X86_EAX) {
4532 non_eax_reg = ins->sreg1;
4533 } else if (ins->sreg1 == X86_EAX) {
4534 non_eax_reg = ins->sreg2;
4536 /* no need to save since we're going to store to it anyway */
4537 if (ins->dreg != X86_EAX) {
4539 amd64_push_reg (code, X86_EAX);
4541 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4542 non_eax_reg = ins->sreg2;
4544 if (ins->dreg == X86_EDX) {
4547 amd64_push_reg (code, X86_EAX);
4551 amd64_push_reg (code, X86_EDX);
4553 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4554 /* save before the check since pop and mov don't change the flags */
4555 if (ins->dreg != X86_EAX)
4556 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4558 amd64_pop_reg (code, X86_EDX);
4560 amd64_pop_reg (code, X86_EAX);
4561 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4565 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4567 case OP_ICOMPARE_IMM:
4568 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4590 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4598 case OP_CMOV_INE_UN:
4599 case OP_CMOV_IGE_UN:
4600 case OP_CMOV_IGT_UN:
4601 case OP_CMOV_ILE_UN:
4602 case OP_CMOV_ILT_UN:
4608 case OP_CMOV_LNE_UN:
4609 case OP_CMOV_LGE_UN:
4610 case OP_CMOV_LGT_UN:
4611 case OP_CMOV_LLE_UN:
4612 case OP_CMOV_LLT_UN:
4613 g_assert (ins->dreg == ins->sreg1);
4614 /* This needs to operate on 64 bit values */
4615 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4619 amd64_not_reg (code, ins->sreg1);
4622 amd64_neg_reg (code, ins->sreg1);
4627 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4628 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4630 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4633 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4634 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4637 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4638 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4641 if (ins->dreg != ins->sreg1)
4642 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4644 case OP_AMD64_SET_XMMREG_R4: {
4646 if (ins->dreg != ins->sreg1)
4647 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4649 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4653 case OP_AMD64_SET_XMMREG_R8: {
4654 if (ins->dreg != ins->sreg1)
4655 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4659 MonoCallInst *call = (MonoCallInst*)ins;
4660 int i, save_area_offset;
4662 g_assert (!cfg->method->save_lmf);
4664 /* Restore callee saved registers */
4665 save_area_offset = cfg->arch.reg_save_area_offset;
4666 for (i = 0; i < AMD64_NREG; ++i)
4667 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4668 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4669 save_area_offset += 8;
4672 if (cfg->arch.omit_fp) {
4673 if (cfg->arch.stack_alloc_size)
4674 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4676 if (call->stack_usage)
4679 /* Copy arguments on the stack to our argument area */
4680 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4681 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4682 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4688 offset = code - cfg->native_code;
4689 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4690 if (cfg->compile_aot)
4691 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4693 amd64_set_reg_template (code, AMD64_R11);
4694 amd64_jump_reg (code, AMD64_R11);
4695 ins->flags |= MONO_INST_GC_CALLSITE;
4696 ins->backend.pc_offset = code - cfg->native_code;
4700 /* ensure ins->sreg1 is not NULL */
4701 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4704 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4705 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4715 call = (MonoCallInst*)ins;
4717 * The AMD64 ABI forces callers to know about varargs.
4719 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4720 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4721 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4723 * Since the unmanaged calling convention doesn't contain a
4724 * 'vararg' entry, we have to treat every pinvoke call as a
4725 * potential vararg call.
4729 for (i = 0; i < AMD64_XMM_NREG; ++i)
4730 if (call->used_fregs & (1 << i))
4733 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4735 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4738 if (ins->flags & MONO_INST_HAS_METHOD)
4739 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4741 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4742 ins->flags |= MONO_INST_GC_CALLSITE;
4743 ins->backend.pc_offset = code - cfg->native_code;
4744 code = emit_move_return_value (cfg, ins, code);
4751 case OP_VOIDCALL_REG:
4753 call = (MonoCallInst*)ins;
4755 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4756 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4757 ins->sreg1 = AMD64_R11;
4761 * The AMD64 ABI forces callers to know about varargs.
4763 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4764 if (ins->sreg1 == AMD64_RAX) {
4765 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4766 ins->sreg1 = AMD64_R11;
4768 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4769 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4771 * Since the unmanaged calling convention doesn't contain a
4772 * 'vararg' entry, we have to treat every pinvoke call as a
4773 * potential vararg call.
4777 for (i = 0; i < AMD64_XMM_NREG; ++i)
4778 if (call->used_fregs & (1 << i))
4780 if (ins->sreg1 == AMD64_RAX) {
4781 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4782 ins->sreg1 = AMD64_R11;
4785 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4787 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4790 amd64_call_reg (code, ins->sreg1);
4791 ins->flags |= MONO_INST_GC_CALLSITE;
4792 ins->backend.pc_offset = code - cfg->native_code;
4793 code = emit_move_return_value (cfg, ins, code);
4795 case OP_FCALL_MEMBASE:
4796 case OP_RCALL_MEMBASE:
4797 case OP_LCALL_MEMBASE:
4798 case OP_VCALL_MEMBASE:
4799 case OP_VCALL2_MEMBASE:
4800 case OP_VOIDCALL_MEMBASE:
4801 case OP_CALL_MEMBASE:
4802 call = (MonoCallInst*)ins;
4804 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4805 ins->flags |= MONO_INST_GC_CALLSITE;
4806 ins->backend.pc_offset = code - cfg->native_code;
4807 code = emit_move_return_value (cfg, ins, code);
4811 MonoInst *var = cfg->dyn_call_var;
4814 g_assert (var->opcode == OP_REGOFFSET);
4816 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4817 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4819 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4821 /* Save args buffer */
4822 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4824 /* Set fp arg regs */
4825 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4826 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4828 amd64_branch8 (code, X86_CC_Z, -1, 1);
4829 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4830 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4831 amd64_patch (label, code);
4833 /* Set stack args */
4834 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4835 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4836 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4839 /* Set argument registers */
4840 for (i = 0; i < PARAM_REGS; ++i)
4841 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4844 amd64_call_reg (code, AMD64_R10);
4846 ins->flags |= MONO_INST_GC_CALLSITE;
4847 ins->backend.pc_offset = code - cfg->native_code;
4850 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4851 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4852 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4853 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4856 case OP_AMD64_SAVE_SP_TO_LMF: {
4857 MonoInst *lmf_var = cfg->lmf_var;
4858 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4862 g_assert_not_reached ();
4863 amd64_push_reg (code, ins->sreg1);
4865 case OP_X86_PUSH_IMM:
4866 g_assert_not_reached ();
4867 g_assert (amd64_is_imm32 (ins->inst_imm));
4868 amd64_push_imm (code, ins->inst_imm);
4870 case OP_X86_PUSH_MEMBASE:
4871 g_assert_not_reached ();
4872 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4874 case OP_X86_PUSH_OBJ: {
4875 int size = ALIGN_TO (ins->inst_imm, 8);
4877 g_assert_not_reached ();
4879 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4880 amd64_push_reg (code, AMD64_RDI);
4881 amd64_push_reg (code, AMD64_RSI);
4882 amd64_push_reg (code, AMD64_RCX);
4883 if (ins->inst_offset)
4884 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4886 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4887 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4888 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4890 amd64_prefix (code, X86_REP_PREFIX);
4892 amd64_pop_reg (code, AMD64_RCX);
4893 amd64_pop_reg (code, AMD64_RSI);
4894 amd64_pop_reg (code, AMD64_RDI);
4897 case OP_GENERIC_CLASS_INIT: {
4898 static int byte_offset = -1;
4899 static guint8 bitmask;
4902 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4904 if (byte_offset < 0)
4905 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4907 amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4909 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4911 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4912 ins->flags |= MONO_INST_GC_CALLSITE;
4913 ins->backend.pc_offset = code - cfg->native_code;
4915 x86_patch (jump, code);
4920 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4922 case OP_X86_LEA_MEMBASE:
4923 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4926 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4929 /* keep alignment */
4930 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4931 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4932 code = mono_emit_stack_alloc (cfg, code, ins);
4933 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4934 if (cfg->param_area)
4935 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4937 case OP_LOCALLOC_IMM: {
4938 guint32 size = ins->inst_imm;
4939 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4941 if (ins->flags & MONO_INST_INIT) {
4945 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4946 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4948 for (i = 0; i < size; i += 8)
4949 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4950 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4952 amd64_mov_reg_imm (code, ins->dreg, size);
4953 ins->sreg1 = ins->dreg;
4955 code = mono_emit_stack_alloc (cfg, code, ins);
4956 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4959 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4960 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4962 if (cfg->param_area)
4963 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4967 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4968 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4969 (gpointer)"mono_arch_throw_exception", FALSE);
4970 ins->flags |= MONO_INST_GC_CALLSITE;
4971 ins->backend.pc_offset = code - cfg->native_code;
4975 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4976 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4977 (gpointer)"mono_arch_rethrow_exception", FALSE);
4978 ins->flags |= MONO_INST_GC_CALLSITE;
4979 ins->backend.pc_offset = code - cfg->native_code;
4982 case OP_CALL_HANDLER:
4984 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4985 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4986 amd64_call_imm (code, 0);
4987 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4988 /* Restore stack alignment */
4989 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4991 case OP_START_HANDLER: {
4992 /* Even though we're saving RSP, use sizeof */
4993 /* gpointer because spvar is of type IntPtr */
4994 /* see: mono_create_spvar_for_region */
4995 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4996 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4998 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4999 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5001 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5005 case OP_ENDFINALLY: {
5006 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5007 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5011 case OP_ENDFILTER: {
5012 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5013 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5014 /* The local allocator will put the result into RAX */
5019 if (ins->dreg != AMD64_RAX)
5020 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5023 ins->inst_c0 = code - cfg->native_code;
5026 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5027 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5029 if (ins->inst_target_bb->native_offset) {
5030 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5032 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5033 if ((cfg->opt & MONO_OPT_BRANCH) &&
5034 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5035 x86_jump8 (code, 0);
5037 x86_jump32 (code, 0);
5041 amd64_jump_reg (code, ins->sreg1);
5064 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5065 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5067 case OP_COND_EXC_EQ:
5068 case OP_COND_EXC_NE_UN:
5069 case OP_COND_EXC_LT:
5070 case OP_COND_EXC_LT_UN:
5071 case OP_COND_EXC_GT:
5072 case OP_COND_EXC_GT_UN:
5073 case OP_COND_EXC_GE:
5074 case OP_COND_EXC_GE_UN:
5075 case OP_COND_EXC_LE:
5076 case OP_COND_EXC_LE_UN:
5077 case OP_COND_EXC_IEQ:
5078 case OP_COND_EXC_INE_UN:
5079 case OP_COND_EXC_ILT:
5080 case OP_COND_EXC_ILT_UN:
5081 case OP_COND_EXC_IGT:
5082 case OP_COND_EXC_IGT_UN:
5083 case OP_COND_EXC_IGE:
5084 case OP_COND_EXC_IGE_UN:
5085 case OP_COND_EXC_ILE:
5086 case OP_COND_EXC_ILE_UN:
5087 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5089 case OP_COND_EXC_OV:
5090 case OP_COND_EXC_NO:
5092 case OP_COND_EXC_NC:
5093 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5094 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5096 case OP_COND_EXC_IOV:
5097 case OP_COND_EXC_INO:
5098 case OP_COND_EXC_IC:
5099 case OP_COND_EXC_INC:
5100 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5101 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5104 /* floating point opcodes */
5106 double d = *(double *)ins->inst_p0;
5108 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5109 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5112 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5113 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5118 float f = *(float *)ins->inst_p0;
5120 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5122 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5124 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5127 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5128 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5130 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5134 case OP_STORER8_MEMBASE_REG:
5135 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5137 case OP_LOADR8_MEMBASE:
5138 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5140 case OP_STORER4_MEMBASE_REG:
5142 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5144 /* This requires a double->single conversion */
5145 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5146 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5149 case OP_LOADR4_MEMBASE:
5151 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5153 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5154 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5157 case OP_ICONV_TO_R4:
5159 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5161 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5162 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5165 case OP_ICONV_TO_R8:
5166 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5168 case OP_LCONV_TO_R4:
5170 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5172 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5173 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5176 case OP_LCONV_TO_R8:
5177 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5179 case OP_FCONV_TO_R4:
5181 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5183 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5184 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5187 case OP_FCONV_TO_I1:
5188 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5190 case OP_FCONV_TO_U1:
5191 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5193 case OP_FCONV_TO_I2:
5194 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5196 case OP_FCONV_TO_U2:
5197 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5199 case OP_FCONV_TO_U4:
5200 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5202 case OP_FCONV_TO_I4:
5204 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5206 case OP_FCONV_TO_I8:
5207 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5210 case OP_RCONV_TO_I1:
5211 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5212 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5214 case OP_RCONV_TO_U1:
5215 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5216 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5218 case OP_RCONV_TO_I2:
5219 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5220 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5222 case OP_RCONV_TO_U2:
5223 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5224 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5226 case OP_RCONV_TO_I4:
5227 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5229 case OP_RCONV_TO_U4:
5230 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5232 case OP_RCONV_TO_I8:
5233 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5235 case OP_RCONV_TO_R8:
5236 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5238 case OP_RCONV_TO_R4:
5239 if (ins->dreg != ins->sreg1)
5240 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5243 case OP_LCONV_TO_R_UN: {
5246 /* Based on gcc code */
5247 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5248 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5251 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5252 br [1] = code; x86_jump8 (code, 0);
5253 amd64_patch (br [0], code);
5256 /* Save to the red zone */
5257 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5258 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5259 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5260 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5261 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5262 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5263 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5264 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5265 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5267 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5268 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5269 amd64_patch (br [1], code);
5272 case OP_LCONV_TO_OVF_U4:
5273 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5274 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5275 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5277 case OP_LCONV_TO_OVF_I4_UN:
5278 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5279 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5280 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5283 if (ins->dreg != ins->sreg1)
5284 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5287 if (ins->dreg != ins->sreg1)
5288 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5290 case OP_MOVE_F_TO_I4:
5292 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5294 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5295 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5298 case OP_MOVE_I4_TO_F:
5299 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5301 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5303 case OP_MOVE_F_TO_I8:
5304 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5306 case OP_MOVE_I8_TO_F:
5307 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5310 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5313 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5316 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5319 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5322 static double r8_0 = -0.0;
5324 g_assert (ins->sreg1 == ins->dreg);
5326 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5327 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5331 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5334 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5337 static guint64 d = 0x7fffffffffffffffUL;
5339 g_assert (ins->sreg1 == ins->dreg);
5341 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5342 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5346 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5350 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5353 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5356 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5359 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5362 static float r4_0 = -0.0;
5364 g_assert (ins->sreg1 == ins->dreg);
5366 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5367 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5368 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5373 g_assert (cfg->opt & MONO_OPT_CMOV);
5374 g_assert (ins->dreg == ins->sreg1);
5375 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5376 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5379 g_assert (cfg->opt & MONO_OPT_CMOV);
5380 g_assert (ins->dreg == ins->sreg1);
5381 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5382 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5385 g_assert (cfg->opt & MONO_OPT_CMOV);
5386 g_assert (ins->dreg == ins->sreg1);
5387 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5388 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5391 g_assert (cfg->opt & MONO_OPT_CMOV);
5392 g_assert (ins->dreg == ins->sreg1);
5393 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5394 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5397 g_assert (cfg->opt & MONO_OPT_CMOV);
5398 g_assert (ins->dreg == ins->sreg1);
5399 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5400 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5403 g_assert (cfg->opt & MONO_OPT_CMOV);
5404 g_assert (ins->dreg == ins->sreg1);
5405 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5406 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5409 g_assert (cfg->opt & MONO_OPT_CMOV);
5410 g_assert (ins->dreg == ins->sreg1);
5411 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5412 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5415 g_assert (cfg->opt & MONO_OPT_CMOV);
5416 g_assert (ins->dreg == ins->sreg1);
5417 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5418 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5424 * The two arguments are swapped because the fbranch instructions
5425 * depend on this for the non-sse case to work.
5427 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5431 * FIXME: Get rid of this.
5432 * The two arguments are swapped because the fbranch instructions
5433 * depend on this for the non-sse case to work.
5435 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5439 /* zeroing the register at the start results in
5440 * shorter and faster code (we can also remove the widening op)
5442 guchar *unordered_check;
5444 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5445 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5446 unordered_check = code;
5447 x86_branch8 (code, X86_CC_P, 0, FALSE);
5449 if (ins->opcode == OP_FCEQ) {
5450 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5451 amd64_patch (unordered_check, code);
5453 guchar *jump_to_end;
5454 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5456 x86_jump8 (code, 0);
5457 amd64_patch (unordered_check, code);
5458 amd64_inc_reg (code, ins->dreg);
5459 amd64_patch (jump_to_end, code);
5465 /* zeroing the register at the start results in
5466 * shorter and faster code (we can also remove the widening op)
5468 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5469 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5470 if (ins->opcode == OP_FCLT_UN) {
5471 guchar *unordered_check = code;
5472 guchar *jump_to_end;
5473 x86_branch8 (code, X86_CC_P, 0, FALSE);
5474 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5476 x86_jump8 (code, 0);
5477 amd64_patch (unordered_check, code);
5478 amd64_inc_reg (code, ins->dreg);
5479 amd64_patch (jump_to_end, code);
5481 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5486 guchar *unordered_check;
5487 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5488 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5489 unordered_check = code;
5490 x86_branch8 (code, X86_CC_P, 0, FALSE);
5491 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5492 amd64_patch (unordered_check, code);
5497 /* zeroing the register at the start results in
5498 * shorter and faster code (we can also remove the widening op)
5500 guchar *unordered_check;
5502 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5503 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5504 if (ins->opcode == OP_FCGT) {
5505 unordered_check = code;
5506 x86_branch8 (code, X86_CC_P, 0, FALSE);
5507 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5508 amd64_patch (unordered_check, code);
5510 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5515 guchar *unordered_check;
5516 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5517 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5518 unordered_check = code;
5519 x86_branch8 (code, X86_CC_P, 0, FALSE);
5520 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5521 amd64_patch (unordered_check, code);
5531 gboolean unordered = FALSE;
5533 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5534 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5536 switch (ins->opcode) {
5538 x86_cond = X86_CC_EQ;
5541 x86_cond = X86_CC_LT;
5544 x86_cond = X86_CC_GT;
5547 x86_cond = X86_CC_GT;
5551 x86_cond = X86_CC_LT;
5555 g_assert_not_reached ();
5560 guchar *unordered_check;
5561 guchar *jump_to_end;
5563 unordered_check = code;
5564 x86_branch8 (code, X86_CC_P, 0, FALSE);
5565 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5567 x86_jump8 (code, 0);
5568 amd64_patch (unordered_check, code);
5569 amd64_inc_reg (code, ins->dreg);
5570 amd64_patch (jump_to_end, code);
5572 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5576 case OP_FCLT_MEMBASE:
5577 case OP_FCGT_MEMBASE:
5578 case OP_FCLT_UN_MEMBASE:
5579 case OP_FCGT_UN_MEMBASE:
5580 case OP_FCEQ_MEMBASE: {
5581 guchar *unordered_check, *jump_to_end;
5584 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5585 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5587 switch (ins->opcode) {
5588 case OP_FCEQ_MEMBASE:
5589 x86_cond = X86_CC_EQ;
5591 case OP_FCLT_MEMBASE:
5592 case OP_FCLT_UN_MEMBASE:
5593 x86_cond = X86_CC_LT;
5595 case OP_FCGT_MEMBASE:
5596 case OP_FCGT_UN_MEMBASE:
5597 x86_cond = X86_CC_GT;
5600 g_assert_not_reached ();
5603 unordered_check = code;
5604 x86_branch8 (code, X86_CC_P, 0, FALSE);
5605 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5607 switch (ins->opcode) {
5608 case OP_FCEQ_MEMBASE:
5609 case OP_FCLT_MEMBASE:
5610 case OP_FCGT_MEMBASE:
5611 amd64_patch (unordered_check, code);
5613 case OP_FCLT_UN_MEMBASE:
5614 case OP_FCGT_UN_MEMBASE:
5616 x86_jump8 (code, 0);
5617 amd64_patch (unordered_check, code);
5618 amd64_inc_reg (code, ins->dreg);
5619 amd64_patch (jump_to_end, code);
5627 guchar *jump = code;
5628 x86_branch8 (code, X86_CC_P, 0, TRUE);
5629 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5630 amd64_patch (jump, code);
5634 /* Branch if C013 != 100 */
5635 /* branch if !ZF or (PF|CF) */
5636 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5637 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5638 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5641 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5644 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5645 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5649 if (ins->opcode == OP_FBGT) {
5652 /* skip branch if C1=1 */
5654 x86_branch8 (code, X86_CC_P, 0, FALSE);
5655 /* branch if (C0 | C3) = 1 */
5656 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5657 amd64_patch (br1, code);
5660 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5664 /* Branch if C013 == 100 or 001 */
5667 /* skip branch if C1=1 */
5669 x86_branch8 (code, X86_CC_P, 0, FALSE);
5670 /* branch if (C0 | C3) = 1 */
5671 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5672 amd64_patch (br1, code);
5676 /* Branch if C013 == 000 */
5677 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5680 /* Branch if C013=000 or 100 */
5683 /* skip branch if C1=1 */
5685 x86_branch8 (code, X86_CC_P, 0, FALSE);
5686 /* branch if C0=0 */
5687 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5688 amd64_patch (br1, code);
5692 /* Branch if C013 != 001 */
5693 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5694 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5697 /* Transfer value to the fp stack */
5698 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5699 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5700 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5702 amd64_push_reg (code, AMD64_RAX);
5704 amd64_fnstsw (code);
5705 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5706 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5707 amd64_pop_reg (code, AMD64_RAX);
5708 amd64_fstp (code, 0);
5709 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5710 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5713 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5716 case OP_TLS_GET_REG:
5717 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5720 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5723 case OP_TLS_SET_REG: {
5724 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5727 case OP_MEMORY_BARRIER: {
5728 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5732 case OP_ATOMIC_ADD_I4:
5733 case OP_ATOMIC_ADD_I8: {
5734 int dreg = ins->dreg;
5735 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5737 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5740 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5741 amd64_prefix (code, X86_LOCK_PREFIX);
5742 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5743 /* dreg contains the old value, add with sreg2 value */
5744 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5746 if (ins->dreg != dreg)
5747 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5751 case OP_ATOMIC_EXCHANGE_I4:
5752 case OP_ATOMIC_EXCHANGE_I8: {
5753 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5755 /* LOCK prefix is implied. */
5756 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5757 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5758 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5761 case OP_ATOMIC_CAS_I4:
5762 case OP_ATOMIC_CAS_I8: {
5765 if (ins->opcode == OP_ATOMIC_CAS_I8)
5771 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5772 * an explanation of how this works.
5774 g_assert (ins->sreg3 == AMD64_RAX);
5775 g_assert (ins->sreg1 != AMD64_RAX);
5776 g_assert (ins->sreg1 != ins->sreg2);
5778 amd64_prefix (code, X86_LOCK_PREFIX);
5779 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5781 if (ins->dreg != AMD64_RAX)
5782 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5785 case OP_ATOMIC_LOAD_I1: {
5786 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5789 case OP_ATOMIC_LOAD_U1: {
5790 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5793 case OP_ATOMIC_LOAD_I2: {
5794 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5797 case OP_ATOMIC_LOAD_U2: {
5798 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5801 case OP_ATOMIC_LOAD_I4: {
5802 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5805 case OP_ATOMIC_LOAD_U4:
5806 case OP_ATOMIC_LOAD_I8:
5807 case OP_ATOMIC_LOAD_U8: {
5808 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5811 case OP_ATOMIC_LOAD_R4: {
5812 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5813 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5816 case OP_ATOMIC_LOAD_R8: {
5817 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5820 case OP_ATOMIC_STORE_I1:
5821 case OP_ATOMIC_STORE_U1:
5822 case OP_ATOMIC_STORE_I2:
5823 case OP_ATOMIC_STORE_U2:
5824 case OP_ATOMIC_STORE_I4:
5825 case OP_ATOMIC_STORE_U4:
5826 case OP_ATOMIC_STORE_I8:
5827 case OP_ATOMIC_STORE_U8: {
5830 switch (ins->opcode) {
5831 case OP_ATOMIC_STORE_I1:
5832 case OP_ATOMIC_STORE_U1:
5835 case OP_ATOMIC_STORE_I2:
5836 case OP_ATOMIC_STORE_U2:
5839 case OP_ATOMIC_STORE_I4:
5840 case OP_ATOMIC_STORE_U4:
5843 case OP_ATOMIC_STORE_I8:
5844 case OP_ATOMIC_STORE_U8:
5849 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5851 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5855 case OP_ATOMIC_STORE_R4: {
5856 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5857 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5859 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5863 case OP_ATOMIC_STORE_R8: {
5866 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5870 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5874 case OP_CARD_TABLE_WBARRIER: {
5875 int ptr = ins->sreg1;
5876 int value = ins->sreg2;
5878 int nursery_shift, card_table_shift;
5879 gpointer card_table_mask;
5880 size_t nursery_size;
5882 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5883 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5884 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5886 /*If either point to the stack we can simply avoid the WB. This happens due to
5887 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5889 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5893 * We need one register we can clobber, we choose EDX and make sreg1
5894 * fixed EAX to work around limitations in the local register allocator.
5895 * sreg2 might get allocated to EDX, but that is not a problem since
5896 * we use it before clobbering EDX.
5898 g_assert (ins->sreg1 == AMD64_RAX);
5901 * This is the code we produce:
5904 * edx >>= nursery_shift
5905 * cmp edx, (nursery_start >> nursery_shift)
5908 * edx >>= card_table_shift
5914 if (mono_gc_card_table_nursery_check ()) {
5915 if (value != AMD64_RDX)
5916 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5917 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5918 if (shifted_nursery_start >> 31) {
5920 * The value we need to compare against is 64 bits, so we need
5921 * another spare register. We use RBX, which we save and
5924 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5925 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5926 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5927 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5929 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5931 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5933 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5934 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5935 if (card_table_mask)
5936 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5938 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5939 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5941 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5943 if (mono_gc_card_table_nursery_check ())
5944 x86_patch (br, code);
5947 #ifdef MONO_ARCH_SIMD_INTRINSICS
5948 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5950 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5953 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5956 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5959 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5962 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5965 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5968 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5969 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5972 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5975 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5978 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5981 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5984 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5987 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5990 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5993 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5996 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5999 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6005 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6008 case OP_PSHUFLEW_HIGH:
6009 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6010 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6012 case OP_PSHUFLEW_LOW:
6013 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6014 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6017 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6018 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6021 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6022 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6025 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6026 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6030 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6033 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6036 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6039 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6042 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6045 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6048 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6049 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6052 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6055 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6058 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6061 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6064 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6067 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6070 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6073 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6076 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6079 case OP_EXTRACT_MASK:
6080 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6084 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6087 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6090 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6097 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6100 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6103 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6107 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6110 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6113 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6116 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6120 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6123 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6126 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6130 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6133 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6136 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6140 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6143 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6147 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6150 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6153 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6157 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6160 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6163 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6167 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6170 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6173 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6176 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6180 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6183 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6186 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6189 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6192 case OP_PSUM_ABS_DIFF:
6193 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6196 case OP_UNPACK_LOWB:
6197 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6199 case OP_UNPACK_LOWW:
6200 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6202 case OP_UNPACK_LOWD:
6203 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6205 case OP_UNPACK_LOWQ:
6206 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6208 case OP_UNPACK_LOWPS:
6209 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6211 case OP_UNPACK_LOWPD:
6212 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6215 case OP_UNPACK_HIGHB:
6216 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6218 case OP_UNPACK_HIGHW:
6219 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6221 case OP_UNPACK_HIGHD:
6222 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6224 case OP_UNPACK_HIGHQ:
6225 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6227 case OP_UNPACK_HIGHPS:
6228 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6230 case OP_UNPACK_HIGHPD:
6231 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6235 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6238 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6241 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6244 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6247 case OP_PADDB_SAT_UN:
6248 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6250 case OP_PSUBB_SAT_UN:
6251 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6253 case OP_PADDW_SAT_UN:
6254 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6256 case OP_PSUBW_SAT_UN:
6257 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6261 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6264 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6267 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6270 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6274 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6277 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6280 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6282 case OP_PMULW_HIGH_UN:
6283 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6286 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6290 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6293 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6297 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6300 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6304 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6307 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6311 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6314 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6318 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6321 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6325 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6328 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6332 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6335 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6338 /*TODO: This is appart of the sse spec but not added
6340 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6343 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6348 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6351 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6354 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6357 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6360 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6363 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6366 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6369 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6372 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6375 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6379 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6382 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6386 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6387 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6389 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6394 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6396 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6397 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6401 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6403 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6404 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6405 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6409 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6411 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6414 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6416 case OP_EXTRACTX_U2:
6417 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6419 case OP_INSERTX_U1_SLOW:
6420 /*sreg1 is the extracted ireg (scratch)
6421 /sreg2 is the to be inserted ireg (scratch)
6422 /dreg is the xreg to receive the value*/
6424 /*clear the bits from the extracted word*/
6425 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6426 /*shift the value to insert if needed*/
6427 if (ins->inst_c0 & 1)
6428 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6429 /*join them together*/
6430 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6431 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6433 case OP_INSERTX_I4_SLOW:
6434 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6435 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6436 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6438 case OP_INSERTX_I8_SLOW:
6439 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6441 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6443 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6446 case OP_INSERTX_R4_SLOW:
6447 switch (ins->inst_c0) {
6450 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6452 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6455 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6457 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6459 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6460 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6463 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6465 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6467 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6468 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6471 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6473 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6475 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6476 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6480 case OP_INSERTX_R8_SLOW:
6482 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6484 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6486 case OP_STOREX_MEMBASE_REG:
6487 case OP_STOREX_MEMBASE:
6488 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6490 case OP_LOADX_MEMBASE:
6491 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6493 case OP_LOADX_ALIGNED_MEMBASE:
6494 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6496 case OP_STOREX_ALIGNED_MEMBASE_REG:
6497 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6499 case OP_STOREX_NTA_MEMBASE_REG:
6500 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6502 case OP_PREFETCH_MEMBASE:
6503 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6507 /*FIXME the peephole pass should have killed this*/
6508 if (ins->dreg != ins->sreg1)
6509 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6512 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6514 case OP_ICONV_TO_R4_RAW:
6515 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6518 case OP_FCONV_TO_R8_X:
6519 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6522 case OP_XCONV_R8_TO_I4:
6523 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6524 switch (ins->backend.source_opcode) {
6525 case OP_FCONV_TO_I1:
6526 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6528 case OP_FCONV_TO_U1:
6529 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6531 case OP_FCONV_TO_I2:
6532 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6534 case OP_FCONV_TO_U2:
6535 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6541 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6542 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6543 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6546 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6547 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6550 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6551 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6555 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6557 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6558 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6560 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6563 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6564 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6567 case OP_LIVERANGE_START: {
6568 if (cfg->verbose_level > 1)
6569 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6570 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6573 case OP_LIVERANGE_END: {
6574 if (cfg->verbose_level > 1)
6575 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6576 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6579 case OP_GC_SAFE_POINT: {
6582 g_assert (mono_threads_is_coop_enabled ());
6584 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6585 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6586 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6587 amd64_patch (br[0], code);
6591 case OP_GC_LIVENESS_DEF:
6592 case OP_GC_LIVENESS_USE:
6593 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6594 ins->backend.pc_offset = code - cfg->native_code;
6596 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6597 ins->backend.pc_offset = code - cfg->native_code;
6598 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6600 case OP_GET_LAST_ERROR:
6601 emit_get_last_error(code, ins->dreg);
6604 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6605 g_assert_not_reached ();
6608 if ((code - cfg->native_code - offset) > max_len) {
6609 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6610 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6611 g_assert_not_reached ();
6615 cfg->code_len = code - cfg->native_code;
6618 #endif /* DISABLE_JIT */
6621 mono_arch_register_lowlevel_calls (void)
6623 /* The signature doesn't matter */
6624 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6628 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6630 unsigned char *ip = ji->ip.i + code;
6633 * Debug code to help track down problems where the target of a near call is
6636 if (amd64_is_near_call (ip)) {
6637 gint64 disp = (guint8*)target - (guint8*)ip;
6639 if (!amd64_is_imm32 (disp)) {
6640 printf ("TYPE: %d\n", ji->type);
6642 case MONO_PATCH_INFO_INTERNAL_METHOD:
6643 printf ("V: %s\n", ji->data.name);
6645 case MONO_PATCH_INFO_METHOD_JUMP:
6646 case MONO_PATCH_INFO_METHOD:
6647 printf ("V: %s\n", ji->data.method->name);
6655 amd64_patch (ip, (gpointer)target);
6661 get_max_epilog_size (MonoCompile *cfg)
6663 int max_epilog_size = 16;
6665 if (cfg->method->save_lmf)
6666 max_epilog_size += 256;
6668 if (mono_jit_trace_calls != NULL)
6669 max_epilog_size += 50;
6671 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6672 max_epilog_size += 50;
6674 max_epilog_size += (AMD64_NREG * 2);
6676 return max_epilog_size;
6680 * This macro is used for testing whenever the unwinder works correctly at every point
6681 * where an async exception can happen.
6683 /* This will generate a SIGSEGV at the given point in the code */
6684 #define async_exc_point(code) do { \
6685 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6686 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6687 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6688 cfg->arch.async_point_count ++; \
6693 mono_arch_emit_prolog (MonoCompile *cfg)
6695 MonoMethod *method = cfg->method;
6697 MonoMethodSignature *sig;
6699 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6702 MonoInst *lmf_var = cfg->lmf_var;
6703 gboolean args_clobbered = FALSE;
6704 gboolean trace = FALSE;
6706 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6708 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6710 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6713 /* Amount of stack space allocated by register saving code */
6716 /* Offset between RSP and the CFA */
6720 * The prolog consists of the following parts:
6722 * - push rbp, mov rbp, rsp
6723 * - save callee saved regs using pushes
6725 * - save rgctx if needed
6726 * - save lmf if needed
6729 * - save rgctx if needed
6730 * - save lmf if needed
6731 * - save callee saved regs using moves
6736 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6737 // IP saved at CFA - 8
6738 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6739 async_exc_point (code);
6740 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6742 if (!cfg->arch.omit_fp) {
6743 amd64_push_reg (code, AMD64_RBP);
6745 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6746 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6747 async_exc_point (code);
6749 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6751 /* These are handled automatically by the stack marking code */
6752 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6754 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6755 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6756 async_exc_point (code);
6758 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6762 /* The param area is always at offset 0 from sp */
6763 /* This needs to be allocated here, since it has to come after the spill area */
6764 if (cfg->param_area) {
6765 if (cfg->arch.omit_fp)
6767 g_assert_not_reached ();
6768 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6771 if (cfg->arch.omit_fp) {
6773 * On enter, the stack is misaligned by the pushing of the return
6774 * address. It is either made aligned by the pushing of %rbp, or by
6777 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6778 if ((alloc_size % 16) == 0) {
6780 /* Mark the padding slot as NOREF */
6781 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6784 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6785 if (cfg->stack_offset != alloc_size) {
6786 /* Mark the padding slot as NOREF */
6787 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6789 cfg->arch.sp_fp_offset = alloc_size;
6793 cfg->arch.stack_alloc_size = alloc_size;
6795 /* Allocate stack frame */
6797 /* See mono_emit_stack_alloc */
6798 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6799 guint32 remaining_size = alloc_size;
6800 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6801 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6802 guint32 offset = code - cfg->native_code;
6803 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6804 while (required_code_size >= (cfg->code_size - offset))
6805 cfg->code_size *= 2;
6806 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6807 code = cfg->native_code + offset;
6808 cfg->stat_code_reallocs++;
6811 while (remaining_size >= 0x1000) {
6812 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6813 if (cfg->arch.omit_fp) {
6814 cfa_offset += 0x1000;
6815 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6817 async_exc_point (code);
6819 if (cfg->arch.omit_fp)
6820 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6823 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6824 remaining_size -= 0x1000;
6826 if (remaining_size) {
6827 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6828 if (cfg->arch.omit_fp) {
6829 cfa_offset += remaining_size;
6830 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6831 async_exc_point (code);
6834 if (cfg->arch.omit_fp)
6835 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6839 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6840 if (cfg->arch.omit_fp) {
6841 cfa_offset += alloc_size;
6842 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6843 async_exc_point (code);
6848 /* Stack alignment check */
6853 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6854 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6855 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6857 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6858 amd64_breakpoint (code);
6859 amd64_patch (buf, code);
6863 if (mini_get_debug_options ()->init_stacks) {
6864 /* Fill the stack frame with a dummy value to force deterministic behavior */
6866 /* Save registers to the red zone */
6867 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6868 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6870 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6871 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6872 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6875 amd64_prefix (code, X86_REP_PREFIX);
6878 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6879 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6883 if (method->save_lmf)
6884 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6886 /* Save callee saved registers */
6887 if (cfg->arch.omit_fp) {
6888 save_area_offset = cfg->arch.reg_save_area_offset;
6889 /* Save caller saved registers after sp is adjusted */
6890 /* The registers are saved at the bottom of the frame */
6891 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6893 /* The registers are saved just below the saved rbp */
6894 save_area_offset = cfg->arch.reg_save_area_offset;
6897 for (i = 0; i < AMD64_NREG; ++i) {
6898 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6899 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6901 if (cfg->arch.omit_fp) {
6902 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6903 /* These are handled automatically by the stack marking code */
6904 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6906 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6910 save_area_offset += 8;
6911 async_exc_point (code);
6915 /* store runtime generic context */
6916 if (cfg->rgctx_var) {
6917 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6918 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6920 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6922 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6923 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6926 /* compute max_length in order to use short forward jumps */
6927 max_epilog_size = get_max_epilog_size (cfg);
6928 if (cfg->opt & MONO_OPT_BRANCH) {
6929 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6933 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6935 /* max alignment for loops */
6936 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6937 max_length += LOOP_ALIGNMENT;
6939 MONO_BB_FOR_EACH_INS (bb, ins) {
6940 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6943 /* Take prolog and epilog instrumentation into account */
6944 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6945 max_length += max_epilog_size;
6947 bb->max_length = max_length;
6951 sig = mono_method_signature (method);
6954 cinfo = (CallInfo *)cfg->arch.cinfo;
6956 if (sig->ret->type != MONO_TYPE_VOID) {
6957 /* Save volatile arguments to the stack */
6958 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6959 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6962 /* Keep this in sync with emit_load_volatile_arguments */
6963 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6964 ArgInfo *ainfo = cinfo->args + i;
6966 ins = cfg->args [i];
6968 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6969 /* Unused arguments */
6972 /* Save volatile arguments to the stack */
6973 if (ins->opcode != OP_REGVAR) {
6974 switch (ainfo->storage) {
6980 if (stack_offset & 0x1)
6982 else if (stack_offset & 0x2)
6984 else if (stack_offset & 0x4)
6989 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6992 * Save the original location of 'this',
6993 * get_generic_info_from_stack_frame () needs this to properly look up
6994 * the argument value during the handling of async exceptions.
6996 if (ins == cfg->args [0]) {
6997 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6998 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7002 case ArgInFloatSSEReg:
7003 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7005 case ArgInDoubleSSEReg:
7006 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7008 case ArgValuetypeInReg:
7009 for (quad = 0; quad < 2; quad ++) {
7010 switch (ainfo->pair_storage [quad]) {
7012 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7014 case ArgInFloatSSEReg:
7015 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7017 case ArgInDoubleSSEReg:
7018 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7023 g_assert_not_reached ();
7027 case ArgValuetypeAddrInIReg:
7028 if (ainfo->pair_storage [0] == ArgInIReg)
7029 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7031 case ArgValuetypeAddrOnStack:
7033 case ArgGSharedVtInReg:
7034 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7040 /* Argument allocated to (non-volatile) register */
7041 switch (ainfo->storage) {
7043 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7046 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7049 g_assert_not_reached ();
7052 if (ins == cfg->args [0]) {
7053 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7054 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7059 if (cfg->method->save_lmf)
7060 args_clobbered = TRUE;
7063 args_clobbered = TRUE;
7064 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7067 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7068 args_clobbered = TRUE;
7071 * Optimize the common case of the first bblock making a call with the same
7072 * arguments as the method. This works because the arguments are still in their
7073 * original argument registers.
7074 * FIXME: Generalize this
7076 if (!args_clobbered) {
7077 MonoBasicBlock *first_bb = cfg->bb_entry;
7079 int filter = FILTER_IL_SEQ_POINT;
7081 next = mono_bb_first_inst (first_bb, filter);
7082 if (!next && first_bb->next_bb) {
7083 first_bb = first_bb->next_bb;
7084 next = mono_bb_first_inst (first_bb, filter);
7087 if (first_bb->in_count > 1)
7090 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7091 ArgInfo *ainfo = cinfo->args + i;
7092 gboolean match = FALSE;
7094 ins = cfg->args [i];
7095 if (ins->opcode != OP_REGVAR) {
7096 switch (ainfo->storage) {
7098 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7099 if (next->dreg == ainfo->reg) {
7103 next->opcode = OP_MOVE;
7104 next->sreg1 = ainfo->reg;
7105 /* Only continue if the instruction doesn't change argument regs */
7106 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7116 /* Argument allocated to (non-volatile) register */
7117 switch (ainfo->storage) {
7119 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7130 next = mono_inst_next (next, filter);
7131 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7138 if (cfg->gen_sdb_seq_points) {
7139 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7141 /* Initialize seq_point_info_var */
7142 if (cfg->compile_aot) {
7143 /* Initialize the variable from a GOT slot */
7144 /* Same as OP_AOTCONST */
7145 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7146 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7147 g_assert (info_var->opcode == OP_REGOFFSET);
7148 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7151 if (cfg->compile_aot) {
7152 /* Initialize ss_tramp_var */
7153 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7154 g_assert (ins->opcode == OP_REGOFFSET);
7156 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7157 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7158 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7160 /* Initialize ss_tramp_var */
7161 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7162 g_assert (ins->opcode == OP_REGOFFSET);
7164 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7165 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7167 /* Initialize bp_tramp_var */
7168 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7169 g_assert (ins->opcode == OP_REGOFFSET);
7171 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7172 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7176 cfg->code_len = code - cfg->native_code;
7178 g_assert (cfg->code_len < cfg->code_size);
7184 mono_arch_emit_epilog (MonoCompile *cfg)
7186 MonoMethod *method = cfg->method;
7189 int max_epilog_size;
7191 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7192 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7194 max_epilog_size = get_max_epilog_size (cfg);
7196 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7197 cfg->code_size *= 2;
7198 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7199 cfg->stat_code_reallocs++;
7201 code = cfg->native_code + cfg->code_len;
7203 cfg->has_unwind_info_for_epilog = TRUE;
7205 /* Mark the start of the epilog */
7206 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7208 /* Save the uwind state which is needed by the out-of-line code */
7209 mono_emit_unwind_op_remember_state (cfg, code);
7211 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7212 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7214 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7216 if (method->save_lmf) {
7217 /* check if we need to restore protection of the stack after a stack overflow */
7218 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7220 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7221 /* we load the value in a separate instruction: this mechanism may be
7222 * used later as a safer way to do thread interruption
7224 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7225 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7227 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7228 /* note that the call trampoline will preserve eax/edx */
7229 x86_call_reg (code, X86_ECX);
7230 x86_patch (patch, code);
7232 /* FIXME: maybe save the jit tls in the prolog */
7234 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7235 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7239 /* Restore callee saved regs */
7240 for (i = 0; i < AMD64_NREG; ++i) {
7241 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7242 /* Restore only used_int_regs, not arch.saved_iregs */
7243 #if defined(MONO_SUPPORT_TASKLETS)
7246 int restore_reg=(cfg->used_int_regs & (1 << i));
7249 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7250 mono_emit_unwind_op_same_value (cfg, code, i);
7251 async_exc_point (code);
7253 save_area_offset += 8;
7257 /* Load returned vtypes into registers if needed */
7258 cinfo = (CallInfo *)cfg->arch.cinfo;
7259 if (cinfo->ret.storage == ArgValuetypeInReg) {
7260 ArgInfo *ainfo = &cinfo->ret;
7261 MonoInst *inst = cfg->ret;
7263 for (quad = 0; quad < 2; quad ++) {
7264 switch (ainfo->pair_storage [quad]) {
7266 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7268 case ArgInFloatSSEReg:
7269 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7271 case ArgInDoubleSSEReg:
7272 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7277 g_assert_not_reached ();
7282 if (cfg->arch.omit_fp) {
7283 if (cfg->arch.stack_alloc_size) {
7284 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7288 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7290 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7291 async_exc_point (code);
7294 /* Restore the unwind state to be the same as before the epilog */
7295 mono_emit_unwind_op_restore_state (cfg, code);
7297 cfg->code_len = code - cfg->native_code;
7299 g_assert (cfg->code_len < cfg->code_size);
7303 mono_arch_emit_exceptions (MonoCompile *cfg)
7305 MonoJumpInfo *patch_info;
7308 MonoClass *exc_classes [16];
7309 guint8 *exc_throw_start [16], *exc_throw_end [16];
7310 guint32 code_size = 0;
7312 /* Compute needed space */
7313 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7314 if (patch_info->type == MONO_PATCH_INFO_EXC)
7316 if (patch_info->type == MONO_PATCH_INFO_R8)
7317 code_size += 8 + 15; /* sizeof (double) + alignment */
7318 if (patch_info->type == MONO_PATCH_INFO_R4)
7319 code_size += 4 + 15; /* sizeof (float) + alignment */
7320 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7321 code_size += 8 + 7; /*sizeof (void*) + alignment */
7324 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7325 cfg->code_size *= 2;
7326 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7327 cfg->stat_code_reallocs++;
7330 code = cfg->native_code + cfg->code_len;
7332 /* add code to raise exceptions */
7334 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7335 switch (patch_info->type) {
7336 case MONO_PATCH_INFO_EXC: {
7337 MonoClass *exc_class;
7341 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7343 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7344 throw_ip = patch_info->ip.i;
7346 //x86_breakpoint (code);
7347 /* Find a throw sequence for the same exception class */
7348 for (i = 0; i < nthrows; ++i)
7349 if (exc_classes [i] == exc_class)
7352 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7353 x86_jump_code (code, exc_throw_start [i]);
7354 patch_info->type = MONO_PATCH_INFO_NONE;
7358 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7362 exc_classes [nthrows] = exc_class;
7363 exc_throw_start [nthrows] = code;
7365 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7367 patch_info->type = MONO_PATCH_INFO_NONE;
7369 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7371 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7376 exc_throw_end [nthrows] = code;
7386 g_assert(code < cfg->native_code + cfg->code_size);
7389 /* Handle relocations with RIP relative addressing */
7390 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7391 gboolean remove = FALSE;
7392 guint8 *orig_code = code;
7394 switch (patch_info->type) {
7395 case MONO_PATCH_INFO_R8:
7396 case MONO_PATCH_INFO_R4: {
7397 guint8 *pos, *patch_pos;
7400 /* The SSE opcodes require a 16 byte alignment */
7401 code = (guint8*)ALIGN_TO (code, 16);
7403 pos = cfg->native_code + patch_info->ip.i;
7404 if (IS_REX (pos [1])) {
7405 patch_pos = pos + 5;
7406 target_pos = code - pos - 9;
7409 patch_pos = pos + 4;
7410 target_pos = code - pos - 8;
7413 if (patch_info->type == MONO_PATCH_INFO_R8) {
7414 *(double*)code = *(double*)patch_info->data.target;
7415 code += sizeof (double);
7417 *(float*)code = *(float*)patch_info->data.target;
7418 code += sizeof (float);
7421 *(guint32*)(patch_pos) = target_pos;
7426 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7429 if (cfg->compile_aot)
7432 /*loading is faster against aligned addresses.*/
7433 code = (guint8*)ALIGN_TO (code, 8);
7434 memset (orig_code, 0, code - orig_code);
7436 pos = cfg->native_code + patch_info->ip.i;
7438 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7439 if (IS_REX (pos [1]))
7440 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7442 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7444 *(gpointer*)code = (gpointer)patch_info->data.target;
7445 code += sizeof (gpointer);
7455 if (patch_info == cfg->patch_info)
7456 cfg->patch_info = patch_info->next;
7460 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7462 tmp->next = patch_info->next;
7465 g_assert (code < cfg->native_code + cfg->code_size);
7468 cfg->code_len = code - cfg->native_code;
7470 g_assert (cfg->code_len < cfg->code_size);
7474 #endif /* DISABLE_JIT */
7477 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7479 guchar *code = (guchar *)p;
7480 MonoMethodSignature *sig;
7482 int i, n, stack_area = 0;
7484 /* Keep this in sync with mono_arch_get_argument_info */
7486 if (enable_arguments) {
7487 /* Allocate a new area on the stack and save arguments there */
7488 sig = mono_method_signature (cfg->method);
7490 n = sig->param_count + sig->hasthis;
7492 stack_area = ALIGN_TO (n * 8, 16);
7494 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7496 for (i = 0; i < n; ++i) {
7497 inst = cfg->args [i];
7499 if (inst->opcode == OP_REGVAR)
7500 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7502 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7503 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7508 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7509 amd64_set_reg_template (code, AMD64_ARG_REG1);
7510 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7511 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7513 if (enable_arguments)
7514 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7528 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7530 guchar *code = (guchar *)p;
7531 int save_mode = SAVE_NONE;
7532 MonoMethod *method = cfg->method;
7533 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7536 switch (ret_type->type) {
7537 case MONO_TYPE_VOID:
7538 /* special case string .ctor icall */
7539 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7540 save_mode = SAVE_EAX;
7542 save_mode = SAVE_NONE;
7546 save_mode = SAVE_EAX;
7550 save_mode = SAVE_XMM;
7552 case MONO_TYPE_GENERICINST:
7553 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7554 save_mode = SAVE_EAX;
7558 case MONO_TYPE_VALUETYPE:
7559 save_mode = SAVE_STRUCT;
7562 save_mode = SAVE_EAX;
7566 /* Save the result and copy it into the proper argument register */
7567 switch (save_mode) {
7569 amd64_push_reg (code, AMD64_RAX);
7571 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7572 if (enable_arguments)
7573 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7577 if (enable_arguments)
7578 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7581 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7582 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7584 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7586 * The result is already in the proper argument register so no copying
7593 g_assert_not_reached ();
7596 /* Set %al since this is a varargs call */
7597 if (save_mode == SAVE_XMM)
7598 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7600 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7602 if (preserve_argument_registers) {
7603 for (i = 0; i < PARAM_REGS; ++i)
7604 amd64_push_reg (code, param_regs [i]);
7607 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7608 amd64_set_reg_template (code, AMD64_ARG_REG1);
7609 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7611 if (preserve_argument_registers) {
7612 for (i = PARAM_REGS - 1; i >= 0; --i)
7613 amd64_pop_reg (code, param_regs [i]);
7616 /* Restore result */
7617 switch (save_mode) {
7619 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7620 amd64_pop_reg (code, AMD64_RAX);
7626 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7627 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7628 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7633 g_assert_not_reached ();
7640 mono_arch_flush_icache (guint8 *code, gint size)
7646 mono_arch_flush_register_windows (void)
7651 mono_arch_is_inst_imm (gint64 imm)
7653 return amd64_use_imm32 (imm);
7657 * Determine whenever the trap whose info is in SIGINFO is caused by
7661 mono_arch_is_int_overflow (void *sigctx, void *info)
7668 mono_sigctx_to_monoctx (sigctx, &ctx);
7670 rip = (guint8*)ctx.gregs [AMD64_RIP];
7672 if (IS_REX (rip [0])) {
7673 reg = amd64_rex_b (rip [0]);
7679 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7681 reg += x86_modrm_rm (rip [1]);
7683 value = ctx.gregs [reg];
7693 mono_arch_get_patch_offset (guint8 *code)
7699 * mono_breakpoint_clean_code:
7701 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7702 * breakpoints in the original code, they are removed in the copy.
7704 * Returns TRUE if no sw breakpoint was present.
7707 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7710 * If method_start is non-NULL we need to perform bound checks, since we access memory
7711 * at code - offset we could go before the start of the method and end up in a different
7712 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7715 if (!method_start || code - offset >= method_start) {
7716 memcpy (buf, code - offset, size);
7718 int diff = code - method_start;
7719 memset (buf, 0, size);
7720 memcpy (buf + offset - diff, method_start, diff + size - offset);
7726 mono_arch_get_this_arg_reg (guint8 *code)
7728 return AMD64_ARG_REG1;
7732 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7734 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7737 #define MAX_ARCH_DELEGATE_PARAMS 10
7740 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7742 guint8 *code, *start;
7743 GSList *unwind_ops = NULL;
7746 unwind_ops = mono_arch_get_cie_program ();
7749 start = code = (guint8 *)mono_global_codeman_reserve (64);
7751 /* Replace the this argument with the target */
7752 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7753 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7754 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7756 g_assert ((code - start) < 64);
7758 start = code = (guint8 *)mono_global_codeman_reserve (64);
7760 if (param_count == 0) {
7761 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7763 /* We have to shift the arguments left */
7764 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7765 for (i = 0; i < param_count; ++i) {
7768 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7770 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7772 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7776 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7778 g_assert ((code - start) < 64);
7781 mono_arch_flush_icache (start, code - start);
7784 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7786 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7787 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7791 if (mono_jit_map_is_enabled ()) {
7794 buff = (char*)"delegate_invoke_has_target";
7796 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7797 mono_emit_jit_tramp (start, code - start, buff);
7801 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7806 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7809 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7811 guint8 *code, *start;
7816 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7819 start = code = (guint8 *)mono_global_codeman_reserve (size);
7821 unwind_ops = mono_arch_get_cie_program ();
7823 /* Replace the this argument with the target */
7824 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7825 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7828 /* Load the IMT reg */
7829 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7832 /* Load the vtable */
7833 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7834 amd64_jump_membase (code, AMD64_RAX, offset);
7835 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7838 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7840 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7841 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7842 g_free (tramp_name);
7848 * mono_arch_get_delegate_invoke_impls:
7850 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7854 mono_arch_get_delegate_invoke_impls (void)
7857 MonoTrampInfo *info;
7860 get_delegate_invoke_impl (&info, TRUE, 0);
7861 res = g_slist_prepend (res, info);
7863 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7864 get_delegate_invoke_impl (&info, FALSE, i);
7865 res = g_slist_prepend (res, info);
7868 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7869 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7870 res = g_slist_prepend (res, info);
7872 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7873 res = g_slist_prepend (res, info);
7880 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7882 guint8 *code, *start;
7885 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7888 /* FIXME: Support more cases */
7889 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7893 static guint8* cached = NULL;
7898 if (mono_aot_only) {
7899 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7901 MonoTrampInfo *info;
7902 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7903 mono_tramp_info_register (info, NULL);
7906 mono_memory_barrier ();
7910 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7911 for (i = 0; i < sig->param_count; ++i)
7912 if (!mono_is_regsize_var (sig->params [i]))
7914 if (sig->param_count > 4)
7917 code = cache [sig->param_count];
7921 if (mono_aot_only) {
7922 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7923 start = (guint8 *)mono_aot_get_trampoline (name);
7926 MonoTrampInfo *info;
7927 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7928 mono_tramp_info_register (info, NULL);
7931 mono_memory_barrier ();
7933 cache [sig->param_count] = start;
7940 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7942 MonoTrampInfo *info;
7945 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7947 mono_tramp_info_register (info, NULL);
7952 mono_arch_finish_init (void)
7954 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7955 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7960 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7964 #define CMP_SIZE (6 + 1)
7965 #define CMP_REG_REG_SIZE (4 + 1)
7966 #define BR_SMALL_SIZE 2
7967 #define BR_LARGE_SIZE 6
7968 #define MOV_REG_IMM_SIZE 10
7969 #define MOV_REG_IMM_32BIT_SIZE 6
7970 #define JUMP_REG_SIZE (2 + 1)
7973 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7975 int i, distance = 0;
7976 for (i = start; i < target; ++i)
7977 distance += imt_entries [i]->chunk_size;
7982 * LOCKING: called with the domain lock held
7985 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7986 gpointer fail_tramp)
7990 guint8 *code, *start;
7991 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7994 for (i = 0; i < count; ++i) {
7995 MonoIMTCheckItem *item = imt_entries [i];
7996 if (item->is_equals) {
7997 if (item->check_target_idx) {
7998 if (!item->compare_done) {
7999 if (amd64_use_imm32 ((gint64)item->key))
8000 item->chunk_size += CMP_SIZE;
8002 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8004 if (item->has_target_code) {
8005 item->chunk_size += MOV_REG_IMM_SIZE;
8007 if (vtable_is_32bit)
8008 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8010 item->chunk_size += MOV_REG_IMM_SIZE;
8012 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8015 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8016 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8018 if (vtable_is_32bit)
8019 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8021 item->chunk_size += MOV_REG_IMM_SIZE;
8022 item->chunk_size += JUMP_REG_SIZE;
8023 /* with assert below:
8024 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8029 if (amd64_use_imm32 ((gint64)item->key))
8030 item->chunk_size += CMP_SIZE;
8032 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8033 item->chunk_size += BR_LARGE_SIZE;
8034 imt_entries [item->check_target_idx]->compare_done = TRUE;
8036 size += item->chunk_size;
8039 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8041 code = (guint8 *)mono_domain_code_reserve (domain, size);
8044 unwind_ops = mono_arch_get_cie_program ();
8046 for (i = 0; i < count; ++i) {
8047 MonoIMTCheckItem *item = imt_entries [i];
8048 item->code_target = code;
8049 if (item->is_equals) {
8050 gboolean fail_case = !item->check_target_idx && fail_tramp;
8052 if (item->check_target_idx || fail_case) {
8053 if (!item->compare_done || fail_case) {
8054 if (amd64_use_imm32 ((gint64)item->key))
8055 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8057 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8058 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8061 item->jmp_code = code;
8062 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8063 if (item->has_target_code) {
8064 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8065 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8067 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8068 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8072 amd64_patch (item->jmp_code, code);
8073 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8074 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8075 item->jmp_code = NULL;
8078 /* enable the commented code to assert on wrong method */
8080 if (amd64_is_imm32 (item->key))
8081 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8083 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8084 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8086 item->jmp_code = code;
8087 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8088 /* See the comment below about R10 */
8089 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8090 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8091 amd64_patch (item->jmp_code, code);
8092 amd64_breakpoint (code);
8093 item->jmp_code = NULL;
8095 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8096 needs to be preserved. R10 needs
8097 to be preserved for calls which
8098 require a runtime generic context,
8099 but interface calls don't. */
8100 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8101 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8105 if (amd64_use_imm32 ((gint64)item->key))
8106 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8108 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8109 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8111 item->jmp_code = code;
8112 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8113 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8115 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8117 g_assert (code - item->code_target <= item->chunk_size);
8119 /* patch the branches to get to the target items */
8120 for (i = 0; i < count; ++i) {
8121 MonoIMTCheckItem *item = imt_entries [i];
8122 if (item->jmp_code) {
8123 if (item->check_target_idx) {
8124 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8130 mono_stats.imt_thunks_size += code - start;
8131 g_assert (code - start <= size);
8133 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8135 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8141 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8143 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8147 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8149 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8153 mono_arch_get_cie_program (void)
8157 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8158 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8166 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8168 MonoInst *ins = NULL;
8171 if (cmethod->klass == mono_defaults.math_class) {
8172 if (strcmp (cmethod->name, "Sin") == 0) {
8174 } else if (strcmp (cmethod->name, "Cos") == 0) {
8176 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8178 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8182 if (opcode && fsig->param_count == 1) {
8183 MONO_INST_NEW (cfg, ins, opcode);
8184 ins->type = STACK_R8;
8185 ins->dreg = mono_alloc_freg (cfg);
8186 ins->sreg1 = args [0]->dreg;
8187 MONO_ADD_INS (cfg->cbb, ins);
8191 if (cfg->opt & MONO_OPT_CMOV) {
8192 if (strcmp (cmethod->name, "Min") == 0) {
8193 if (fsig->params [0]->type == MONO_TYPE_I4)
8195 if (fsig->params [0]->type == MONO_TYPE_U4)
8196 opcode = OP_IMIN_UN;
8197 else if (fsig->params [0]->type == MONO_TYPE_I8)
8199 else if (fsig->params [0]->type == MONO_TYPE_U8)
8200 opcode = OP_LMIN_UN;
8201 } else if (strcmp (cmethod->name, "Max") == 0) {
8202 if (fsig->params [0]->type == MONO_TYPE_I4)
8204 if (fsig->params [0]->type == MONO_TYPE_U4)
8205 opcode = OP_IMAX_UN;
8206 else if (fsig->params [0]->type == MONO_TYPE_I8)
8208 else if (fsig->params [0]->type == MONO_TYPE_U8)
8209 opcode = OP_LMAX_UN;
8213 if (opcode && fsig->param_count == 2) {
8214 MONO_INST_NEW (cfg, ins, opcode);
8215 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8216 ins->dreg = mono_alloc_ireg (cfg);
8217 ins->sreg1 = args [0]->dreg;
8218 ins->sreg2 = args [1]->dreg;
8219 MONO_ADD_INS (cfg->cbb, ins);
8223 /* OP_FREM is not IEEE compatible */
8224 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8225 MONO_INST_NEW (cfg, ins, OP_FREM);
8226 ins->inst_i0 = args [0];
8227 ins->inst_i1 = args [1];
8237 mono_arch_print_tree (MonoInst *tree, int arity)
8243 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8245 return ctx->gregs [reg];
8249 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8251 ctx->gregs [reg] = val;
8255 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8257 gpointer *sp, old_value;
8261 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8262 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8265 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8274 * mono_arch_emit_load_aotconst:
8276 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8277 * TARGET from the mscorlib GOT in full-aot code.
8278 * On AMD64, the result is placed into R11.
8281 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8283 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8284 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8290 * mono_arch_get_trampolines:
8292 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8296 mono_arch_get_trampolines (gboolean aot)
8298 return mono_amd64_get_exception_trampolines (aot);
8301 /* Soft Debug support */
8302 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8305 * mono_arch_set_breakpoint:
8307 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8308 * The location should contain code emitted by OP_SEQ_POINT.
8311 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8316 guint32 native_offset = ip - (guint8*)ji->code_start;
8317 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8319 g_assert (info->bp_addrs [native_offset] == 0);
8320 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8322 /* ip points to a mov r11, 0 */
8323 g_assert (code [0] == 0x41);
8324 g_assert (code [1] == 0xbb);
8325 amd64_mov_reg_imm (code, AMD64_R11, 1);
8330 * mono_arch_clear_breakpoint:
8332 * Clear the breakpoint at IP.
8335 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8340 guint32 native_offset = ip - (guint8*)ji->code_start;
8341 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8343 info->bp_addrs [native_offset] = NULL;
8345 amd64_mov_reg_imm (code, AMD64_R11, 0);
8350 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8352 /* We use soft breakpoints on amd64 */
8357 * mono_arch_skip_breakpoint:
8359 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8360 * we resume, the instruction is not executed again.
8363 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8365 g_assert_not_reached ();
8369 * mono_arch_start_single_stepping:
8371 * Start single stepping.
8374 mono_arch_start_single_stepping (void)
8376 ss_trampoline = mini_get_single_step_trampoline ();
8380 * mono_arch_stop_single_stepping:
8382 * Stop single stepping.
8385 mono_arch_stop_single_stepping (void)
8387 ss_trampoline = NULL;
8391 * mono_arch_is_single_step_event:
8393 * Return whenever the machine state in SIGCTX corresponds to a single
8397 mono_arch_is_single_step_event (void *info, void *sigctx)
8399 /* We use soft breakpoints on amd64 */
8404 * mono_arch_skip_single_step:
8406 * Modify CTX so the ip is placed after the single step trigger instruction,
8407 * we resume, the instruction is not executed again.
8410 mono_arch_skip_single_step (MonoContext *ctx)
8412 g_assert_not_reached ();
8416 * mono_arch_create_seq_point_info:
8418 * Return a pointer to a data structure which is used by the sequence
8419 * point implementation in AOTed code.
8422 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8427 // FIXME: Add a free function
8429 mono_domain_lock (domain);
8430 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8432 mono_domain_unlock (domain);
8435 ji = mono_jit_info_table_find (domain, (char*)code);
8438 // FIXME: Optimize the size
8439 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8441 info->ss_tramp_addr = &ss_trampoline;
8443 mono_domain_lock (domain);
8444 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8446 mono_domain_unlock (domain);
8453 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8455 ext->lmf.previous_lmf = prev_lmf;
8456 /* Mark that this is a MonoLMFExt */
8457 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8458 ext->lmf.rsp = (gssize)ext;
8464 mono_arch_opcode_supported (int opcode)
8467 case OP_ATOMIC_ADD_I4:
8468 case OP_ATOMIC_ADD_I8:
8469 case OP_ATOMIC_EXCHANGE_I4:
8470 case OP_ATOMIC_EXCHANGE_I8:
8471 case OP_ATOMIC_CAS_I4:
8472 case OP_ATOMIC_CAS_I8:
8473 case OP_ATOMIC_LOAD_I1:
8474 case OP_ATOMIC_LOAD_I2:
8475 case OP_ATOMIC_LOAD_I4:
8476 case OP_ATOMIC_LOAD_I8:
8477 case OP_ATOMIC_LOAD_U1:
8478 case OP_ATOMIC_LOAD_U2:
8479 case OP_ATOMIC_LOAD_U4:
8480 case OP_ATOMIC_LOAD_U8:
8481 case OP_ATOMIC_LOAD_R4:
8482 case OP_ATOMIC_LOAD_R8:
8483 case OP_ATOMIC_STORE_I1:
8484 case OP_ATOMIC_STORE_I2:
8485 case OP_ATOMIC_STORE_I4:
8486 case OP_ATOMIC_STORE_I8:
8487 case OP_ATOMIC_STORE_U1:
8488 case OP_ATOMIC_STORE_U2:
8489 case OP_ATOMIC_STORE_U4:
8490 case OP_ATOMIC_STORE_U8:
8491 case OP_ATOMIC_STORE_R4:
8492 case OP_ATOMIC_STORE_R8:
8500 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8502 return get_call_info (mp, sig);