mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internals.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /* The single step trampoline */
  69 static gpointer ss_trampoline;
  70
  71 /* The breakpoint trampoline */
  72 static gpointer bp_trampoline;
  73
  74 /* Offset between fp and the first argument in the callee */
  75 #define ARGS_OFFSET 16
  76 #define GP_SCRATCH_REG AMD64_R11
  77
  78 /*
  79  * AMD64 register usage:
  80  * - callee saved registers are used for global register allocation
  81  * - %r11 is used for materializing 64 bit constants in opcodes
  82  * - the rest is used for local allocation
  83  */
  84
  85 /*
  86  * Floating point comparison results:
  87  *                  ZF PF CF
  88  * A > B            0  0  0
  89  * A < B            0  0  1
  90  * A = B            1  0  0
  91  * A > B            0  0  0
  92  * UNORDERED        1  1  1
  93  */
  94
  95 const char*
  96 mono_arch_regname (int reg)
  97 {
  98         switch (reg) {
  99         case AMD64_RAX: return "%rax";
 100         case AMD64_RBX: return "%rbx";
 101         case AMD64_RCX: return "%rcx";
 102         case AMD64_RDX: return "%rdx";
 103         case AMD64_RSP: return "%rsp";
 104         case AMD64_RBP: return "%rbp";
 105         case AMD64_RDI: return "%rdi";
 106         case AMD64_RSI: return "%rsi";
 107         case AMD64_R8: return "%r8";
 108         case AMD64_R9: return "%r9";
 109         case AMD64_R10: return "%r10";
 110         case AMD64_R11: return "%r11";
 111         case AMD64_R12: return "%r12";
 112         case AMD64_R13: return "%r13";
 113         case AMD64_R14: return "%r14";
 114         case AMD64_R15: return "%r15";
 115         }
 116         return "unknown";
 117 }
 118
 119 static const char * packed_xmmregs [] = {
 120         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 121         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 122 };
 123
 124 static const char * single_xmmregs [] = {
 125         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 126         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 127 };
 128
 129 const char*
 130 mono_arch_fregname (int reg)
 131 {
 132         if (reg < AMD64_XMM_NREG)
 133                 return single_xmmregs [reg];
 134         else
 135                 return "unknown";
 136 }
 137
 138 const char *
 139 mono_arch_xregname (int reg)
 140 {
 141         if (reg < AMD64_XMM_NREG)
 142                 return packed_xmmregs [reg];
 143         else
 144                 return "unknown";
 145 }
 146
 147 static gboolean
 148 debug_omit_fp (void)
 149 {
 150 #if 0
 151         return mono_debug_count ();
 152 #else
 153         return TRUE;
 154 #endif
 155 }
 156
 157 static inline gboolean
 158 amd64_is_near_call (guint8 *code)
 159 {
 160         /* Skip REX */
 161         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 162                 code += 1;
 163
 164         return code [0] == 0xe8;
 165 }
 166
 167 static inline gboolean
 168 amd64_use_imm32 (gint64 val)
 169 {
 170         if (mini_get_debug_options()->single_imm_size)
 171                 return FALSE;
 172
 173         return amd64_is_imm32 (val);
 174 }
 175
 176 #ifdef __native_client_codegen__
 177
 178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 179 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 181 /* We only want to force bundle alignment for the top level instruction,    */
 182 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 183 static MonoNativeTlsKey nacl_instruction_depth;
 184
 185 static MonoNativeTlsKey nacl_rex_tag;
 186 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 187
 188 void
 189 amd64_nacl_clear_legacy_prefix_tag ()
 190 {
 191         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 192 }
 193
 194 void
 195 amd64_nacl_tag_legacy_prefix (guint8* code)
 196 {
 197         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 198                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 199 }
 200
 201 void
 202 amd64_nacl_tag_rex (guint8* code)
 203 {
 204         mono_native_tls_set_value (nacl_rex_tag, code);
 205 }
 206
 207 guint8*
 208 amd64_nacl_get_legacy_prefix_tag ()
 209 {
 210         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 211 }
 212
 213 guint8*
 214 amd64_nacl_get_rex_tag ()
 215 {
 216         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 217 }
 218
 219 /* Increment the instruction "depth" described above */
 220 void
 221 amd64_nacl_instruction_pre ()
 222 {
 223         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 224         depth++;
 225         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 226 }
 227
 228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 229 /* alignment if depth == 0 (top level instruction)                          */
 230 /* IN: start, end    pointers to instruction beginning and end              */
 231 /* OUT: start, end   pointers to beginning and end after possible alignment */
 232 /* GLOBALS: nacl_instruction_depth     defined above                        */
 233 void
 234 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 235 {
 236         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 237         depth--;
 238         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 239
 240         g_assert ( depth >= 0 );
 241         if (depth == 0) {
 242                 uintptr_t space_in_block;
 243                 uintptr_t instlen;
 244                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 245                 /* if legacy prefix is present, and if it was emitted before */
 246                 /* the start of the instruction sequence, adjust the start   */
 247                 if (prefix != NULL && prefix < *start) {
 248                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 249                         *start = prefix;
 250                 }
 251                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 252                 instlen = (uintptr_t)(*end - *start);
 253                 /* Only check for instructions which are less than        */
 254                 /* kNaClAlignment. The only instructions that should ever */
 255                 /* be that long are call sequences, which are already     */
 256                 /* padded out to align the return to the next bundle.     */
 257                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 258                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 259                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 260                         const size_t length = (size_t)((*end)-(*start));
 261                         g_assert (length < MAX_NACL_INST_LENGTH);
 262
 263                         memcpy (copy_of_instruction, *start, length);
 264                         *start = mono_arch_nacl_pad (*start, space_in_block);
 265                         memcpy (*start, copy_of_instruction, length);
 266                         *end = *start + length;
 267                 }
 268                 amd64_nacl_clear_legacy_prefix_tag ();
 269                 amd64_nacl_tag_rex (NULL);
 270         }
 271 }
 272
 273 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 274 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 275 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 276 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 277 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 278 /* IN:      code                                                            */
 279 /*             pointer to current instruction stream (in the                */
 280 /*             middle of an instruction, after opcode is emitted)           */
 281 /*          basereg/offset/dreg                                             */
 282 /*             operands of normal membase address                           */
 283 /* OUT:     code                                                            */
 284 /*             pointer to the end of the membase/memindex emit              */
 285 /* GLOBALS: nacl_rex_tag                                                    */
 286 /*             position in instruction stream that rex prefix was emitted   */
 287 /*          nacl_legacy_prefix_tag                                          */
 288 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 289 void
 290 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 291 {
 292         gint8 true_basereg = basereg;
 293
 294         /* Cache these values, they might change  */
 295         /* as new instructions are emitted below. */
 296         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 297         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 298
 299         /* 'basereg' is given masked to 0x7 at this point, so check */
 300         /* the rex prefix to see if this is an extended register.   */
 301         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 302                 true_basereg |= 0x8;
 303         }
 304
 305 #define X86_LEA_OPCODE (0x8D)
 306
 307         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 308                 guint8* old_instruction_start;
 309
 310                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 311                 /* 32-bits of the old base register (new index register)     */
 312                 guint8 buf[32];
 313                 guint8* buf_ptr = buf;
 314                 size_t insert_len;
 315
 316                 g_assert (rex_tag != NULL);
 317
 318                 if (IS_REX(*rex_tag)) {
 319                         /* The old rex.B should be the new rex.X */
 320                         if (*rex_tag & AMD64_REX_B) {
 321                                 *rex_tag |= AMD64_REX_X;
 322                         }
 323                         /* Since our new base is %r15 set rex.B */
 324                         *rex_tag |= AMD64_REX_B;
 325                 } else {
 326                         /* Shift the instruction by one byte  */
 327                         /* so we can insert a rex prefix      */
 328                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 329                         *code += 1;
 330                         /* New rex prefix only needs rex.B for %r15 base */
 331                         *rex_tag = AMD64_REX(AMD64_REX_B);
 332                 }
 333
 334                 if (legacy_prefix_tag) {
 335                         old_instruction_start = legacy_prefix_tag;
 336                 } else {
 337                         old_instruction_start = rex_tag;
 338                 }
 339
 340                 /* Clears the upper 32-bits of the previous base register */
 341                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 342                 insert_len = buf_ptr - buf;
 343
 344                 /* Move the old instruction forward to make */
 345                 /* room for 'mov' stored in 'buf_ptr'       */
 346                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 347                 *code += insert_len;
 348                 memcpy (old_instruction_start, buf, insert_len);
 349
 350                 /* Sandboxed replacement for the normal membase_emit */
 351                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 352
 353         } else {
 354                 /* Normal default behavior, emit membase memory location */
 355                 x86_membase_emit_body (*code, dreg, basereg, offset);
 356         }
 357 }
 358
 359
 360 static inline unsigned char*
 361 amd64_skip_nops (unsigned char* code)
 362 {
 363         guint8 in_nop;
 364         do {
 365                 in_nop = 0;
 366                 if (   code[0] == 0x90) {
 367                         in_nop = 1;
 368                         code += 1;
 369                 }
 370                 if (   code[0] == 0x66 && code[1] == 0x90) {
 371                         in_nop = 1;
 372                         code += 2;
 373                 }
 374                 if (code[0] == 0x0f && code[1] == 0x1f
 375                  && code[2] == 0x00) {
 376                         in_nop = 1;
 377                         code += 3;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x40 && code[3] == 0x00) {
 381                         in_nop = 1;
 382                         code += 4;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x44 && code[3] == 0x00
 386                  && code[4] == 0x00) {
 387                         in_nop = 1;
 388                         code += 5;
 389                 }
 390                 if (code[0] == 0x66 && code[1] == 0x0f
 391                  && code[2] == 0x1f && code[3] == 0x44
 392                  && code[4] == 0x00 && code[5] == 0x00) {
 393                         in_nop = 1;
 394                         code += 6;
 395                 }
 396                 if (code[0] == 0x0f && code[1] == 0x1f
 397                  && code[2] == 0x80 && code[3] == 0x00
 398                  && code[4] == 0x00 && code[5] == 0x00
 399                  && code[6] == 0x00) {
 400                         in_nop = 1;
 401                         code += 7;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x84 && code[3] == 0x00
 405                  && code[4] == 0x00 && code[5] == 0x00
 406                  && code[6] == 0x00 && code[7] == 0x00) {
 407                         in_nop = 1;
 408                         code += 8;
 409                 }
 410         } while ( in_nop );
 411         return code;
 412 }
 413
 414 guint8*
 415 mono_arch_nacl_skip_nops (guint8* code)
 416 {
 417   return amd64_skip_nops(code);
 418 }
 419
 420 #endif /*__native_client_codegen__*/
 421
 422 static void
 423 amd64_patch (unsigned char* code, gpointer target)
 424 {
 425         guint8 rex = 0;
 426
 427 #ifdef __native_client_codegen__
 428         code = amd64_skip_nops (code);
 429 #endif
 430 #if defined(__native_client_codegen__) && defined(__native_client__)
 431         if (nacl_is_code_address (code)) {
 432                 /* For tail calls, code is patched after being installed */
 433                 /* but not through the normal "patch callsite" method.   */
 434                 unsigned char buf[kNaClAlignment];
 435                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 436                 int ret;
 437                 memcpy (buf, aligned_code, kNaClAlignment);
 438                 /* Patch a temp buffer of bundle size, */
 439                 /* then install to actual location.    */
 440                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 441                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 442                 g_assert (ret == 0);
 443                 return;
 444         }
 445         target = nacl_modify_patch_target (target);
 446 #endif
 447
 448         /* Skip REX */
 449         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 450                 rex = code [0];
 451                 code += 1;
 452         }
 453
 454         if ((code [0] & 0xf8) == 0xb8) {
 455                 /* amd64_set_reg_template */
 456                 *(guint64*)(code + 1) = (guint64)target;
 457         }
 458         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 459                 /* mov 0(%rip), %dreg */
 460                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 461         }
 462         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 463                 /* call *<OFFSET>(%rip) */
 464                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 465         }
 466         else if (code [0] == 0xe8) {
 467                 /* call <DISP> */
 468                 gint64 disp = (guint8*)target - (guint8*)code;
 469                 g_assert (amd64_is_imm32 (disp));
 470                 x86_patch (code, (unsigned char*)target);
 471         }
 472         else
 473                 x86_patch (code, (unsigned char*)target);
 474 }
 475
 476 void
 477 mono_amd64_patch (unsigned char* code, gpointer target)
 478 {
 479         amd64_patch (code, target);
 480 }
 481
 482 typedef enum {
 483         ArgInIReg,
 484         ArgInFloatSSEReg,
 485         ArgInDoubleSSEReg,
 486         ArgOnStack,
 487         ArgValuetypeInReg,
 488         ArgValuetypeAddrInIReg,
 489         /* gsharedvt argument passed by addr */
 490         ArgGSharedVtInReg,
 491         ArgGSharedVtOnStack,
 492         ArgNone /* only in pair_storage */
 493 } ArgStorage;
 494
 495 typedef struct {
 496         gint16 offset;
 497         gint8  reg;
 498         ArgStorage storage : 8;
 499         gboolean is_gsharedvt_return_value : 1;
 500
 501         /* Only if storage == ArgValuetypeInReg */
 502         ArgStorage pair_storage [2];
 503         gint8 pair_regs [2];
 504         /* The size of each pair (bytes) */
 505         int pair_size [2];
 506         int nregs;
 507         /* Only if storage == ArgOnStack */
 508         int arg_size; // Bytes, will always be rounded up/aligned to 8 byte boundary
 509 } ArgInfo;
 510
 511 typedef struct {
 512         int nargs;
 513         guint32 stack_usage;
 514         guint32 reg_usage;
 515         guint32 freg_usage;
 516         gboolean need_stack_align;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 static void inline
 527 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 528 {
 529     ainfo->offset = *stack_size;
 530
 531     if (*gr >= PARAM_REGS) {
 532                 ainfo->storage = ArgOnStack;
 533                 ainfo->arg_size = sizeof (mgreg_t);
 534                 /* Since the same stack slot size is used for all arg */
 535                 /*  types, it needs to be big enough to hold them all */
 536                 (*stack_size) += sizeof(mgreg_t);
 537     }
 538     else {
 539                 ainfo->storage = ArgInIReg;
 540                 ainfo->reg = param_regs [*gr];
 541                 (*gr) ++;
 542     }
 543 }
 544
 545 static void inline
 546 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 547 {
 548     ainfo->offset = *stack_size;
 549
 550     if (*gr >= FLOAT_PARAM_REGS) {
 551                 ainfo->storage = ArgOnStack;
 552                 ainfo->arg_size = sizeof (mgreg_t);
 553                 /* Since the same stack slot size is used for both float */
 554                 /*  types, it needs to be big enough to hold them both */
 555                 (*stack_size) += sizeof(mgreg_t);
 556     }
 557     else {
 558                 /* A double register */
 559                 if (is_double)
 560                         ainfo->storage = ArgInDoubleSSEReg;
 561                 else
 562                         ainfo->storage = ArgInFloatSSEReg;
 563                 ainfo->reg = *gr;
 564                 (*gr) += 1;
 565     }
 566 }
 567
 568 typedef enum ArgumentClass {
 569         ARG_CLASS_NO_CLASS,
 570         ARG_CLASS_MEMORY,
 571         ARG_CLASS_INTEGER,
 572         ARG_CLASS_SSE
 573 } ArgumentClass;
 574
 575 static ArgumentClass
 576 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 577 {
 578         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 579         MonoType *ptype;
 580
 581         ptype = mini_get_underlying_type (type);
 582         switch (ptype->type) {
 583         case MONO_TYPE_I1:
 584         case MONO_TYPE_U1:
 585         case MONO_TYPE_I2:
 586         case MONO_TYPE_U2:
 587         case MONO_TYPE_I4:
 588         case MONO_TYPE_U4:
 589         case MONO_TYPE_I:
 590         case MONO_TYPE_U:
 591         case MONO_TYPE_STRING:
 592         case MONO_TYPE_OBJECT:
 593         case MONO_TYPE_CLASS:
 594         case MONO_TYPE_SZARRAY:
 595         case MONO_TYPE_PTR:
 596         case MONO_TYPE_FNPTR:
 597         case MONO_TYPE_ARRAY:
 598         case MONO_TYPE_I8:
 599         case MONO_TYPE_U8:
 600                 class2 = ARG_CLASS_INTEGER;
 601                 break;
 602         case MONO_TYPE_R4:
 603         case MONO_TYPE_R8:
 604 #ifdef TARGET_WIN32
 605                 class2 = ARG_CLASS_INTEGER;
 606 #else
 607                 class2 = ARG_CLASS_SSE;
 608 #endif
 609                 break;
 610
 611         case MONO_TYPE_TYPEDBYREF:
 612                 g_assert_not_reached ();
 613
 614         case MONO_TYPE_GENERICINST:
 615                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 616                         class2 = ARG_CLASS_INTEGER;
 617                         break;
 618                 }
 619                 /* fall through */
 620         case MONO_TYPE_VALUETYPE: {
 621                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 622                 int i;
 623
 624                 for (i = 0; i < info->num_fields; ++i) {
 625                         class2 = class1;
 626                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 627                 }
 628                 break;
 629         }
 630         default:
 631                 g_assert_not_reached ();
 632         }
 633
 634         /* Merge */
 635         if (class1 == class2)
 636                 ;
 637         else if (class1 == ARG_CLASS_NO_CLASS)
 638                 class1 = class2;
 639         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 640                 class1 = ARG_CLASS_MEMORY;
 641         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 642                 class1 = ARG_CLASS_INTEGER;
 643         else
 644                 class1 = ARG_CLASS_SSE;
 645
 646         return class1;
 647 }
 648 #ifdef __native_client_codegen__
 649
 650 /* Default alignment for Native Client is 32-byte. */
 651 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 652
 653 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 654 /* Check that alignment doesn't cross an alignment boundary.             */
 655 guint8*
 656 mono_arch_nacl_pad(guint8 *code, int pad)
 657 {
 658         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 659
 660         if (pad == 0) return code;
 661         /* assertion: alignment cannot cross a block boundary */
 662         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 663                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 664         while (pad >= kMaxPadding) {
 665                 amd64_padding (code, kMaxPadding);
 666                 pad -= kMaxPadding;
 667         }
 668         if (pad != 0) amd64_padding (code, pad);
 669         return code;
 670 }
 671 #endif
 672
 673 static int
 674 count_fields_nested (MonoClass *klass)
 675 {
 676         MonoMarshalType *info;
 677         int i, count;
 678
 679         info = mono_marshal_load_type_info (klass);
 680         g_assert(info);
 681         count = 0;
 682         for (i = 0; i < info->num_fields; ++i) {
 683                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 684                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 685                 else
 686                         count ++;
 687         }
 688         return count;
 689 }
 690
 691 static int
 692 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 693 {
 694         MonoMarshalType *info;
 695         int i;
 696
 697         info = mono_marshal_load_type_info (klass);
 698         g_assert(info);
 699         for (i = 0; i < info->num_fields; ++i) {
 700                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 701                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 702                 } else {
 703                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 704                         fields [index].offset += offset;
 705                         index ++;
 706                 }
 707         }
 708         return index;
 709 }
 710
 711 #ifdef TARGET_WIN32
 712 static void
 713 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 714                                          gboolean is_return,
 715                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 716 {
 717         guint32 size, i, nfields;
 718         guint32 argsize = 8;
 719         ArgumentClass arg_class;
 720         MonoMarshalType *info = NULL;
 721         MonoMarshalField *fields = NULL;
 722         MonoClass *klass;
 723         gboolean pass_on_stack = FALSE;
 724
 725         klass = mono_class_from_mono_type (type);
 726         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 727         if (!sig->pinvoke)
 728                 pass_on_stack = TRUE;
 729
 730         /* If this struct can't be split up naturally into 8-byte */
 731         /* chunks (registers), pass it on the stack.              */
 732         if (sig->pinvoke && !pass_on_stack) {
 733                 guint32 align;
 734                 guint32 field_size;
 735
 736                 info = mono_marshal_load_type_info (klass);
 737                 g_assert (info);
 738
 739                 /*
 740                  * Collect field information recursively to be able to
 741                  * handle nested structures.
 742                  */
 743                 nfields = count_fields_nested (klass);
 744                 fields = g_new0 (MonoMarshalField, nfields);
 745                 collect_field_info_nested (klass, fields, 0, 0);
 746
 747                 for (i = 0; i < nfields; ++i) {
 748                         field_size = mono_marshal_type_size (fields [i].field->type,
 749                                                            fields [i].mspec,
 750                                                            &align, TRUE, klass->unicode);
 751                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 752                                 pass_on_stack = TRUE;
 753                                 break;
 754                         }
 755                 }
 756         }
 757
 758         if (pass_on_stack) {
 759                 /* Allways pass in memory */
 760                 ainfo->offset = *stack_size;
 761                 *stack_size += ALIGN_TO (size, 8);
 762                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 763                 if (!is_return)
 764                         ainfo->arg_size = ALIGN_TO (size, 8);
 765
 766                 g_free (fields);
 767                 return;
 768         }
 769
 770         if (!sig->pinvoke) {
 771                 int n = mono_class_value_size (klass, NULL);
 772
 773                 argsize = n;
 774
 775                 if (n > 8)
 776                         arg_class = ARG_CLASS_MEMORY;
 777                 else
 778                         /* Always pass in 1 integer register */
 779                         arg_class = ARG_CLASS_INTEGER;
 780         } else {
 781                 g_assert (info);
 782
 783                 if (!fields) {
 784                         ainfo->storage = ArgValuetypeInReg;
 785                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 786                         return;
 787                 }
 788
 789                 switch (info->native_size) {
 790                 case 1: case 2: case 4: case 8:
 791                         break;
 792                 default:
 793                         if (is_return) {
 794                                 ainfo->storage = ArgValuetypeAddrInIReg;
 795                                 ainfo->offset = *stack_size;
 796                                 *stack_size += ALIGN_TO (info->native_size, 8);
 797                         }
 798                         else {
 799                                 ainfo->storage = ArgValuetypeAddrInIReg;
 800
 801                                 if (*gr < PARAM_REGS) {
 802                                         ainfo->pair_storage [0] = ArgInIReg;
 803                                         ainfo->pair_regs [0] = param_regs [*gr];
 804                                         (*gr) ++;
 805                                 }
 806                                 else {
 807                                         ainfo->pair_storage [0] = ArgOnStack;
 808                                         ainfo->offset = *stack_size;
 809                                         ainfo->arg_size = sizeof (mgreg_t);
 810                                         *stack_size += 8;
 811                                 }
 812                         }
 813
 814                         g_free (fields);
 815                         return;
 816                 }
 817
 818                 int size;
 819                 guint32 align;
 820                 ArgumentClass class1;
 821
 822                 if (nfields == 0)
 823                         class1 = ARG_CLASS_MEMORY;
 824                 else
 825                         class1 = ARG_CLASS_NO_CLASS;
 826                 for (i = 0; i < nfields; ++i) {
 827                         size = mono_marshal_type_size (fields [i].field->type,
 828                                                                                    fields [i].mspec,
 829                                                                                    &align, TRUE, klass->unicode);
 830                         /* How far into this quad this data extends.*/
 831                         /* (8 is size of quad) */
 832                         argsize = fields [i].offset + size;
 833
 834                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 835                 }
 836                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 837                 arg_class = class1;
 838         }
 839
 840         g_free (fields);
 841
 842         /* Allocate registers */
 843         {
 844                 int orig_gr = *gr;
 845                 int orig_fr = *fr;
 846
 847                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 848                         argsize ++;
 849
 850                 ainfo->storage = ArgValuetypeInReg;
 851                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 852                 ainfo->pair_size [0] = argsize;
 853                 ainfo->pair_size [1] = 0;
 854                 ainfo->nregs = 1;
 855                 switch (arg_class) {
 856                 case ARG_CLASS_INTEGER:
 857                         if (*gr >= PARAM_REGS)
 858                                 arg_class = ARG_CLASS_MEMORY;
 859                         else {
 860                                 ainfo->pair_storage [0] = ArgInIReg;
 861                                 if (is_return)
 862                                         ainfo->pair_regs [0] = return_regs [*gr];
 863                                 else
 864                                         ainfo->pair_regs [0] = param_regs [*gr];
 865                                 (*gr) ++;
 866                         }
 867                         break;
 868                 case ARG_CLASS_SSE:
 869                         if (*fr >= FLOAT_PARAM_REGS)
 870                                 arg_class = ARG_CLASS_MEMORY;
 871                         else {
 872                                 if (argsize <= 4)
 873                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 874                                 else
 875                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 876                                 ainfo->pair_regs [0] = *fr;
 877                                 (*fr) ++;
 878                         }
 879                         break;
 880                 case ARG_CLASS_MEMORY:
 881                         break;
 882                 default:
 883                         g_assert_not_reached ();
 884                 }
 885
 886                 if (arg_class == ARG_CLASS_MEMORY) {
 887                         /* Revert possible register assignments */
 888                         *gr = orig_gr;
 889                         *fr = orig_fr;
 890
 891                         ainfo->offset = *stack_size;
 892                         *stack_size += sizeof (mgreg_t);
 893                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 894                         if (!is_return)
 895                                 ainfo->arg_size = sizeof (mgreg_t);
 896                 }
 897         }
 898 }
 899 #endif /* TARGET_WIN32 */
 900
 901 static void
 902 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 903                            gboolean is_return,
 904                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 905 {
 906 #ifdef TARGET_WIN32
 907         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 908 #else
 909         guint32 size, quad, nquads, i, nfields;
 910         /* Keep track of the size used in each quad so we can */
 911         /* use the right size when copying args/return vars.  */
 912         guint32 quadsize [2] = {8, 8};
 913         ArgumentClass args [2];
 914         MonoMarshalType *info = NULL;
 915         MonoMarshalField *fields = NULL;
 916         MonoClass *klass;
 917         gboolean pass_on_stack = FALSE;
 918
 919         klass = mono_class_from_mono_type (type);
 920         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 921         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 922                 /* We pass and return vtypes of size 8 in a register */
 923         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 924                 pass_on_stack = TRUE;
 925         }
 926
 927         /* If this struct can't be split up naturally into 8-byte */
 928         /* chunks (registers), pass it on the stack.              */
 929         if (sig->pinvoke && !pass_on_stack) {
 930                 guint32 align;
 931                 guint32 field_size;
 932
 933                 info = mono_marshal_load_type_info (klass);
 934                 g_assert (info);
 935
 936                 /*
 937                  * Collect field information recursively to be able to
 938                  * handle nested structures.
 939                  */
 940                 nfields = count_fields_nested (klass);
 941                 fields = g_new0 (MonoMarshalField, nfields);
 942                 collect_field_info_nested (klass, fields, 0, 0);
 943
 944                 for (i = 0; i < nfields; ++i) {
 945                         field_size = mono_marshal_type_size (fields [i].field->type,
 946                                                            fields [i].mspec,
 947                                                            &align, TRUE, klass->unicode);
 948                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 949                                 pass_on_stack = TRUE;
 950                                 break;
 951                         }
 952                 }
 953         }
 954
 955         if (size == 0) {
 956                 ainfo->storage = ArgValuetypeInReg;
 957                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 958                 return;
 959         }
 960
 961         if (pass_on_stack) {
 962                 /* Allways pass in memory */
 963                 ainfo->offset = *stack_size;
 964                 *stack_size += ALIGN_TO (size, 8);
 965                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 966                 if (!is_return)
 967                         ainfo->arg_size = ALIGN_TO (size, 8);
 968
 969                 g_free (fields);
 970                 return;
 971         }
 972
 973         if (size > 8)
 974                 nquads = 2;
 975         else
 976                 nquads = 1;
 977
 978         if (!sig->pinvoke) {
 979                 int n = mono_class_value_size (klass, NULL);
 980
 981                 quadsize [0] = n >= 8 ? 8 : n;
 982                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 983
 984                 /* Always pass in 1 or 2 integer registers */
 985                 args [0] = ARG_CLASS_INTEGER;
 986                 args [1] = ARG_CLASS_INTEGER;
 987                 /* Only the simplest cases are supported */
 988                 if (is_return && nquads != 1) {
 989                         args [0] = ARG_CLASS_MEMORY;
 990                         args [1] = ARG_CLASS_MEMORY;
 991                 }
 992         } else {
 993                 /*
 994                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 995                  * The X87 and SSEUP stuff is left out since there are no such types in
 996                  * the CLR.
 997                  */
 998                 g_assert (info);
 999
1000                 if (!fields) {
1001                         ainfo->storage = ArgValuetypeInReg;
1002                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1003                         return;
1004                 }
1005
1006                 if (info->native_size > 16) {
1007                         ainfo->offset = *stack_size;
1008                         *stack_size += ALIGN_TO (info->native_size, 8);
1009                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1010                         if (!is_return)
1011                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
1012
1013                         g_free (fields);
1014                         return;
1015                 }
1016
1017                 args [0] = ARG_CLASS_NO_CLASS;
1018                 args [1] = ARG_CLASS_NO_CLASS;
1019                 for (quad = 0; quad < nquads; ++quad) {
1020                         int size;
1021                         guint32 align;
1022                         ArgumentClass class1;
1023
1024                         if (nfields == 0)
1025                                 class1 = ARG_CLASS_MEMORY;
1026                         else
1027                                 class1 = ARG_CLASS_NO_CLASS;
1028                         for (i = 0; i < nfields; ++i) {
1029                                 size = mono_marshal_type_size (fields [i].field->type,
1030                                                                                            fields [i].mspec,
1031                                                                                            &align, TRUE, klass->unicode);
1032                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
1033                                         /* Unaligned field */
1034                                         NOT_IMPLEMENTED;
1035                                 }
1036
1037                                 /* Skip fields in other quad */
1038                                 if ((quad == 0) && (fields [i].offset >= 8))
1039                                         continue;
1040                                 if ((quad == 1) && (fields [i].offset < 8))
1041                                         continue;
1042
1043                                 /* How far into this quad this data extends.*/
1044                                 /* (8 is size of quad) */
1045                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1046
1047                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1048                         }
1049                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1050                         args [quad] = class1;
1051                 }
1052         }
1053
1054         g_free (fields);
1055
1056         /* Post merger cleanup */
1057         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1058                 args [0] = args [1] = ARG_CLASS_MEMORY;
1059
1060         /* Allocate registers */
1061         {
1062                 int orig_gr = *gr;
1063                 int orig_fr = *fr;
1064
1065                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1066                         quadsize [0] ++;
1067                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1068                         quadsize [1] ++;
1069
1070                 ainfo->storage = ArgValuetypeInReg;
1071                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1072                 g_assert (quadsize [0] <= 8);
1073                 g_assert (quadsize [1] <= 8);
1074                 ainfo->pair_size [0] = quadsize [0];
1075                 ainfo->pair_size [1] = quadsize [1];
1076                 ainfo->nregs = nquads;
1077                 for (quad = 0; quad < nquads; ++quad) {
1078                         switch (args [quad]) {
1079                         case ARG_CLASS_INTEGER:
1080                                 if (*gr >= PARAM_REGS)
1081                                         args [quad] = ARG_CLASS_MEMORY;
1082                                 else {
1083                                         ainfo->pair_storage [quad] = ArgInIReg;
1084                                         if (is_return)
1085                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1086                                         else
1087                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1088                                         (*gr) ++;
1089                                 }
1090                                 break;
1091                         case ARG_CLASS_SSE:
1092                                 if (*fr >= FLOAT_PARAM_REGS)
1093                                         args [quad] = ARG_CLASS_MEMORY;
1094                                 else {
1095                                         if (quadsize[quad] <= 4)
1096                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1097                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1098                                         ainfo->pair_regs [quad] = *fr;
1099                                         (*fr) ++;
1100                                 }
1101                                 break;
1102                         case ARG_CLASS_MEMORY:
1103                                 break;
1104                         default:
1105                                 g_assert_not_reached ();
1106                         }
1107                 }
1108
1109                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1110                         int arg_size;
1111                         /* Revert possible register assignments */
1112                         *gr = orig_gr;
1113                         *fr = orig_fr;
1114
1115                         ainfo->offset = *stack_size;
1116                         if (sig->pinvoke)
1117                                 arg_size = ALIGN_TO (info->native_size, 8);
1118                         else
1119                                 arg_size = nquads * sizeof(mgreg_t);
1120                         *stack_size += arg_size;
1121                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1122                         if (!is_return)
1123                                 ainfo->arg_size = arg_size;
1124                 }
1125         }
1126 #endif /* !TARGET_WIN32 */
1127 }
1128
1129 /*
1130  * get_call_info:
1131  *
1132  *  Obtain information about a call according to the calling convention.
1133  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1134  * Draft Version 0.23" document for more information.
1135  */
1136 static CallInfo*
1137 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1138 {
1139         guint32 i, gr, fr, pstart;
1140         MonoType *ret_type;
1141         int n = sig->hasthis + sig->param_count;
1142         guint32 stack_size = 0;
1143         CallInfo *cinfo;
1144         gboolean is_pinvoke = sig->pinvoke;
1145
1146         if (mp)
1147                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1148         else
1149                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1150
1151         cinfo->nargs = n;
1152
1153         gr = 0;
1154         fr = 0;
1155
1156 #ifdef TARGET_WIN32
1157         /* Reserve space where the callee can save the argument registers */
1158         stack_size = 4 * sizeof (mgreg_t);
1159 #endif
1160
1161         /* return value */
1162         ret_type = mini_get_underlying_type (sig->ret);
1163         switch (ret_type->type) {
1164         case MONO_TYPE_I1:
1165         case MONO_TYPE_U1:
1166         case MONO_TYPE_I2:
1167         case MONO_TYPE_U2:
1168         case MONO_TYPE_I4:
1169         case MONO_TYPE_U4:
1170         case MONO_TYPE_I:
1171         case MONO_TYPE_U:
1172         case MONO_TYPE_PTR:
1173         case MONO_TYPE_FNPTR:
1174         case MONO_TYPE_CLASS:
1175         case MONO_TYPE_OBJECT:
1176         case MONO_TYPE_SZARRAY:
1177         case MONO_TYPE_ARRAY:
1178         case MONO_TYPE_STRING:
1179                 cinfo->ret.storage = ArgInIReg;
1180                 cinfo->ret.reg = AMD64_RAX;
1181                 break;
1182         case MONO_TYPE_U8:
1183         case MONO_TYPE_I8:
1184                 cinfo->ret.storage = ArgInIReg;
1185                 cinfo->ret.reg = AMD64_RAX;
1186                 break;
1187         case MONO_TYPE_R4:
1188                 cinfo->ret.storage = ArgInFloatSSEReg;
1189                 cinfo->ret.reg = AMD64_XMM0;
1190                 break;
1191         case MONO_TYPE_R8:
1192                 cinfo->ret.storage = ArgInDoubleSSEReg;
1193                 cinfo->ret.reg = AMD64_XMM0;
1194                 break;
1195         case MONO_TYPE_GENERICINST:
1196                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1197                         cinfo->ret.storage = ArgInIReg;
1198                         cinfo->ret.reg = AMD64_RAX;
1199                         break;
1200                 }
1201                 if (mini_is_gsharedvt_type (ret_type)) {
1202                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1203                         cinfo->ret.is_gsharedvt_return_value = 1;
1204                         break;
1205                 }
1206                 /* fall through */
1207         case MONO_TYPE_VALUETYPE:
1208         case MONO_TYPE_TYPEDBYREF: {
1209                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1210
1211                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1212                 g_assert (cinfo->ret.storage != ArgInIReg);
1213                 break;
1214         }
1215         case MONO_TYPE_VAR:
1216         case MONO_TYPE_MVAR:
1217                 g_assert (mini_is_gsharedvt_type (ret_type));
1218                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1219                 cinfo->ret.is_gsharedvt_return_value = 1;
1220                 break;
1221         case MONO_TYPE_VOID:
1222                 break;
1223         default:
1224                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1225         }
1226
1227         pstart = 0;
1228         /*
1229          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1230          * the first argument, allowing 'this' to be always passed in the first arg reg.
1231          * Also do this if the first argument is a reference type, since virtual calls
1232          * are sometimes made using calli without sig->hasthis set, like in the delegate
1233          * invoke wrappers.
1234          */
1235         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1236                 if (sig->hasthis) {
1237                         add_general (&gr, &stack_size, cinfo->args + 0);
1238                 } else {
1239                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1240                         pstart = 1;
1241                 }
1242                 add_general (&gr, &stack_size, &cinfo->ret);
1243                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1244                 cinfo->vret_arg_index = 1;
1245         } else {
1246                 /* this */
1247                 if (sig->hasthis)
1248                         add_general (&gr, &stack_size, cinfo->args + 0);
1249
1250                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1251                         add_general (&gr, &stack_size, &cinfo->ret);
1252                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1253                 }
1254         }
1255
1256         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1257                 gr = PARAM_REGS;
1258                 fr = FLOAT_PARAM_REGS;
1259
1260                 /* Emit the signature cookie just before the implicit arguments */
1261                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1262         }
1263
1264         for (i = pstart; i < sig->param_count; ++i) {
1265                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1266                 MonoType *ptype;
1267
1268 #ifdef TARGET_WIN32
1269                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1270                 if (gr > fr)
1271                         fr = gr;
1272                 else if (fr > gr)
1273                         gr = fr;
1274 #endif
1275
1276                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1277                         /* We allways pass the sig cookie on the stack for simplicity */
1278                         /*
1279                          * Prevent implicit arguments + the sig cookie from being passed
1280                          * in registers.
1281                          */
1282                         gr = PARAM_REGS;
1283                         fr = FLOAT_PARAM_REGS;
1284
1285                         /* Emit the signature cookie just before the implicit arguments */
1286                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1287                 }
1288
1289                 ptype = mini_get_underlying_type (sig->params [i]);
1290                 switch (ptype->type) {
1291                 case MONO_TYPE_I1:
1292                 case MONO_TYPE_U1:
1293                         add_general (&gr, &stack_size, ainfo);
1294                         break;
1295                 case MONO_TYPE_I2:
1296                 case MONO_TYPE_U2:
1297                         add_general (&gr, &stack_size, ainfo);
1298                         break;
1299                 case MONO_TYPE_I4:
1300                 case MONO_TYPE_U4:
1301                         add_general (&gr, &stack_size, ainfo);
1302                         break;
1303                 case MONO_TYPE_I:
1304                 case MONO_TYPE_U:
1305                 case MONO_TYPE_PTR:
1306                 case MONO_TYPE_FNPTR:
1307                 case MONO_TYPE_CLASS:
1308                 case MONO_TYPE_OBJECT:
1309                 case MONO_TYPE_STRING:
1310                 case MONO_TYPE_SZARRAY:
1311                 case MONO_TYPE_ARRAY:
1312                         add_general (&gr, &stack_size, ainfo);
1313                         break;
1314                 case MONO_TYPE_GENERICINST:
1315                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1316                                 add_general (&gr, &stack_size, ainfo);
1317                                 break;
1318                         }
1319                         if (mini_is_gsharedvt_variable_type (ptype)) {
1320                                 /* gsharedvt arguments are passed by ref */
1321                                 add_general (&gr, &stack_size, ainfo);
1322                                 if (ainfo->storage == ArgInIReg)
1323                                         ainfo->storage = ArgGSharedVtInReg;
1324                                 else
1325                                         ainfo->storage = ArgGSharedVtOnStack;
1326                                 break;
1327                         }
1328                         /* fall through */
1329                 case MONO_TYPE_VALUETYPE:
1330                 case MONO_TYPE_TYPEDBYREF:
1331                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1332                         break;
1333                 case MONO_TYPE_U8:
1334
1335                 case MONO_TYPE_I8:
1336                         add_general (&gr, &stack_size, ainfo);
1337                         break;
1338                 case MONO_TYPE_R4:
1339                         add_float (&fr, &stack_size, ainfo, FALSE);
1340                         break;
1341                 case MONO_TYPE_R8:
1342                         add_float (&fr, &stack_size, ainfo, TRUE);
1343                         break;
1344                 case MONO_TYPE_VAR:
1345                 case MONO_TYPE_MVAR:
1346                         /* gsharedvt arguments are passed by ref */
1347                         g_assert (mini_is_gsharedvt_type (ptype));
1348                         add_general (&gr, &stack_size, ainfo);
1349                         if (ainfo->storage == ArgInIReg)
1350                                 ainfo->storage = ArgGSharedVtInReg;
1351                         else
1352                                 ainfo->storage = ArgGSharedVtOnStack;
1353                         break;
1354                 default:
1355                         g_assert_not_reached ();
1356                 }
1357         }
1358
1359         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1360                 gr = PARAM_REGS;
1361                 fr = FLOAT_PARAM_REGS;
1362
1363                 /* Emit the signature cookie just before the implicit arguments */
1364                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1365         }
1366
1367         cinfo->stack_usage = stack_size;
1368         cinfo->reg_usage = gr;
1369         cinfo->freg_usage = fr;
1370         return cinfo;
1371 }
1372
1373 /*
1374  * mono_arch_get_argument_info:
1375  * @csig:  a method signature
1376  * @param_count: the number of parameters to consider
1377  * @arg_info: an array to store the result infos
1378  *
1379  * Gathers information on parameters such as size, alignment and
1380  * padding. arg_info should be large enought to hold param_count + 1 entries.
1381  *
1382  * Returns the size of the argument area on the stack.
1383  */
1384 int
1385 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1386 {
1387         int k;
1388         CallInfo *cinfo = get_call_info (NULL, csig);
1389         guint32 args_size = cinfo->stack_usage;
1390
1391         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1392         if (csig->hasthis) {
1393                 arg_info [0].offset = 0;
1394         }
1395
1396         for (k = 0; k < param_count; k++) {
1397                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1398                 /* FIXME: */
1399                 arg_info [k + 1].size = 0;
1400         }
1401
1402         g_free (cinfo);
1403
1404         return args_size;
1405 }
1406
1407 gboolean
1408 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1409 {
1410         CallInfo *c1, *c2;
1411         gboolean res;
1412         MonoType *callee_ret;
1413
1414         c1 = get_call_info (NULL, caller_sig);
1415         c2 = get_call_info (NULL, callee_sig);
1416         res = c1->stack_usage >= c2->stack_usage;
1417         callee_ret = mini_get_underlying_type (callee_sig->ret);
1418         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1419                 /* An address on the callee's stack is passed as the first argument */
1420                 res = FALSE;
1421
1422         g_free (c1);
1423         g_free (c2);
1424
1425         return res;
1426 }
1427
1428 /*
1429  * Initialize the cpu to execute managed code.
1430  */
1431 void
1432 mono_arch_cpu_init (void)
1433 {
1434 #ifndef _MSC_VER
1435         guint16 fpcw;
1436
1437         /* spec compliance requires running with double precision */
1438         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1439         fpcw &= ~X86_FPCW_PRECC_MASK;
1440         fpcw |= X86_FPCW_PREC_DOUBLE;
1441         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1442         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1443 #else
1444         /* TODO: This is crashing on Win64 right now.
1445         * _control87 (_PC_53, MCW_PC);
1446         */
1447 #endif
1448 }
1449
1450 /*
1451  * Initialize architecture specific code.
1452  */
1453 void
1454 mono_arch_init (void)
1455 {
1456         mono_os_mutex_init_recursive (&mini_arch_mutex);
1457 #if defined(__native_client_codegen__)
1458         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1459         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1460         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1461         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1462 #endif
1463
1464         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1465         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1466         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1467         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1468 #if defined(ENABLE_GSHAREDVT)
1469         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1470 #endif
1471
1472         if (!mono_aot_only)
1473                 bp_trampoline = mini_get_breakpoint_trampoline ();
1474 }
1475
1476 /*
1477  * Cleanup architecture specific code.
1478  */
1479 void
1480 mono_arch_cleanup (void)
1481 {
1482         mono_os_mutex_destroy (&mini_arch_mutex);
1483 #if defined(__native_client_codegen__)
1484         mono_native_tls_free (nacl_instruction_depth);
1485         mono_native_tls_free (nacl_rex_tag);
1486         mono_native_tls_free (nacl_legacy_prefix_tag);
1487 #endif
1488 }
1489
1490 /*
1491  * This function returns the optimizations supported on this cpu.
1492  */
1493 guint32
1494 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1495 {
1496         guint32 opts = 0;
1497
1498         *exclude_mask = 0;
1499
1500         if (mono_hwcap_x86_has_cmov) {
1501                 opts |= MONO_OPT_CMOV;
1502
1503                 if (mono_hwcap_x86_has_fcmov)
1504                         opts |= MONO_OPT_FCMOV;
1505                 else
1506                         *exclude_mask |= MONO_OPT_FCMOV;
1507         } else {
1508                 *exclude_mask |= MONO_OPT_CMOV;
1509         }
1510
1511         return opts;
1512 }
1513
1514 /*
1515  * This function test for all SSE functions supported.
1516  *
1517  * Returns a bitmask corresponding to all supported versions.
1518  *
1519  */
1520 guint32
1521 mono_arch_cpu_enumerate_simd_versions (void)
1522 {
1523         guint32 sse_opts = 0;
1524
1525         if (mono_hwcap_x86_has_sse1)
1526                 sse_opts |= SIMD_VERSION_SSE1;
1527
1528         if (mono_hwcap_x86_has_sse2)
1529                 sse_opts |= SIMD_VERSION_SSE2;
1530
1531         if (mono_hwcap_x86_has_sse3)
1532                 sse_opts |= SIMD_VERSION_SSE3;
1533
1534         if (mono_hwcap_x86_has_ssse3)
1535                 sse_opts |= SIMD_VERSION_SSSE3;
1536
1537         if (mono_hwcap_x86_has_sse41)
1538                 sse_opts |= SIMD_VERSION_SSE41;
1539
1540         if (mono_hwcap_x86_has_sse42)
1541                 sse_opts |= SIMD_VERSION_SSE42;
1542
1543         if (mono_hwcap_x86_has_sse4a)
1544                 sse_opts |= SIMD_VERSION_SSE4a;
1545
1546         return sse_opts;
1547 }
1548
1549 #ifndef DISABLE_JIT
1550
1551 GList *
1552 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1553 {
1554         GList *vars = NULL;
1555         int i;
1556
1557         for (i = 0; i < cfg->num_varinfo; i++) {
1558                 MonoInst *ins = cfg->varinfo [i];
1559                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1560
1561                 /* unused vars */
1562                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1563                         continue;
1564
1565                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1566                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1567                         continue;
1568
1569                 if (mono_is_regsize_var (ins->inst_vtype)) {
1570                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1571                         g_assert (i == vmv->idx);
1572                         vars = g_list_prepend (vars, vmv);
1573                 }
1574         }
1575
1576         vars = mono_varlist_sort (cfg, vars, 0);
1577
1578         return vars;
1579 }
1580
1581 /**
1582  * mono_arch_compute_omit_fp:
1583  *
1584  *   Determine whenever the frame pointer can be eliminated.
1585  */
1586 static void
1587 mono_arch_compute_omit_fp (MonoCompile *cfg)
1588 {
1589         MonoMethodSignature *sig;
1590         MonoMethodHeader *header;
1591         int i, locals_size;
1592         CallInfo *cinfo;
1593
1594         if (cfg->arch.omit_fp_computed)
1595                 return;
1596
1597         header = cfg->header;
1598
1599         sig = mono_method_signature (cfg->method);
1600
1601         if (!cfg->arch.cinfo)
1602                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1603         cinfo = (CallInfo *)cfg->arch.cinfo;
1604
1605         /*
1606          * FIXME: Remove some of the restrictions.
1607          */
1608         cfg->arch.omit_fp = TRUE;
1609         cfg->arch.omit_fp_computed = TRUE;
1610
1611 #ifdef __native_client_codegen__
1612         /* NaCl modules may not change the value of RBP, so it cannot be */
1613         /* used as a normal register, but it can be used as a frame pointer*/
1614         cfg->disable_omit_fp = TRUE;
1615         cfg->arch.omit_fp = FALSE;
1616 #endif
1617
1618         if (cfg->disable_omit_fp)
1619                 cfg->arch.omit_fp = FALSE;
1620
1621         if (!debug_omit_fp ())
1622                 cfg->arch.omit_fp = FALSE;
1623         /*
1624         if (cfg->method->save_lmf)
1625                 cfg->arch.omit_fp = FALSE;
1626         */
1627         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1628                 cfg->arch.omit_fp = FALSE;
1629         if (header->num_clauses)
1630                 cfg->arch.omit_fp = FALSE;
1631         if (cfg->param_area)
1632                 cfg->arch.omit_fp = FALSE;
1633         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1634                 cfg->arch.omit_fp = FALSE;
1635         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1636                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1637                 cfg->arch.omit_fp = FALSE;
1638         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1639                 ArgInfo *ainfo = &cinfo->args [i];
1640
1641                 if (ainfo->storage == ArgOnStack) {
1642                         /*
1643                          * The stack offset can only be determined when the frame
1644                          * size is known.
1645                          */
1646                         cfg->arch.omit_fp = FALSE;
1647                 }
1648         }
1649
1650         locals_size = 0;
1651         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1652                 MonoInst *ins = cfg->varinfo [i];
1653                 int ialign;
1654
1655                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1656         }
1657 }
1658
1659 GList *
1660 mono_arch_get_global_int_regs (MonoCompile *cfg)
1661 {
1662         GList *regs = NULL;
1663
1664         mono_arch_compute_omit_fp (cfg);
1665
1666         if (cfg->arch.omit_fp)
1667                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1668
1669         /* We use the callee saved registers for global allocation */
1670         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1671         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1672         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1673         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1674 #ifndef __native_client_codegen__
1675         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1676 #endif
1677 #ifdef TARGET_WIN32
1678         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1679         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1680 #endif
1681
1682         return regs;
1683 }
1684
1685 GList*
1686 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1687 {
1688         GList *regs = NULL;
1689         int i;
1690
1691         /* All XMM registers */
1692         for (i = 0; i < 16; ++i)
1693                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1694
1695         return regs;
1696 }
1697
1698 GList*
1699 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1700 {
1701         static GList *r = NULL;
1702
1703         if (r == NULL) {
1704                 GList *regs = NULL;
1705
1706                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1707                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1708                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1709                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1710                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1711 #ifndef __native_client_codegen__
1712                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1713 #endif
1714
1715                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1716                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1717                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1718                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1719                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1720                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1721                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1722                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1723
1724                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1725         }
1726
1727         return r;
1728 }
1729
1730 GList*
1731 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1732 {
1733         int i;
1734         static GList *r = NULL;
1735
1736         if (r == NULL) {
1737                 GList *regs = NULL;
1738
1739                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1740                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1741
1742                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1743         }
1744
1745         return r;
1746 }
1747
1748 /*
1749  * mono_arch_regalloc_cost:
1750  *
1751  *  Return the cost, in number of memory references, of the action of
1752  * allocating the variable VMV into a register during global register
1753  * allocation.
1754  */
1755 guint32
1756 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1757 {
1758         MonoInst *ins = cfg->varinfo [vmv->idx];
1759
1760         if (cfg->method->save_lmf)
1761                 /* The register is already saved */
1762                 /* substract 1 for the invisible store in the prolog */
1763                 return (ins->opcode == OP_ARG) ? 0 : 1;
1764         else
1765                 /* push+pop */
1766                 return (ins->opcode == OP_ARG) ? 1 : 2;
1767 }
1768
1769 /*
1770  * mono_arch_fill_argument_info:
1771  *
1772  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1773  * of the method.
1774  */
1775 void
1776 mono_arch_fill_argument_info (MonoCompile *cfg)
1777 {
1778         MonoType *sig_ret;
1779         MonoMethodSignature *sig;
1780         MonoInst *ins;
1781         int i;
1782         CallInfo *cinfo;
1783
1784         sig = mono_method_signature (cfg->method);
1785
1786         cinfo = (CallInfo *)cfg->arch.cinfo;
1787         sig_ret = mini_get_underlying_type (sig->ret);
1788
1789         /*
1790          * Contrary to mono_arch_allocate_vars (), the information should describe
1791          * where the arguments are at the beginning of the method, not where they can be
1792          * accessed during the execution of the method. The later makes no sense for the
1793          * global register allocator, since a variable can be in more than one location.
1794          */
1795         switch (cinfo->ret.storage) {
1796         case ArgInIReg:
1797         case ArgInFloatSSEReg:
1798         case ArgInDoubleSSEReg:
1799                 cfg->ret->opcode = OP_REGVAR;
1800                 cfg->ret->inst_c0 = cinfo->ret.reg;
1801                 break;
1802         case ArgValuetypeInReg:
1803                 cfg->ret->opcode = OP_REGOFFSET;
1804                 cfg->ret->inst_basereg = -1;
1805                 cfg->ret->inst_offset = -1;
1806                 break;
1807         case ArgNone:
1808                 break;
1809         default:
1810                 g_assert_not_reached ();
1811         }
1812
1813         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1814                 ArgInfo *ainfo = &cinfo->args [i];
1815
1816                 ins = cfg->args [i];
1817
1818                 switch (ainfo->storage) {
1819                 case ArgInIReg:
1820                 case ArgInFloatSSEReg:
1821                 case ArgInDoubleSSEReg:
1822                         ins->opcode = OP_REGVAR;
1823                         ins->inst_c0 = ainfo->reg;
1824                         break;
1825                 case ArgOnStack:
1826                         ins->opcode = OP_REGOFFSET;
1827                         ins->inst_basereg = -1;
1828                         ins->inst_offset = -1;
1829                         break;
1830                 case ArgValuetypeInReg:
1831                         /* Dummy */
1832                         ins->opcode = OP_NOP;
1833                         break;
1834                 default:
1835                         g_assert_not_reached ();
1836                 }
1837         }
1838 }
1839
1840 void
1841 mono_arch_allocate_vars (MonoCompile *cfg)
1842 {
1843         MonoType *sig_ret;
1844         MonoMethodSignature *sig;
1845         MonoInst *ins;
1846         int i, offset;
1847         guint32 locals_stack_size, locals_stack_align;
1848         gint32 *offsets;
1849         CallInfo *cinfo;
1850
1851         sig = mono_method_signature (cfg->method);
1852
1853         cinfo = (CallInfo *)cfg->arch.cinfo;
1854         sig_ret = mini_get_underlying_type (sig->ret);
1855
1856         mono_arch_compute_omit_fp (cfg);
1857
1858         /*
1859          * We use the ABI calling conventions for managed code as well.
1860          * Exception: valuetypes are only sometimes passed or returned in registers.
1861          */
1862
1863         /*
1864          * The stack looks like this:
1865          * <incoming arguments passed on the stack>
1866          * <return value>
1867          * <lmf/caller saved registers>
1868          * <locals>
1869          * <spill area>
1870          * <localloc area>  -> grows dynamically
1871          * <params area>
1872          */
1873
1874         if (cfg->arch.omit_fp) {
1875                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1876                 cfg->frame_reg = AMD64_RSP;
1877                 offset = 0;
1878         } else {
1879                 /* Locals are allocated backwards from %fp */
1880                 cfg->frame_reg = AMD64_RBP;
1881                 offset = 0;
1882         }
1883
1884         cfg->arch.saved_iregs = cfg->used_int_regs;
1885         if (cfg->method->save_lmf)
1886                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1887                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1888
1889         if (cfg->arch.omit_fp)
1890                 cfg->arch.reg_save_area_offset = offset;
1891         /* Reserve space for callee saved registers */
1892         for (i = 0; i < AMD64_NREG; ++i)
1893                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1894                         offset += sizeof(mgreg_t);
1895                 }
1896         if (!cfg->arch.omit_fp)
1897                 cfg->arch.reg_save_area_offset = -offset;
1898
1899         if (sig_ret->type != MONO_TYPE_VOID) {
1900                 switch (cinfo->ret.storage) {
1901                 case ArgInIReg:
1902                 case ArgInFloatSSEReg:
1903                 case ArgInDoubleSSEReg:
1904                         cfg->ret->opcode = OP_REGVAR;
1905                         cfg->ret->inst_c0 = cinfo->ret.reg;
1906                         cfg->ret->dreg = cinfo->ret.reg;
1907                         break;
1908                 case ArgValuetypeAddrInIReg:
1909                         /* The register is volatile */
1910                         cfg->vret_addr->opcode = OP_REGOFFSET;
1911                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1912                         if (cfg->arch.omit_fp) {
1913                                 cfg->vret_addr->inst_offset = offset;
1914                                 offset += 8;
1915                         } else {
1916                                 offset += 8;
1917                                 cfg->vret_addr->inst_offset = -offset;
1918                         }
1919                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1920                                 printf ("vret_addr =");
1921                                 mono_print_ins (cfg->vret_addr);
1922                         }
1923                         break;
1924                 case ArgValuetypeInReg:
1925                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1926                         cfg->ret->opcode = OP_REGOFFSET;
1927                         cfg->ret->inst_basereg = cfg->frame_reg;
1928                         if (cfg->arch.omit_fp) {
1929                                 cfg->ret->inst_offset = offset;
1930                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1931                         } else {
1932                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1933                                 cfg->ret->inst_offset = - offset;
1934                         }
1935                         break;
1936                 default:
1937                         g_assert_not_reached ();
1938                 }
1939         }
1940
1941         /* Allocate locals */
1942         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1943         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1944                 char *mname = mono_method_full_name (cfg->method, TRUE);
1945                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1946                 g_free (mname);
1947                 return;
1948         }
1949
1950         if (locals_stack_align) {
1951                 offset += (locals_stack_align - 1);
1952                 offset &= ~(locals_stack_align - 1);
1953         }
1954         if (cfg->arch.omit_fp) {
1955                 cfg->locals_min_stack_offset = offset;
1956                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1957         } else {
1958                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1959                 cfg->locals_max_stack_offset = - offset;
1960         }
1961
1962         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1963                 if (offsets [i] != -1) {
1964                         MonoInst *ins = cfg->varinfo [i];
1965                         ins->opcode = OP_REGOFFSET;
1966                         ins->inst_basereg = cfg->frame_reg;
1967                         if (cfg->arch.omit_fp)
1968                                 ins->inst_offset = (offset + offsets [i]);
1969                         else
1970                                 ins->inst_offset = - (offset + offsets [i]);
1971                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1972                 }
1973         }
1974         offset += locals_stack_size;
1975
1976         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1977                 g_assert (!cfg->arch.omit_fp);
1978                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1979                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1980         }
1981
1982         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1983                 ins = cfg->args [i];
1984                 if (ins->opcode != OP_REGVAR) {
1985                         ArgInfo *ainfo = &cinfo->args [i];
1986                         gboolean inreg = TRUE;
1987
1988                         /* FIXME: Allocate volatile arguments to registers */
1989                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1990                                 inreg = FALSE;
1991
1992                         /*
1993                          * Under AMD64, all registers used to pass arguments to functions
1994                          * are volatile across calls.
1995                          * FIXME: Optimize this.
1996                          */
1997                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1998                                 inreg = FALSE;
1999
2000                         ins->opcode = OP_REGOFFSET;
2001
2002                         switch (ainfo->storage) {
2003                         case ArgInIReg:
2004                         case ArgInFloatSSEReg:
2005                         case ArgInDoubleSSEReg:
2006                         case ArgGSharedVtInReg:
2007                                 if (inreg) {
2008                                         ins->opcode = OP_REGVAR;
2009                                         ins->dreg = ainfo->reg;
2010                                 }
2011                                 break;
2012                         case ArgOnStack:
2013                         case ArgGSharedVtOnStack:
2014                                 g_assert (!cfg->arch.omit_fp);
2015                                 ins->opcode = OP_REGOFFSET;
2016                                 ins->inst_basereg = cfg->frame_reg;
2017                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
2018                                 break;
2019                         case ArgValuetypeInReg:
2020                                 break;
2021                         case ArgValuetypeAddrInIReg: {
2022                                 MonoInst *indir;
2023                                 g_assert (!cfg->arch.omit_fp);
2024
2025                                 MONO_INST_NEW (cfg, indir, 0);
2026                                 indir->opcode = OP_REGOFFSET;
2027                                 if (ainfo->pair_storage [0] == ArgInIReg) {
2028                                         indir->inst_basereg = cfg->frame_reg;
2029                                         offset = ALIGN_TO (offset, sizeof (gpointer));
2030                                         offset += (sizeof (gpointer));
2031                                         indir->inst_offset = - offset;
2032                                 }
2033                                 else {
2034                                         indir->inst_basereg = cfg->frame_reg;
2035                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
2036                                 }
2037
2038                                 ins->opcode = OP_VTARG_ADDR;
2039                                 ins->inst_left = indir;
2040
2041                                 break;
2042                         }
2043                         default:
2044                                 NOT_IMPLEMENTED;
2045                         }
2046
2047                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
2048                                 ins->opcode = OP_REGOFFSET;
2049                                 ins->inst_basereg = cfg->frame_reg;
2050                                 /* These arguments are saved to the stack in the prolog */
2051                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2052                                 if (cfg->arch.omit_fp) {
2053                                         ins->inst_offset = offset;
2054                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2055                                         // Arguments are yet supported by the stack map creation code
2056                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2057                                 } else {
2058                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2059                                         ins->inst_offset = - offset;
2060                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2061                                 }
2062                         }
2063                 }
2064         }
2065
2066         cfg->stack_offset = offset;
2067 }
2068
2069 void
2070 mono_arch_create_vars (MonoCompile *cfg)
2071 {
2072         MonoMethodSignature *sig;
2073         CallInfo *cinfo;
2074         MonoType *sig_ret;
2075
2076         sig = mono_method_signature (cfg->method);
2077
2078         if (!cfg->arch.cinfo)
2079                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2080         cinfo = (CallInfo *)cfg->arch.cinfo;
2081
2082         if (cinfo->ret.storage == ArgValuetypeInReg)
2083                 cfg->ret_var_is_local = TRUE;
2084
2085         sig_ret = mini_get_underlying_type (sig->ret);
2086         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2087                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2088                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2089                         printf ("vret_addr = ");
2090                         mono_print_ins (cfg->vret_addr);
2091                 }
2092         }
2093
2094         if (cfg->gen_sdb_seq_points) {
2095                 MonoInst *ins;
2096
2097                 if (cfg->compile_aot) {
2098                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2099                         ins->flags |= MONO_INST_VOLATILE;
2100                         cfg->arch.seq_point_info_var = ins;
2101                 }
2102                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2103                 ins->flags |= MONO_INST_VOLATILE;
2104                 cfg->arch.ss_tramp_var = ins;
2105
2106                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2107                 ins->flags |= MONO_INST_VOLATILE;
2108                 cfg->arch.bp_tramp_var = ins;
2109         }
2110
2111         if (cfg->method->save_lmf)
2112                 cfg->create_lmf_var = TRUE;
2113
2114         if (cfg->method->save_lmf) {
2115                 cfg->lmf_ir = TRUE;
2116 #if !defined(TARGET_WIN32)
2117                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2118                         cfg->lmf_ir_mono_lmf = TRUE;
2119 #endif
2120         }
2121 }
2122
2123 static void
2124 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2125 {
2126         MonoInst *ins;
2127
2128         switch (storage) {
2129         case ArgInIReg:
2130                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2131                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2132                 ins->sreg1 = tree->dreg;
2133                 MONO_ADD_INS (cfg->cbb, ins);
2134                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2135                 break;
2136         case ArgInFloatSSEReg:
2137                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2138                 ins->dreg = mono_alloc_freg (cfg);
2139                 ins->sreg1 = tree->dreg;
2140                 MONO_ADD_INS (cfg->cbb, ins);
2141
2142                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2143                 break;
2144         case ArgInDoubleSSEReg:
2145                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2146                 ins->dreg = mono_alloc_freg (cfg);
2147                 ins->sreg1 = tree->dreg;
2148                 MONO_ADD_INS (cfg->cbb, ins);
2149
2150                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2151
2152                 break;
2153         default:
2154                 g_assert_not_reached ();
2155         }
2156 }
2157
2158 static int
2159 arg_storage_to_load_membase (ArgStorage storage)
2160 {
2161         switch (storage) {
2162         case ArgInIReg:
2163 #if defined(__mono_ilp32__)
2164                 return OP_LOADI8_MEMBASE;
2165 #else
2166                 return OP_LOAD_MEMBASE;
2167 #endif
2168         case ArgInDoubleSSEReg:
2169                 return OP_LOADR8_MEMBASE;
2170         case ArgInFloatSSEReg:
2171                 return OP_LOADR4_MEMBASE;
2172         default:
2173                 g_assert_not_reached ();
2174         }
2175
2176         return -1;
2177 }
2178
2179 static void
2180 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2181 {
2182         MonoMethodSignature *tmp_sig;
2183         int sig_reg;
2184
2185         if (call->tail_call)
2186                 NOT_IMPLEMENTED;
2187
2188         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2189
2190         /*
2191          * mono_ArgIterator_Setup assumes the signature cookie is
2192          * passed first and all the arguments which were before it are
2193          * passed on the stack after the signature. So compensate by
2194          * passing a different signature.
2195          */
2196         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2197         tmp_sig->param_count -= call->signature->sentinelpos;
2198         tmp_sig->sentinelpos = 0;
2199         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2200
2201         sig_reg = mono_alloc_ireg (cfg);
2202         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2203
2204         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2205 }
2206
2207 #ifdef ENABLE_LLVM
2208 static inline LLVMArgStorage
2209 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2210 {
2211         switch (storage) {
2212         case ArgInIReg:
2213                 return LLVMArgInIReg;
2214         case ArgNone:
2215                 return LLVMArgNone;
2216         case ArgGSharedVtInReg:
2217         case ArgGSharedVtOnStack:
2218                 return LLVMArgGSharedVt;
2219         default:
2220                 g_assert_not_reached ();
2221                 return LLVMArgNone;
2222         }
2223 }
2224
2225 LLVMCallInfo*
2226 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2227 {
2228         int i, n;
2229         CallInfo *cinfo;
2230         ArgInfo *ainfo;
2231         int j;
2232         LLVMCallInfo *linfo;
2233         MonoType *t, *sig_ret;
2234
2235         n = sig->param_count + sig->hasthis;
2236         sig_ret = mini_get_underlying_type (sig->ret);
2237
2238         cinfo = get_call_info (cfg->mempool, sig);
2239
2240         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2241
2242         /*
2243          * LLVM always uses the native ABI while we use our own ABI, the
2244          * only difference is the handling of vtypes:
2245          * - we only pass/receive them in registers in some cases, and only
2246          *   in 1 or 2 integer registers.
2247          */
2248         switch (cinfo->ret.storage) {
2249         case ArgNone:
2250                 linfo->ret.storage = LLVMArgNone;
2251                 break;
2252         case ArgInIReg:
2253         case ArgInFloatSSEReg:
2254         case ArgInDoubleSSEReg:
2255                 linfo->ret.storage = LLVMArgNormal;
2256                 break;
2257         case ArgValuetypeInReg: {
2258                 ainfo = &cinfo->ret;
2259
2260                 if (sig->pinvoke &&
2261                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2262                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2263                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
2264                         cfg->disable_llvm = TRUE;
2265                         return linfo;
2266                 }
2267
2268                 linfo->ret.storage = LLVMArgVtypeInReg;
2269                 for (j = 0; j < 2; ++j)
2270                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2271                 break;
2272         }
2273         case ArgValuetypeAddrInIReg:
2274                 /* Vtype returned using a hidden argument */
2275                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2276                 linfo->vret_arg_index = cinfo->vret_arg_index;
2277                 break;
2278         default:
2279                 g_assert_not_reached ();
2280                 break;
2281         }
2282
2283         for (i = 0; i < n; ++i) {
2284                 ainfo = cinfo->args + i;
2285
2286                 if (i >= sig->hasthis)
2287                         t = sig->params [i - sig->hasthis];
2288                 else
2289                         t = &mono_defaults.int_class->byval_arg;
2290
2291                 linfo->args [i].storage = LLVMArgNone;
2292
2293                 switch (ainfo->storage) {
2294                 case ArgInIReg:
2295                         linfo->args [i].storage = LLVMArgNormal;
2296                         break;
2297                 case ArgInDoubleSSEReg:
2298                 case ArgInFloatSSEReg:
2299                         linfo->args [i].storage = LLVMArgNormal;
2300                         break;
2301                 case ArgOnStack:
2302                         if (MONO_TYPE_ISSTRUCT (t))
2303                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2304                         else
2305                                 linfo->args [i].storage = LLVMArgNormal;
2306                         break;
2307                 case ArgValuetypeInReg:
2308                         if (sig->pinvoke &&
2309                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2310                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2311                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2312                                 cfg->disable_llvm = TRUE;
2313                                 return linfo;
2314                         }
2315
2316                         linfo->args [i].storage = LLVMArgVtypeInReg;
2317                         for (j = 0; j < 2; ++j)
2318                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2319                         break;
2320                 case ArgGSharedVtInReg:
2321                 case ArgGSharedVtOnStack:
2322                         linfo->args [i].storage = LLVMArgGSharedVt;
2323                         break;
2324                 default:
2325                         cfg->exception_message = g_strdup ("ainfo->storage");
2326                         cfg->disable_llvm = TRUE;
2327                         break;
2328                 }
2329         }
2330
2331         return linfo;
2332 }
2333 #endif
2334
2335 void
2336 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2337 {
2338         MonoInst *arg, *in;
2339         MonoMethodSignature *sig;
2340         MonoType *sig_ret;
2341         int i, n;
2342         CallInfo *cinfo;
2343         ArgInfo *ainfo;
2344
2345         sig = call->signature;
2346         n = sig->param_count + sig->hasthis;
2347
2348         cinfo = get_call_info (cfg->mempool, sig);
2349
2350         sig_ret = sig->ret;
2351
2352         if (COMPILE_LLVM (cfg)) {
2353                 /* We shouldn't be called in the llvm case */
2354                 cfg->disable_llvm = TRUE;
2355                 return;
2356         }
2357
2358         /*
2359          * Emit all arguments which are passed on the stack to prevent register
2360          * allocation problems.
2361          */
2362         for (i = 0; i < n; ++i) {
2363                 MonoType *t;
2364                 ainfo = cinfo->args + i;
2365
2366                 in = call->args [i];
2367
2368                 if (sig->hasthis && i == 0)
2369                         t = &mono_defaults.object_class->byval_arg;
2370                 else
2371                         t = sig->params [i - sig->hasthis];
2372
2373                 t = mini_get_underlying_type (t);
2374                 //XXX what about ArgGSharedVtOnStack here?
2375                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2376                         if (!t->byref) {
2377                                 if (t->type == MONO_TYPE_R4)
2378                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2379                                 else if (t->type == MONO_TYPE_R8)
2380                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2381                                 else
2382                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2383                         } else {
2384                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2385                         }
2386                         if (cfg->compute_gc_maps) {
2387                                 MonoInst *def;
2388
2389                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2390                         }
2391                 }
2392         }
2393
2394         /*
2395          * Emit all parameters passed in registers in non-reverse order for better readability
2396          * and to help the optimization in emit_prolog ().
2397          */
2398         for (i = 0; i < n; ++i) {
2399                 ainfo = cinfo->args + i;
2400
2401                 in = call->args [i];
2402
2403                 if (ainfo->storage == ArgInIReg)
2404                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2405         }
2406
2407         for (i = n - 1; i >= 0; --i) {
2408                 MonoType *t;
2409
2410                 ainfo = cinfo->args + i;
2411
2412                 in = call->args [i];
2413
2414                 if (sig->hasthis && i == 0)
2415                         t = &mono_defaults.object_class->byval_arg;
2416                 else
2417                         t = sig->params [i - sig->hasthis];
2418                 t = mini_get_underlying_type (t);
2419
2420                 switch (ainfo->storage) {
2421                 case ArgInIReg:
2422                         /* Already done */
2423                         break;
2424                 case ArgInFloatSSEReg:
2425                 case ArgInDoubleSSEReg:
2426                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2427                         break;
2428                 case ArgOnStack:
2429                 case ArgValuetypeInReg:
2430                 case ArgValuetypeAddrInIReg:
2431                 case ArgGSharedVtInReg:
2432                 case ArgGSharedVtOnStack: {
2433                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2434                                 /* Already emitted above */
2435                                 break;
2436                         //FIXME what about ArgGSharedVtOnStack ?
2437                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2438                                 MonoInst *call_inst = (MonoInst*)call;
2439                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2440                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2441                                 break;
2442                         }
2443
2444                         guint32 align;
2445                         guint32 size;
2446
2447                         if (sig->pinvoke)
2448                                 size = mono_type_native_stack_size (t, &align);
2449                         else {
2450                                 /*
2451                                  * Other backends use mono_type_stack_size (), but that
2452                                  * aligns the size to 8, which is larger than the size of
2453                                  * the source, leading to reads of invalid memory if the
2454                                  * source is at the end of address space.
2455                                  */
2456                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2457                         }
2458
2459                         if (size >= 10000) {
2460                                 /* Avoid asserts in emit_memcpy () */
2461                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2462                                 /* Continue normally */
2463                         }
2464
2465                         if (size > 0) {
2466                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2467                                 arg->sreg1 = in->dreg;
2468                                 arg->klass = mono_class_from_mono_type (t);
2469                                 arg->backend.size = size;
2470                                 arg->inst_p0 = call;
2471                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2472                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2473
2474                                 MONO_ADD_INS (cfg->cbb, arg);
2475                         }
2476                         break;
2477                 }
2478                 default:
2479                         g_assert_not_reached ();
2480                 }
2481
2482                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2483                         /* Emit the signature cookie just before the implicit arguments */
2484                         emit_sig_cookie (cfg, call, cinfo);
2485         }
2486
2487         /* Handle the case where there are no implicit arguments */
2488         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2489                 emit_sig_cookie (cfg, call, cinfo);
2490
2491         switch (cinfo->ret.storage) {
2492         case ArgValuetypeInReg:
2493                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2494                         /*
2495                          * Tell the JIT to use a more efficient calling convention: call using
2496                          * OP_CALL, compute the result location after the call, and save the
2497                          * result there.
2498                          */
2499                         call->vret_in_reg = TRUE;
2500                         /*
2501                          * Nullify the instruction computing the vret addr to enable
2502                          * future optimizations.
2503                          */
2504                         if (call->vret_var)
2505                                 NULLIFY_INS (call->vret_var);
2506                 } else {
2507                         if (call->tail_call)
2508                                 NOT_IMPLEMENTED;
2509                         /*
2510                          * The valuetype is in RAX:RDX after the call, need to be copied to
2511                          * the stack. Push the address here, so the call instruction can
2512                          * access it.
2513                          */
2514                         if (!cfg->arch.vret_addr_loc) {
2515                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2516                                 /* Prevent it from being register allocated or optimized away */
2517                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2518                         }
2519
2520                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2521                 }
2522                 break;
2523         case ArgValuetypeAddrInIReg: {
2524                 MonoInst *vtarg;
2525                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2526                 vtarg->sreg1 = call->vret_var->dreg;
2527                 vtarg->dreg = mono_alloc_preg (cfg);
2528                 MONO_ADD_INS (cfg->cbb, vtarg);
2529
2530                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2531                 break;
2532         }
2533         default:
2534                 break;
2535         }
2536
2537         if (cfg->method->save_lmf) {
2538                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2539                 MONO_ADD_INS (cfg->cbb, arg);
2540         }
2541
2542         call->stack_usage = cinfo->stack_usage;
2543 }
2544
2545 void
2546 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2547 {
2548         MonoInst *arg;
2549         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2550         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2551         int size = ins->backend.size;
2552
2553         switch (ainfo->storage) {
2554         case ArgValuetypeInReg: {
2555                 MonoInst *load;
2556                 int part;
2557
2558                 for (part = 0; part < 2; ++part) {
2559                         if (ainfo->pair_storage [part] == ArgNone)
2560                                 continue;
2561
2562                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2563                         load->inst_basereg = src->dreg;
2564                         load->inst_offset = part * sizeof(mgreg_t);
2565
2566                         switch (ainfo->pair_storage [part]) {
2567                         case ArgInIReg:
2568                                 load->dreg = mono_alloc_ireg (cfg);
2569                                 break;
2570                         case ArgInDoubleSSEReg:
2571                         case ArgInFloatSSEReg:
2572                                 load->dreg = mono_alloc_freg (cfg);
2573                                 break;
2574                         default:
2575                                 g_assert_not_reached ();
2576                         }
2577                         MONO_ADD_INS (cfg->cbb, load);
2578
2579                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2580                 }
2581                 break;
2582         }
2583         case ArgValuetypeAddrInIReg: {
2584                 MonoInst *vtaddr, *load;
2585                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2586
2587                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2588                 cfg->has_indirection = TRUE;
2589                 load->inst_p0 = vtaddr;
2590                 vtaddr->flags |= MONO_INST_INDIRECT;
2591                 load->type = STACK_MP;
2592                 load->klass = vtaddr->klass;
2593                 load->dreg = mono_alloc_ireg (cfg);
2594                 MONO_ADD_INS (cfg->cbb, load);
2595                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2596
2597                 if (ainfo->pair_storage [0] == ArgInIReg) {
2598                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2599                         arg->dreg = mono_alloc_ireg (cfg);
2600                         arg->sreg1 = load->dreg;
2601                         arg->inst_imm = 0;
2602                         MONO_ADD_INS (cfg->cbb, arg);
2603                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2604                 } else {
2605                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2606                 }
2607                 break;
2608         }
2609         case ArgGSharedVtInReg:
2610                 /* Pass by addr */
2611                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2612                 break;
2613         case ArgGSharedVtOnStack:
2614                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2615                 break;
2616         default:
2617                 if (size == 8) {
2618                         int dreg = mono_alloc_ireg (cfg);
2619
2620                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2621                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2622                 } else if (size <= 40) {
2623                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2624                 } else {
2625                         // FIXME: Code growth
2626                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2627                 }
2628
2629                 if (cfg->compute_gc_maps) {
2630                         MonoInst *def;
2631                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2632                 }
2633         }
2634 }
2635
2636 void
2637 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2638 {
2639         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2640
2641         if (ret->type == MONO_TYPE_R4) {
2642                 if (COMPILE_LLVM (cfg))
2643                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2644                 else
2645                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2646                 return;
2647         } else if (ret->type == MONO_TYPE_R8) {
2648                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2649                 return;
2650         }
2651
2652         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2653 }
2654
2655 #endif /* DISABLE_JIT */
2656
2657 #define EMIT_COND_BRANCH(ins,cond,sign) \
2658         if (ins->inst_true_bb->native_offset) { \
2659                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2660         } else { \
2661                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2662                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2663             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2664                         x86_branch8 (code, cond, 0, sign); \
2665                 else \
2666                         x86_branch32 (code, cond, 0, sign); \
2667 }
2668
2669 typedef struct {
2670         MonoMethodSignature *sig;
2671         CallInfo *cinfo;
2672 } ArchDynCallInfo;
2673
2674 static gboolean
2675 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2676 {
2677         int i;
2678
2679 #ifdef HOST_WIN32
2680         return FALSE;
2681 #endif
2682
2683         switch (cinfo->ret.storage) {
2684         case ArgNone:
2685         case ArgInIReg:
2686         case ArgInFloatSSEReg:
2687         case ArgInDoubleSSEReg:
2688                 break;
2689         case ArgValuetypeInReg: {
2690                 ArgInfo *ainfo = &cinfo->ret;
2691
2692                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2693                         return FALSE;
2694                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2695                         return FALSE;
2696                 break;
2697         }
2698         default:
2699                 return FALSE;
2700         }
2701
2702         for (i = 0; i < cinfo->nargs; ++i) {
2703                 ArgInfo *ainfo = &cinfo->args [i];
2704                 switch (ainfo->storage) {
2705                 case ArgInIReg:
2706                 case ArgInFloatSSEReg:
2707                 case ArgInDoubleSSEReg:
2708                         break;
2709                 case ArgValuetypeInReg:
2710                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2711                                 return FALSE;
2712                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2713                                 return FALSE;
2714                         break;
2715                 default:
2716                         return FALSE;
2717                 }
2718         }
2719
2720         return TRUE;
2721 }
2722
2723 /*
2724  * mono_arch_dyn_call_prepare:
2725  *
2726  *   Return a pointer to an arch-specific structure which contains information
2727  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2728  * supported for SIG.
2729  * This function is equivalent to ffi_prep_cif in libffi.
2730  */
2731 MonoDynCallInfo*
2732 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2733 {
2734         ArchDynCallInfo *info;
2735         CallInfo *cinfo;
2736
2737         cinfo = get_call_info (NULL, sig);
2738
2739         if (!dyn_call_supported (sig, cinfo)) {
2740                 g_free (cinfo);
2741                 return NULL;
2742         }
2743
2744         info = g_new0 (ArchDynCallInfo, 1);
2745         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2746         info->sig = sig;
2747         info->cinfo = cinfo;
2748
2749         return (MonoDynCallInfo*)info;
2750 }
2751
2752 /*
2753  * mono_arch_dyn_call_free:
2754  *
2755  *   Free a MonoDynCallInfo structure.
2756  */
2757 void
2758 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2759 {
2760         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2761
2762         g_free (ainfo->cinfo);
2763         g_free (ainfo);
2764 }
2765
2766 #if !defined(__native_client__)
2767 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2768 #define GREG_TO_PTR(greg) (gpointer)(greg)
2769 #else
2770 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2771 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2772 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2773 #endif
2774
2775 /*
2776  * mono_arch_get_start_dyn_call:
2777  *
2778  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2779  * store the result into BUF.
2780  * ARGS should be an array of pointers pointing to the arguments.
2781  * RET should point to a memory buffer large enought to hold the result of the
2782  * call.
2783  * This function should be as fast as possible, any work which does not depend
2784  * on the actual values of the arguments should be done in
2785  * mono_arch_dyn_call_prepare ().
2786  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2787  * libffi.
2788  */
2789 void
2790 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2791 {
2792         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2793         DynCallArgs *p = (DynCallArgs*)buf;
2794         int arg_index, greg, freg, i, pindex;
2795         MonoMethodSignature *sig = dinfo->sig;
2796         int buffer_offset = 0;
2797
2798         g_assert (buf_len >= sizeof (DynCallArgs));
2799
2800         p->res = 0;
2801         p->ret = ret;
2802
2803         arg_index = 0;
2804         greg = 0;
2805         freg = 0;
2806         pindex = 0;
2807
2808         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2809                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2810                 if (!sig->hasthis)
2811                         pindex = 1;
2812         }
2813
2814         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2815                 p->regs [greg ++] = PTR_TO_GREG(ret);
2816
2817         for (i = pindex; i < sig->param_count; i++) {
2818                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2819                 gpointer *arg = args [arg_index ++];
2820
2821                 if (t->byref) {
2822                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2823                         continue;
2824                 }
2825
2826                 switch (t->type) {
2827                 case MONO_TYPE_STRING:
2828                 case MONO_TYPE_CLASS:
2829                 case MONO_TYPE_ARRAY:
2830                 case MONO_TYPE_SZARRAY:
2831                 case MONO_TYPE_OBJECT:
2832                 case MONO_TYPE_PTR:
2833                 case MONO_TYPE_I:
2834                 case MONO_TYPE_U:
2835 #if !defined(__mono_ilp32__)
2836                 case MONO_TYPE_I8:
2837                 case MONO_TYPE_U8:
2838 #endif
2839                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2840                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2841                         break;
2842 #if defined(__mono_ilp32__)
2843                 case MONO_TYPE_I8:
2844                 case MONO_TYPE_U8:
2845                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2846                         p->regs [greg ++] = *(guint64*)(arg);
2847                         break;
2848 #endif
2849                 case MONO_TYPE_U1:
2850                         p->regs [greg ++] = *(guint8*)(arg);
2851                         break;
2852                 case MONO_TYPE_I1:
2853                         p->regs [greg ++] = *(gint8*)(arg);
2854                         break;
2855                 case MONO_TYPE_I2:
2856                         p->regs [greg ++] = *(gint16*)(arg);
2857                         break;
2858                 case MONO_TYPE_U2:
2859                         p->regs [greg ++] = *(guint16*)(arg);
2860                         break;
2861                 case MONO_TYPE_I4:
2862                         p->regs [greg ++] = *(gint32*)(arg);
2863                         break;
2864                 case MONO_TYPE_U4:
2865                         p->regs [greg ++] = *(guint32*)(arg);
2866                         break;
2867                 case MONO_TYPE_R4: {
2868                         double d;
2869
2870                         *(float*)&d = *(float*)(arg);
2871                         p->has_fp = 1;
2872                         p->fregs [freg ++] = d;
2873                         break;
2874                 }
2875                 case MONO_TYPE_R8:
2876                         p->has_fp = 1;
2877                         p->fregs [freg ++] = *(double*)(arg);
2878                         break;
2879                 case MONO_TYPE_GENERICINST:
2880                     if (MONO_TYPE_IS_REFERENCE (t)) {
2881                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2882                                 break;
2883                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2884                                         MonoClass *klass = mono_class_from_mono_type (t);
2885                                         guint8 *nullable_buf;
2886                                         int size;
2887
2888                                         size = mono_class_value_size (klass, NULL);
2889                                         nullable_buf = p->buffer + buffer_offset;
2890                                         buffer_offset += size;
2891                                         g_assert (buffer_offset <= 256);
2892
2893                                         /* The argument pointed to by arg is either a boxed vtype or null */
2894                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2895
2896                                         arg = (gpointer*)nullable_buf;
2897                                         /* Fall though */
2898
2899                         } else {
2900                                 /* Fall through */
2901                         }
2902                 case MONO_TYPE_VALUETYPE: {
2903                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2904
2905                         g_assert (ainfo->storage == ArgValuetypeInReg);
2906                         if (ainfo->pair_storage [0] != ArgNone) {
2907                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2908                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2909                         }
2910                         if (ainfo->pair_storage [1] != ArgNone) {
2911                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2912                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2913                         }
2914                         break;
2915                 }
2916                 default:
2917                         g_assert_not_reached ();
2918                 }
2919         }
2920
2921         g_assert (greg <= PARAM_REGS);
2922 }
2923
2924 /*
2925  * mono_arch_finish_dyn_call:
2926  *
2927  *   Store the result of a dyn call into the return value buffer passed to
2928  * start_dyn_call ().
2929  * This function should be as fast as possible, any work which does not depend
2930  * on the actual values of the arguments should be done in
2931  * mono_arch_dyn_call_prepare ().
2932  */
2933 void
2934 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2935 {
2936         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2937         MonoMethodSignature *sig = dinfo->sig;
2938         DynCallArgs *dargs = (DynCallArgs*)buf;
2939         guint8 *ret = dargs->ret;
2940         mgreg_t res = dargs->res;
2941         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2942
2943         switch (sig_ret->type) {
2944         case MONO_TYPE_VOID:
2945                 *(gpointer*)ret = NULL;
2946                 break;
2947         case MONO_TYPE_STRING:
2948         case MONO_TYPE_CLASS:
2949         case MONO_TYPE_ARRAY:
2950         case MONO_TYPE_SZARRAY:
2951         case MONO_TYPE_OBJECT:
2952         case MONO_TYPE_I:
2953         case MONO_TYPE_U:
2954         case MONO_TYPE_PTR:
2955                 *(gpointer*)ret = GREG_TO_PTR(res);
2956                 break;
2957         case MONO_TYPE_I1:
2958                 *(gint8*)ret = res;
2959                 break;
2960         case MONO_TYPE_U1:
2961                 *(guint8*)ret = res;
2962                 break;
2963         case MONO_TYPE_I2:
2964                 *(gint16*)ret = res;
2965                 break;
2966         case MONO_TYPE_U2:
2967                 *(guint16*)ret = res;
2968                 break;
2969         case MONO_TYPE_I4:
2970                 *(gint32*)ret = res;
2971                 break;
2972         case MONO_TYPE_U4:
2973                 *(guint32*)ret = res;
2974                 break;
2975         case MONO_TYPE_I8:
2976                 *(gint64*)ret = res;
2977                 break;
2978         case MONO_TYPE_U8:
2979                 *(guint64*)ret = res;
2980                 break;
2981         case MONO_TYPE_R4:
2982                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2983                 break;
2984         case MONO_TYPE_R8:
2985                 *(double*)ret = dargs->fregs [0];
2986                 break;
2987         case MONO_TYPE_GENERICINST:
2988                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2989                         *(gpointer*)ret = GREG_TO_PTR(res);
2990                         break;
2991                 } else {
2992                         /* Fall through */
2993                 }
2994         case MONO_TYPE_VALUETYPE:
2995                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2996                         /* Nothing to do */
2997                 } else {
2998                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2999
3000                         g_assert (ainfo->storage == ArgValuetypeInReg);
3001
3002                         if (ainfo->pair_storage [0] != ArgNone) {
3003                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
3004                                 ((mgreg_t*)ret)[0] = res;
3005                         }
3006
3007                         g_assert (ainfo->pair_storage [1] == ArgNone);
3008                 }
3009                 break;
3010         default:
3011                 g_assert_not_reached ();
3012         }
3013 }
3014
3015 /* emit an exception if condition is fail */
3016 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
3017         do {                                                        \
3018                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
3019                 if (tins == NULL) {                                                                             \
3020                         mono_add_patch_info (cfg, code - cfg->native_code,   \
3021                                         MONO_PATCH_INFO_EXC, exc_name);  \
3022                         x86_branch32 (code, cond, 0, signed);               \
3023                 } else {        \
3024                         EMIT_COND_BRANCH (tins, cond, signed);  \
3025                 }                       \
3026         } while (0);
3027
3028 #define EMIT_FPCOMPARE(code) do { \
3029         amd64_fcompp (code); \
3030         amd64_fnstsw (code); \
3031 } while (0);
3032
3033 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3034     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3035         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3036         amd64_ ##op (code); \
3037         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3038         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3039 } while (0);
3040
3041 static guint8*
3042 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3043 {
3044         gboolean no_patch = FALSE;
3045
3046         /*
3047          * FIXME: Add support for thunks
3048          */
3049         {
3050                 gboolean near_call = FALSE;
3051
3052                 /*
3053                  * Indirect calls are expensive so try to make a near call if possible.
3054                  * The caller memory is allocated by the code manager so it is
3055                  * guaranteed to be at a 32 bit offset.
3056                  */
3057
3058                 if (patch_type != MONO_PATCH_INFO_ABS) {
3059                         /* The target is in memory allocated using the code manager */
3060                         near_call = TRUE;
3061
3062                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3063                                 if (((MonoMethod*)data)->klass->image->aot_module)
3064                                         /* The callee might be an AOT method */
3065                                         near_call = FALSE;
3066                                 if (((MonoMethod*)data)->dynamic)
3067                                         /* The target is in malloc-ed memory */
3068                                         near_call = FALSE;
3069                         }
3070
3071                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3072                                 /*
3073                                  * The call might go directly to a native function without
3074                                  * the wrapper.
3075                                  */
3076                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3077                                 if (mi) {
3078                                         gconstpointer target = mono_icall_get_wrapper (mi);
3079                                         if ((((guint64)target) >> 32) != 0)
3080                                                 near_call = FALSE;
3081                                 }
3082                         }
3083                 }
3084                 else {
3085                         MonoJumpInfo *jinfo = NULL;
3086
3087                         if (cfg->abs_patches)
3088                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3089                         if (jinfo) {
3090                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3091                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3092                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3093                                                 near_call = TRUE;
3094                                         no_patch = TRUE;
3095                                 } else {
3096                                         /*
3097                                          * This is not really an optimization, but required because the
3098                                          * generic class init trampolines use R11 to pass the vtable.
3099                                          */
3100                                         near_call = TRUE;
3101                                 }
3102                         } else {
3103                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3104                                 if (info) {
3105                                         if (info->func == info->wrapper) {
3106                                                 /* No wrapper */
3107                                                 if ((((guint64)info->func) >> 32) == 0)
3108                                                         near_call = TRUE;
3109                                         }
3110                                         else {
3111                                                 /* See the comment in mono_codegen () */
3112                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3113                                                         near_call = TRUE;
3114                                         }
3115                                 }
3116                                 else if ((((guint64)data) >> 32) == 0) {
3117                                         near_call = TRUE;
3118                                         no_patch = TRUE;
3119                                 }
3120                         }
3121                 }
3122
3123                 if (cfg->method->dynamic)
3124                         /* These methods are allocated using malloc */
3125                         near_call = FALSE;
3126
3127 #ifdef MONO_ARCH_NOMAP32BIT
3128                 near_call = FALSE;
3129 #endif
3130 #if defined(__native_client__)
3131                 /* Always use near_call == TRUE for Native Client */
3132                 near_call = TRUE;
3133 #endif
3134                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3135                 if (optimize_for_xen)
3136                         near_call = FALSE;
3137
3138                 if (cfg->compile_aot) {
3139                         near_call = TRUE;
3140                         no_patch = TRUE;
3141                 }
3142
3143                 if (near_call) {
3144                         /*
3145                          * Align the call displacement to an address divisible by 4 so it does
3146                          * not span cache lines. This is required for code patching to work on SMP
3147                          * systems.
3148                          */
3149                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3150                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3151                                 amd64_padding (code, pad_size);
3152                         }
3153                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3154                         amd64_call_code (code, 0);
3155                 }
3156                 else {
3157                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3158                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3159                         amd64_call_reg (code, GP_SCRATCH_REG);
3160                 }
3161         }
3162
3163         return code;
3164 }
3165
3166 static inline guint8*
3167 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3168 {
3169 #ifdef TARGET_WIN32
3170         if (win64_adjust_stack)
3171                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3172 #endif
3173         code = emit_call_body (cfg, code, patch_type, data);
3174 #ifdef TARGET_WIN32
3175         if (win64_adjust_stack)
3176                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3177 #endif
3178
3179         return code;
3180 }
3181
3182 static inline int
3183 store_membase_imm_to_store_membase_reg (int opcode)
3184 {
3185         switch (opcode) {
3186         case OP_STORE_MEMBASE_IMM:
3187                 return OP_STORE_MEMBASE_REG;
3188         case OP_STOREI4_MEMBASE_IMM:
3189                 return OP_STOREI4_MEMBASE_REG;
3190         case OP_STOREI8_MEMBASE_IMM:
3191                 return OP_STOREI8_MEMBASE_REG;
3192         }
3193
3194         return -1;
3195 }
3196
3197 #ifndef DISABLE_JIT
3198
3199 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3200
3201 /*
3202  * mono_arch_peephole_pass_1:
3203  *
3204  *   Perform peephole opts which should/can be performed before local regalloc
3205  */
3206 void
3207 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3208 {
3209         MonoInst *ins, *n;
3210
3211         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3212                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3213
3214                 switch (ins->opcode) {
3215                 case OP_ADD_IMM:
3216                 case OP_IADD_IMM:
3217                 case OP_LADD_IMM:
3218                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3219                                 /*
3220                                  * X86_LEA is like ADD, but doesn't have the
3221                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3222                                  * its operand to 64 bit.
3223                                  */
3224                                 ins->opcode = OP_X86_LEA_MEMBASE;
3225                                 ins->inst_basereg = ins->sreg1;
3226                         }
3227                         break;
3228                 case OP_LXOR:
3229                 case OP_IXOR:
3230                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3231                                 MonoInst *ins2;
3232
3233                                 /*
3234                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3235                                  * the latter has length 2-3 instead of 6 (reverse constant
3236                                  * propagation). These instruction sequences are very common
3237                                  * in the initlocals bblock.
3238                                  */
3239                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3240                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3241                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3242                                                 ins2->sreg1 = ins->dreg;
3243                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3244                                                 /* Continue */
3245                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3246                                                 NULLIFY_INS (ins2);
3247                                                 /* Continue */
3248                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3249                                                 /* Continue */
3250                                         } else {
3251                                                 break;
3252                                         }
3253                                 }
3254                         }
3255                         break;
3256                 case OP_COMPARE_IMM:
3257                 case OP_LCOMPARE_IMM:
3258                         /* OP_COMPARE_IMM (reg, 0)
3259                          * -->
3260                          * OP_AMD64_TEST_NULL (reg)
3261                          */
3262                         if (!ins->inst_imm)
3263                                 ins->opcode = OP_AMD64_TEST_NULL;
3264                         break;
3265                 case OP_ICOMPARE_IMM:
3266                         if (!ins->inst_imm)
3267                                 ins->opcode = OP_X86_TEST_NULL;
3268                         break;
3269                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3270                         /*
3271                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3272                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3273                          * -->
3274                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3275                          * OP_COMPARE_IMM reg, imm
3276                          *
3277                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3278                          */
3279                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3280                             ins->inst_basereg == last_ins->inst_destbasereg &&
3281                             ins->inst_offset == last_ins->inst_offset) {
3282                                         ins->opcode = OP_ICOMPARE_IMM;
3283                                         ins->sreg1 = last_ins->sreg1;
3284
3285                                         /* check if we can remove cmp reg,0 with test null */
3286                                         if (!ins->inst_imm)
3287                                                 ins->opcode = OP_X86_TEST_NULL;
3288                                 }
3289
3290                         break;
3291                 }
3292
3293                 mono_peephole_ins (bb, ins);
3294         }
3295 }
3296
3297 void
3298 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3299 {
3300         MonoInst *ins, *n;
3301
3302         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3303                 switch (ins->opcode) {
3304                 case OP_ICONST:
3305                 case OP_I8CONST: {
3306                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3307                         /* reg = 0 -> XOR (reg, reg) */
3308                         /* XOR sets cflags on x86, so we cant do it always */
3309                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3310                                 ins->opcode = OP_LXOR;
3311                                 ins->sreg1 = ins->dreg;
3312                                 ins->sreg2 = ins->dreg;
3313                                 /* Fall through */
3314                         } else {
3315                                 break;
3316                         }
3317                 }
3318                 case OP_LXOR:
3319                         /*
3320                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3321                          * 0 result into 64 bits.
3322                          */
3323                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3324                                 ins->opcode = OP_IXOR;
3325                         }
3326                         /* Fall through */
3327                 case OP_IXOR:
3328                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3329                                 MonoInst *ins2;
3330
3331                                 /*
3332                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3333                                  * the latter has length 2-3 instead of 6 (reverse constant
3334                                  * propagation). These instruction sequences are very common
3335                                  * in the initlocals bblock.
3336                                  */
3337                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3338                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3339                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3340                                                 ins2->sreg1 = ins->dreg;
3341                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3342                                                 /* Continue */
3343                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3344                                                 NULLIFY_INS (ins2);
3345                                                 /* Continue */
3346                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3347                                                 /* Continue */
3348                                         } else {
3349                                                 break;
3350                                         }
3351                                 }
3352                         }
3353                         break;
3354                 case OP_IADD_IMM:
3355                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3356                                 ins->opcode = OP_X86_INC_REG;
3357                         break;
3358                 case OP_ISUB_IMM:
3359                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3360                                 ins->opcode = OP_X86_DEC_REG;
3361                         break;
3362                 }
3363
3364                 mono_peephole_ins (bb, ins);
3365         }
3366 }
3367
3368 #define NEW_INS(cfg,ins,dest,op) do {   \
3369                 MONO_INST_NEW ((cfg), (dest), (op)); \
3370         (dest)->cil_code = (ins)->cil_code; \
3371         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3372         } while (0)
3373
3374 /*
3375  * mono_arch_lowering_pass:
3376  *
3377  *  Converts complex opcodes into simpler ones so that each IR instruction
3378  * corresponds to one machine instruction.
3379  */
3380 void
3381 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3382 {
3383         MonoInst *ins, *n, *temp;
3384
3385         /*
3386          * FIXME: Need to add more instructions, but the current machine
3387          * description can't model some parts of the composite instructions like
3388          * cdq.
3389          */
3390         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3391                 switch (ins->opcode) {
3392                 case OP_DIV_IMM:
3393                 case OP_REM_IMM:
3394                 case OP_IDIV_IMM:
3395                 case OP_IDIV_UN_IMM:
3396                 case OP_IREM_UN_IMM:
3397                 case OP_LREM_IMM:
3398                 case OP_IREM_IMM:
3399                         mono_decompose_op_imm (cfg, bb, ins);
3400                         break;
3401                 case OP_COMPARE_IMM:
3402                 case OP_LCOMPARE_IMM:
3403                         if (!amd64_use_imm32 (ins->inst_imm)) {
3404                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3405                                 temp->inst_c0 = ins->inst_imm;
3406                                 temp->dreg = mono_alloc_ireg (cfg);
3407                                 ins->opcode = OP_COMPARE;
3408                                 ins->sreg2 = temp->dreg;
3409                         }
3410                         break;
3411 #ifndef __mono_ilp32__
3412                 case OP_LOAD_MEMBASE:
3413 #endif
3414                 case OP_LOADI8_MEMBASE:
3415 #ifndef __native_client_codegen__
3416                 /*  Don't generate memindex opcodes (to simplify */
3417                 /*  read sandboxing) */
3418                         if (!amd64_use_imm32 (ins->inst_offset)) {
3419                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3420                                 temp->inst_c0 = ins->inst_offset;
3421                                 temp->dreg = mono_alloc_ireg (cfg);
3422                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3423                                 ins->inst_indexreg = temp->dreg;
3424                         }
3425 #endif
3426                         break;
3427 #ifndef __mono_ilp32__
3428                 case OP_STORE_MEMBASE_IMM:
3429 #endif
3430                 case OP_STOREI8_MEMBASE_IMM:
3431                         if (!amd64_use_imm32 (ins->inst_imm)) {
3432                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3433                                 temp->inst_c0 = ins->inst_imm;
3434                                 temp->dreg = mono_alloc_ireg (cfg);
3435                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3436                                 ins->sreg1 = temp->dreg;
3437                         }
3438                         break;
3439 #ifdef MONO_ARCH_SIMD_INTRINSICS
3440                 case OP_EXPAND_I1: {
3441                                 int temp_reg1 = mono_alloc_ireg (cfg);
3442                                 int temp_reg2 = mono_alloc_ireg (cfg);
3443                                 int original_reg = ins->sreg1;
3444
3445                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3446                                 temp->sreg1 = original_reg;
3447                                 temp->dreg = temp_reg1;
3448
3449                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3450                                 temp->sreg1 = temp_reg1;
3451                                 temp->dreg = temp_reg2;
3452                                 temp->inst_imm = 8;
3453
3454                                 NEW_INS (cfg, ins, temp, OP_LOR);
3455                                 temp->sreg1 = temp->dreg = temp_reg2;
3456                                 temp->sreg2 = temp_reg1;
3457
3458                                 ins->opcode = OP_EXPAND_I2;
3459                                 ins->sreg1 = temp_reg2;
3460                         }
3461                         break;
3462 #endif
3463                 default:
3464                         break;
3465                 }
3466         }
3467
3468         bb->max_vreg = cfg->next_vreg;
3469 }
3470
3471 static const int
3472 branch_cc_table [] = {
3473         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3474         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3475         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3476 };
3477
3478 /* Maps CMP_... constants to X86_CC_... constants */
3479 static const int
3480 cc_table [] = {
3481         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3482         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3483 };
3484
3485 static const int
3486 cc_signed_table [] = {
3487         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3488         FALSE, FALSE, FALSE, FALSE
3489 };
3490
3491 /*#include "cprop.c"*/
3492
3493 static unsigned char*
3494 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3495 {
3496         if (size == 8)
3497                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3498         else
3499                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3500
3501         if (size == 1)
3502                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3503         else if (size == 2)
3504                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3505         return code;
3506 }
3507
3508 static unsigned char*
3509 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3510 {
3511         int sreg = tree->sreg1;
3512         int need_touch = FALSE;
3513
3514 #if defined(TARGET_WIN32)
3515         need_touch = TRUE;
3516 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3517         if (!tree->flags & MONO_INST_INIT)
3518                 need_touch = TRUE;
3519 #endif
3520
3521         if (need_touch) {
3522                 guint8* br[5];
3523
3524                 /*
3525                  * Under Windows:
3526                  * If requested stack size is larger than one page,
3527                  * perform stack-touch operation
3528                  */
3529                 /*
3530                  * Generate stack probe code.
3531                  * Under Windows, it is necessary to allocate one page at a time,
3532                  * "touching" stack after each successful sub-allocation. This is
3533                  * because of the way stack growth is implemented - there is a
3534                  * guard page before the lowest stack page that is currently commited.
3535                  * Stack normally grows sequentially so OS traps access to the
3536                  * guard page and commits more pages when needed.
3537                  */
3538                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3539                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3540
3541                 br[2] = code; /* loop */
3542                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3543                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3544                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3545                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3546                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3547                 amd64_patch (br[3], br[2]);
3548                 amd64_test_reg_reg (code, sreg, sreg);
3549                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3550                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3551
3552                 br[1] = code; x86_jump8 (code, 0);
3553
3554                 amd64_patch (br[0], code);
3555                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3556                 amd64_patch (br[1], code);
3557                 amd64_patch (br[4], code);
3558         }
3559         else
3560                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3561
3562         if (tree->flags & MONO_INST_INIT) {
3563                 int offset = 0;
3564                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3565                         amd64_push_reg (code, AMD64_RAX);
3566                         offset += 8;
3567                 }
3568                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3569                         amd64_push_reg (code, AMD64_RCX);
3570                         offset += 8;
3571                 }
3572                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3573                         amd64_push_reg (code, AMD64_RDI);
3574                         offset += 8;
3575                 }
3576
3577                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3578                 if (sreg != AMD64_RCX)
3579                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3580                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3581
3582                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3583                 if (cfg->param_area)
3584                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3585                 amd64_cld (code);
3586 #if defined(__default_codegen__)
3587                 amd64_prefix (code, X86_REP_PREFIX);
3588                 amd64_stosl (code);
3589 #elif defined(__native_client_codegen__)
3590                 /* NaCl stos pseudo-instruction */
3591                 amd64_codegen_pre(code);
3592                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3593                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3594                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3595                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3596                 amd64_prefix (code, X86_REP_PREFIX);
3597                 amd64_stosl (code);
3598                 amd64_codegen_post(code);
3599 #endif /* __native_client_codegen__ */
3600
3601                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3602                         amd64_pop_reg (code, AMD64_RDI);
3603                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3604                         amd64_pop_reg (code, AMD64_RCX);
3605                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3606                         amd64_pop_reg (code, AMD64_RAX);
3607         }
3608         return code;
3609 }
3610
3611 static guint8*
3612 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3613 {
3614         CallInfo *cinfo;
3615         guint32 quad;
3616
3617         /* Move return value to the target register */
3618         /* FIXME: do this in the local reg allocator */
3619         switch (ins->opcode) {
3620         case OP_CALL:
3621         case OP_CALL_REG:
3622         case OP_CALL_MEMBASE:
3623         case OP_LCALL:
3624         case OP_LCALL_REG:
3625         case OP_LCALL_MEMBASE:
3626                 g_assert (ins->dreg == AMD64_RAX);
3627                 break;
3628         case OP_FCALL:
3629         case OP_FCALL_REG:
3630         case OP_FCALL_MEMBASE: {
3631                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3632                 if (rtype->type == MONO_TYPE_R4) {
3633                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3634                 }
3635                 else {
3636                         if (ins->dreg != AMD64_XMM0)
3637                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3638                 }
3639                 break;
3640         }
3641         case OP_RCALL:
3642         case OP_RCALL_REG:
3643         case OP_RCALL_MEMBASE:
3644                 if (ins->dreg != AMD64_XMM0)
3645                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3646                 break;
3647         case OP_VCALL:
3648         case OP_VCALL_REG:
3649         case OP_VCALL_MEMBASE:
3650         case OP_VCALL2:
3651         case OP_VCALL2_REG:
3652         case OP_VCALL2_MEMBASE:
3653                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3654                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3655                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3656
3657                         /* Load the destination address */
3658                         g_assert (loc->opcode == OP_REGOFFSET);
3659                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3660
3661                         for (quad = 0; quad < 2; quad ++) {
3662                                 switch (cinfo->ret.pair_storage [quad]) {
3663                                 case ArgInIReg:
3664                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3665                                         break;
3666                                 case ArgInFloatSSEReg:
3667                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3668                                         break;
3669                                 case ArgInDoubleSSEReg:
3670                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3671                                         break;
3672                                 case ArgNone:
3673                                         break;
3674                                 default:
3675                                         NOT_IMPLEMENTED;
3676                                 }
3677                         }
3678                 }
3679                 break;
3680         }
3681
3682         return code;
3683 }
3684
3685 #endif /* DISABLE_JIT */
3686
3687 #ifdef __APPLE__
3688 static int tls_gs_offset;
3689 #endif
3690
3691 gboolean
3692 mono_amd64_have_tls_get (void)
3693 {
3694 #ifdef TARGET_MACH
3695         static gboolean have_tls_get = FALSE;
3696         static gboolean inited = FALSE;
3697
3698         if (inited)
3699                 return have_tls_get;
3700
3701 #if MONO_HAVE_FAST_TLS
3702         guint8 *ins = (guint8*)pthread_getspecific;
3703
3704         /*
3705          * We're looking for these two instructions:
3706          *
3707          * mov    %gs:[offset](,%rdi,8),%rax
3708          * retq
3709          */
3710         have_tls_get = ins [0] == 0x65 &&
3711                        ins [1] == 0x48 &&
3712                        ins [2] == 0x8b &&
3713                        ins [3] == 0x04 &&
3714                        ins [4] == 0xfd &&
3715                        ins [6] == 0x00 &&
3716                        ins [7] == 0x00 &&
3717                        ins [8] == 0x00 &&
3718                        ins [9] == 0xc3;
3719
3720         tls_gs_offset = ins[5];
3721
3722         /*
3723          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3724          * For that version we're looking for these instructions:
3725          *
3726          * pushq  %rbp
3727          * movq   %rsp, %rbp
3728          * mov    %gs:[offset](,%rdi,8),%rax
3729          * popq   %rbp
3730          * retq
3731          */
3732         if (!have_tls_get) {
3733                 have_tls_get = ins [0] == 0x55 &&
3734                                ins [1] == 0x48 &&
3735                                ins [2] == 0x89 &&
3736                                ins [3] == 0xe5 &&
3737                                ins [4] == 0x65 &&
3738                                ins [5] == 0x48 &&
3739                                ins [6] == 0x8b &&
3740                                ins [7] == 0x04 &&
3741                                ins [8] == 0xfd &&
3742                                ins [10] == 0x00 &&
3743                                ins [11] == 0x00 &&
3744                                ins [12] == 0x00 &&
3745                                ins [13] == 0x5d &&
3746                                ins [14] == 0xc3;
3747
3748                 tls_gs_offset = ins[9];
3749         }
3750 #endif
3751
3752         inited = TRUE;
3753
3754         return have_tls_get;
3755 #elif defined(TARGET_ANDROID)
3756         return FALSE;
3757 #else
3758         return TRUE;
3759 #endif
3760 }
3761
3762 int
3763 mono_amd64_get_tls_gs_offset (void)
3764 {
3765 #ifdef TARGET_OSX
3766         return tls_gs_offset;
3767 #else
3768         g_assert_not_reached ();
3769         return -1;
3770 #endif
3771 }
3772
3773 /*
3774  * mono_amd64_emit_tls_get:
3775  * @code: buffer to store code to
3776  * @dreg: hard register where to place the result
3777  * @tls_offset: offset info
3778  *
3779  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3780  * the dreg register the item in the thread local storage identified
3781  * by tls_offset.
3782  *
3783  * Returns: a pointer to the end of the stored code
3784  */
3785 guint8*
3786 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3787 {
3788 #ifdef TARGET_WIN32
3789         if (tls_offset < 64) {
3790                 x86_prefix (code, X86_GS_PREFIX);
3791                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3792         } else {
3793                 guint8 *buf [16];
3794
3795                 g_assert (tls_offset < 0x440);
3796                 /* Load TEB->TlsExpansionSlots */
3797                 x86_prefix (code, X86_GS_PREFIX);
3798                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3799                 amd64_test_reg_reg (code, dreg, dreg);
3800                 buf [0] = code;
3801                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3802                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3803                 amd64_patch (buf [0], code);
3804         }
3805 #elif defined(__APPLE__)
3806         x86_prefix (code, X86_GS_PREFIX);
3807         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3808 #else
3809         if (optimize_for_xen) {
3810                 x86_prefix (code, X86_FS_PREFIX);
3811                 amd64_mov_reg_mem (code, dreg, 0, 8);
3812                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3813         } else {
3814                 x86_prefix (code, X86_FS_PREFIX);
3815                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3816         }
3817 #endif
3818         return code;
3819 }
3820
3821 static guint8*
3822 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3823 {
3824         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3825 #ifdef TARGET_OSX
3826         if (dreg != offset_reg)
3827                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3828         amd64_prefix (code, X86_GS_PREFIX);
3829         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3830 #elif defined(__linux__)
3831         int tmpreg = -1;
3832
3833         if (dreg == offset_reg) {
3834                 /* Use a temporary reg by saving it to the redzone */
3835                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3836                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3837                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3838                 offset_reg = tmpreg;
3839         }
3840         x86_prefix (code, X86_FS_PREFIX);
3841         amd64_mov_reg_mem (code, dreg, 0, 8);
3842         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3843         if (tmpreg != -1)
3844                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3845 #else
3846         g_assert_not_reached ();
3847 #endif
3848         return code;
3849 }
3850
3851 static guint8*
3852 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3853 {
3854 #ifdef TARGET_WIN32
3855         g_assert_not_reached ();
3856 #elif defined(__APPLE__)
3857         x86_prefix (code, X86_GS_PREFIX);
3858         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3859 #else
3860         g_assert (!optimize_for_xen);
3861         x86_prefix (code, X86_FS_PREFIX);
3862         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3863 #endif
3864         return code;
3865 }
3866
3867 static guint8*
3868 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3869 {
3870         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3871 #ifdef TARGET_WIN32
3872         g_assert_not_reached ();
3873 #elif defined(__APPLE__)
3874         x86_prefix (code, X86_GS_PREFIX);
3875         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3876 #else
3877         x86_prefix (code, X86_FS_PREFIX);
3878         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3879 #endif
3880         return code;
3881 }
3882
3883  /*
3884  * mono_arch_translate_tls_offset:
3885  *
3886  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3887  */
3888 int
3889 mono_arch_translate_tls_offset (int offset)
3890 {
3891 #ifdef __APPLE__
3892         return tls_gs_offset + (offset * 8);
3893 #else
3894         return offset;
3895 #endif
3896 }
3897
3898 /*
3899  * emit_setup_lmf:
3900  *
3901  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3902  */
3903 static guint8*
3904 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3905 {
3906         /*
3907          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3908          */
3909         /*
3910          * sp is saved right before calls but we need to save it here too so
3911          * async stack walks would work.
3912          */
3913         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3914         /* Save rbp */
3915         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3916         if (cfg->arch.omit_fp && cfa_offset != -1)
3917                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3918
3919         /* These can't contain refs */
3920         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3921         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3922         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3923         /* These are handled automatically by the stack marking code */
3924         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3925
3926         return code;
3927 }
3928
3929 #define REAL_PRINT_REG(text,reg) \
3930 mono_assert (reg >= 0); \
3931 amd64_push_reg (code, AMD64_RAX); \
3932 amd64_push_reg (code, AMD64_RDX); \
3933 amd64_push_reg (code, AMD64_RCX); \
3934 amd64_push_reg (code, reg); \
3935 amd64_push_imm (code, reg); \
3936 amd64_push_imm (code, text " %d %p\n"); \
3937 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3938 amd64_call_reg (code, AMD64_RAX); \
3939 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3940 amd64_pop_reg (code, AMD64_RCX); \
3941 amd64_pop_reg (code, AMD64_RDX); \
3942 amd64_pop_reg (code, AMD64_RAX);
3943
3944 /* benchmark and set based on cpu */
3945 #define LOOP_ALIGNMENT 8
3946 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3947
3948 #ifndef DISABLE_JIT
3949 void
3950 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3951 {
3952         MonoInst *ins;
3953         MonoCallInst *call;
3954         guint offset;
3955         guint8 *code = cfg->native_code + cfg->code_len;
3956         int max_len;
3957
3958         /* Fix max_offset estimate for each successor bb */
3959         if (cfg->opt & MONO_OPT_BRANCH) {
3960                 int current_offset = cfg->code_len;
3961                 MonoBasicBlock *current_bb;
3962                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3963                         current_bb->max_offset = current_offset;
3964                         current_offset += current_bb->max_length;
3965                 }
3966         }
3967
3968         if (cfg->opt & MONO_OPT_LOOP) {
3969                 int pad, align = LOOP_ALIGNMENT;
3970                 /* set alignment depending on cpu */
3971                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3972                         pad = align - pad;
3973                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3974                         amd64_padding (code, pad);
3975                         cfg->code_len += pad;
3976                         bb->native_offset = cfg->code_len;
3977                 }
3978         }
3979
3980 #if defined(__native_client_codegen__)
3981         /* For Native Client, all indirect call/jump targets must be */
3982         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3983         /* indirectly as well.                                       */
3984         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3985                                       (bb->flags & BB_EXCEPTION_HANDLER);
3986
3987         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3988                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3989                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3990                 cfg->code_len += pad;
3991                 bb->native_offset = cfg->code_len;
3992         }
3993 #endif  /*__native_client_codegen__*/
3994
3995         if (cfg->verbose_level > 2)
3996                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3997
3998         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3999                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
4000                 g_assert (!cfg->compile_aot);
4001
4002                 cov->data [bb->dfn].cil_code = bb->cil_code;
4003                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
4004                 /* this is not thread save, but good enough */
4005                 amd64_inc_membase (code, AMD64_R11, 0);
4006         }
4007
4008         offset = code - cfg->native_code;
4009
4010         mono_debug_open_block (cfg, bb, offset);
4011
4012     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
4013                 x86_breakpoint (code);
4014
4015         MONO_BB_FOR_EACH_INS (bb, ins) {
4016                 offset = code - cfg->native_code;
4017
4018                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4019
4020 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
4021
4022                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
4023                         cfg->code_size *= 2;
4024                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
4025                         code = cfg->native_code + offset;
4026                         cfg->stat_code_reallocs++;
4027                 }
4028
4029                 if (cfg->debug_info)
4030                         mono_debug_record_line_number (cfg, ins, offset);
4031
4032                 switch (ins->opcode) {
4033                 case OP_BIGMUL:
4034                         amd64_mul_reg (code, ins->sreg2, TRUE);
4035                         break;
4036                 case OP_BIGMUL_UN:
4037                         amd64_mul_reg (code, ins->sreg2, FALSE);
4038                         break;
4039                 case OP_X86_SETEQ_MEMBASE:
4040                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
4041                         break;
4042                 case OP_STOREI1_MEMBASE_IMM:
4043                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
4044                         break;
4045                 case OP_STOREI2_MEMBASE_IMM:
4046                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
4047                         break;
4048                 case OP_STOREI4_MEMBASE_IMM:
4049                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
4050                         break;
4051                 case OP_STOREI1_MEMBASE_REG:
4052                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4053                         break;
4054                 case OP_STOREI2_MEMBASE_REG:
4055                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4056                         break;
4057                 /* In AMD64 NaCl, pointers are 4 bytes, */
4058                 /*  so STORE_* != STOREI8_*. Likewise below. */
4059                 case OP_STORE_MEMBASE_REG:
4060                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4061                         break;
4062                 case OP_STOREI8_MEMBASE_REG:
4063                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4064                         break;
4065                 case OP_STOREI4_MEMBASE_REG:
4066                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4067                         break;
4068                 case OP_STORE_MEMBASE_IMM:
4069 #ifndef __native_client_codegen__
4070                         /* In NaCl, this could be a PCONST type, which could */
4071                         /* mean a pointer type was copied directly into the  */
4072                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4073                         /* the value would be 0x00000000FFFFFFFF which is    */
4074                         /* not proper for an imm32 unless you cast it.       */
4075                         g_assert (amd64_is_imm32 (ins->inst_imm));
4076 #endif
4077                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4078                         break;
4079                 case OP_STOREI8_MEMBASE_IMM:
4080                         g_assert (amd64_is_imm32 (ins->inst_imm));
4081                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4082                         break;
4083                 case OP_LOAD_MEM:
4084 #ifdef __mono_ilp32__
4085                         /* In ILP32, pointers are 4 bytes, so separate these */
4086                         /* cases, use literal 8 below where we really want 8 */
4087                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4088                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4089                         break;
4090 #endif
4091                 case OP_LOADI8_MEM:
4092                         // FIXME: Decompose this earlier
4093                         if (amd64_use_imm32 (ins->inst_imm))
4094                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4095                         else {
4096                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4097                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4098                         }
4099                         break;
4100                 case OP_LOADI4_MEM:
4101                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4102                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4103                         break;
4104                 case OP_LOADU4_MEM:
4105                         // FIXME: Decompose this earlier
4106                         if (amd64_use_imm32 (ins->inst_imm))
4107                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4108                         else {
4109                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4110                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4111                         }
4112                         break;
4113                 case OP_LOADU1_MEM:
4114                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4115                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4116                         break;
4117                 case OP_LOADU2_MEM:
4118                         /* For NaCl, pointers are 4 bytes, so separate these */
4119                         /* cases, use literal 8 below where we really want 8 */
4120                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4121                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4122                         break;
4123                 case OP_LOAD_MEMBASE:
4124                         g_assert (amd64_is_imm32 (ins->inst_offset));
4125                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4126                         break;
4127                 case OP_LOADI8_MEMBASE:
4128                         /* Use literal 8 instead of sizeof pointer or */
4129                         /* register, we really want 8 for this opcode */
4130                         g_assert (amd64_is_imm32 (ins->inst_offset));
4131                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4132                         break;
4133                 case OP_LOADI4_MEMBASE:
4134                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4135                         break;
4136                 case OP_LOADU4_MEMBASE:
4137                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4138                         break;
4139                 case OP_LOADU1_MEMBASE:
4140                         /* The cpu zero extends the result into 64 bits */
4141                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4142                         break;
4143                 case OP_LOADI1_MEMBASE:
4144                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4145                         break;
4146                 case OP_LOADU2_MEMBASE:
4147                         /* The cpu zero extends the result into 64 bits */
4148                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4149                         break;
4150                 case OP_LOADI2_MEMBASE:
4151                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4152                         break;
4153                 case OP_AMD64_LOADI8_MEMINDEX:
4154                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4155                         break;
4156                 case OP_LCONV_TO_I1:
4157                 case OP_ICONV_TO_I1:
4158                 case OP_SEXT_I1:
4159                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4160                         break;
4161                 case OP_LCONV_TO_I2:
4162                 case OP_ICONV_TO_I2:
4163                 case OP_SEXT_I2:
4164                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4165                         break;
4166                 case OP_LCONV_TO_U1:
4167                 case OP_ICONV_TO_U1:
4168                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4169                         break;
4170                 case OP_LCONV_TO_U2:
4171                 case OP_ICONV_TO_U2:
4172                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4173                         break;
4174                 case OP_ZEXT_I4:
4175                         /* Clean out the upper word */
4176                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4177                         break;
4178                 case OP_SEXT_I4:
4179                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4180                         break;
4181                 case OP_COMPARE:
4182                 case OP_LCOMPARE:
4183                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4184                         break;
4185                 case OP_COMPARE_IMM:
4186 #if defined(__mono_ilp32__)
4187                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4188                         g_assert (amd64_is_imm32 (ins->inst_imm));
4189                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4190                         break;
4191 #endif
4192                 case OP_LCOMPARE_IMM:
4193                         g_assert (amd64_is_imm32 (ins->inst_imm));
4194                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4195                         break;
4196                 case OP_X86_COMPARE_REG_MEMBASE:
4197                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4198                         break;
4199                 case OP_X86_TEST_NULL:
4200                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4201                         break;
4202                 case OP_AMD64_TEST_NULL:
4203                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4204                         break;
4205
4206                 case OP_X86_ADD_REG_MEMBASE:
4207                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4208                         break;
4209                 case OP_X86_SUB_REG_MEMBASE:
4210                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4211                         break;
4212                 case OP_X86_AND_REG_MEMBASE:
4213                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4214                         break;
4215                 case OP_X86_OR_REG_MEMBASE:
4216                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4217                         break;
4218                 case OP_X86_XOR_REG_MEMBASE:
4219                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4220                         break;
4221
4222                 case OP_X86_ADD_MEMBASE_IMM:
4223                         /* FIXME: Make a 64 version too */
4224                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4225                         break;
4226                 case OP_X86_SUB_MEMBASE_IMM:
4227                         g_assert (amd64_is_imm32 (ins->inst_imm));
4228                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4229                         break;
4230                 case OP_X86_AND_MEMBASE_IMM:
4231                         g_assert (amd64_is_imm32 (ins->inst_imm));
4232                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4233                         break;
4234                 case OP_X86_OR_MEMBASE_IMM:
4235                         g_assert (amd64_is_imm32 (ins->inst_imm));
4236                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4237                         break;
4238                 case OP_X86_XOR_MEMBASE_IMM:
4239                         g_assert (amd64_is_imm32 (ins->inst_imm));
4240                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4241                         break;
4242                 case OP_X86_ADD_MEMBASE_REG:
4243                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4244                         break;
4245                 case OP_X86_SUB_MEMBASE_REG:
4246                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4247                         break;
4248                 case OP_X86_AND_MEMBASE_REG:
4249                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4250                         break;
4251                 case OP_X86_OR_MEMBASE_REG:
4252                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4253                         break;
4254                 case OP_X86_XOR_MEMBASE_REG:
4255                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4256                         break;
4257                 case OP_X86_INC_MEMBASE:
4258                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4259                         break;
4260                 case OP_X86_INC_REG:
4261                         amd64_inc_reg_size (code, ins->dreg, 4);
4262                         break;
4263                 case OP_X86_DEC_MEMBASE:
4264                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4265                         break;
4266                 case OP_X86_DEC_REG:
4267                         amd64_dec_reg_size (code, ins->dreg, 4);
4268                         break;
4269                 case OP_X86_MUL_REG_MEMBASE:
4270                 case OP_X86_MUL_MEMBASE_REG:
4271                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4272                         break;
4273                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4274                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4275                         break;
4276                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4277                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4278                         break;
4279                 case OP_AMD64_COMPARE_MEMBASE_REG:
4280                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4281                         break;
4282                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4283                         g_assert (amd64_is_imm32 (ins->inst_imm));
4284                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4285                         break;
4286                 case OP_X86_COMPARE_MEMBASE8_IMM:
4287                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4288                         break;
4289                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4290                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4291                         break;
4292                 case OP_AMD64_COMPARE_REG_MEMBASE:
4293                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4294                         break;
4295
4296                 case OP_AMD64_ADD_REG_MEMBASE:
4297                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4298                         break;
4299                 case OP_AMD64_SUB_REG_MEMBASE:
4300                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4301                         break;
4302                 case OP_AMD64_AND_REG_MEMBASE:
4303                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4304                         break;
4305                 case OP_AMD64_OR_REG_MEMBASE:
4306                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4307                         break;
4308                 case OP_AMD64_XOR_REG_MEMBASE:
4309                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4310                         break;
4311
4312                 case OP_AMD64_ADD_MEMBASE_REG:
4313                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4314                         break;
4315                 case OP_AMD64_SUB_MEMBASE_REG:
4316                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4317                         break;
4318                 case OP_AMD64_AND_MEMBASE_REG:
4319                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4320                         break;
4321                 case OP_AMD64_OR_MEMBASE_REG:
4322                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4323                         break;
4324                 case OP_AMD64_XOR_MEMBASE_REG:
4325                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4326                         break;
4327
4328                 case OP_AMD64_ADD_MEMBASE_IMM:
4329                         g_assert (amd64_is_imm32 (ins->inst_imm));
4330                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4331                         break;
4332                 case OP_AMD64_SUB_MEMBASE_IMM:
4333                         g_assert (amd64_is_imm32 (ins->inst_imm));
4334                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4335                         break;
4336                 case OP_AMD64_AND_MEMBASE_IMM:
4337                         g_assert (amd64_is_imm32 (ins->inst_imm));
4338                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4339                         break;
4340                 case OP_AMD64_OR_MEMBASE_IMM:
4341                         g_assert (amd64_is_imm32 (ins->inst_imm));
4342                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4343                         break;
4344                 case OP_AMD64_XOR_MEMBASE_IMM:
4345                         g_assert (amd64_is_imm32 (ins->inst_imm));
4346                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4347                         break;
4348
4349                 case OP_BREAK:
4350                         amd64_breakpoint (code);
4351                         break;
4352                 case OP_RELAXED_NOP:
4353                         x86_prefix (code, X86_REP_PREFIX);
4354                         x86_nop (code);
4355                         break;
4356                 case OP_HARD_NOP:
4357                         x86_nop (code);
4358                         break;
4359                 case OP_NOP:
4360                 case OP_DUMMY_USE:
4361                 case OP_DUMMY_STORE:
4362                 case OP_DUMMY_ICONST:
4363                 case OP_DUMMY_R8CONST:
4364                 case OP_NOT_REACHED:
4365                 case OP_NOT_NULL:
4366                         break;
4367                 case OP_IL_SEQ_POINT:
4368                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4369                         break;
4370                 case OP_SEQ_POINT: {
4371                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4372                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4373                                 guint8 *label;
4374
4375                                 /* Load ss_tramp_var */
4376                                 /* This is equal to &ss_trampoline */
4377                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4378                                 /* Load the trampoline address */
4379                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4380                                 /* Call it if it is non-null */
4381                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4382                                 label = code;
4383                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4384                                 amd64_call_reg (code, AMD64_R11);
4385                                 amd64_patch (label, code);
4386                         }
4387
4388                         /*
4389                          * This is the address which is saved in seq points,
4390                          */
4391                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4392
4393                         if (cfg->compile_aot) {
4394                                 guint32 offset = code - cfg->native_code;
4395                                 guint32 val;
4396                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4397                                 guint8 *label;
4398
4399                                 /* Load info var */
4400                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4401                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4402                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4403                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4404                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4405                                 label = code;
4406                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4407                                 /* Call the trampoline */
4408                                 amd64_call_reg (code, AMD64_R11);
4409                                 amd64_patch (label, code);
4410                         } else {
4411                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4412                                 guint8 *label;
4413
4414                                 /*
4415                                  * Emit a test+branch against a constant, the constant will be overwritten
4416                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4417                                  */
4418                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4419                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4420                                 label = code;
4421                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4422
4423                                 g_assert (var);
4424                                 g_assert (var->opcode == OP_REGOFFSET);
4425                                 /* Load bp_tramp_var */
4426                                 /* This is equal to &bp_trampoline */
4427                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4428                                 /* Call the trampoline */
4429                                 amd64_call_membase (code, AMD64_R11, 0);
4430                                 amd64_patch (label, code);
4431                         }
4432                         /*
4433                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4434                          * to another IL offset.
4435                          */
4436                         x86_nop (code);
4437                         break;
4438                 }
4439                 case OP_ADDCC:
4440                 case OP_LADDCC:
4441                 case OP_LADD:
4442                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4443                         break;
4444                 case OP_ADC:
4445                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4446                         break;
4447                 case OP_ADD_IMM:
4448                 case OP_LADD_IMM:
4449                         g_assert (amd64_is_imm32 (ins->inst_imm));
4450                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4451                         break;
4452                 case OP_ADC_IMM:
4453                         g_assert (amd64_is_imm32 (ins->inst_imm));
4454                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4455                         break;
4456                 case OP_SUBCC:
4457                 case OP_LSUBCC:
4458                 case OP_LSUB:
4459                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4460                         break;
4461                 case OP_SBB:
4462                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4463                         break;
4464                 case OP_SUB_IMM:
4465                 case OP_LSUB_IMM:
4466                         g_assert (amd64_is_imm32 (ins->inst_imm));
4467                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4468                         break;
4469                 case OP_SBB_IMM:
4470                         g_assert (amd64_is_imm32 (ins->inst_imm));
4471                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4472                         break;
4473                 case OP_LAND:
4474                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4475                         break;
4476                 case OP_AND_IMM:
4477                 case OP_LAND_IMM:
4478                         g_assert (amd64_is_imm32 (ins->inst_imm));
4479                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4480                         break;
4481                 case OP_LMUL:
4482                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4483                         break;
4484                 case OP_MUL_IMM:
4485                 case OP_LMUL_IMM:
4486                 case OP_IMUL_IMM: {
4487                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4488
4489                         switch (ins->inst_imm) {
4490                         case 2:
4491                                 /* MOV r1, r2 */
4492                                 /* ADD r1, r1 */
4493                                 if (ins->dreg != ins->sreg1)
4494                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4495                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4496                                 break;
4497                         case 3:
4498                                 /* LEA r1, [r2 + r2*2] */
4499                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4500                                 break;
4501                         case 5:
4502                                 /* LEA r1, [r2 + r2*4] */
4503                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4504                                 break;
4505                         case 6:
4506                                 /* LEA r1, [r2 + r2*2] */
4507                                 /* ADD r1, r1          */
4508                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4509                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4510                                 break;
4511                         case 9:
4512                                 /* LEA r1, [r2 + r2*8] */
4513                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4514                                 break;
4515                         case 10:
4516                                 /* LEA r1, [r2 + r2*4] */
4517                                 /* ADD r1, r1          */
4518                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4519                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4520                                 break;
4521                         case 12:
4522                                 /* LEA r1, [r2 + r2*2] */
4523                                 /* SHL r1, 2           */
4524                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4525                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4526                                 break;
4527                         case 25:
4528                                 /* LEA r1, [r2 + r2*4] */
4529                                 /* LEA r1, [r1 + r1*4] */
4530                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4531                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4532                                 break;
4533                         case 100:
4534                                 /* LEA r1, [r2 + r2*4] */
4535                                 /* SHL r1, 2           */
4536                                 /* LEA r1, [r1 + r1*4] */
4537                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4538                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4539                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4540                                 break;
4541                         default:
4542                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4543                                 break;
4544                         }
4545                         break;
4546                 }
4547                 case OP_LDIV:
4548                 case OP_LREM:
4549 #if defined( __native_client_codegen__ )
4550                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4551                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4552 #endif
4553                         /* Regalloc magic makes the div/rem cases the same */
4554                         if (ins->sreg2 == AMD64_RDX) {
4555                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4556                                 amd64_cdq (code);
4557                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4558                         } else {
4559                                 amd64_cdq (code);
4560                                 amd64_div_reg (code, ins->sreg2, TRUE);
4561                         }
4562                         break;
4563                 case OP_LDIV_UN:
4564                 case OP_LREM_UN:
4565 #if defined( __native_client_codegen__ )
4566                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4567                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4568 #endif
4569                         if (ins->sreg2 == AMD64_RDX) {
4570                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4571                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4572                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4573                         } else {
4574                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4575                                 amd64_div_reg (code, ins->sreg2, FALSE);
4576                         }
4577                         break;
4578                 case OP_IDIV:
4579                 case OP_IREM:
4580 #if defined( __native_client_codegen__ )
4581                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4582                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4583 #endif
4584                         if (ins->sreg2 == AMD64_RDX) {
4585                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4586                                 amd64_cdq_size (code, 4);
4587                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4588                         } else {
4589                                 amd64_cdq_size (code, 4);
4590                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4591                         }
4592                         break;
4593                 case OP_IDIV_UN:
4594                 case OP_IREM_UN:
4595 #if defined( __native_client_codegen__ )
4596                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4597                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4598 #endif
4599                         if (ins->sreg2 == AMD64_RDX) {
4600                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4601                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4602                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4603                         } else {
4604                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4605                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4606                         }
4607                         break;
4608                 case OP_LMUL_OVF:
4609                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4610                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4611                         break;
4612                 case OP_LOR:
4613                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4614                         break;
4615                 case OP_OR_IMM:
4616                 case OP_LOR_IMM:
4617                         g_assert (amd64_is_imm32 (ins->inst_imm));
4618                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4619                         break;
4620                 case OP_LXOR:
4621                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4622                         break;
4623                 case OP_XOR_IMM:
4624                 case OP_LXOR_IMM:
4625                         g_assert (amd64_is_imm32 (ins->inst_imm));
4626                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4627                         break;
4628                 case OP_LSHL:
4629                         g_assert (ins->sreg2 == AMD64_RCX);
4630                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4631                         break;
4632                 case OP_LSHR:
4633                         g_assert (ins->sreg2 == AMD64_RCX);
4634                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4635                         break;
4636                 case OP_SHR_IMM:
4637                 case OP_LSHR_IMM:
4638                         g_assert (amd64_is_imm32 (ins->inst_imm));
4639                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4640                         break;
4641                 case OP_SHR_UN_IMM:
4642                         g_assert (amd64_is_imm32 (ins->inst_imm));
4643                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4644                         break;
4645                 case OP_LSHR_UN_IMM:
4646                         g_assert (amd64_is_imm32 (ins->inst_imm));
4647                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4648                         break;
4649                 case OP_LSHR_UN:
4650                         g_assert (ins->sreg2 == AMD64_RCX);
4651                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4652                         break;
4653                 case OP_SHL_IMM:
4654                 case OP_LSHL_IMM:
4655                         g_assert (amd64_is_imm32 (ins->inst_imm));
4656                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4657                         break;
4658
4659                 case OP_IADDCC:
4660                 case OP_IADD:
4661                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4662                         break;
4663                 case OP_IADC:
4664                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4665                         break;
4666                 case OP_IADD_IMM:
4667                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4668                         break;
4669                 case OP_IADC_IMM:
4670                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4671                         break;
4672                 case OP_ISUBCC:
4673                 case OP_ISUB:
4674                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4675                         break;
4676                 case OP_ISBB:
4677                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4678                         break;
4679                 case OP_ISUB_IMM:
4680                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4681                         break;
4682                 case OP_ISBB_IMM:
4683                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4684                         break;
4685                 case OP_IAND:
4686                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4687                         break;
4688                 case OP_IAND_IMM:
4689                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4690                         break;
4691                 case OP_IOR:
4692                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4693                         break;
4694                 case OP_IOR_IMM:
4695                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4696                         break;
4697                 case OP_IXOR:
4698                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4699                         break;
4700                 case OP_IXOR_IMM:
4701                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4702                         break;
4703                 case OP_INEG:
4704                         amd64_neg_reg_size (code, ins->sreg1, 4);
4705                         break;
4706                 case OP_INOT:
4707                         amd64_not_reg_size (code, ins->sreg1, 4);
4708                         break;
4709                 case OP_ISHL:
4710                         g_assert (ins->sreg2 == AMD64_RCX);
4711                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4712                         break;
4713                 case OP_ISHR:
4714                         g_assert (ins->sreg2 == AMD64_RCX);
4715                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4716                         break;
4717                 case OP_ISHR_IMM:
4718                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4719                         break;
4720                 case OP_ISHR_UN_IMM:
4721                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4722                         break;
4723                 case OP_ISHR_UN:
4724                         g_assert (ins->sreg2 == AMD64_RCX);
4725                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4726                         break;
4727                 case OP_ISHL_IMM:
4728                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4729                         break;
4730                 case OP_IMUL:
4731                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4732                         break;
4733                 case OP_IMUL_OVF:
4734                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4735                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4736                         break;
4737                 case OP_IMUL_OVF_UN:
4738                 case OP_LMUL_OVF_UN: {
4739                         /* the mul operation and the exception check should most likely be split */
4740                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4741                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4742                         /*g_assert (ins->sreg2 == X86_EAX);
4743                         g_assert (ins->dreg == X86_EAX);*/
4744                         if (ins->sreg2 == X86_EAX) {
4745                                 non_eax_reg = ins->sreg1;
4746                         } else if (ins->sreg1 == X86_EAX) {
4747                                 non_eax_reg = ins->sreg2;
4748                         } else {
4749                                 /* no need to save since we're going to store to it anyway */
4750                                 if (ins->dreg != X86_EAX) {
4751                                         saved_eax = TRUE;
4752                                         amd64_push_reg (code, X86_EAX);
4753                                 }
4754                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4755                                 non_eax_reg = ins->sreg2;
4756                         }
4757                         if (ins->dreg == X86_EDX) {
4758                                 if (!saved_eax) {
4759                                         saved_eax = TRUE;
4760                                         amd64_push_reg (code, X86_EAX);
4761                                 }
4762                         } else {
4763                                 saved_edx = TRUE;
4764                                 amd64_push_reg (code, X86_EDX);
4765                         }
4766                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4767                         /* save before the check since pop and mov don't change the flags */
4768                         if (ins->dreg != X86_EAX)
4769                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4770                         if (saved_edx)
4771                                 amd64_pop_reg (code, X86_EDX);
4772                         if (saved_eax)
4773                                 amd64_pop_reg (code, X86_EAX);
4774                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4775                         break;
4776                 }
4777                 case OP_ICOMPARE:
4778                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4779                         break;
4780                 case OP_ICOMPARE_IMM:
4781                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4782                         break;
4783                 case OP_IBEQ:
4784                 case OP_IBLT:
4785                 case OP_IBGT:
4786                 case OP_IBGE:
4787                 case OP_IBLE:
4788                 case OP_LBEQ:
4789                 case OP_LBLT:
4790                 case OP_LBGT:
4791                 case OP_LBGE:
4792                 case OP_LBLE:
4793                 case OP_IBNE_UN:
4794                 case OP_IBLT_UN:
4795                 case OP_IBGT_UN:
4796                 case OP_IBGE_UN:
4797                 case OP_IBLE_UN:
4798                 case OP_LBNE_UN:
4799                 case OP_LBLT_UN:
4800                 case OP_LBGT_UN:
4801                 case OP_LBGE_UN:
4802                 case OP_LBLE_UN:
4803                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4804                         break;
4805
4806                 case OP_CMOV_IEQ:
4807                 case OP_CMOV_IGE:
4808                 case OP_CMOV_IGT:
4809                 case OP_CMOV_ILE:
4810                 case OP_CMOV_ILT:
4811                 case OP_CMOV_INE_UN:
4812                 case OP_CMOV_IGE_UN:
4813                 case OP_CMOV_IGT_UN:
4814                 case OP_CMOV_ILE_UN:
4815                 case OP_CMOV_ILT_UN:
4816                 case OP_CMOV_LEQ:
4817                 case OP_CMOV_LGE:
4818                 case OP_CMOV_LGT:
4819                 case OP_CMOV_LLE:
4820                 case OP_CMOV_LLT:
4821                 case OP_CMOV_LNE_UN:
4822                 case OP_CMOV_LGE_UN:
4823                 case OP_CMOV_LGT_UN:
4824                 case OP_CMOV_LLE_UN:
4825                 case OP_CMOV_LLT_UN:
4826                         g_assert (ins->dreg == ins->sreg1);
4827                         /* This needs to operate on 64 bit values */
4828                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4829                         break;
4830
4831                 case OP_LNOT:
4832                         amd64_not_reg (code, ins->sreg1);
4833                         break;
4834                 case OP_LNEG:
4835                         amd64_neg_reg (code, ins->sreg1);
4836                         break;
4837
4838                 case OP_ICONST:
4839                 case OP_I8CONST:
4840                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4841                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4842                         else
4843                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4844                         break;
4845                 case OP_AOTCONST:
4846                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4847                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4848                         break;
4849                 case OP_JUMP_TABLE:
4850                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4851                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4852                         break;
4853                 case OP_MOVE:
4854                         if (ins->dreg != ins->sreg1)
4855                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4856                         break;
4857                 case OP_AMD64_SET_XMMREG_R4: {
4858                         if (cfg->r4fp) {
4859                                 if (ins->dreg != ins->sreg1)
4860                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4861                         } else {
4862                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4863                         }
4864                         break;
4865                 }
4866                 case OP_AMD64_SET_XMMREG_R8: {
4867                         if (ins->dreg != ins->sreg1)
4868                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4869                         break;
4870                 }
4871                 case OP_TAILCALL: {
4872                         MonoCallInst *call = (MonoCallInst*)ins;
4873                         int i, save_area_offset;
4874
4875                         g_assert (!cfg->method->save_lmf);
4876
4877                         /* Restore callee saved registers */
4878                         save_area_offset = cfg->arch.reg_save_area_offset;
4879                         for (i = 0; i < AMD64_NREG; ++i)
4880                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4881                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4882                                         save_area_offset += 8;
4883                                 }
4884
4885                         if (cfg->arch.omit_fp) {
4886                                 if (cfg->arch.stack_alloc_size)
4887                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4888                                 // FIXME:
4889                                 if (call->stack_usage)
4890                                         NOT_IMPLEMENTED;
4891                         } else {
4892                                 /* Copy arguments on the stack to our argument area */
4893                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4894                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4895                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4896                                 }
4897
4898                                 amd64_leave (code);
4899                         }
4900
4901                         offset = code - cfg->native_code;
4902                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4903                         if (cfg->compile_aot)
4904                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4905                         else
4906                                 amd64_set_reg_template (code, AMD64_R11);
4907                         amd64_jump_reg (code, AMD64_R11);
4908                         ins->flags |= MONO_INST_GC_CALLSITE;
4909                         ins->backend.pc_offset = code - cfg->native_code;
4910                         break;
4911                 }
4912                 case OP_CHECK_THIS:
4913                         /* ensure ins->sreg1 is not NULL */
4914                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4915                         break;
4916                 case OP_ARGLIST: {
4917                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4918                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4919                         break;
4920                 }
4921                 case OP_CALL:
4922                 case OP_FCALL:
4923                 case OP_RCALL:
4924                 case OP_LCALL:
4925                 case OP_VCALL:
4926                 case OP_VCALL2:
4927                 case OP_VOIDCALL:
4928                         call = (MonoCallInst*)ins;
4929                         /*
4930                          * The AMD64 ABI forces callers to know about varargs.
4931                          */
4932                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4933                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4934                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4935                                 /*
4936                                  * Since the unmanaged calling convention doesn't contain a
4937                                  * 'vararg' entry, we have to treat every pinvoke call as a
4938                                  * potential vararg call.
4939                                  */
4940                                 guint32 nregs, i;
4941                                 nregs = 0;
4942                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4943                                         if (call->used_fregs & (1 << i))
4944                                                 nregs ++;
4945                                 if (!nregs)
4946                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4947                                 else
4948                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4949                         }
4950
4951                         if (ins->flags & MONO_INST_HAS_METHOD)
4952                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4953                         else
4954                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4955                         ins->flags |= MONO_INST_GC_CALLSITE;
4956                         ins->backend.pc_offset = code - cfg->native_code;
4957                         code = emit_move_return_value (cfg, ins, code);
4958                         break;
4959                 case OP_FCALL_REG:
4960                 case OP_RCALL_REG:
4961                 case OP_LCALL_REG:
4962                 case OP_VCALL_REG:
4963                 case OP_VCALL2_REG:
4964                 case OP_VOIDCALL_REG:
4965                 case OP_CALL_REG:
4966                         call = (MonoCallInst*)ins;
4967
4968                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4969                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4970                                 ins->sreg1 = AMD64_R11;
4971                         }
4972
4973                         /*
4974                          * The AMD64 ABI forces callers to know about varargs.
4975                          */
4976                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4977                                 if (ins->sreg1 == AMD64_RAX) {
4978                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4979                                         ins->sreg1 = AMD64_R11;
4980                                 }
4981                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4982                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4983                                 /*
4984                                  * Since the unmanaged calling convention doesn't contain a
4985                                  * 'vararg' entry, we have to treat every pinvoke call as a
4986                                  * potential vararg call.
4987                                  */
4988                                 guint32 nregs, i;
4989                                 nregs = 0;
4990                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4991                                         if (call->used_fregs & (1 << i))
4992                                                 nregs ++;
4993                                 if (ins->sreg1 == AMD64_RAX) {
4994                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4995                                         ins->sreg1 = AMD64_R11;
4996                                 }
4997                                 if (!nregs)
4998                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4999                                 else
5000                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
5001                         }
5002
5003                         amd64_call_reg (code, ins->sreg1);
5004                         ins->flags |= MONO_INST_GC_CALLSITE;
5005                         ins->backend.pc_offset = code - cfg->native_code;
5006                         code = emit_move_return_value (cfg, ins, code);
5007                         break;
5008                 case OP_FCALL_MEMBASE:
5009                 case OP_RCALL_MEMBASE:
5010                 case OP_LCALL_MEMBASE:
5011                 case OP_VCALL_MEMBASE:
5012                 case OP_VCALL2_MEMBASE:
5013                 case OP_VOIDCALL_MEMBASE:
5014                 case OP_CALL_MEMBASE:
5015                         call = (MonoCallInst*)ins;
5016
5017                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
5018                         ins->flags |= MONO_INST_GC_CALLSITE;
5019                         ins->backend.pc_offset = code - cfg->native_code;
5020                         code = emit_move_return_value (cfg, ins, code);
5021                         break;
5022                 case OP_DYN_CALL: {
5023                         int i;
5024                         MonoInst *var = cfg->dyn_call_var;
5025                         guint8 *label;
5026
5027                         g_assert (var->opcode == OP_REGOFFSET);
5028
5029                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
5030                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
5031                         /* r10 = ftn */
5032                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
5033
5034                         /* Save args buffer */
5035                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
5036
5037                         /* Set fp arg regs */
5038                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
5039                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5040                         label = code;
5041                         amd64_branch8 (code, X86_CC_Z, -1, 1);
5042                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
5043                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
5044                         amd64_patch (label, code);
5045
5046                         /* Set argument registers */
5047                         for (i = 0; i < PARAM_REGS; ++i)
5048                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
5049
5050                         /* Make the call */
5051                         amd64_call_reg (code, AMD64_R10);
5052
5053                         ins->flags |= MONO_INST_GC_CALLSITE;
5054                         ins->backend.pc_offset = code - cfg->native_code;
5055
5056                         /* Save result */
5057                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5058                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5059                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
5060                         break;
5061                 }
5062                 case OP_AMD64_SAVE_SP_TO_LMF: {
5063                         MonoInst *lmf_var = cfg->lmf_var;
5064                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5065                         break;
5066                 }
5067                 case OP_X86_PUSH:
5068                         g_assert_not_reached ();
5069                         amd64_push_reg (code, ins->sreg1);
5070                         break;
5071                 case OP_X86_PUSH_IMM:
5072                         g_assert_not_reached ();
5073                         g_assert (amd64_is_imm32 (ins->inst_imm));
5074                         amd64_push_imm (code, ins->inst_imm);
5075                         break;
5076                 case OP_X86_PUSH_MEMBASE:
5077                         g_assert_not_reached ();
5078                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5079                         break;
5080                 case OP_X86_PUSH_OBJ: {
5081                         int size = ALIGN_TO (ins->inst_imm, 8);
5082
5083                         g_assert_not_reached ();
5084
5085                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5086                         amd64_push_reg (code, AMD64_RDI);
5087                         amd64_push_reg (code, AMD64_RSI);
5088                         amd64_push_reg (code, AMD64_RCX);
5089                         if (ins->inst_offset)
5090                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5091                         else
5092                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5093                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5094                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5095                         amd64_cld (code);
5096                         amd64_prefix (code, X86_REP_PREFIX);
5097                         amd64_movsd (code);
5098                         amd64_pop_reg (code, AMD64_RCX);
5099                         amd64_pop_reg (code, AMD64_RSI);
5100                         amd64_pop_reg (code, AMD64_RDI);
5101                         break;
5102                 }
5103                 case OP_GENERIC_CLASS_INIT: {
5104                         static int byte_offset = -1;
5105                         static guint8 bitmask;
5106                         guint8 *jump;
5107
5108                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5109
5110                         if (byte_offset < 0)
5111                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5112
5113                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5114                         jump = code;
5115                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5116
5117                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5118                         ins->flags |= MONO_INST_GC_CALLSITE;
5119                         ins->backend.pc_offset = code - cfg->native_code;
5120
5121                         x86_patch (jump, code);
5122                         break;
5123                 }
5124
5125                 case OP_X86_LEA:
5126                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5127                         break;
5128                 case OP_X86_LEA_MEMBASE:
5129                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5130                         break;
5131                 case OP_X86_XCHG:
5132                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5133                         break;
5134                 case OP_LOCALLOC:
5135                         /* keep alignment */
5136                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5137                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5138                         code = mono_emit_stack_alloc (cfg, code, ins);
5139                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5140                         if (cfg->param_area)
5141                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5142                         break;
5143                 case OP_LOCALLOC_IMM: {
5144                         guint32 size = ins->inst_imm;
5145                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5146
5147                         if (ins->flags & MONO_INST_INIT) {
5148                                 if (size < 64) {
5149                                         int i;
5150
5151                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5152                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5153
5154                                         for (i = 0; i < size; i += 8)
5155                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5156                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5157                                 } else {
5158                                         amd64_mov_reg_imm (code, ins->dreg, size);
5159                                         ins->sreg1 = ins->dreg;
5160
5161                                         code = mono_emit_stack_alloc (cfg, code, ins);
5162                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5163                                 }
5164                         } else {
5165                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5166                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5167                         }
5168                         if (cfg->param_area)
5169                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5170                         break;
5171                 }
5172                 case OP_THROW: {
5173                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5174                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5175                                              (gpointer)"mono_arch_throw_exception", FALSE);
5176                         ins->flags |= MONO_INST_GC_CALLSITE;
5177                         ins->backend.pc_offset = code - cfg->native_code;
5178                         break;
5179                 }
5180                 case OP_RETHROW: {
5181                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5182                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5183                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5184                         ins->flags |= MONO_INST_GC_CALLSITE;
5185                         ins->backend.pc_offset = code - cfg->native_code;
5186                         break;
5187                 }
5188                 case OP_CALL_HANDLER:
5189                         /* Align stack */
5190                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5191                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5192                         amd64_call_imm (code, 0);
5193                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5194                         /* Restore stack alignment */
5195                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5196                         break;
5197                 case OP_START_HANDLER: {
5198                         /* Even though we're saving RSP, use sizeof */
5199                         /* gpointer because spvar is of type IntPtr */
5200                         /* see: mono_create_spvar_for_region */
5201                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5202                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5203
5204                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5205                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5206                                 cfg->param_area) {
5207                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5208                         }
5209                         break;
5210                 }
5211                 case OP_ENDFINALLY: {
5212                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5213                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5214                         amd64_ret (code);
5215                         break;
5216                 }
5217                 case OP_ENDFILTER: {
5218                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5219                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5220                         /* The local allocator will put the result into RAX */
5221                         amd64_ret (code);
5222                         break;
5223                 }
5224                 case OP_GET_EX_OBJ:
5225                         if (ins->dreg != AMD64_RAX)
5226                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5227                         break;
5228                 case OP_LABEL:
5229                         ins->inst_c0 = code - cfg->native_code;
5230                         break;
5231                 case OP_BR:
5232                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5233                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5234                         //break;
5235                                 if (ins->inst_target_bb->native_offset) {
5236                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5237                                 } else {
5238                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5239                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5240                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5241                                                 x86_jump8 (code, 0);
5242                                         else
5243                                                 x86_jump32 (code, 0);
5244                         }
5245                         break;
5246                 case OP_BR_REG:
5247                         amd64_jump_reg (code, ins->sreg1);
5248                         break;
5249                 case OP_ICNEQ:
5250                 case OP_ICGE:
5251                 case OP_ICLE:
5252                 case OP_ICGE_UN:
5253                 case OP_ICLE_UN:
5254
5255                 case OP_CEQ:
5256                 case OP_LCEQ:
5257                 case OP_ICEQ:
5258                 case OP_CLT:
5259                 case OP_LCLT:
5260                 case OP_ICLT:
5261                 case OP_CGT:
5262                 case OP_ICGT:
5263                 case OP_LCGT:
5264                 case OP_CLT_UN:
5265                 case OP_LCLT_UN:
5266                 case OP_ICLT_UN:
5267                 case OP_CGT_UN:
5268                 case OP_LCGT_UN:
5269                 case OP_ICGT_UN:
5270                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5271                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5272                         break;
5273                 case OP_COND_EXC_EQ:
5274                 case OP_COND_EXC_NE_UN:
5275                 case OP_COND_EXC_LT:
5276                 case OP_COND_EXC_LT_UN:
5277                 case OP_COND_EXC_GT:
5278                 case OP_COND_EXC_GT_UN:
5279                 case OP_COND_EXC_GE:
5280                 case OP_COND_EXC_GE_UN:
5281                 case OP_COND_EXC_LE:
5282                 case OP_COND_EXC_LE_UN:
5283                 case OP_COND_EXC_IEQ:
5284                 case OP_COND_EXC_INE_UN:
5285                 case OP_COND_EXC_ILT:
5286                 case OP_COND_EXC_ILT_UN:
5287                 case OP_COND_EXC_IGT:
5288                 case OP_COND_EXC_IGT_UN:
5289                 case OP_COND_EXC_IGE:
5290                 case OP_COND_EXC_IGE_UN:
5291                 case OP_COND_EXC_ILE:
5292                 case OP_COND_EXC_ILE_UN:
5293                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5294                         break;
5295                 case OP_COND_EXC_OV:
5296                 case OP_COND_EXC_NO:
5297                 case OP_COND_EXC_C:
5298                 case OP_COND_EXC_NC:
5299                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5300                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5301                         break;
5302                 case OP_COND_EXC_IOV:
5303                 case OP_COND_EXC_INO:
5304                 case OP_COND_EXC_IC:
5305                 case OP_COND_EXC_INC:
5306                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5307                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5308                         break;
5309
5310                 /* floating point opcodes */
5311                 case OP_R8CONST: {
5312                         double d = *(double *)ins->inst_p0;
5313
5314                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5315                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5316                         }
5317                         else {
5318                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5319                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5320                         }
5321                         break;
5322                 }
5323                 case OP_R4CONST: {
5324                         float f = *(float *)ins->inst_p0;
5325
5326                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5327                                 if (cfg->r4fp)
5328                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5329                                 else
5330                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5331                         }
5332                         else {
5333                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5334                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5335                                 if (!cfg->r4fp)
5336                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5337                         }
5338                         break;
5339                 }
5340                 case OP_STORER8_MEMBASE_REG:
5341                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5342                         break;
5343                 case OP_LOADR8_MEMBASE:
5344                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5345                         break;
5346                 case OP_STORER4_MEMBASE_REG:
5347                         if (cfg->r4fp) {
5348                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5349                         } else {
5350                                 /* This requires a double->single conversion */
5351                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5352                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5353                         }
5354                         break;
5355                 case OP_LOADR4_MEMBASE:
5356                         if (cfg->r4fp) {
5357                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5358                         } else {
5359                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5360                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5361                         }
5362                         break;
5363                 case OP_ICONV_TO_R4:
5364                         if (cfg->r4fp) {
5365                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5366                         } else {
5367                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5368                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5369                         }
5370                         break;
5371                 case OP_ICONV_TO_R8:
5372                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5373                         break;
5374                 case OP_LCONV_TO_R4:
5375                         if (cfg->r4fp) {
5376                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5377                         } else {
5378                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5379                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5380                         }
5381                         break;
5382                 case OP_LCONV_TO_R8:
5383                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5384                         break;
5385                 case OP_FCONV_TO_R4:
5386                         if (cfg->r4fp) {
5387                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5388                         } else {
5389                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5390                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5391                         }
5392                         break;
5393                 case OP_FCONV_TO_I1:
5394                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5395                         break;
5396                 case OP_FCONV_TO_U1:
5397                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5398                         break;
5399                 case OP_FCONV_TO_I2:
5400                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5401                         break;
5402                 case OP_FCONV_TO_U2:
5403                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5404                         break;
5405                 case OP_FCONV_TO_U4:
5406                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5407                         break;
5408                 case OP_FCONV_TO_I4:
5409                 case OP_FCONV_TO_I:
5410                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5411                         break;
5412                 case OP_FCONV_TO_I8:
5413                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5414                         break;
5415
5416                 case OP_RCONV_TO_I1:
5417                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5418                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5419                         break;
5420                 case OP_RCONV_TO_U1:
5421                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5422                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5423                         break;
5424                 case OP_RCONV_TO_I2:
5425                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5426                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5427                         break;
5428                 case OP_RCONV_TO_U2:
5429                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5430                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5431                         break;
5432                 case OP_RCONV_TO_I4:
5433                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5434                         break;
5435                 case OP_RCONV_TO_U4:
5436                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5437                         break;
5438                 case OP_RCONV_TO_I8:
5439                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5440                         break;
5441                 case OP_RCONV_TO_R8:
5442                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5443                         break;
5444                 case OP_RCONV_TO_R4:
5445                         if (ins->dreg != ins->sreg1)
5446                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5447                         break;
5448
5449                 case OP_LCONV_TO_R_UN: {
5450                         guint8 *br [2];
5451
5452                         /* Based on gcc code */
5453                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5454                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5455
5456                         /* Positive case */
5457                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5458                         br [1] = code; x86_jump8 (code, 0);
5459                         amd64_patch (br [0], code);
5460
5461                         /* Negative case */
5462                         /* Save to the red zone */
5463                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5464                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5465                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5466                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5467                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5468                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5469                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5470                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5471                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5472                         /* Restore */
5473                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5474                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5475                         amd64_patch (br [1], code);
5476                         break;
5477                 }
5478                 case OP_LCONV_TO_OVF_U4:
5479                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5480                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5481                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5482                         break;
5483                 case OP_LCONV_TO_OVF_I4_UN:
5484                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5485                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5486                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5487                         break;
5488                 case OP_FMOVE:
5489                         if (ins->dreg != ins->sreg1)
5490                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5491                         break;
5492                 case OP_RMOVE:
5493                         if (ins->dreg != ins->sreg1)
5494                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5495                         break;
5496                 case OP_MOVE_F_TO_I4:
5497                         if (cfg->r4fp) {
5498                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5499                         } else {
5500                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5501                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5502                         }
5503                         break;
5504                 case OP_MOVE_I4_TO_F:
5505                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5506                         if (!cfg->r4fp)
5507                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5508                         break;
5509                 case OP_MOVE_F_TO_I8:
5510                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5511                         break;
5512                 case OP_MOVE_I8_TO_F:
5513                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5514                         break;
5515                 case OP_FADD:
5516                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5517                         break;
5518                 case OP_FSUB:
5519                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5520                         break;
5521                 case OP_FMUL:
5522                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5523                         break;
5524                 case OP_FDIV:
5525                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5526                         break;
5527                 case OP_FNEG: {
5528                         static double r8_0 = -0.0;
5529
5530                         g_assert (ins->sreg1 == ins->dreg);
5531
5532                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5533                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5534                         break;
5535                 }
5536                 case OP_SIN:
5537                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5538                         break;
5539                 case OP_COS:
5540                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5541                         break;
5542                 case OP_ABS: {
5543                         static guint64 d = 0x7fffffffffffffffUL;
5544
5545                         g_assert (ins->sreg1 == ins->dreg);
5546
5547                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5548                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5549                         break;
5550                 }
5551                 case OP_SQRT:
5552                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5553                         break;
5554
5555                 case OP_RADD:
5556                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5557                         break;
5558                 case OP_RSUB:
5559                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5560                         break;
5561                 case OP_RMUL:
5562                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5563                         break;
5564                 case OP_RDIV:
5565                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5566                         break;
5567                 case OP_RNEG: {
5568                         static float r4_0 = -0.0;
5569
5570                         g_assert (ins->sreg1 == ins->dreg);
5571
5572                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5573                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5574                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5575                         break;
5576                 }
5577
5578                 case OP_IMIN:
5579                         g_assert (cfg->opt & MONO_OPT_CMOV);
5580                         g_assert (ins->dreg == ins->sreg1);
5581                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5582                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5583                         break;
5584                 case OP_IMIN_UN:
5585                         g_assert (cfg->opt & MONO_OPT_CMOV);
5586                         g_assert (ins->dreg == ins->sreg1);
5587                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5588                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5589                         break;
5590                 case OP_IMAX:
5591                         g_assert (cfg->opt & MONO_OPT_CMOV);
5592                         g_assert (ins->dreg == ins->sreg1);
5593                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5594                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5595                         break;
5596                 case OP_IMAX_UN:
5597                         g_assert (cfg->opt & MONO_OPT_CMOV);
5598                         g_assert (ins->dreg == ins->sreg1);
5599                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5600                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5601                         break;
5602                 case OP_LMIN:
5603                         g_assert (cfg->opt & MONO_OPT_CMOV);
5604                         g_assert (ins->dreg == ins->sreg1);
5605                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5606                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5607                         break;
5608                 case OP_LMIN_UN:
5609                         g_assert (cfg->opt & MONO_OPT_CMOV);
5610                         g_assert (ins->dreg == ins->sreg1);
5611                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5612                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5613                         break;
5614                 case OP_LMAX:
5615                         g_assert (cfg->opt & MONO_OPT_CMOV);
5616                         g_assert (ins->dreg == ins->sreg1);
5617                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5618                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5619                         break;
5620                 case OP_LMAX_UN:
5621                         g_assert (cfg->opt & MONO_OPT_CMOV);
5622                         g_assert (ins->dreg == ins->sreg1);
5623                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5624                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5625                         break;
5626                 case OP_X86_FPOP:
5627                         break;
5628                 case OP_FCOMPARE:
5629                         /*
5630                          * The two arguments are swapped because the fbranch instructions
5631                          * depend on this for the non-sse case to work.
5632                          */
5633                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5634                         break;
5635                 case OP_RCOMPARE:
5636                         /*
5637                          * FIXME: Get rid of this.
5638                          * The two arguments are swapped because the fbranch instructions
5639                          * depend on this for the non-sse case to work.
5640                          */
5641                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5642                         break;
5643                 case OP_FCNEQ:
5644                 case OP_FCEQ: {
5645                         /* zeroing the register at the start results in
5646                          * shorter and faster code (we can also remove the widening op)
5647                          */
5648                         guchar *unordered_check;
5649
5650                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5651                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5652                         unordered_check = code;
5653                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5654
5655                         if (ins->opcode == OP_FCEQ) {
5656                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5657                                 amd64_patch (unordered_check, code);
5658                         } else {
5659                                 guchar *jump_to_end;
5660                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5661                                 jump_to_end = code;
5662                                 x86_jump8 (code, 0);
5663                                 amd64_patch (unordered_check, code);
5664                                 amd64_inc_reg (code, ins->dreg);
5665                                 amd64_patch (jump_to_end, code);
5666                         }
5667                         break;
5668                 }
5669                 case OP_FCLT:
5670                 case OP_FCLT_UN: {
5671                         /* zeroing the register at the start results in
5672                          * shorter and faster code (we can also remove the widening op)
5673                          */
5674                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5675                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5676                         if (ins->opcode == OP_FCLT_UN) {
5677                                 guchar *unordered_check = code;
5678                                 guchar *jump_to_end;
5679                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5680                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5681                                 jump_to_end = code;
5682                                 x86_jump8 (code, 0);
5683                                 amd64_patch (unordered_check, code);
5684                                 amd64_inc_reg (code, ins->dreg);
5685                                 amd64_patch (jump_to_end, code);
5686                         } else {
5687                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5688                         }
5689                         break;
5690                 }
5691                 case OP_FCLE: {
5692                         guchar *unordered_check;
5693                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5694                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5695                         unordered_check = code;
5696                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5697                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5698                         amd64_patch (unordered_check, code);
5699                         break;
5700                 }
5701                 case OP_FCGT:
5702                 case OP_FCGT_UN: {
5703                         /* zeroing the register at the start results in
5704                          * shorter and faster code (we can also remove the widening op)
5705                          */
5706                         guchar *unordered_check;
5707
5708                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5709                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5710                         if (ins->opcode == OP_FCGT) {
5711                                 unordered_check = code;
5712                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5713                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5714                                 amd64_patch (unordered_check, code);
5715                         } else {
5716                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5717                         }
5718                         break;
5719                 }
5720                 case OP_FCGE: {
5721                         guchar *unordered_check;
5722                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5723                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5724                         unordered_check = code;
5725                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5726                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5727                         amd64_patch (unordered_check, code);
5728                         break;
5729                 }
5730
5731                 case OP_RCEQ:
5732                 case OP_RCGT:
5733                 case OP_RCLT:
5734                 case OP_RCLT_UN:
5735                 case OP_RCGT_UN: {
5736                         int x86_cond;
5737                         gboolean unordered = FALSE;
5738
5739                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5740                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5741
5742                         switch (ins->opcode) {
5743                         case OP_RCEQ:
5744                                 x86_cond = X86_CC_EQ;
5745                                 break;
5746                         case OP_RCGT:
5747                                 x86_cond = X86_CC_LT;
5748                                 break;
5749                         case OP_RCLT:
5750                                 x86_cond = X86_CC_GT;
5751                                 break;
5752                         case OP_RCLT_UN:
5753                                 x86_cond = X86_CC_GT;
5754                                 unordered = TRUE;
5755                                 break;
5756                         case OP_RCGT_UN:
5757                                 x86_cond = X86_CC_LT;
5758                                 unordered = TRUE;
5759                                 break;
5760                         default:
5761                                 g_assert_not_reached ();
5762                                 break;
5763                         }
5764
5765                         if (unordered) {
5766                                 guchar *unordered_check;
5767                                 guchar *jump_to_end;
5768
5769                                 unordered_check = code;
5770                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5771                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5772                                 jump_to_end = code;
5773                                 x86_jump8 (code, 0);
5774                                 amd64_patch (unordered_check, code);
5775                                 amd64_inc_reg (code, ins->dreg);
5776                                 amd64_patch (jump_to_end, code);
5777                         } else {
5778                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5779                         }
5780                         break;
5781                 }
5782                 case OP_FCLT_MEMBASE:
5783                 case OP_FCGT_MEMBASE:
5784                 case OP_FCLT_UN_MEMBASE:
5785                 case OP_FCGT_UN_MEMBASE:
5786                 case OP_FCEQ_MEMBASE: {
5787                         guchar *unordered_check, *jump_to_end;
5788                         int x86_cond;
5789
5790                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5791                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5792
5793                         switch (ins->opcode) {
5794                         case OP_FCEQ_MEMBASE:
5795                                 x86_cond = X86_CC_EQ;
5796                                 break;
5797                         case OP_FCLT_MEMBASE:
5798                         case OP_FCLT_UN_MEMBASE:
5799                                 x86_cond = X86_CC_LT;
5800                                 break;
5801                         case OP_FCGT_MEMBASE:
5802                         case OP_FCGT_UN_MEMBASE:
5803                                 x86_cond = X86_CC_GT;
5804                                 break;
5805                         default:
5806                                 g_assert_not_reached ();
5807                         }
5808
5809                         unordered_check = code;
5810                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5811                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5812
5813                         switch (ins->opcode) {
5814                         case OP_FCEQ_MEMBASE:
5815                         case OP_FCLT_MEMBASE:
5816                         case OP_FCGT_MEMBASE:
5817                                 amd64_patch (unordered_check, code);
5818                                 break;
5819                         case OP_FCLT_UN_MEMBASE:
5820                         case OP_FCGT_UN_MEMBASE:
5821                                 jump_to_end = code;
5822                                 x86_jump8 (code, 0);
5823                                 amd64_patch (unordered_check, code);
5824                                 amd64_inc_reg (code, ins->dreg);
5825                                 amd64_patch (jump_to_end, code);
5826                                 break;
5827                         default:
5828                                 break;
5829                         }
5830                         break;
5831                 }
5832                 case OP_FBEQ: {
5833                         guchar *jump = code;
5834                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5835                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5836                         amd64_patch (jump, code);
5837                         break;
5838                 }
5839                 case OP_FBNE_UN:
5840                         /* Branch if C013 != 100 */
5841                         /* branch if !ZF or (PF|CF) */
5842                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5843                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5844                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5845                         break;
5846                 case OP_FBLT:
5847                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5848                         break;
5849                 case OP_FBLT_UN:
5850                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5851                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5852                         break;
5853                 case OP_FBGT:
5854                 case OP_FBGT_UN:
5855                         if (ins->opcode == OP_FBGT) {
5856                                 guchar *br1;
5857
5858                                 /* skip branch if C1=1 */
5859                                 br1 = code;
5860                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5861                                 /* branch if (C0 | C3) = 1 */
5862                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5863                                 amd64_patch (br1, code);
5864                                 break;
5865                         } else {
5866                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5867                         }
5868                         break;
5869                 case OP_FBGE: {
5870                         /* Branch if C013 == 100 or 001 */
5871                         guchar *br1;
5872
5873                         /* skip branch if C1=1 */
5874                         br1 = code;
5875                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5876                         /* branch if (C0 | C3) = 1 */
5877                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5878                         amd64_patch (br1, code);
5879                         break;
5880                 }
5881                 case OP_FBGE_UN:
5882                         /* Branch if C013 == 000 */
5883                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5884                         break;
5885                 case OP_FBLE: {
5886                         /* Branch if C013=000 or 100 */
5887                         guchar *br1;
5888
5889                         /* skip branch if C1=1 */
5890                         br1 = code;
5891                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5892                         /* branch if C0=0 */
5893                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5894                         amd64_patch (br1, code);
5895                         break;
5896                 }
5897                 case OP_FBLE_UN:
5898                         /* Branch if C013 != 001 */
5899                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5900                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5901                         break;
5902                 case OP_CKFINITE:
5903                         /* Transfer value to the fp stack */
5904                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5905                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5906                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5907
5908                         amd64_push_reg (code, AMD64_RAX);
5909                         amd64_fxam (code);
5910                         amd64_fnstsw (code);
5911                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5912                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5913                         amd64_pop_reg (code, AMD64_RAX);
5914                         amd64_fstp (code, 0);
5915                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5916                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5917                         break;
5918                 case OP_TLS_GET: {
5919                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5920                         break;
5921                 }
5922                 case OP_TLS_GET_REG:
5923                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5924                         break;
5925                 case OP_TLS_SET: {
5926                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5927                         break;
5928                 }
5929                 case OP_TLS_SET_REG: {
5930                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 }
5933                 case OP_MEMORY_BARRIER: {
5934                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5935                                 x86_mfence (code);
5936                         break;
5937                 }
5938                 case OP_ATOMIC_ADD_I4:
5939                 case OP_ATOMIC_ADD_I8: {
5940                         int dreg = ins->dreg;
5941                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5942
5943                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5944                                 dreg = AMD64_R11;
5945
5946                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5947                         amd64_prefix (code, X86_LOCK_PREFIX);
5948                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5949                         /* dreg contains the old value, add with sreg2 value */
5950                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5951
5952                         if (ins->dreg != dreg)
5953                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5954
5955                         break;
5956                 }
5957                 case OP_ATOMIC_EXCHANGE_I4:
5958                 case OP_ATOMIC_EXCHANGE_I8: {
5959                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5960
5961                         /* LOCK prefix is implied. */
5962                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5963                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5964                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5965                         break;
5966                 }
5967                 case OP_ATOMIC_CAS_I4:
5968                 case OP_ATOMIC_CAS_I8: {
5969                         guint32 size;
5970
5971                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5972                                 size = 8;
5973                         else
5974                                 size = 4;
5975
5976                         /*
5977                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5978                          * an explanation of how this works.
5979                          */
5980                         g_assert (ins->sreg3 == AMD64_RAX);
5981                         g_assert (ins->sreg1 != AMD64_RAX);
5982                         g_assert (ins->sreg1 != ins->sreg2);
5983
5984                         amd64_prefix (code, X86_LOCK_PREFIX);
5985                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5986
5987                         if (ins->dreg != AMD64_RAX)
5988                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5989                         break;
5990                 }
5991                 case OP_ATOMIC_LOAD_I1: {
5992                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5993                         break;
5994                 }
5995                 case OP_ATOMIC_LOAD_U1: {
5996                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5997                         break;
5998                 }
5999                 case OP_ATOMIC_LOAD_I2: {
6000                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
6001                         break;
6002                 }
6003                 case OP_ATOMIC_LOAD_U2: {
6004                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
6005                         break;
6006                 }
6007                 case OP_ATOMIC_LOAD_I4: {
6008                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6009                         break;
6010                 }
6011                 case OP_ATOMIC_LOAD_U4:
6012                 case OP_ATOMIC_LOAD_I8:
6013                 case OP_ATOMIC_LOAD_U8: {
6014                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
6015                         break;
6016                 }
6017                 case OP_ATOMIC_LOAD_R4: {
6018                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6019                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6020                         break;
6021                 }
6022                 case OP_ATOMIC_LOAD_R8: {
6023                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6024                         break;
6025                 }
6026                 case OP_ATOMIC_STORE_I1:
6027                 case OP_ATOMIC_STORE_U1:
6028                 case OP_ATOMIC_STORE_I2:
6029                 case OP_ATOMIC_STORE_U2:
6030                 case OP_ATOMIC_STORE_I4:
6031                 case OP_ATOMIC_STORE_U4:
6032                 case OP_ATOMIC_STORE_I8:
6033                 case OP_ATOMIC_STORE_U8: {
6034                         int size;
6035
6036                         switch (ins->opcode) {
6037                         case OP_ATOMIC_STORE_I1:
6038                         case OP_ATOMIC_STORE_U1:
6039                                 size = 1;
6040                                 break;
6041                         case OP_ATOMIC_STORE_I2:
6042                         case OP_ATOMIC_STORE_U2:
6043                                 size = 2;
6044                                 break;
6045                         case OP_ATOMIC_STORE_I4:
6046                         case OP_ATOMIC_STORE_U4:
6047                                 size = 4;
6048                                 break;
6049                         case OP_ATOMIC_STORE_I8:
6050                         case OP_ATOMIC_STORE_U8:
6051                                 size = 8;
6052                                 break;
6053                         }
6054
6055                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6056
6057                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6058                                 x86_mfence (code);
6059                         break;
6060                 }
6061                 case OP_ATOMIC_STORE_R4: {
6062                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6063                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6064
6065                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6066                                 x86_mfence (code);
6067                         break;
6068                 }
6069                 case OP_ATOMIC_STORE_R8: {
6070                         x86_nop (code);
6071                         x86_nop (code);
6072                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6073                         x86_nop (code);
6074                         x86_nop (code);
6075
6076                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6077                                 x86_mfence (code);
6078                         break;
6079                 }
6080                 case OP_CARD_TABLE_WBARRIER: {
6081                         int ptr = ins->sreg1;
6082                         int value = ins->sreg2;
6083                         guchar *br = 0;
6084                         int nursery_shift, card_table_shift;
6085                         gpointer card_table_mask;
6086                         size_t nursery_size;
6087
6088                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6089                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6090                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6091
6092                         /*If either point to the stack we can simply avoid the WB. This happens due to
6093                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6094                          */
6095                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6096                                 continue;
6097
6098                         /*
6099                          * We need one register we can clobber, we choose EDX and make sreg1
6100                          * fixed EAX to work around limitations in the local register allocator.
6101                          * sreg2 might get allocated to EDX, but that is not a problem since
6102                          * we use it before clobbering EDX.
6103                          */
6104                         g_assert (ins->sreg1 == AMD64_RAX);
6105
6106                         /*
6107                          * This is the code we produce:
6108                          *
6109                          *   edx = value
6110                          *   edx >>= nursery_shift
6111                          *   cmp edx, (nursery_start >> nursery_shift)
6112                          *   jne done
6113                          *   edx = ptr
6114                          *   edx >>= card_table_shift
6115                          *   edx += cardtable
6116                          *   [edx] = 1
6117                          * done:
6118                          */
6119
6120                         if (mono_gc_card_table_nursery_check ()) {
6121                                 if (value != AMD64_RDX)
6122                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6123                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6124                                 if (shifted_nursery_start >> 31) {
6125                                         /*
6126                                          * The value we need to compare against is 64 bits, so we need
6127                                          * another spare register.  We use RBX, which we save and
6128                                          * restore.
6129                                          */
6130                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6131                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6132                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6133                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6134                                 } else {
6135                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6136                                 }
6137                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6138                         }
6139                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6140                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6141                         if (card_table_mask)
6142                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6143
6144                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6145                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6146
6147                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6148
6149                         if (mono_gc_card_table_nursery_check ())
6150                                 x86_patch (br, code);
6151                         break;
6152                 }
6153 #ifdef MONO_ARCH_SIMD_INTRINSICS
6154                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6155                 case OP_ADDPS:
6156                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6157                         break;
6158                 case OP_DIVPS:
6159                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6160                         break;
6161                 case OP_MULPS:
6162                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_SUBPS:
6165                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_MAXPS:
6168                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170                 case OP_MINPS:
6171                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6172                         break;
6173                 case OP_COMPPS:
6174                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6175                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6176                         break;
6177                 case OP_ANDPS:
6178                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6179                         break;
6180                 case OP_ANDNPS:
6181                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_ORPS:
6184                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_XORPS:
6187                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_SQRTPS:
6190                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6191                         break;
6192                 case OP_RSQRTPS:
6193                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6194                         break;
6195                 case OP_RCPPS:
6196                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6197                         break;
6198                 case OP_ADDSUBPS:
6199                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_HADDPS:
6202                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_HSUBPS:
6205                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_DUPPS_HIGH:
6208                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6209                         break;
6210                 case OP_DUPPS_LOW:
6211                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6212                         break;
6213
6214                 case OP_PSHUFLEW_HIGH:
6215                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6216                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6217                         break;
6218                 case OP_PSHUFLEW_LOW:
6219                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6220                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6221                         break;
6222                 case OP_PSHUFLED:
6223                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6224                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6225                         break;
6226                 case OP_SHUFPS:
6227                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6228                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6229                         break;
6230                 case OP_SHUFPD:
6231                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6232                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6233                         break;
6234
6235                 case OP_ADDPD:
6236                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6237                         break;
6238                 case OP_DIVPD:
6239                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6240                         break;
6241                 case OP_MULPD:
6242                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6243                         break;
6244                 case OP_SUBPD:
6245                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6246                         break;
6247                 case OP_MAXPD:
6248                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6249                         break;
6250                 case OP_MINPD:
6251                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6252                         break;
6253                 case OP_COMPPD:
6254                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6255                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6256                         break;
6257                 case OP_ANDPD:
6258                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6259                         break;
6260                 case OP_ANDNPD:
6261                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6262                         break;
6263                 case OP_ORPD:
6264                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6265                         break;
6266                 case OP_XORPD:
6267                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6268                         break;
6269                 case OP_SQRTPD:
6270                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6271                         break;
6272                 case OP_ADDSUBPD:
6273                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6274                         break;
6275                 case OP_HADDPD:
6276                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6277                         break;
6278                 case OP_HSUBPD:
6279                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6280                         break;
6281                 case OP_DUPPD:
6282                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6283                         break;
6284
6285                 case OP_EXTRACT_MASK:
6286                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6287                         break;
6288
6289                 case OP_PAND:
6290                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6291                         break;
6292                 case OP_POR:
6293                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6294                         break;
6295                 case OP_PXOR:
6296                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6297                         break;
6298
6299                 case OP_PADDB:
6300                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6301                         break;
6302                 case OP_PADDW:
6303                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6304                         break;
6305                 case OP_PADDD:
6306                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6307                         break;
6308                 case OP_PADDQ:
6309                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6310                         break;
6311
6312                 case OP_PSUBB:
6313                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6314                         break;
6315                 case OP_PSUBW:
6316                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6317                         break;
6318                 case OP_PSUBD:
6319                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6320                         break;
6321                 case OP_PSUBQ:
6322                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6323                         break;
6324
6325                 case OP_PMAXB_UN:
6326                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6327                         break;
6328                 case OP_PMAXW_UN:
6329                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6330                         break;
6331                 case OP_PMAXD_UN:
6332                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6333                         break;
6334
6335                 case OP_PMAXB:
6336                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6337                         break;
6338                 case OP_PMAXW:
6339                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6340                         break;
6341                 case OP_PMAXD:
6342                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6343                         break;
6344
6345                 case OP_PAVGB_UN:
6346                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6347                         break;
6348                 case OP_PAVGW_UN:
6349                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6350                         break;
6351
6352                 case OP_PMINB_UN:
6353                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6354                         break;
6355                 case OP_PMINW_UN:
6356                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6357                         break;
6358                 case OP_PMIND_UN:
6359                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6360                         break;
6361
6362                 case OP_PMINB:
6363                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6364                         break;
6365                 case OP_PMINW:
6366                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6367                         break;
6368                 case OP_PMIND:
6369                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6370                         break;
6371
6372                 case OP_PCMPEQB:
6373                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6374                         break;
6375                 case OP_PCMPEQW:
6376                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6377                         break;
6378                 case OP_PCMPEQD:
6379                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6380                         break;
6381                 case OP_PCMPEQQ:
6382                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6383                         break;
6384
6385                 case OP_PCMPGTB:
6386                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6387                         break;
6388                 case OP_PCMPGTW:
6389                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6390                         break;
6391                 case OP_PCMPGTD:
6392                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6393                         break;
6394                 case OP_PCMPGTQ:
6395                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6396                         break;
6397
6398                 case OP_PSUM_ABS_DIFF:
6399                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6400                         break;
6401
6402                 case OP_UNPACK_LOWB:
6403                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6404                         break;
6405                 case OP_UNPACK_LOWW:
6406                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6407                         break;
6408                 case OP_UNPACK_LOWD:
6409                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6410                         break;
6411                 case OP_UNPACK_LOWQ:
6412                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6413                         break;
6414                 case OP_UNPACK_LOWPS:
6415                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6416                         break;
6417                 case OP_UNPACK_LOWPD:
6418                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6419                         break;
6420
6421                 case OP_UNPACK_HIGHB:
6422                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6423                         break;
6424                 case OP_UNPACK_HIGHW:
6425                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6426                         break;
6427                 case OP_UNPACK_HIGHD:
6428                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6429                         break;
6430                 case OP_UNPACK_HIGHQ:
6431                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6432                         break;
6433                 case OP_UNPACK_HIGHPS:
6434                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6435                         break;
6436                 case OP_UNPACK_HIGHPD:
6437                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6438                         break;
6439
6440                 case OP_PACKW:
6441                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6442                         break;
6443                 case OP_PACKD:
6444                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6445                         break;
6446                 case OP_PACKW_UN:
6447                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6448                         break;
6449                 case OP_PACKD_UN:
6450                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6451                         break;
6452
6453                 case OP_PADDB_SAT_UN:
6454                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6455                         break;
6456                 case OP_PSUBB_SAT_UN:
6457                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6458                         break;
6459                 case OP_PADDW_SAT_UN:
6460                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6461                         break;
6462                 case OP_PSUBW_SAT_UN:
6463                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6464                         break;
6465
6466                 case OP_PADDB_SAT:
6467                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6468                         break;
6469                 case OP_PSUBB_SAT:
6470                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6471                         break;
6472                 case OP_PADDW_SAT:
6473                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6474                         break;
6475                 case OP_PSUBW_SAT:
6476                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6477                         break;
6478
6479                 case OP_PMULW:
6480                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6481                         break;
6482                 case OP_PMULD:
6483                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6484                         break;
6485                 case OP_PMULQ:
6486                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6487                         break;
6488                 case OP_PMULW_HIGH_UN:
6489                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6490                         break;
6491                 case OP_PMULW_HIGH:
6492                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6493                         break;
6494
6495                 case OP_PSHRW:
6496                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6497                         break;
6498                 case OP_PSHRW_REG:
6499                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6500                         break;
6501
6502                 case OP_PSARW:
6503                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6504                         break;
6505                 case OP_PSARW_REG:
6506                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6507                         break;
6508
6509                 case OP_PSHLW:
6510                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6511                         break;
6512                 case OP_PSHLW_REG:
6513                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6514                         break;
6515
6516                 case OP_PSHRD:
6517                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6518                         break;
6519                 case OP_PSHRD_REG:
6520                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6521                         break;
6522
6523                 case OP_PSARD:
6524                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6525                         break;
6526                 case OP_PSARD_REG:
6527                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6528                         break;
6529
6530                 case OP_PSHLD:
6531                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6532                         break;
6533                 case OP_PSHLD_REG:
6534                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6535                         break;
6536
6537                 case OP_PSHRQ:
6538                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6539                         break;
6540                 case OP_PSHRQ_REG:
6541                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6542                         break;
6543
6544                 /*TODO: This is appart of the sse spec but not added
6545                 case OP_PSARQ:
6546                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6547                         break;
6548                 case OP_PSARQ_REG:
6549                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6550                         break;
6551                 */
6552
6553                 case OP_PSHLQ:
6554                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6555                         break;
6556                 case OP_PSHLQ_REG:
6557                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6558                         break;
6559                 case OP_CVTDQ2PD:
6560                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6561                         break;
6562                 case OP_CVTDQ2PS:
6563                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6564                         break;
6565                 case OP_CVTPD2DQ:
6566                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6567                         break;
6568                 case OP_CVTPD2PS:
6569                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6570                         break;
6571                 case OP_CVTPS2DQ:
6572                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6573                         break;
6574                 case OP_CVTPS2PD:
6575                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6576                         break;
6577                 case OP_CVTTPD2DQ:
6578                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6579                         break;
6580                 case OP_CVTTPS2DQ:
6581                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6582                         break;
6583
6584                 case OP_ICONV_TO_X:
6585                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6586                         break;
6587                 case OP_EXTRACT_I4:
6588                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6589                         break;
6590                 case OP_EXTRACT_I8:
6591                         if (ins->inst_c0) {
6592                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6593                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6594                         } else {
6595                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6596                         }
6597                         break;
6598                 case OP_EXTRACT_I1:
6599                 case OP_EXTRACT_U1:
6600                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6601                         if (ins->inst_c0)
6602                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6603                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6604                         break;
6605                 case OP_EXTRACT_I2:
6606                 case OP_EXTRACT_U2:
6607                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6608                         if (ins->inst_c0)
6609                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6610                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6611                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6612                         break;
6613                 case OP_EXTRACT_R8:
6614                         if (ins->inst_c0)
6615                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6616                         else
6617                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6618                         break;
6619                 case OP_INSERT_I2:
6620                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6621                         break;
6622                 case OP_EXTRACTX_U2:
6623                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6624                         break;
6625                 case OP_INSERTX_U1_SLOW:
6626                         /*sreg1 is the extracted ireg (scratch)
6627                         /sreg2 is the to be inserted ireg (scratch)
6628                         /dreg is the xreg to receive the value*/
6629
6630                         /*clear the bits from the extracted word*/
6631                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6632                         /*shift the value to insert if needed*/
6633                         if (ins->inst_c0 & 1)
6634                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6635                         /*join them together*/
6636                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6637                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6638                         break;
6639                 case OP_INSERTX_I4_SLOW:
6640                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6641                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6642                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6643                         break;
6644                 case OP_INSERTX_I8_SLOW:
6645                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6646                         if (ins->inst_c0)
6647                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6648                         else
6649                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6650                         break;
6651
6652                 case OP_INSERTX_R4_SLOW:
6653                         switch (ins->inst_c0) {
6654                         case 0:
6655                                 if (cfg->r4fp)
6656                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6657                                 else
6658                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6659                                 break;
6660                         case 1:
6661                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6662                                 if (cfg->r4fp)
6663                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6664                                 else
6665                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6666                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6667                                 break;
6668                         case 2:
6669                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6670                                 if (cfg->r4fp)
6671                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6672                                 else
6673                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6674                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6675                                 break;
6676                         case 3:
6677                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6678                                 if (cfg->r4fp)
6679                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6680                                 else
6681                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6682                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6683                                 break;
6684                         }
6685                         break;
6686                 case OP_INSERTX_R8_SLOW:
6687                         if (ins->inst_c0)
6688                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6689                         else
6690                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6691                         break;
6692                 case OP_STOREX_MEMBASE_REG:
6693                 case OP_STOREX_MEMBASE:
6694                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6695                         break;
6696                 case OP_LOADX_MEMBASE:
6697                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6698                         break;
6699                 case OP_LOADX_ALIGNED_MEMBASE:
6700                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6701                         break;
6702                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6703                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6704                         break;
6705                 case OP_STOREX_NTA_MEMBASE_REG:
6706                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6707                         break;
6708                 case OP_PREFETCH_MEMBASE:
6709                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6710                         break;
6711
6712                 case OP_XMOVE:
6713                         /*FIXME the peephole pass should have killed this*/
6714                         if (ins->dreg != ins->sreg1)
6715                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6716                         break;
6717                 case OP_XZERO:
6718                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6719                         break;
6720                 case OP_ICONV_TO_R4_RAW:
6721                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6722                         break;
6723
6724                 case OP_FCONV_TO_R8_X:
6725                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6726                         break;
6727
6728                 case OP_XCONV_R8_TO_I4:
6729                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6730                         switch (ins->backend.source_opcode) {
6731                         case OP_FCONV_TO_I1:
6732                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6733                                 break;
6734                         case OP_FCONV_TO_U1:
6735                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6736                                 break;
6737                         case OP_FCONV_TO_I2:
6738                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6739                                 break;
6740                         case OP_FCONV_TO_U2:
6741                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6742                                 break;
6743                         }
6744                         break;
6745
6746                 case OP_EXPAND_I2:
6747                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6748                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6749                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6750                         break;
6751                 case OP_EXPAND_I4:
6752                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6753                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6754                         break;
6755                 case OP_EXPAND_I8:
6756                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6757                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6758                         break;
6759                 case OP_EXPAND_R4:
6760                         if (cfg->r4fp) {
6761                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6762                         } else {
6763                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6764                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6765                         }
6766                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6767                         break;
6768                 case OP_EXPAND_R8:
6769                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6770                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6771                         break;
6772 #endif
6773                 case OP_LIVERANGE_START: {
6774                         if (cfg->verbose_level > 1)
6775                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6776                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6777                         break;
6778                 }
6779                 case OP_LIVERANGE_END: {
6780                         if (cfg->verbose_level > 1)
6781                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6782                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6783                         break;
6784                 }
6785                 case OP_GC_SAFE_POINT: {
6786                         const char *polling_func = NULL;
6787                         int compare_val = 0;
6788                         guint8 *br [1];
6789
6790 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6791                         polling_func = "mono_nacl_gc";
6792                         compare_val = 0xFFFFFFFF;
6793 #else
6794                         g_assert (mono_threads_is_coop_enabled ());
6795                         polling_func = "mono_threads_state_poll";
6796                         compare_val = 1;
6797 #endif
6798
6799                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6800                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6801                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6802                         amd64_patch (br[0], code);
6803                         break;
6804                 }
6805
6806                 case OP_GC_LIVENESS_DEF:
6807                 case OP_GC_LIVENESS_USE:
6808                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6809                         ins->backend.pc_offset = code - cfg->native_code;
6810                         break;
6811                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6812                         ins->backend.pc_offset = code - cfg->native_code;
6813                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6814                         break;
6815                 default:
6816                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6817                         g_assert_not_reached ();
6818                 }
6819
6820                 if ((code - cfg->native_code - offset) > max_len) {
6821 #if !defined(__native_client_codegen__)
6822                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6823                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6824                         g_assert_not_reached ();
6825 #endif
6826                 }
6827         }
6828
6829         cfg->code_len = code - cfg->native_code;
6830 }
6831
6832 #endif /* DISABLE_JIT */
6833
6834 void
6835 mono_arch_register_lowlevel_calls (void)
6836 {
6837         /* The signature doesn't matter */
6838         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6839 }
6840
6841 void
6842 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6843 {
6844         unsigned char *ip = ji->ip.i + code;
6845
6846         /*
6847          * Debug code to help track down problems where the target of a near call is
6848          * is not valid.
6849          */
6850         if (amd64_is_near_call (ip)) {
6851                 gint64 disp = (guint8*)target - (guint8*)ip;
6852
6853                 if (!amd64_is_imm32 (disp)) {
6854                         printf ("TYPE: %d\n", ji->type);
6855                         switch (ji->type) {
6856                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6857                                 printf ("V: %s\n", ji->data.name);
6858                                 break;
6859                         case MONO_PATCH_INFO_METHOD_JUMP:
6860                         case MONO_PATCH_INFO_METHOD:
6861                                 printf ("V: %s\n", ji->data.method->name);
6862                                 break;
6863                         default:
6864                                 break;
6865                         }
6866                 }
6867         }
6868
6869         amd64_patch (ip, (gpointer)target);
6870 }
6871
6872 #ifndef DISABLE_JIT
6873
6874 static int
6875 get_max_epilog_size (MonoCompile *cfg)
6876 {
6877         int max_epilog_size = 16;
6878
6879         if (cfg->method->save_lmf)
6880                 max_epilog_size += 256;
6881
6882         if (mono_jit_trace_calls != NULL)
6883                 max_epilog_size += 50;
6884
6885         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6886                 max_epilog_size += 50;
6887
6888         max_epilog_size += (AMD64_NREG * 2);
6889
6890         return max_epilog_size;
6891 }
6892
6893 /*
6894  * This macro is used for testing whenever the unwinder works correctly at every point
6895  * where an async exception can happen.
6896  */
6897 /* This will generate a SIGSEGV at the given point in the code */
6898 #define async_exc_point(code) do { \
6899     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6900          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6901              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6902          cfg->arch.async_point_count ++; \
6903     } \
6904 } while (0)
6905
6906 guint8 *
6907 mono_arch_emit_prolog (MonoCompile *cfg)
6908 {
6909         MonoMethod *method = cfg->method;
6910         MonoBasicBlock *bb;
6911         MonoMethodSignature *sig;
6912         MonoInst *ins;
6913         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6914         guint8 *code;
6915         CallInfo *cinfo;
6916         MonoInst *lmf_var = cfg->lmf_var;
6917         gboolean args_clobbered = FALSE;
6918         gboolean trace = FALSE;
6919 #ifdef __native_client_codegen__
6920         guint alignment_check;
6921 #endif
6922
6923         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6924
6925 #if defined(__default_codegen__)
6926         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6927 #elif defined(__native_client_codegen__)
6928         /* native_code_alloc is not 32-byte aligned, native_code is. */
6929         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6930
6931         /* Align native_code to next nearest kNaclAlignment byte. */
6932         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6933         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6934
6935         code = cfg->native_code;
6936
6937         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6938         g_assert (alignment_check == 0);
6939 #endif
6940
6941         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6942                 trace = TRUE;
6943
6944         /* Amount of stack space allocated by register saving code */
6945         pos = 0;
6946
6947         /* Offset between RSP and the CFA */
6948         cfa_offset = 0;
6949
6950         /*
6951          * The prolog consists of the following parts:
6952          * FP present:
6953          * - push rbp, mov rbp, rsp
6954          * - save callee saved regs using pushes
6955          * - allocate frame
6956          * - save rgctx if needed
6957          * - save lmf if needed
6958          * FP not present:
6959          * - allocate frame
6960          * - save rgctx if needed
6961          * - save lmf if needed
6962          * - save callee saved regs using moves
6963          */
6964
6965         // CFA = sp + 8
6966         cfa_offset = 8;
6967         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6968         // IP saved at CFA - 8
6969         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6970         async_exc_point (code);
6971         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6972
6973         if (!cfg->arch.omit_fp) {
6974                 amd64_push_reg (code, AMD64_RBP);
6975                 cfa_offset += 8;
6976                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6977                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6978                 async_exc_point (code);
6979 #ifdef TARGET_WIN32
6980                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6981 #endif
6982                 /* These are handled automatically by the stack marking code */
6983                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6984
6985                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6986                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6987                 async_exc_point (code);
6988 #ifdef TARGET_WIN32
6989                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6990 #endif
6991         }
6992
6993         /* The param area is always at offset 0 from sp */
6994         /* This needs to be allocated here, since it has to come after the spill area */
6995         if (cfg->param_area) {
6996                 if (cfg->arch.omit_fp)
6997                         // FIXME:
6998                         g_assert_not_reached ();
6999                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
7000         }
7001
7002         if (cfg->arch.omit_fp) {
7003                 /*
7004                  * On enter, the stack is misaligned by the pushing of the return
7005                  * address. It is either made aligned by the pushing of %rbp, or by
7006                  * this.
7007                  */
7008                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
7009                 if ((alloc_size % 16) == 0) {
7010                         alloc_size += 8;
7011                         /* Mark the padding slot as NOREF */
7012                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
7013                 }
7014         } else {
7015                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
7016                 if (cfg->stack_offset != alloc_size) {
7017                         /* Mark the padding slot as NOREF */
7018                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
7019                 }
7020                 cfg->arch.sp_fp_offset = alloc_size;
7021                 alloc_size -= pos;
7022         }
7023
7024         cfg->arch.stack_alloc_size = alloc_size;
7025
7026         /* Allocate stack frame */
7027         if (alloc_size) {
7028                 /* See mono_emit_stack_alloc */
7029 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
7030                 guint32 remaining_size = alloc_size;
7031                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
7032                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
7033                 guint32 offset = code - cfg->native_code;
7034                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
7035                         while (required_code_size >= (cfg->code_size - offset))
7036                                 cfg->code_size *= 2;
7037                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7038                         code = cfg->native_code + offset;
7039                         cfg->stat_code_reallocs++;
7040                 }
7041
7042                 while (remaining_size >= 0x1000) {
7043                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
7044                         if (cfg->arch.omit_fp) {
7045                                 cfa_offset += 0x1000;
7046                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7047                         }
7048                         async_exc_point (code);
7049 #ifdef TARGET_WIN32
7050                         if (cfg->arch.omit_fp)
7051                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
7052 #endif
7053
7054                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
7055                         remaining_size -= 0x1000;
7056                 }
7057                 if (remaining_size) {
7058                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7059                         if (cfg->arch.omit_fp) {
7060                                 cfa_offset += remaining_size;
7061                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7062                                 async_exc_point (code);
7063                         }
7064 #ifdef TARGET_WIN32
7065                         if (cfg->arch.omit_fp)
7066                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7067 #endif
7068                 }
7069 #else
7070                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7071                 if (cfg->arch.omit_fp) {
7072                         cfa_offset += alloc_size;
7073                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7074                         async_exc_point (code);
7075                 }
7076 #endif
7077         }
7078
7079         /* Stack alignment check */
7080 #if 0
7081         {
7082                 guint8 *buf;
7083
7084                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7085                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7086                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7087                 buf = code;
7088                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
7089                 amd64_breakpoint (code);
7090                 amd64_patch (buf, code);
7091         }
7092 #endif
7093
7094         if (mini_get_debug_options ()->init_stacks) {
7095                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7096
7097                 /* Save registers to the red zone */
7098                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7099                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7100
7101                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7102                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7103                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7104
7105                 amd64_cld (code);
7106 #if defined(__default_codegen__)
7107                 amd64_prefix (code, X86_REP_PREFIX);
7108                 amd64_stosl (code);
7109 #elif defined(__native_client_codegen__)
7110                 /* NaCl stos pseudo-instruction */
7111                 amd64_codegen_pre (code);
7112                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7113                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7114                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7115                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7116                 amd64_prefix (code, X86_REP_PREFIX);
7117                 amd64_stosl (code);
7118                 amd64_codegen_post (code);
7119 #endif /* __native_client_codegen__ */
7120
7121                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7122                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7123         }
7124
7125         /* Save LMF */
7126         if (method->save_lmf)
7127                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7128
7129         /* Save callee saved registers */
7130         if (cfg->arch.omit_fp) {
7131                 save_area_offset = cfg->arch.reg_save_area_offset;
7132                 /* Save caller saved registers after sp is adjusted */
7133                 /* The registers are saved at the bottom of the frame */
7134                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7135         } else {
7136                 /* The registers are saved just below the saved rbp */
7137                 save_area_offset = cfg->arch.reg_save_area_offset;
7138         }
7139
7140         for (i = 0; i < AMD64_NREG; ++i) {
7141                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7142                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7143
7144                         if (cfg->arch.omit_fp) {
7145                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7146                                 /* These are handled automatically by the stack marking code */
7147                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7148                         } else {
7149                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7150                                 // FIXME: GC
7151                         }
7152
7153                         save_area_offset += 8;
7154                         async_exc_point (code);
7155                 }
7156         }
7157
7158         /* store runtime generic context */
7159         if (cfg->rgctx_var) {
7160                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7161                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7162
7163                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7164
7165                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7166                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7167         }
7168
7169         /* compute max_length in order to use short forward jumps */
7170         max_epilog_size = get_max_epilog_size (cfg);
7171         if (cfg->opt & MONO_OPT_BRANCH) {
7172                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7173                         MonoInst *ins;
7174                         int max_length = 0;
7175
7176                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7177                                 max_length += 6;
7178                         /* max alignment for loops */
7179                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7180                                 max_length += LOOP_ALIGNMENT;
7181 #ifdef __native_client_codegen__
7182                         /* max alignment for native client */
7183                         max_length += kNaClAlignment;
7184 #endif
7185
7186                         MONO_BB_FOR_EACH_INS (bb, ins) {
7187 #ifdef __native_client_codegen__
7188                                 {
7189                                         int space_in_block = kNaClAlignment -
7190                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7191                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7192                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7193                                                 max_length += space_in_block;
7194                                         }
7195                                 }
7196 #endif  /*__native_client_codegen__*/
7197                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7198                         }
7199
7200                         /* Take prolog and epilog instrumentation into account */
7201                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7202                                 max_length += max_epilog_size;
7203
7204                         bb->max_length = max_length;
7205                 }
7206         }
7207
7208         sig = mono_method_signature (method);
7209         pos = 0;
7210
7211         cinfo = (CallInfo *)cfg->arch.cinfo;
7212
7213         if (sig->ret->type != MONO_TYPE_VOID) {
7214                 /* Save volatile arguments to the stack */
7215                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7216                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7217         }
7218
7219         /* Keep this in sync with emit_load_volatile_arguments */
7220         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7221                 ArgInfo *ainfo = cinfo->args + i;
7222
7223                 ins = cfg->args [i];
7224
7225                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7226                         /* Unused arguments */
7227                         continue;
7228
7229                 /* Save volatile arguments to the stack */
7230                 if (ins->opcode != OP_REGVAR) {
7231                         switch (ainfo->storage) {
7232                         case ArgInIReg: {
7233                                 guint32 size = 8;
7234
7235                                 /* FIXME: I1 etc */
7236                                 /*
7237                                 if (stack_offset & 0x1)
7238                                         size = 1;
7239                                 else if (stack_offset & 0x2)
7240                                         size = 2;
7241                                 else if (stack_offset & 0x4)
7242                                         size = 4;
7243                                 else
7244                                         size = 8;
7245                                 */
7246                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7247
7248                                 /*
7249                                  * Save the original location of 'this',
7250                                  * get_generic_info_from_stack_frame () needs this to properly look up
7251                                  * the argument value during the handling of async exceptions.
7252                                  */
7253                                 if (ins == cfg->args [0]) {
7254                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7255                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7256                                 }
7257                                 break;
7258                         }
7259                         case ArgInFloatSSEReg:
7260                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7261                                 break;
7262                         case ArgInDoubleSSEReg:
7263                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7264                                 break;
7265                         case ArgValuetypeInReg:
7266                                 for (quad = 0; quad < 2; quad ++) {
7267                                         switch (ainfo->pair_storage [quad]) {
7268                                         case ArgInIReg:
7269                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7270                                                 break;
7271                                         case ArgInFloatSSEReg:
7272                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7273                                                 break;
7274                                         case ArgInDoubleSSEReg:
7275                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7276                                                 break;
7277                                         case ArgNone:
7278                                                 break;
7279                                         default:
7280                                                 g_assert_not_reached ();
7281                                         }
7282                                 }
7283                                 break;
7284                         case ArgValuetypeAddrInIReg:
7285                                 if (ainfo->pair_storage [0] == ArgInIReg)
7286                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7287                                 break;
7288                         case ArgGSharedVtInReg:
7289                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7290                                 break;
7291                         default:
7292                                 break;
7293                         }
7294                 } else {
7295                         /* Argument allocated to (non-volatile) register */
7296                         switch (ainfo->storage) {
7297                         case ArgInIReg:
7298                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7299                                 break;
7300                         case ArgOnStack:
7301                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7302                                 break;
7303                         default:
7304                                 g_assert_not_reached ();
7305                         }
7306
7307                         if (ins == cfg->args [0]) {
7308                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7309                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7310                         }
7311                 }
7312         }
7313
7314         if (cfg->method->save_lmf)
7315                 args_clobbered = TRUE;
7316
7317         if (trace) {
7318                 args_clobbered = TRUE;
7319                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7320         }
7321
7322         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7323                 args_clobbered = TRUE;
7324
7325         /*
7326          * Optimize the common case of the first bblock making a call with the same
7327          * arguments as the method. This works because the arguments are still in their
7328          * original argument registers.
7329          * FIXME: Generalize this
7330          */
7331         if (!args_clobbered) {
7332                 MonoBasicBlock *first_bb = cfg->bb_entry;
7333                 MonoInst *next;
7334                 int filter = FILTER_IL_SEQ_POINT;
7335
7336                 next = mono_bb_first_inst (first_bb, filter);
7337                 if (!next && first_bb->next_bb) {
7338                         first_bb = first_bb->next_bb;
7339                         next = mono_bb_first_inst (first_bb, filter);
7340                 }
7341
7342                 if (first_bb->in_count > 1)
7343                         next = NULL;
7344
7345                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7346                         ArgInfo *ainfo = cinfo->args + i;
7347                         gboolean match = FALSE;
7348
7349                         ins = cfg->args [i];
7350                         if (ins->opcode != OP_REGVAR) {
7351                                 switch (ainfo->storage) {
7352                                 case ArgInIReg: {
7353                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7354                                                 if (next->dreg == ainfo->reg) {
7355                                                         NULLIFY_INS (next);
7356                                                         match = TRUE;
7357                                                 } else {
7358                                                         next->opcode = OP_MOVE;
7359                                                         next->sreg1 = ainfo->reg;
7360                                                         /* Only continue if the instruction doesn't change argument regs */
7361                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7362                                                                 match = TRUE;
7363                                                 }
7364                                         }
7365                                         break;
7366                                 }
7367                                 default:
7368                                         break;
7369                                 }
7370                         } else {
7371                                 /* Argument allocated to (non-volatile) register */
7372                                 switch (ainfo->storage) {
7373                                 case ArgInIReg:
7374                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7375                                                 NULLIFY_INS (next);
7376                                                 match = TRUE;
7377                                         }
7378                                         break;
7379                                 default:
7380                                         break;
7381                                 }
7382                         }
7383
7384                         if (match) {
7385                                 next = mono_inst_next (next, filter);
7386                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7387                                 if (!next)
7388                                         break;
7389                         }
7390                 }
7391         }
7392
7393         if (cfg->gen_sdb_seq_points) {
7394                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7395
7396                 /* Initialize seq_point_info_var */
7397                 if (cfg->compile_aot) {
7398                         /* Initialize the variable from a GOT slot */
7399                         /* Same as OP_AOTCONST */
7400                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7401                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7402                         g_assert (info_var->opcode == OP_REGOFFSET);
7403                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7404                 }
7405
7406                 if (cfg->compile_aot) {
7407                         /* Initialize ss_tramp_var */
7408                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7409                         g_assert (ins->opcode == OP_REGOFFSET);
7410
7411                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7412                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7413                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7414                 } else {
7415                         /* Initialize ss_tramp_var */
7416                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7417                         g_assert (ins->opcode == OP_REGOFFSET);
7418
7419                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7420                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7421
7422                         /* Initialize bp_tramp_var */
7423                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7424                         g_assert (ins->opcode == OP_REGOFFSET);
7425
7426                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7427                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7428                 }
7429         }
7430
7431         cfg->code_len = code - cfg->native_code;
7432
7433         g_assert (cfg->code_len < cfg->code_size);
7434
7435         return code;
7436 }
7437
7438 void
7439 mono_arch_emit_epilog (MonoCompile *cfg)
7440 {
7441         MonoMethod *method = cfg->method;
7442         int quad, i;
7443         guint8 *code;
7444         int max_epilog_size;
7445         CallInfo *cinfo;
7446         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7447         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7448
7449         max_epilog_size = get_max_epilog_size (cfg);
7450
7451         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7452                 cfg->code_size *= 2;
7453                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7454                 cfg->stat_code_reallocs++;
7455         }
7456         code = cfg->native_code + cfg->code_len;
7457
7458         cfg->has_unwind_info_for_epilog = TRUE;
7459
7460         /* Mark the start of the epilog */
7461         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7462
7463         /* Save the uwind state which is needed by the out-of-line code */
7464         mono_emit_unwind_op_remember_state (cfg, code);
7465
7466         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7467                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7468
7469         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7470
7471         if (method->save_lmf) {
7472                 /* check if we need to restore protection of the stack after a stack overflow */
7473                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7474                         guint8 *patch;
7475                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7476                         /* we load the value in a separate instruction: this mechanism may be
7477                          * used later as a safer way to do thread interruption
7478                          */
7479                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7480                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7481                         patch = code;
7482                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7483                         /* note that the call trampoline will preserve eax/edx */
7484                         x86_call_reg (code, X86_ECX);
7485                         x86_patch (patch, code);
7486                 } else {
7487                         /* FIXME: maybe save the jit tls in the prolog */
7488                 }
7489                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7490                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7491                 }
7492         }
7493
7494         /* Restore callee saved regs */
7495         for (i = 0; i < AMD64_NREG; ++i) {
7496                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7497                         /* Restore only used_int_regs, not arch.saved_iregs */
7498                         if (cfg->used_int_regs & (1 << i)) {
7499                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7500                                 mono_emit_unwind_op_same_value (cfg, code, i);
7501                                 async_exc_point (code);
7502                         }
7503                         save_area_offset += 8;
7504                 }
7505         }
7506
7507         /* Load returned vtypes into registers if needed */
7508         cinfo = (CallInfo *)cfg->arch.cinfo;
7509         if (cinfo->ret.storage == ArgValuetypeInReg) {
7510                 ArgInfo *ainfo = &cinfo->ret;
7511                 MonoInst *inst = cfg->ret;
7512
7513                 for (quad = 0; quad < 2; quad ++) {
7514                         switch (ainfo->pair_storage [quad]) {
7515                         case ArgInIReg:
7516                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7517                                 break;
7518                         case ArgInFloatSSEReg:
7519                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7520                                 break;
7521                         case ArgInDoubleSSEReg:
7522                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7523                                 break;
7524                         case ArgNone:
7525                                 break;
7526                         default:
7527                                 g_assert_not_reached ();
7528                         }
7529                 }
7530         }
7531
7532         if (cfg->arch.omit_fp) {
7533                 if (cfg->arch.stack_alloc_size) {
7534                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7535                 }
7536         } else {
7537                 amd64_leave (code);
7538                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7539         }
7540         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7541         async_exc_point (code);
7542         amd64_ret (code);
7543
7544         /* Restore the unwind state to be the same as before the epilog */
7545         mono_emit_unwind_op_restore_state (cfg, code);
7546
7547         cfg->code_len = code - cfg->native_code;
7548
7549         g_assert (cfg->code_len < cfg->code_size);
7550 }
7551
7552 void
7553 mono_arch_emit_exceptions (MonoCompile *cfg)
7554 {
7555         MonoJumpInfo *patch_info;
7556         int nthrows, i;
7557         guint8 *code;
7558         MonoClass *exc_classes [16];
7559         guint8 *exc_throw_start [16], *exc_throw_end [16];
7560         guint32 code_size = 0;
7561
7562         /* Compute needed space */
7563         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7564                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7565                         code_size += 40;
7566                 if (patch_info->type == MONO_PATCH_INFO_R8)
7567                         code_size += 8 + 15; /* sizeof (double) + alignment */
7568                 if (patch_info->type == MONO_PATCH_INFO_R4)
7569                         code_size += 4 + 15; /* sizeof (float) + alignment */
7570                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7571                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7572         }
7573
7574 #ifdef __native_client_codegen__
7575         /* Give us extra room on Native Client.  This could be   */
7576         /* more carefully calculated, but bundle alignment makes */
7577         /* it much trickier, so *2 like other places is good.    */
7578         code_size *= 2;
7579 #endif
7580
7581         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7582                 cfg->code_size *= 2;
7583                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7584                 cfg->stat_code_reallocs++;
7585         }
7586
7587         code = cfg->native_code + cfg->code_len;
7588
7589         /* add code to raise exceptions */
7590         nthrows = 0;
7591         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7592                 switch (patch_info->type) {
7593                 case MONO_PATCH_INFO_EXC: {
7594                         MonoClass *exc_class;
7595                         guint8 *buf, *buf2;
7596                         guint32 throw_ip;
7597
7598                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7599
7600                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7601                         throw_ip = patch_info->ip.i;
7602
7603                         //x86_breakpoint (code);
7604                         /* Find a throw sequence for the same exception class */
7605                         for (i = 0; i < nthrows; ++i)
7606                                 if (exc_classes [i] == exc_class)
7607                                         break;
7608                         if (i < nthrows) {
7609                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7610                                 x86_jump_code (code, exc_throw_start [i]);
7611                                 patch_info->type = MONO_PATCH_INFO_NONE;
7612                         }
7613                         else {
7614                                 buf = code;
7615                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7616                                 buf2 = code;
7617
7618                                 if (nthrows < 16) {
7619                                         exc_classes [nthrows] = exc_class;
7620                                         exc_throw_start [nthrows] = code;
7621                                 }
7622                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7623
7624                                 patch_info->type = MONO_PATCH_INFO_NONE;
7625
7626                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7627
7628                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7629                                 while (buf < buf2)
7630                                         x86_nop (buf);
7631
7632                                 if (nthrows < 16) {
7633                                         exc_throw_end [nthrows] = code;
7634                                         nthrows ++;
7635                                 }
7636                         }
7637                         break;
7638                 }
7639                 default:
7640                         /* do nothing */
7641                         break;
7642                 }
7643                 g_assert(code < cfg->native_code + cfg->code_size);
7644         }
7645
7646         /* Handle relocations with RIP relative addressing */
7647         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7648                 gboolean remove = FALSE;
7649                 guint8 *orig_code = code;
7650
7651                 switch (patch_info->type) {
7652                 case MONO_PATCH_INFO_R8:
7653                 case MONO_PATCH_INFO_R4: {
7654                         guint8 *pos, *patch_pos;
7655                         guint32 target_pos;
7656
7657                         /* The SSE opcodes require a 16 byte alignment */
7658 #if defined(__default_codegen__)
7659                         code = (guint8*)ALIGN_TO (code, 16);
7660 #elif defined(__native_client_codegen__)
7661                         {
7662                                 /* Pad this out with HLT instructions  */
7663                                 /* or we can get garbage bytes emitted */
7664                                 /* which will fail validation          */
7665                                 guint8 *aligned_code;
7666                                 /* extra align to make room for  */
7667                                 /* mov/push below                      */
7668                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7669                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7670                                 /* The technique of hiding data in an  */
7671                                 /* instruction has a problem here: we  */
7672                                 /* need the data aligned to a 16-byte  */
7673                                 /* boundary but the instruction cannot */
7674                                 /* cross the bundle boundary. so only  */
7675                                 /* odd multiples of 16 can be used     */
7676                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7677                                         aligned_code += 16;
7678                                 }
7679                                 while (code < aligned_code) {
7680                                         *(code++) = 0xf4; /* hlt */
7681                                 }
7682                         }
7683 #endif
7684
7685                         pos = cfg->native_code + patch_info->ip.i;
7686                         if (IS_REX (pos [1])) {
7687                                 patch_pos = pos + 5;
7688                                 target_pos = code - pos - 9;
7689                         }
7690                         else {
7691                                 patch_pos = pos + 4;
7692                                 target_pos = code - pos - 8;
7693                         }
7694
7695                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7696 #ifdef __native_client_codegen__
7697                                 /* Hide 64-bit data in a         */
7698                                 /* "mov imm64, r11" instruction. */
7699                                 /* write it before the start of  */
7700                                 /* the data*/
7701                                 *(code-2) = 0x49; /* prefix      */
7702                                 *(code-1) = 0xbb; /* mov X, %r11 */
7703 #endif
7704                                 *(double*)code = *(double*)patch_info->data.target;
7705                                 code += sizeof (double);
7706                         } else {
7707 #ifdef __native_client_codegen__
7708                                 /* Hide 32-bit data in a        */
7709                                 /* "push imm32" instruction.    */
7710                                 *(code-1) = 0x68; /* push */
7711 #endif
7712                                 *(float*)code = *(float*)patch_info->data.target;
7713                                 code += sizeof (float);
7714                         }
7715
7716                         *(guint32*)(patch_pos) = target_pos;
7717
7718                         remove = TRUE;
7719                         break;
7720                 }
7721                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7722                         guint8 *pos;
7723
7724                         if (cfg->compile_aot)
7725                                 continue;
7726
7727                         /*loading is faster against aligned addresses.*/
7728                         code = (guint8*)ALIGN_TO (code, 8);
7729                         memset (orig_code, 0, code - orig_code);
7730
7731                         pos = cfg->native_code + patch_info->ip.i;
7732
7733                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7734                         if (IS_REX (pos [1]))
7735                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7736                         else
7737                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7738
7739                         *(gpointer*)code = (gpointer)patch_info->data.target;
7740                         code += sizeof (gpointer);
7741
7742                         remove = TRUE;
7743                         break;
7744                 }
7745                 default:
7746                         break;
7747                 }
7748
7749                 if (remove) {
7750                         if (patch_info == cfg->patch_info)
7751                                 cfg->patch_info = patch_info->next;
7752                         else {
7753                                 MonoJumpInfo *tmp;
7754
7755                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7756                                         ;
7757                                 tmp->next = patch_info->next;
7758                         }
7759                 }
7760                 g_assert (code < cfg->native_code + cfg->code_size);
7761         }
7762
7763         cfg->code_len = code - cfg->native_code;
7764
7765         g_assert (cfg->code_len < cfg->code_size);
7766
7767 }
7768
7769 #endif /* DISABLE_JIT */
7770
7771 void*
7772 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7773 {
7774         guchar *code = (guchar *)p;
7775         MonoMethodSignature *sig;
7776         MonoInst *inst;
7777         int i, n, stack_area = 0;
7778
7779         /* Keep this in sync with mono_arch_get_argument_info */
7780
7781         if (enable_arguments) {
7782                 /* Allocate a new area on the stack and save arguments there */
7783                 sig = mono_method_signature (cfg->method);
7784
7785                 n = sig->param_count + sig->hasthis;
7786
7787                 stack_area = ALIGN_TO (n * 8, 16);
7788
7789                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7790
7791                 for (i = 0; i < n; ++i) {
7792                         inst = cfg->args [i];
7793
7794                         if (inst->opcode == OP_REGVAR)
7795                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7796                         else {
7797                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7798                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7799                         }
7800                 }
7801         }
7802
7803         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7804         amd64_set_reg_template (code, AMD64_ARG_REG1);
7805         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7806         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7807
7808         if (enable_arguments)
7809                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7810
7811         return code;
7812 }
7813
7814 enum {
7815         SAVE_NONE,
7816         SAVE_STRUCT,
7817         SAVE_EAX,
7818         SAVE_EAX_EDX,
7819         SAVE_XMM
7820 };
7821
7822 void*
7823 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7824 {
7825         guchar *code = (guchar *)p;
7826         int save_mode = SAVE_NONE;
7827         MonoMethod *method = cfg->method;
7828         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7829         int i;
7830
7831         switch (ret_type->type) {
7832         case MONO_TYPE_VOID:
7833                 /* special case string .ctor icall */
7834                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7835                         save_mode = SAVE_EAX;
7836                 else
7837                         save_mode = SAVE_NONE;
7838                 break;
7839         case MONO_TYPE_I8:
7840         case MONO_TYPE_U8:
7841                 save_mode = SAVE_EAX;
7842                 break;
7843         case MONO_TYPE_R4:
7844         case MONO_TYPE_R8:
7845                 save_mode = SAVE_XMM;
7846                 break;
7847         case MONO_TYPE_GENERICINST:
7848                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7849                         save_mode = SAVE_EAX;
7850                         break;
7851                 }
7852                 /* Fall through */
7853         case MONO_TYPE_VALUETYPE:
7854                 save_mode = SAVE_STRUCT;
7855                 break;
7856         default:
7857                 save_mode = SAVE_EAX;
7858                 break;
7859         }
7860
7861         /* Save the result and copy it into the proper argument register */
7862         switch (save_mode) {
7863         case SAVE_EAX:
7864                 amd64_push_reg (code, AMD64_RAX);
7865                 /* Align stack */
7866                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7867                 if (enable_arguments)
7868                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7869                 break;
7870         case SAVE_STRUCT:
7871                 /* FIXME: */
7872                 if (enable_arguments)
7873                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7874                 break;
7875         case SAVE_XMM:
7876                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7877                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7878                 /* Align stack */
7879                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7880                 /*
7881                  * The result is already in the proper argument register so no copying
7882                  * needed.
7883                  */
7884                 break;
7885         case SAVE_NONE:
7886                 break;
7887         default:
7888                 g_assert_not_reached ();
7889         }
7890
7891         /* Set %al since this is a varargs call */
7892         if (save_mode == SAVE_XMM)
7893                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7894         else
7895                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7896
7897         if (preserve_argument_registers) {
7898                 for (i = 0; i < PARAM_REGS; ++i)
7899                         amd64_push_reg (code, param_regs [i]);
7900         }
7901
7902         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7903         amd64_set_reg_template (code, AMD64_ARG_REG1);
7904         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7905
7906         if (preserve_argument_registers) {
7907                 for (i = PARAM_REGS - 1; i >= 0; --i)
7908                         amd64_pop_reg (code, param_regs [i]);
7909         }
7910
7911         /* Restore result */
7912         switch (save_mode) {
7913         case SAVE_EAX:
7914                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7915                 amd64_pop_reg (code, AMD64_RAX);
7916                 break;
7917         case SAVE_STRUCT:
7918                 /* FIXME: */
7919                 break;
7920         case SAVE_XMM:
7921                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7922                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7923                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7924                 break;
7925         case SAVE_NONE:
7926                 break;
7927         default:
7928                 g_assert_not_reached ();
7929         }
7930
7931         return code;
7932 }
7933
7934 void
7935 mono_arch_flush_icache (guint8 *code, gint size)
7936 {
7937         /* Not needed */
7938 }
7939
7940 void
7941 mono_arch_flush_register_windows (void)
7942 {
7943 }
7944
7945 gboolean
7946 mono_arch_is_inst_imm (gint64 imm)
7947 {
7948         return amd64_use_imm32 (imm);
7949 }
7950
7951 /*
7952  * Determine whenever the trap whose info is in SIGINFO is caused by
7953  * integer overflow.
7954  */
7955 gboolean
7956 mono_arch_is_int_overflow (void *sigctx, void *info)
7957 {
7958         MonoContext ctx;
7959         guint8* rip;
7960         int reg;
7961         gint64 value;
7962
7963         mono_sigctx_to_monoctx (sigctx, &ctx);
7964
7965         rip = (guint8*)ctx.gregs [AMD64_RIP];
7966
7967         if (IS_REX (rip [0])) {
7968                 reg = amd64_rex_b (rip [0]);
7969                 rip ++;
7970         }
7971         else
7972                 reg = 0;
7973
7974         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7975                 /* idiv REG */
7976                 reg += x86_modrm_rm (rip [1]);
7977
7978                 value = ctx.gregs [reg];
7979
7980                 if (value == -1)
7981                         return TRUE;
7982         }
7983
7984         return FALSE;
7985 }
7986
7987 guint32
7988 mono_arch_get_patch_offset (guint8 *code)
7989 {
7990         return 3;
7991 }
7992
7993 /**
7994  * mono_breakpoint_clean_code:
7995  *
7996  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7997  * breakpoints in the original code, they are removed in the copy.
7998  *
7999  * Returns TRUE if no sw breakpoint was present.
8000  */
8001 gboolean
8002 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
8003 {
8004         /*
8005          * If method_start is non-NULL we need to perform bound checks, since we access memory
8006          * at code - offset we could go before the start of the method and end up in a different
8007          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
8008          * instead.
8009          */
8010         if (!method_start || code - offset >= method_start) {
8011                 memcpy (buf, code - offset, size);
8012         } else {
8013                 int diff = code - method_start;
8014                 memset (buf, 0, size);
8015                 memcpy (buf + offset - diff, method_start, diff + size - offset);
8016         }
8017         return TRUE;
8018 }
8019
8020 #if defined(__native_client_codegen__)
8021 /* For membase calls, we want the base register. for Native Client,  */
8022 /* all indirect calls have the following sequence with the given sizes: */
8023 /* mov %eXX,%eXX                                [2-3]   */
8024 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
8025 /* and $0xffffffffffffffe0,%r11d                [4]     */
8026 /* add %r15,%r11                                [3]     */
8027 /* callq *%r11                                  [3]     */
8028
8029
8030 /* Determine if code points to a NaCl call-through-register sequence, */
8031 /* (i.e., the last 3 instructions listed above) */
8032 int
8033 is_nacl_call_reg_sequence(guint8* code)
8034 {
8035         const char *sequence = "\x41\x83\xe3\xe0" /* and */
8036                                "\x4d\x03\xdf"     /* add */
8037                                "\x41\xff\xd3";   /* call */
8038         return memcmp(code, sequence, 10) == 0;
8039 }
8040
8041 /* Determine if code points to the first opcode of the mov membase component */
8042 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
8043 /* (there could be a REX prefix before the opcode but it is ignored) */
8044 static int
8045 is_nacl_indirect_call_membase_sequence(guint8* code)
8046 {
8047                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
8048         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
8049                /* and that src reg = dest reg */
8050                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
8051                /* Check that next inst is mov, uses SIB byte (rm = 4), */
8052                IS_REX(code[2]) &&
8053                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
8054                /* and has dst of r11 and base of r15 */
8055                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8056                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8057 }
8058 #endif /* __native_client_codegen__ */
8059
8060 int
8061 mono_arch_get_this_arg_reg (guint8 *code)
8062 {
8063         return AMD64_ARG_REG1;
8064 }
8065
8066 gpointer
8067 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8068 {
8069         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8070 }
8071
8072 #define MAX_ARCH_DELEGATE_PARAMS 10
8073
8074 static gpointer
8075 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8076 {
8077         guint8 *code, *start;
8078         GSList *unwind_ops = NULL;
8079         int i;
8080
8081         unwind_ops = mono_arch_get_cie_program ();
8082
8083         if (has_target) {
8084                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8085
8086                 /* Replace the this argument with the target */
8087                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8088                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8089                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8090
8091                 g_assert ((code - start) < 64);
8092         } else {
8093                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8094
8095                 if (param_count == 0) {
8096                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8097                 } else {
8098                         /* We have to shift the arguments left */
8099                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8100                         for (i = 0; i < param_count; ++i) {
8101 #ifdef TARGET_WIN32
8102                                 if (i < 3)
8103                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8104                                 else
8105                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8106 #else
8107                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8108 #endif
8109                         }
8110
8111                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8112                 }
8113                 g_assert ((code - start) < 64);
8114         }
8115
8116         nacl_global_codeman_validate (&start, 64, &code);
8117         mono_arch_flush_icache (start, code - start);
8118
8119         if (has_target) {
8120                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8121         } else {
8122                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8123                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8124                 g_free (name);
8125         }
8126
8127         if (mono_jit_map_is_enabled ()) {
8128                 char *buff;
8129                 if (has_target)
8130                         buff = (char*)"delegate_invoke_has_target";
8131                 else
8132                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8133                 mono_emit_jit_tramp (start, code - start, buff);
8134                 if (!has_target)
8135                         g_free (buff);
8136         }
8137         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8138
8139         return start;
8140 }
8141
8142 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8143
8144 static gpointer
8145 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8146 {
8147         guint8 *code, *start;
8148         int size = 20;
8149         char *tramp_name;
8150         GSList *unwind_ops;
8151
8152         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8153                 return NULL;
8154
8155         start = code = (guint8 *)mono_global_codeman_reserve (size);
8156
8157         unwind_ops = mono_arch_get_cie_program ();
8158
8159         /* Replace the this argument with the target */
8160         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8161         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8162
8163         if (load_imt_reg) {
8164                 /* Load the IMT reg */
8165                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8166         }
8167
8168         /* Load the vtable */
8169         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8170         amd64_jump_membase (code, AMD64_RAX, offset);
8171         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8172
8173         if (load_imt_reg)
8174                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8175         else
8176                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8177         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8178         g_free (tramp_name);
8179
8180         return start;
8181 }
8182
8183 /*
8184  * mono_arch_get_delegate_invoke_impls:
8185  *
8186  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8187  * trampolines.
8188  */
8189 GSList*
8190 mono_arch_get_delegate_invoke_impls (void)
8191 {
8192         GSList *res = NULL;
8193         MonoTrampInfo *info;
8194         int i;
8195
8196         get_delegate_invoke_impl (&info, TRUE, 0);
8197         res = g_slist_prepend (res, info);
8198
8199         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8200                 get_delegate_invoke_impl (&info, FALSE, i);
8201                 res = g_slist_prepend (res, info);
8202         }
8203
8204         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8205                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8206                 res = g_slist_prepend (res, info);
8207
8208                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8209                 res = g_slist_prepend (res, info);
8210         }
8211
8212         return res;
8213 }
8214
8215 gpointer
8216 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8217 {
8218         guint8 *code, *start;
8219         int i;
8220
8221         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8222                 return NULL;
8223
8224         /* FIXME: Support more cases */
8225         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8226                 return NULL;
8227
8228         if (has_target) {
8229                 static guint8* cached = NULL;
8230
8231                 if (cached)
8232                         return cached;
8233
8234                 if (mono_aot_only) {
8235                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8236                 } else {
8237                         MonoTrampInfo *info;
8238                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8239                         mono_tramp_info_register (info, NULL);
8240                 }
8241
8242                 mono_memory_barrier ();
8243
8244                 cached = start;
8245         } else {
8246                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8247                 for (i = 0; i < sig->param_count; ++i)
8248                         if (!mono_is_regsize_var (sig->params [i]))
8249                                 return NULL;
8250                 if (sig->param_count > 4)
8251                         return NULL;
8252
8253                 code = cache [sig->param_count];
8254                 if (code)
8255                         return code;
8256
8257                 if (mono_aot_only) {
8258                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8259                         start = (guint8 *)mono_aot_get_trampoline (name);
8260                         g_free (name);
8261                 } else {
8262                         MonoTrampInfo *info;
8263                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8264                         mono_tramp_info_register (info, NULL);
8265                 }
8266
8267                 mono_memory_barrier ();
8268
8269                 cache [sig->param_count] = start;
8270         }
8271
8272         return start;
8273 }
8274
8275 gpointer
8276 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8277 {
8278         MonoTrampInfo *info;
8279         gpointer code;
8280
8281         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8282         if (code)
8283                 mono_tramp_info_register (info, NULL);
8284         return code;
8285 }
8286
8287 void
8288 mono_arch_finish_init (void)
8289 {
8290 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8291         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8292 #endif
8293 }
8294
8295 void
8296 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8297 {
8298 }
8299
8300 #if defined(__default_codegen__)
8301 #define CMP_SIZE (6 + 1)
8302 #define CMP_REG_REG_SIZE (4 + 1)
8303 #define BR_SMALL_SIZE 2
8304 #define BR_LARGE_SIZE 6
8305 #define MOV_REG_IMM_SIZE 10
8306 #define MOV_REG_IMM_32BIT_SIZE 6
8307 #define JUMP_REG_SIZE (2 + 1)
8308 #elif defined(__native_client_codegen__)
8309 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8310 #define CMP_SIZE ((6 + 1) * 2 - 1)
8311 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8312 #define BR_SMALL_SIZE (2 * 2 - 1)
8313 #define BR_LARGE_SIZE (6 * 2 - 1)
8314 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8315 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8316 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8317 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8318 /* Jump membase's size is large and unpredictable    */
8319 /* in native client, just pad it out a whole bundle. */
8320 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8321 #endif
8322
8323 static int
8324 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8325 {
8326         int i, distance = 0;
8327         for (i = start; i < target; ++i)
8328                 distance += imt_entries [i]->chunk_size;
8329         return distance;
8330 }
8331
8332 /*
8333  * LOCKING: called with the domain lock held
8334  */
8335 gpointer
8336 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8337         gpointer fail_tramp)
8338 {
8339         int i;
8340         int size = 0;
8341         guint8 *code, *start;
8342         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8343         GSList *unwind_ops;
8344
8345         for (i = 0; i < count; ++i) {
8346                 MonoIMTCheckItem *item = imt_entries [i];
8347                 if (item->is_equals) {
8348                         if (item->check_target_idx) {
8349                                 if (!item->compare_done) {
8350                                         if (amd64_use_imm32 ((gint64)item->key))
8351                                                 item->chunk_size += CMP_SIZE;
8352                                         else
8353                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8354                                 }
8355                                 if (item->has_target_code) {
8356                                         item->chunk_size += MOV_REG_IMM_SIZE;
8357                                 } else {
8358                                         if (vtable_is_32bit)
8359                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8360                                         else
8361                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8362 #ifdef __native_client_codegen__
8363                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8364 #endif
8365                                 }
8366                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8367                         } else {
8368                                 if (fail_tramp) {
8369                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8370                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8371                                 } else {
8372                                         if (vtable_is_32bit)
8373                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8374                                         else
8375                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8376                                         item->chunk_size += JUMP_REG_SIZE;
8377                                         /* with assert below:
8378                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8379                                          */
8380 #ifdef __native_client_codegen__
8381                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8382 #endif
8383                                 }
8384                         }
8385                 } else {
8386                         if (amd64_use_imm32 ((gint64)item->key))
8387                                 item->chunk_size += CMP_SIZE;
8388                         else
8389                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8390                         item->chunk_size += BR_LARGE_SIZE;
8391                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8392                 }
8393                 size += item->chunk_size;
8394         }
8395 #if defined(__native_client__) && defined(__native_client_codegen__)
8396         /* In Native Client, we don't re-use thunks, allocate from the */
8397         /* normal code manager paths. */
8398         code = mono_domain_code_reserve (domain, size);
8399 #else
8400         if (fail_tramp)
8401                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8402         else
8403                 code = (guint8 *)mono_domain_code_reserve (domain, size);
8404 #endif
8405         start = code;
8406
8407         unwind_ops = mono_arch_get_cie_program ();
8408
8409         for (i = 0; i < count; ++i) {
8410                 MonoIMTCheckItem *item = imt_entries [i];
8411                 item->code_target = code;
8412                 if (item->is_equals) {
8413                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8414
8415                         if (item->check_target_idx || fail_case) {
8416                                 if (!item->compare_done || fail_case) {
8417                                         if (amd64_use_imm32 ((gint64)item->key))
8418                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8419                                         else {
8420                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8421                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8422                                         }
8423                                 }
8424                                 item->jmp_code = code;
8425                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8426                                 if (item->has_target_code) {
8427                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8428                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8429                                 } else {
8430                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8431                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8432                                 }
8433
8434                                 if (fail_case) {
8435                                         amd64_patch (item->jmp_code, code);
8436                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8437                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8438                                         item->jmp_code = NULL;
8439                                 }
8440                         } else {
8441                                 /* enable the commented code to assert on wrong method */
8442 #if 0
8443                                 if (amd64_is_imm32 (item->key))
8444                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8445                                 else {
8446                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8447                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8448                                 }
8449                                 item->jmp_code = code;
8450                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8451                                 /* See the comment below about R10 */
8452                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8453                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8454                                 amd64_patch (item->jmp_code, code);
8455                                 amd64_breakpoint (code);
8456                                 item->jmp_code = NULL;
8457 #else
8458                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8459                                    needs to be preserved.  R10 needs
8460                                    to be preserved for calls which
8461                                    require a runtime generic context,
8462                                    but interface calls don't. */
8463                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8464                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8465 #endif
8466                         }
8467                 } else {
8468                         if (amd64_use_imm32 ((gint64)item->key))
8469                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8470                         else {
8471                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8472                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8473                         }
8474                         item->jmp_code = code;
8475                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8476                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8477                         else
8478                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8479                 }
8480                 g_assert (code - item->code_target <= item->chunk_size);
8481         }
8482         /* patch the branches to get to the target items */
8483         for (i = 0; i < count; ++i) {
8484                 MonoIMTCheckItem *item = imt_entries [i];
8485                 if (item->jmp_code) {
8486                         if (item->check_target_idx) {
8487                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8488                         }
8489                 }
8490         }
8491
8492         if (!fail_tramp)
8493                 mono_stats.imt_thunks_size += code - start;
8494         g_assert (code - start <= size);
8495
8496         nacl_domain_code_validate(domain, &start, size, &code);
8497         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8498
8499         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8500
8501         return start;
8502 }
8503
8504 MonoMethod*
8505 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8506 {
8507         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8508 }
8509
8510 MonoVTable*
8511 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8512 {
8513         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8514 }
8515
8516 GSList*
8517 mono_arch_get_cie_program (void)
8518 {
8519         GSList *l = NULL;
8520
8521         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8522         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8523
8524         return l;
8525 }
8526
8527 #ifndef DISABLE_JIT
8528
8529 MonoInst*
8530 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8531 {
8532         MonoInst *ins = NULL;
8533         int opcode = 0;
8534
8535         if (cmethod->klass == mono_defaults.math_class) {
8536                 if (strcmp (cmethod->name, "Sin") == 0) {
8537                         opcode = OP_SIN;
8538                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8539                         opcode = OP_COS;
8540                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8541                         opcode = OP_SQRT;
8542                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8543                         opcode = OP_ABS;
8544                 }
8545
8546                 if (opcode && fsig->param_count == 1) {
8547                         MONO_INST_NEW (cfg, ins, opcode);
8548                         ins->type = STACK_R8;
8549                         ins->dreg = mono_alloc_freg (cfg);
8550                         ins->sreg1 = args [0]->dreg;
8551                         MONO_ADD_INS (cfg->cbb, ins);
8552                 }
8553
8554                 opcode = 0;
8555                 if (cfg->opt & MONO_OPT_CMOV) {
8556                         if (strcmp (cmethod->name, "Min") == 0) {
8557                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8558                                         opcode = OP_IMIN;
8559                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8560                                         opcode = OP_IMIN_UN;
8561                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8562                                         opcode = OP_LMIN;
8563                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8564                                         opcode = OP_LMIN_UN;
8565                         } else if (strcmp (cmethod->name, "Max") == 0) {
8566                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8567                                         opcode = OP_IMAX;
8568                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8569                                         opcode = OP_IMAX_UN;
8570                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8571                                         opcode = OP_LMAX;
8572                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8573                                         opcode = OP_LMAX_UN;
8574                         }
8575                 }
8576
8577                 if (opcode && fsig->param_count == 2) {
8578                         MONO_INST_NEW (cfg, ins, opcode);
8579                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8580                         ins->dreg = mono_alloc_ireg (cfg);
8581                         ins->sreg1 = args [0]->dreg;
8582                         ins->sreg2 = args [1]->dreg;
8583                         MONO_ADD_INS (cfg->cbb, ins);
8584                 }
8585
8586 #if 0
8587                 /* OP_FREM is not IEEE compatible */
8588                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8589                         MONO_INST_NEW (cfg, ins, OP_FREM);
8590                         ins->inst_i0 = args [0];
8591                         ins->inst_i1 = args [1];
8592                 }
8593 #endif
8594         }
8595
8596         return ins;
8597 }
8598 #endif
8599
8600 gboolean
8601 mono_arch_print_tree (MonoInst *tree, int arity)
8602 {
8603         return 0;
8604 }
8605
8606 mgreg_t
8607 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8608 {
8609         return ctx->gregs [reg];
8610 }
8611
8612 void
8613 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8614 {
8615         ctx->gregs [reg] = val;
8616 }
8617
8618 gpointer
8619 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8620 {
8621         gpointer *sp, old_value;
8622         char *bp;
8623
8624         /*Load the spvar*/
8625         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8626         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8627
8628         old_value = *sp;
8629         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8630                 return old_value;
8631
8632         *sp = new_value;
8633
8634         return old_value;
8635 }
8636
8637 /*
8638  * mono_arch_emit_load_aotconst:
8639  *
8640  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8641  * TARGET from the mscorlib GOT in full-aot code.
8642  * On AMD64, the result is placed into R11.
8643  */
8644 guint8*
8645 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8646 {
8647         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8648         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8649
8650         return code;
8651 }
8652
8653 /*
8654  * mono_arch_get_trampolines:
8655  *
8656  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8657  * for AOT.
8658  */
8659 GSList *
8660 mono_arch_get_trampolines (gboolean aot)
8661 {
8662         return mono_amd64_get_exception_trampolines (aot);
8663 }
8664
8665 /* Soft Debug support */
8666 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8667
8668 /*
8669  * mono_arch_set_breakpoint:
8670  *
8671  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8672  * The location should contain code emitted by OP_SEQ_POINT.
8673  */
8674 void
8675 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8676 {
8677         guint8 *code = ip;
8678
8679         if (ji->from_aot) {
8680                 guint32 native_offset = ip - (guint8*)ji->code_start;
8681                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8682
8683                 g_assert (info->bp_addrs [native_offset] == 0);
8684                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8685         } else {
8686                 /* ip points to a mov r11, 0 */
8687                 g_assert (code [0] == 0x41);
8688                 g_assert (code [1] == 0xbb);
8689                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8690         }
8691 }
8692
8693 /*
8694  * mono_arch_clear_breakpoint:
8695  *
8696  *   Clear the breakpoint at IP.
8697  */
8698 void
8699 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8700 {
8701         guint8 *code = ip;
8702
8703         if (ji->from_aot) {
8704                 guint32 native_offset = ip - (guint8*)ji->code_start;
8705                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8706
8707                 info->bp_addrs [native_offset] = NULL;
8708         } else {
8709                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8710         }
8711 }
8712
8713 gboolean
8714 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8715 {
8716         /* We use soft breakpoints on amd64 */
8717         return FALSE;
8718 }
8719
8720 /*
8721  * mono_arch_skip_breakpoint:
8722  *
8723  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8724  * we resume, the instruction is not executed again.
8725  */
8726 void
8727 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8728 {
8729         g_assert_not_reached ();
8730 }
8731
8732 /*
8733  * mono_arch_start_single_stepping:
8734  *
8735  *   Start single stepping.
8736  */
8737 void
8738 mono_arch_start_single_stepping (void)
8739 {
8740         ss_trampoline = mini_get_single_step_trampoline ();
8741 }
8742
8743 /*
8744  * mono_arch_stop_single_stepping:
8745  *
8746  *   Stop single stepping.
8747  */
8748 void
8749 mono_arch_stop_single_stepping (void)
8750 {
8751         ss_trampoline = NULL;
8752 }
8753
8754 /*
8755  * mono_arch_is_single_step_event:
8756  *
8757  *   Return whenever the machine state in SIGCTX corresponds to a single
8758  * step event.
8759  */
8760 gboolean
8761 mono_arch_is_single_step_event (void *info, void *sigctx)
8762 {
8763         /* We use soft breakpoints on amd64 */
8764         return FALSE;
8765 }
8766
8767 /*
8768  * mono_arch_skip_single_step:
8769  *
8770  *   Modify CTX so the ip is placed after the single step trigger instruction,
8771  * we resume, the instruction is not executed again.
8772  */
8773 void
8774 mono_arch_skip_single_step (MonoContext *ctx)
8775 {
8776         g_assert_not_reached ();
8777 }
8778
8779 /*
8780  * mono_arch_create_seq_point_info:
8781  *
8782  *   Return a pointer to a data structure which is used by the sequence
8783  * point implementation in AOTed code.
8784  */
8785 gpointer
8786 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8787 {
8788         SeqPointInfo *info;
8789         MonoJitInfo *ji;
8790
8791         // FIXME: Add a free function
8792
8793         mono_domain_lock (domain);
8794         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8795                                                                 code);
8796         mono_domain_unlock (domain);
8797
8798         if (!info) {
8799                 ji = mono_jit_info_table_find (domain, (char*)code);
8800                 g_assert (ji);
8801
8802                 // FIXME: Optimize the size
8803                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8804
8805                 info->ss_tramp_addr = &ss_trampoline;
8806
8807                 mono_domain_lock (domain);
8808                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8809                                                          code, info);
8810                 mono_domain_unlock (domain);
8811         }
8812
8813         return info;
8814 }
8815
8816 void
8817 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8818 {
8819         ext->lmf.previous_lmf = prev_lmf;
8820         /* Mark that this is a MonoLMFExt */
8821         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8822         ext->lmf.rsp = (gssize)ext;
8823 }
8824
8825 #endif
8826
8827 gboolean
8828 mono_arch_opcode_supported (int opcode)
8829 {
8830         switch (opcode) {
8831         case OP_ATOMIC_ADD_I4:
8832         case OP_ATOMIC_ADD_I8:
8833         case OP_ATOMIC_EXCHANGE_I4:
8834         case OP_ATOMIC_EXCHANGE_I8:
8835         case OP_ATOMIC_CAS_I4:
8836         case OP_ATOMIC_CAS_I8:
8837         case OP_ATOMIC_LOAD_I1:
8838         case OP_ATOMIC_LOAD_I2:
8839         case OP_ATOMIC_LOAD_I4:
8840         case OP_ATOMIC_LOAD_I8:
8841         case OP_ATOMIC_LOAD_U1:
8842         case OP_ATOMIC_LOAD_U2:
8843         case OP_ATOMIC_LOAD_U4:
8844         case OP_ATOMIC_LOAD_U8:
8845         case OP_ATOMIC_LOAD_R4:
8846         case OP_ATOMIC_LOAD_R8:
8847         case OP_ATOMIC_STORE_I1:
8848         case OP_ATOMIC_STORE_I2:
8849         case OP_ATOMIC_STORE_I4:
8850         case OP_ATOMIC_STORE_I8:
8851         case OP_ATOMIC_STORE_U1:
8852         case OP_ATOMIC_STORE_U2:
8853         case OP_ATOMIC_STORE_U4:
8854         case OP_ATOMIC_STORE_U8:
8855         case OP_ATOMIC_STORE_R4:
8856         case OP_ATOMIC_STORE_R8:
8857                 return TRUE;
8858         default:
8859                 return FALSE;
8860         }
8861 }
8862
8863 #if defined(ENABLE_GSHAREDVT) && defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
8864
8865 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8866
8867 #endif /* !ENABLE_GSHAREDVT */