2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
11 * Johan Lorensson (lateralusx.github@gmail.com)
13 * (C) 2003 Ximian, Inc.
14 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
15 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
16 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
25 #include <mono/metadata/abi-details.h>
26 #include <mono/metadata/appdomain.h>
27 #include <mono/metadata/debug-helpers.h>
28 #include <mono/metadata/threads.h>
29 #include <mono/metadata/profiler-private.h>
30 #include <mono/metadata/mono-debug.h>
31 #include <mono/metadata/gc-internals.h>
32 #include <mono/utils/mono-math.h>
33 #include <mono/utils/mono-mmap.h>
34 #include <mono/utils/mono-memory-model.h>
35 #include <mono/utils/mono-tls.h>
36 #include <mono/utils/mono-hwcap-x86.h>
37 #include <mono/utils/mono-threads.h>
41 #include "mini-amd64.h"
42 #include "cpu-amd64.h"
43 #include "debugger-agent.h"
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
59 /* Under windows, the calling convention is never stdcall */
60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
65 /* This mutex protects architecture specific caches */
66 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
67 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
68 static mono_mutex_t mini_arch_mutex;
70 /* The single step trampoline */
71 static gpointer ss_trampoline;
73 /* The breakpoint trampoline */
74 static gpointer bp_trampoline;
76 /* Offset between fp and the first argument in the callee */
77 #define ARGS_OFFSET 16
78 #define GP_SCRATCH_REG AMD64_R11
81 * AMD64 register usage:
82 * - callee saved registers are used for global register allocation
83 * - %r11 is used for materializing 64 bit constants in opcodes
84 * - the rest is used for local allocation
88 * Floating point comparison results:
98 mono_arch_regname (int reg)
101 case AMD64_RAX: return "%rax";
102 case AMD64_RBX: return "%rbx";
103 case AMD64_RCX: return "%rcx";
104 case AMD64_RDX: return "%rdx";
105 case AMD64_RSP: return "%rsp";
106 case AMD64_RBP: return "%rbp";
107 case AMD64_RDI: return "%rdi";
108 case AMD64_RSI: return "%rsi";
109 case AMD64_R8: return "%r8";
110 case AMD64_R9: return "%r9";
111 case AMD64_R10: return "%r10";
112 case AMD64_R11: return "%r11";
113 case AMD64_R12: return "%r12";
114 case AMD64_R13: return "%r13";
115 case AMD64_R14: return "%r14";
116 case AMD64_R15: return "%r15";
121 static const char * packed_xmmregs [] = {
122 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
123 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
126 static const char * single_xmmregs [] = {
127 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
128 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
132 mono_arch_fregname (int reg)
134 if (reg < AMD64_XMM_NREG)
135 return single_xmmregs [reg];
141 mono_arch_xregname (int reg)
143 if (reg < AMD64_XMM_NREG)
144 return packed_xmmregs [reg];
153 return mono_debug_count ();
159 static inline gboolean
160 amd64_is_near_call (guint8 *code)
163 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
166 return code [0] == 0xe8;
169 static inline gboolean
170 amd64_use_imm32 (gint64 val)
172 if (mini_get_debug_options()->single_imm_size)
175 return amd64_is_imm32 (val);
179 amd64_patch (unsigned char* code, gpointer target)
184 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
189 if ((code [0] & 0xf8) == 0xb8) {
190 /* amd64_set_reg_template */
191 *(guint64*)(code + 1) = (guint64)target;
193 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
194 /* mov 0(%rip), %dreg */
195 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
197 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
198 /* call *<OFFSET>(%rip) */
199 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
201 else if (code [0] == 0xe8) {
203 gint64 disp = (guint8*)target - (guint8*)code;
204 g_assert (amd64_is_imm32 (disp));
205 x86_patch (code, (unsigned char*)target);
208 x86_patch (code, (unsigned char*)target);
212 mono_amd64_patch (unsigned char* code, gpointer target)
214 amd64_patch (code, target);
217 #define DEBUG(a) if (cfg->verbose_level > 1) a
220 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
222 ainfo->offset = *stack_size;
224 if (*gr >= PARAM_REGS) {
225 ainfo->storage = ArgOnStack;
226 ainfo->arg_size = sizeof (mgreg_t);
227 /* Since the same stack slot size is used for all arg */
228 /* types, it needs to be big enough to hold them all */
229 (*stack_size) += sizeof(mgreg_t);
232 ainfo->storage = ArgInIReg;
233 ainfo->reg = param_regs [*gr];
239 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
241 ainfo->offset = *stack_size;
243 if (*gr >= FLOAT_PARAM_REGS) {
244 ainfo->storage = ArgOnStack;
245 ainfo->arg_size = sizeof (mgreg_t);
246 /* Since the same stack slot size is used for both float */
247 /* types, it needs to be big enough to hold them both */
248 (*stack_size) += sizeof(mgreg_t);
251 /* A double register */
253 ainfo->storage = ArgInDoubleSSEReg;
255 ainfo->storage = ArgInFloatSSEReg;
261 typedef enum ArgumentClass {
269 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
271 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
274 ptype = mini_get_underlying_type (type);
275 switch (ptype->type) {
284 case MONO_TYPE_STRING:
285 case MONO_TYPE_OBJECT:
286 case MONO_TYPE_CLASS:
287 case MONO_TYPE_SZARRAY:
289 case MONO_TYPE_FNPTR:
290 case MONO_TYPE_ARRAY:
293 class2 = ARG_CLASS_INTEGER;
298 class2 = ARG_CLASS_INTEGER;
300 class2 = ARG_CLASS_SSE;
304 case MONO_TYPE_TYPEDBYREF:
305 g_assert_not_reached ();
307 case MONO_TYPE_GENERICINST:
308 if (!mono_type_generic_inst_is_valuetype (ptype)) {
309 class2 = ARG_CLASS_INTEGER;
313 case MONO_TYPE_VALUETYPE: {
314 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
317 for (i = 0; i < info->num_fields; ++i) {
319 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
324 g_assert_not_reached ();
328 if (class1 == class2)
330 else if (class1 == ARG_CLASS_NO_CLASS)
332 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
333 class1 = ARG_CLASS_MEMORY;
334 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
335 class1 = ARG_CLASS_INTEGER;
337 class1 = ARG_CLASS_SSE;
343 count_fields_nested (MonoClass *klass, gboolean pinvoke)
345 MonoMarshalType *info;
350 info = mono_marshal_load_type_info (klass);
352 for (i = 0; i < info->num_fields; ++i) {
353 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
354 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type), pinvoke);
360 MonoClassField *field;
363 while ((field = mono_class_get_fields (klass, &iter))) {
364 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
366 if (MONO_TYPE_ISSTRUCT (field->type))
367 count += count_fields_nested (mono_class_from_mono_type (field->type), pinvoke);
381 * collect_field_info_nested:
383 * Collect field info from KLASS recursively into FIELDS.
386 collect_field_info_nested (MonoClass *klass, StructFieldInfo *fields, int index, int offset, gboolean pinvoke, gboolean unicode)
388 MonoMarshalType *info;
392 info = mono_marshal_load_type_info (klass);
394 for (i = 0; i < info->num_fields; ++i) {
395 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
396 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset, pinvoke, unicode);
400 fields [index].type = info->fields [i].field->type;
401 fields [index].size = mono_marshal_type_size (info->fields [i].field->type,
402 info->fields [i].mspec,
403 &align, TRUE, unicode);
404 fields [index].offset = offset + info->fields [i].offset;
410 MonoClassField *field;
413 while ((field = mono_class_get_fields (klass, &iter))) {
414 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
416 if (MONO_TYPE_ISSTRUCT (field->type)) {
417 index = collect_field_info_nested (mono_class_from_mono_type (field->type), fields, index, field->offset - sizeof (MonoObject), pinvoke, unicode);
421 fields [index].type = field->type;
422 fields [index].size = mono_type_size (field->type, &align);
423 fields [index].offset = field->offset - sizeof (MonoObject) + offset;
433 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
434 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
437 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
439 gboolean result = FALSE;
441 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
442 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
444 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
445 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
446 arg_info->pair_size [0] = 0;
447 arg_info->pair_size [1] = 0;
450 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
451 /* Pass parameter in integer register. */
452 arg_info->pair_storage [0] = ArgInIReg;
453 arg_info->pair_regs [0] = int_regs [*current_int_reg];
454 (*current_int_reg) ++;
456 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
457 /* Pass parameter in float register. */
458 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
459 arg_info->pair_regs [0] = float_regs [*current_float_reg];
460 (*current_float_reg) ++;
464 if (result == TRUE) {
465 arg_info->pair_size [0] = arg_size;
473 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
475 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
479 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
481 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
485 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
486 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
488 /* Windows x64 value type ABI.
490 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
492 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
493 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
494 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
495 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
497 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
499 * Integers/Float types smaller than or equal to 8 bytes
500 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
501 * Properly sized struct/unions (1,2,4,8)
502 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
503 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
504 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
507 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
511 /* Parameter cases. */
512 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
513 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
515 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
516 arg_info->storage = ArgValuetypeInReg;
517 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
518 /* No more registers, fallback passing parameter on stack as value. */
519 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
521 /* Passing value directly on stack, so use size of value. */
522 arg_info->storage = ArgOnStack;
523 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
524 arg_info->offset = *stack_size;
525 arg_info->arg_size = arg_size;
526 *stack_size += arg_size;
529 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
530 arg_info->storage = ArgValuetypeAddrInIReg;
531 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
532 /* No more registers, fallback passing address to parameter on stack. */
533 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
535 /* Passing an address to value on stack, so use size of register as argument size. */
536 arg_info->storage = ArgValuetypeAddrOnStack;
537 arg_size = sizeof (mgreg_t);
538 arg_info->offset = *stack_size;
539 arg_info->arg_size = arg_size;
540 *stack_size += arg_size;
544 /* Return value cases. */
545 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
546 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
548 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
549 arg_info->storage = ArgValuetypeInReg;
550 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
552 /* Only RAX/XMM0 should be used to return valuetype. */
553 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
555 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
556 arg_info->storage = ArgValuetypeAddrInIReg;
557 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
559 /* Only RAX should be used to return valuetype address. */
560 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
562 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
563 arg_info->offset = *stack_size;
564 *stack_size += arg_size;
570 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
573 *arg_class = ARG_CLASS_NO_CLASS;
575 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
578 /* Calculate argument class type and size of marshalled type. */
579 MonoMarshalType *info = mono_marshal_load_type_info (klass);
580 *arg_size = info->native_size;
582 /* Calculate argument class type and size of managed type. */
583 *arg_size = mono_class_value_size (klass, NULL);
586 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
587 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
589 if (*arg_class == ARG_CLASS_MEMORY) {
590 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
591 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
595 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
596 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
597 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
598 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
599 * it must be represented in call and cannot be dropped.
601 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
602 arg_info->pass_empty_struct = TRUE;
603 *arg_size = SIZEOF_REGISTER;
604 *arg_class = ARG_CLASS_INTEGER;
607 assert (*arg_class != ARG_CLASS_NO_CLASS);
611 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
612 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
614 guint32 arg_size = SIZEOF_REGISTER;
615 MonoClass *klass = NULL;
616 ArgumentClass arg_class;
618 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
620 klass = mono_class_from_mono_type (type);
621 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
623 /* Only drop value type if its not an empty struct as input that must be represented in call */
624 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
625 arg_info->storage = ArgValuetypeInReg;
626 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
628 /* Alocate storage for value type. */
629 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
633 #endif /* TARGET_WIN32 */
636 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
638 guint32 *gr, guint32 *fr, guint32 *stack_size)
641 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
643 guint32 size, quad, nquads, i, nfields;
644 /* Keep track of the size used in each quad so we can */
645 /* use the right size when copying args/return vars. */
646 guint32 quadsize [2] = {8, 8};
647 ArgumentClass args [2];
648 StructFieldInfo *fields = NULL;
650 gboolean pass_on_stack = FALSE;
653 klass = mono_class_from_mono_type (type);
654 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
656 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
657 /* We pass and return vtypes of size 8 in a register */
658 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
659 pass_on_stack = TRUE;
662 /* If this struct can't be split up naturally into 8-byte */
663 /* chunks (registers), pass it on the stack. */
665 MonoMarshalType *info = mono_marshal_load_type_info (klass);
667 struct_size = info->native_size;
669 struct_size = mono_class_value_size (klass, NULL);
672 * Collect field information recursively to be able to
673 * handle nested structures.
675 nfields = count_fields_nested (klass, sig->pinvoke);
676 fields = g_new0 (StructFieldInfo, nfields);
677 collect_field_info_nested (klass, fields, 0, 0, sig->pinvoke, klass->unicode);
679 for (i = 0; i < nfields; ++i) {
680 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
681 pass_on_stack = TRUE;
687 ainfo->storage = ArgValuetypeInReg;
688 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
693 /* Allways pass in memory */
694 ainfo->offset = *stack_size;
695 *stack_size += ALIGN_TO (size, 8);
696 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
698 ainfo->arg_size = ALIGN_TO (size, 8);
710 int n = mono_class_value_size (klass, NULL);
712 quadsize [0] = n >= 8 ? 8 : n;
713 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
715 /* Always pass in 1 or 2 integer registers */
716 args [0] = ARG_CLASS_INTEGER;
717 args [1] = ARG_CLASS_INTEGER;
718 /* Only the simplest cases are supported */
719 if (is_return && nquads != 1) {
720 args [0] = ARG_CLASS_MEMORY;
721 args [1] = ARG_CLASS_MEMORY;
725 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
726 * The X87 and SSEUP stuff is left out since there are no such types in
730 ainfo->storage = ArgValuetypeInReg;
731 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
735 if (struct_size > 16) {
736 ainfo->offset = *stack_size;
737 *stack_size += ALIGN_TO (struct_size, 8);
738 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
740 ainfo->arg_size = ALIGN_TO (struct_size, 8);
746 args [0] = ARG_CLASS_NO_CLASS;
747 args [1] = ARG_CLASS_NO_CLASS;
748 for (quad = 0; quad < nquads; ++quad) {
749 ArgumentClass class1;
752 class1 = ARG_CLASS_MEMORY;
754 class1 = ARG_CLASS_NO_CLASS;
755 for (i = 0; i < nfields; ++i) {
756 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
757 /* Unaligned field */
761 /* Skip fields in other quad */
762 if ((quad == 0) && (fields [i].offset >= 8))
764 if ((quad == 1) && (fields [i].offset < 8))
767 /* How far into this quad this data extends.*/
768 /* (8 is size of quad) */
769 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
771 class1 = merge_argument_class_from_type (fields [i].type, class1);
773 /* Empty structs have a nonzero size, causing this assert to be hit */
775 g_assert (class1 != ARG_CLASS_NO_CLASS);
776 args [quad] = class1;
782 /* Post merger cleanup */
783 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
784 args [0] = args [1] = ARG_CLASS_MEMORY;
786 /* Allocate registers */
791 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
793 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
796 ainfo->storage = ArgValuetypeInReg;
797 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
798 g_assert (quadsize [0] <= 8);
799 g_assert (quadsize [1] <= 8);
800 ainfo->pair_size [0] = quadsize [0];
801 ainfo->pair_size [1] = quadsize [1];
802 ainfo->nregs = nquads;
803 for (quad = 0; quad < nquads; ++quad) {
804 switch (args [quad]) {
805 case ARG_CLASS_INTEGER:
806 if (*gr >= PARAM_REGS)
807 args [quad] = ARG_CLASS_MEMORY;
809 ainfo->pair_storage [quad] = ArgInIReg;
811 ainfo->pair_regs [quad] = return_regs [*gr];
813 ainfo->pair_regs [quad] = param_regs [*gr];
818 if (*fr >= FLOAT_PARAM_REGS)
819 args [quad] = ARG_CLASS_MEMORY;
821 if (quadsize[quad] <= 4)
822 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
823 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
824 ainfo->pair_regs [quad] = *fr;
828 case ARG_CLASS_MEMORY:
830 case ARG_CLASS_NO_CLASS:
833 g_assert_not_reached ();
837 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
839 /* Revert possible register assignments */
843 ainfo->offset = *stack_size;
845 arg_size = ALIGN_TO (struct_size, 8);
847 arg_size = nquads * sizeof(mgreg_t);
848 *stack_size += arg_size;
849 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
851 ainfo->arg_size = arg_size;
854 #endif /* !TARGET_WIN32 */
860 * Obtain information about a call according to the calling convention.
861 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
862 * Draft Version 0.23" document for more information.
863 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
864 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
867 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
869 guint32 i, gr, fr, pstart;
871 int n = sig->hasthis + sig->param_count;
872 guint32 stack_size = 0;
874 gboolean is_pinvoke = sig->pinvoke;
877 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
879 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
882 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
888 /* Reserve space where the callee can save the argument registers */
889 stack_size = 4 * sizeof (mgreg_t);
893 ret_type = mini_get_underlying_type (sig->ret);
894 switch (ret_type->type) {
904 case MONO_TYPE_FNPTR:
905 case MONO_TYPE_CLASS:
906 case MONO_TYPE_OBJECT:
907 case MONO_TYPE_SZARRAY:
908 case MONO_TYPE_ARRAY:
909 case MONO_TYPE_STRING:
910 cinfo->ret.storage = ArgInIReg;
911 cinfo->ret.reg = AMD64_RAX;
915 cinfo->ret.storage = ArgInIReg;
916 cinfo->ret.reg = AMD64_RAX;
919 cinfo->ret.storage = ArgInFloatSSEReg;
920 cinfo->ret.reg = AMD64_XMM0;
923 cinfo->ret.storage = ArgInDoubleSSEReg;
924 cinfo->ret.reg = AMD64_XMM0;
926 case MONO_TYPE_GENERICINST:
927 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
928 cinfo->ret.storage = ArgInIReg;
929 cinfo->ret.reg = AMD64_RAX;
932 if (mini_is_gsharedvt_type (ret_type)) {
933 cinfo->ret.storage = ArgGsharedvtVariableInReg;
937 case MONO_TYPE_VALUETYPE:
938 case MONO_TYPE_TYPEDBYREF: {
939 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
941 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
942 g_assert (cinfo->ret.storage != ArgInIReg);
947 g_assert (mini_is_gsharedvt_type (ret_type));
948 cinfo->ret.storage = ArgGsharedvtVariableInReg;
953 g_error ("Can't handle as return value 0x%x", ret_type->type);
958 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
959 * the first argument, allowing 'this' to be always passed in the first arg reg.
960 * Also do this if the first argument is a reference type, since virtual calls
961 * are sometimes made using calli without sig->hasthis set, like in the delegate
964 ArgStorage ret_storage = cinfo->ret.storage;
965 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
967 add_general (&gr, &stack_size, cinfo->args + 0);
969 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
972 add_general (&gr, &stack_size, &cinfo->ret);
973 cinfo->ret.storage = ret_storage;
974 cinfo->vret_arg_index = 1;
978 add_general (&gr, &stack_size, cinfo->args + 0);
980 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
981 add_general (&gr, &stack_size, &cinfo->ret);
982 cinfo->ret.storage = ret_storage;
986 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
988 fr = FLOAT_PARAM_REGS;
990 /* Emit the signature cookie just before the implicit arguments */
991 add_general (&gr, &stack_size, &cinfo->sig_cookie);
994 for (i = pstart; i < sig->param_count; ++i) {
995 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
999 /* The float param registers and other param registers must be the same index on Windows x64.*/
1006 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1007 /* We allways pass the sig cookie on the stack for simplicity */
1009 * Prevent implicit arguments + the sig cookie from being passed
1013 fr = FLOAT_PARAM_REGS;
1015 /* Emit the signature cookie just before the implicit arguments */
1016 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1019 ptype = mini_get_underlying_type (sig->params [i]);
1020 switch (ptype->type) {
1023 add_general (&gr, &stack_size, ainfo);
1027 add_general (&gr, &stack_size, ainfo);
1031 add_general (&gr, &stack_size, ainfo);
1036 case MONO_TYPE_FNPTR:
1037 case MONO_TYPE_CLASS:
1038 case MONO_TYPE_OBJECT:
1039 case MONO_TYPE_STRING:
1040 case MONO_TYPE_SZARRAY:
1041 case MONO_TYPE_ARRAY:
1042 add_general (&gr, &stack_size, ainfo);
1044 case MONO_TYPE_GENERICINST:
1045 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1046 add_general (&gr, &stack_size, ainfo);
1049 if (mini_is_gsharedvt_variable_type (ptype)) {
1050 /* gsharedvt arguments are passed by ref */
1051 add_general (&gr, &stack_size, ainfo);
1052 if (ainfo->storage == ArgInIReg)
1053 ainfo->storage = ArgGSharedVtInReg;
1055 ainfo->storage = ArgGSharedVtOnStack;
1059 case MONO_TYPE_VALUETYPE:
1060 case MONO_TYPE_TYPEDBYREF:
1061 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1066 add_general (&gr, &stack_size, ainfo);
1069 add_float (&fr, &stack_size, ainfo, FALSE);
1072 add_float (&fr, &stack_size, ainfo, TRUE);
1075 case MONO_TYPE_MVAR:
1076 /* gsharedvt arguments are passed by ref */
1077 g_assert (mini_is_gsharedvt_type (ptype));
1078 add_general (&gr, &stack_size, ainfo);
1079 if (ainfo->storage == ArgInIReg)
1080 ainfo->storage = ArgGSharedVtInReg;
1082 ainfo->storage = ArgGSharedVtOnStack;
1085 g_assert_not_reached ();
1089 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1091 fr = FLOAT_PARAM_REGS;
1093 /* Emit the signature cookie just before the implicit arguments */
1094 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1097 cinfo->stack_usage = stack_size;
1098 cinfo->reg_usage = gr;
1099 cinfo->freg_usage = fr;
1104 * mono_arch_get_argument_info:
1105 * @csig: a method signature
1106 * @param_count: the number of parameters to consider
1107 * @arg_info: an array to store the result infos
1109 * Gathers information on parameters such as size, alignment and
1110 * padding. arg_info should be large enought to hold param_count + 1 entries.
1112 * Returns the size of the argument area on the stack.
1115 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1118 CallInfo *cinfo = get_call_info (NULL, csig);
1119 guint32 args_size = cinfo->stack_usage;
1121 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1122 if (csig->hasthis) {
1123 arg_info [0].offset = 0;
1126 for (k = 0; k < param_count; k++) {
1127 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1129 arg_info [k + 1].size = 0;
1138 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1142 MonoType *callee_ret;
1144 c1 = get_call_info (NULL, caller_sig);
1145 c2 = get_call_info (NULL, callee_sig);
1146 res = c1->stack_usage >= c2->stack_usage;
1147 callee_ret = mini_get_underlying_type (callee_sig->ret);
1148 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1149 /* An address on the callee's stack is passed as the first argument */
1159 * Initialize the cpu to execute managed code.
1162 mono_arch_cpu_init (void)
1167 /* spec compliance requires running with double precision */
1168 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1169 fpcw &= ~X86_FPCW_PRECC_MASK;
1170 fpcw |= X86_FPCW_PREC_DOUBLE;
1171 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1172 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1174 /* TODO: This is crashing on Win64 right now.
1175 * _control87 (_PC_53, MCW_PC);
1181 * Initialize architecture specific code.
1184 mono_arch_init (void)
1186 mono_os_mutex_init_recursive (&mini_arch_mutex);
1188 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1189 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1190 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1191 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1192 mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1194 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1195 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1199 bp_trampoline = mini_get_breakpoint_trampoline ();
1203 * Cleanup architecture specific code.
1206 mono_arch_cleanup (void)
1208 mono_os_mutex_destroy (&mini_arch_mutex);
1212 * This function returns the optimizations supported on this cpu.
1215 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1221 if (mono_hwcap_x86_has_cmov) {
1222 opts |= MONO_OPT_CMOV;
1224 if (mono_hwcap_x86_has_fcmov)
1225 opts |= MONO_OPT_FCMOV;
1227 *exclude_mask |= MONO_OPT_FCMOV;
1229 *exclude_mask |= MONO_OPT_CMOV;
1233 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1234 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1235 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1236 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1237 /* will now have a reference to an argument that won't be fully decomposed. */
1238 *exclude_mask |= MONO_OPT_SIMD;
1245 * This function test for all SSE functions supported.
1247 * Returns a bitmask corresponding to all supported versions.
1251 mono_arch_cpu_enumerate_simd_versions (void)
1253 guint32 sse_opts = 0;
1255 if (mono_hwcap_x86_has_sse1)
1256 sse_opts |= SIMD_VERSION_SSE1;
1258 if (mono_hwcap_x86_has_sse2)
1259 sse_opts |= SIMD_VERSION_SSE2;
1261 if (mono_hwcap_x86_has_sse3)
1262 sse_opts |= SIMD_VERSION_SSE3;
1264 if (mono_hwcap_x86_has_ssse3)
1265 sse_opts |= SIMD_VERSION_SSSE3;
1267 if (mono_hwcap_x86_has_sse41)
1268 sse_opts |= SIMD_VERSION_SSE41;
1270 if (mono_hwcap_x86_has_sse42)
1271 sse_opts |= SIMD_VERSION_SSE42;
1273 if (mono_hwcap_x86_has_sse4a)
1274 sse_opts |= SIMD_VERSION_SSE4a;
1282 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1287 for (i = 0; i < cfg->num_varinfo; i++) {
1288 MonoInst *ins = cfg->varinfo [i];
1289 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1292 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1295 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1296 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1299 if (mono_is_regsize_var (ins->inst_vtype)) {
1300 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1301 g_assert (i == vmv->idx);
1302 vars = g_list_prepend (vars, vmv);
1306 vars = mono_varlist_sort (cfg, vars, 0);
1312 * mono_arch_compute_omit_fp:
1314 * Determine whenever the frame pointer can be eliminated.
1317 mono_arch_compute_omit_fp (MonoCompile *cfg)
1319 MonoMethodSignature *sig;
1320 MonoMethodHeader *header;
1324 if (cfg->arch.omit_fp_computed)
1327 header = cfg->header;
1329 sig = mono_method_signature (cfg->method);
1331 if (!cfg->arch.cinfo)
1332 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1333 cinfo = (CallInfo *)cfg->arch.cinfo;
1336 * FIXME: Remove some of the restrictions.
1338 cfg->arch.omit_fp = TRUE;
1339 cfg->arch.omit_fp_computed = TRUE;
1341 if (cfg->disable_omit_fp)
1342 cfg->arch.omit_fp = FALSE;
1344 if (!debug_omit_fp ())
1345 cfg->arch.omit_fp = FALSE;
1347 if (cfg->method->save_lmf)
1348 cfg->arch.omit_fp = FALSE;
1350 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1351 cfg->arch.omit_fp = FALSE;
1352 if (header->num_clauses)
1353 cfg->arch.omit_fp = FALSE;
1354 if (cfg->param_area)
1355 cfg->arch.omit_fp = FALSE;
1356 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1357 cfg->arch.omit_fp = FALSE;
1358 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1359 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1360 cfg->arch.omit_fp = FALSE;
1361 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1362 ArgInfo *ainfo = &cinfo->args [i];
1364 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1366 * The stack offset can only be determined when the frame
1369 cfg->arch.omit_fp = FALSE;
1374 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1375 MonoInst *ins = cfg->varinfo [i];
1378 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1383 mono_arch_get_global_int_regs (MonoCompile *cfg)
1387 mono_arch_compute_omit_fp (cfg);
1389 if (cfg->arch.omit_fp)
1390 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1392 /* We use the callee saved registers for global allocation */
1393 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1394 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1395 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1396 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1397 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1399 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1400 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1407 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1412 /* All XMM registers */
1413 for (i = 0; i < 16; ++i)
1414 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1420 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1422 static GList *r = NULL;
1427 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1428 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1429 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1430 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1431 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1432 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1434 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1435 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1436 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1437 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1438 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1439 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1440 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1441 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1443 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1450 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1453 static GList *r = NULL;
1458 for (i = 0; i < AMD64_XMM_NREG; ++i)
1459 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1461 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1468 * mono_arch_regalloc_cost:
1470 * Return the cost, in number of memory references, of the action of
1471 * allocating the variable VMV into a register during global register
1475 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1477 MonoInst *ins = cfg->varinfo [vmv->idx];
1479 if (cfg->method->save_lmf)
1480 /* The register is already saved */
1481 /* substract 1 for the invisible store in the prolog */
1482 return (ins->opcode == OP_ARG) ? 0 : 1;
1485 return (ins->opcode == OP_ARG) ? 1 : 2;
1489 * mono_arch_fill_argument_info:
1491 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1495 mono_arch_fill_argument_info (MonoCompile *cfg)
1498 MonoMethodSignature *sig;
1503 sig = mono_method_signature (cfg->method);
1505 cinfo = (CallInfo *)cfg->arch.cinfo;
1506 sig_ret = mini_get_underlying_type (sig->ret);
1509 * Contrary to mono_arch_allocate_vars (), the information should describe
1510 * where the arguments are at the beginning of the method, not where they can be
1511 * accessed during the execution of the method. The later makes no sense for the
1512 * global register allocator, since a variable can be in more than one location.
1514 switch (cinfo->ret.storage) {
1516 case ArgInFloatSSEReg:
1517 case ArgInDoubleSSEReg:
1518 cfg->ret->opcode = OP_REGVAR;
1519 cfg->ret->inst_c0 = cinfo->ret.reg;
1521 case ArgValuetypeInReg:
1522 cfg->ret->opcode = OP_REGOFFSET;
1523 cfg->ret->inst_basereg = -1;
1524 cfg->ret->inst_offset = -1;
1529 g_assert_not_reached ();
1532 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1533 ArgInfo *ainfo = &cinfo->args [i];
1535 ins = cfg->args [i];
1537 switch (ainfo->storage) {
1539 case ArgInFloatSSEReg:
1540 case ArgInDoubleSSEReg:
1541 ins->opcode = OP_REGVAR;
1542 ins->inst_c0 = ainfo->reg;
1545 ins->opcode = OP_REGOFFSET;
1546 ins->inst_basereg = -1;
1547 ins->inst_offset = -1;
1549 case ArgValuetypeInReg:
1551 ins->opcode = OP_NOP;
1554 g_assert_not_reached ();
1560 mono_arch_allocate_vars (MonoCompile *cfg)
1563 MonoMethodSignature *sig;
1566 guint32 locals_stack_size, locals_stack_align;
1570 sig = mono_method_signature (cfg->method);
1572 cinfo = (CallInfo *)cfg->arch.cinfo;
1573 sig_ret = mini_get_underlying_type (sig->ret);
1575 mono_arch_compute_omit_fp (cfg);
1578 * We use the ABI calling conventions for managed code as well.
1579 * Exception: valuetypes are only sometimes passed or returned in registers.
1583 * The stack looks like this:
1584 * <incoming arguments passed on the stack>
1586 * <lmf/caller saved registers>
1589 * <localloc area> -> grows dynamically
1593 if (cfg->arch.omit_fp) {
1594 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1595 cfg->frame_reg = AMD64_RSP;
1598 /* Locals are allocated backwards from %fp */
1599 cfg->frame_reg = AMD64_RBP;
1603 cfg->arch.saved_iregs = cfg->used_int_regs;
1604 if (cfg->method->save_lmf) {
1605 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1606 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1607 cfg->arch.saved_iregs |= iregs_to_save;
1610 if (cfg->arch.omit_fp)
1611 cfg->arch.reg_save_area_offset = offset;
1612 /* Reserve space for callee saved registers */
1613 for (i = 0; i < AMD64_NREG; ++i)
1614 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1615 offset += sizeof(mgreg_t);
1617 if (!cfg->arch.omit_fp)
1618 cfg->arch.reg_save_area_offset = -offset;
1620 if (sig_ret->type != MONO_TYPE_VOID) {
1621 switch (cinfo->ret.storage) {
1623 case ArgInFloatSSEReg:
1624 case ArgInDoubleSSEReg:
1625 cfg->ret->opcode = OP_REGVAR;
1626 cfg->ret->inst_c0 = cinfo->ret.reg;
1627 cfg->ret->dreg = cinfo->ret.reg;
1629 case ArgValuetypeAddrInIReg:
1630 case ArgGsharedvtVariableInReg:
1631 /* The register is volatile */
1632 cfg->vret_addr->opcode = OP_REGOFFSET;
1633 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1634 if (cfg->arch.omit_fp) {
1635 cfg->vret_addr->inst_offset = offset;
1639 cfg->vret_addr->inst_offset = -offset;
1641 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1642 printf ("vret_addr =");
1643 mono_print_ins (cfg->vret_addr);
1646 case ArgValuetypeInReg:
1647 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1648 cfg->ret->opcode = OP_REGOFFSET;
1649 cfg->ret->inst_basereg = cfg->frame_reg;
1650 if (cfg->arch.omit_fp) {
1651 cfg->ret->inst_offset = offset;
1652 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1654 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1655 cfg->ret->inst_offset = - offset;
1659 g_assert_not_reached ();
1663 /* Allocate locals */
1664 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1665 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1666 char *mname = mono_method_full_name (cfg->method, TRUE);
1667 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1672 if (locals_stack_align) {
1673 offset += (locals_stack_align - 1);
1674 offset &= ~(locals_stack_align - 1);
1676 if (cfg->arch.omit_fp) {
1677 cfg->locals_min_stack_offset = offset;
1678 cfg->locals_max_stack_offset = offset + locals_stack_size;
1680 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1681 cfg->locals_max_stack_offset = - offset;
1684 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1685 if (offsets [i] != -1) {
1686 MonoInst *ins = cfg->varinfo [i];
1687 ins->opcode = OP_REGOFFSET;
1688 ins->inst_basereg = cfg->frame_reg;
1689 if (cfg->arch.omit_fp)
1690 ins->inst_offset = (offset + offsets [i]);
1692 ins->inst_offset = - (offset + offsets [i]);
1693 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1696 offset += locals_stack_size;
1698 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1699 g_assert (!cfg->arch.omit_fp);
1700 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1701 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1704 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1705 ins = cfg->args [i];
1706 if (ins->opcode != OP_REGVAR) {
1707 ArgInfo *ainfo = &cinfo->args [i];
1708 gboolean inreg = TRUE;
1710 /* FIXME: Allocate volatile arguments to registers */
1711 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1715 * Under AMD64, all registers used to pass arguments to functions
1716 * are volatile across calls.
1717 * FIXME: Optimize this.
1719 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1722 ins->opcode = OP_REGOFFSET;
1724 switch (ainfo->storage) {
1726 case ArgInFloatSSEReg:
1727 case ArgInDoubleSSEReg:
1728 case ArgGSharedVtInReg:
1730 ins->opcode = OP_REGVAR;
1731 ins->dreg = ainfo->reg;
1735 case ArgGSharedVtOnStack:
1736 g_assert (!cfg->arch.omit_fp);
1737 ins->opcode = OP_REGOFFSET;
1738 ins->inst_basereg = cfg->frame_reg;
1739 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1741 case ArgValuetypeInReg:
1743 case ArgValuetypeAddrInIReg:
1744 case ArgValuetypeAddrOnStack: {
1746 g_assert (!cfg->arch.omit_fp);
1747 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1748 MONO_INST_NEW (cfg, indir, 0);
1750 indir->opcode = OP_REGOFFSET;
1751 if (ainfo->pair_storage [0] == ArgInIReg) {
1752 indir->inst_basereg = cfg->frame_reg;
1753 offset = ALIGN_TO (offset, sizeof (gpointer));
1754 offset += (sizeof (gpointer));
1755 indir->inst_offset = - offset;
1758 indir->inst_basereg = cfg->frame_reg;
1759 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1762 ins->opcode = OP_VTARG_ADDR;
1763 ins->inst_left = indir;
1771 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1772 ins->opcode = OP_REGOFFSET;
1773 ins->inst_basereg = cfg->frame_reg;
1774 /* These arguments are saved to the stack in the prolog */
1775 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1776 if (cfg->arch.omit_fp) {
1777 ins->inst_offset = offset;
1778 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1779 // Arguments are yet supported by the stack map creation code
1780 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1782 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1783 ins->inst_offset = - offset;
1784 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1790 cfg->stack_offset = offset;
1794 mono_arch_create_vars (MonoCompile *cfg)
1796 MonoMethodSignature *sig;
1800 sig = mono_method_signature (cfg->method);
1802 if (!cfg->arch.cinfo)
1803 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1804 cinfo = (CallInfo *)cfg->arch.cinfo;
1806 if (cinfo->ret.storage == ArgValuetypeInReg)
1807 cfg->ret_var_is_local = TRUE;
1809 sig_ret = mini_get_underlying_type (sig->ret);
1810 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1811 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1812 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1813 printf ("vret_addr = ");
1814 mono_print_ins (cfg->vret_addr);
1818 if (cfg->gen_sdb_seq_points) {
1821 if (cfg->compile_aot) {
1822 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1823 ins->flags |= MONO_INST_VOLATILE;
1824 cfg->arch.seq_point_info_var = ins;
1826 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1827 ins->flags |= MONO_INST_VOLATILE;
1828 cfg->arch.ss_tramp_var = ins;
1830 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1831 ins->flags |= MONO_INST_VOLATILE;
1832 cfg->arch.bp_tramp_var = ins;
1835 if (cfg->method->save_lmf)
1836 cfg->create_lmf_var = TRUE;
1838 if (cfg->method->save_lmf) {
1840 #if !defined(TARGET_WIN32)
1841 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1842 cfg->lmf_ir_mono_lmf = TRUE;
1848 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1854 MONO_INST_NEW (cfg, ins, OP_MOVE);
1855 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1856 ins->sreg1 = tree->dreg;
1857 MONO_ADD_INS (cfg->cbb, ins);
1858 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1860 case ArgInFloatSSEReg:
1861 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1862 ins->dreg = mono_alloc_freg (cfg);
1863 ins->sreg1 = tree->dreg;
1864 MONO_ADD_INS (cfg->cbb, ins);
1866 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1868 case ArgInDoubleSSEReg:
1869 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1870 ins->dreg = mono_alloc_freg (cfg);
1871 ins->sreg1 = tree->dreg;
1872 MONO_ADD_INS (cfg->cbb, ins);
1874 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1878 g_assert_not_reached ();
1883 arg_storage_to_load_membase (ArgStorage storage)
1887 #if defined(__mono_ilp32__)
1888 return OP_LOADI8_MEMBASE;
1890 return OP_LOAD_MEMBASE;
1892 case ArgInDoubleSSEReg:
1893 return OP_LOADR8_MEMBASE;
1894 case ArgInFloatSSEReg:
1895 return OP_LOADR4_MEMBASE;
1897 g_assert_not_reached ();
1904 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1906 MonoMethodSignature *tmp_sig;
1909 if (call->tail_call)
1912 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1915 * mono_ArgIterator_Setup assumes the signature cookie is
1916 * passed first and all the arguments which were before it are
1917 * passed on the stack after the signature. So compensate by
1918 * passing a different signature.
1920 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1921 tmp_sig->param_count -= call->signature->sentinelpos;
1922 tmp_sig->sentinelpos = 0;
1923 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1925 sig_reg = mono_alloc_ireg (cfg);
1926 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1928 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1932 static inline LLVMArgStorage
1933 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1937 return LLVMArgInIReg;
1940 case ArgGSharedVtInReg:
1941 case ArgGSharedVtOnStack:
1942 return LLVMArgGSharedVt;
1944 g_assert_not_reached ();
1950 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1956 LLVMCallInfo *linfo;
1957 MonoType *t, *sig_ret;
1959 n = sig->param_count + sig->hasthis;
1960 sig_ret = mini_get_underlying_type (sig->ret);
1962 cinfo = get_call_info (cfg->mempool, sig);
1964 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1967 * LLVM always uses the native ABI while we use our own ABI, the
1968 * only difference is the handling of vtypes:
1969 * - we only pass/receive them in registers in some cases, and only
1970 * in 1 or 2 integer registers.
1972 switch (cinfo->ret.storage) {
1974 linfo->ret.storage = LLVMArgNone;
1977 case ArgInFloatSSEReg:
1978 case ArgInDoubleSSEReg:
1979 linfo->ret.storage = LLVMArgNormal;
1981 case ArgValuetypeInReg: {
1982 ainfo = &cinfo->ret;
1985 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1986 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1987 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1988 cfg->disable_llvm = TRUE;
1992 linfo->ret.storage = LLVMArgVtypeInReg;
1993 for (j = 0; j < 2; ++j)
1994 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1997 case ArgValuetypeAddrInIReg:
1998 case ArgGsharedvtVariableInReg:
1999 /* Vtype returned using a hidden argument */
2000 linfo->ret.storage = LLVMArgVtypeRetAddr;
2001 linfo->vret_arg_index = cinfo->vret_arg_index;
2004 g_assert_not_reached ();
2008 for (i = 0; i < n; ++i) {
2009 ainfo = cinfo->args + i;
2011 if (i >= sig->hasthis)
2012 t = sig->params [i - sig->hasthis];
2014 t = &mono_defaults.int_class->byval_arg;
2015 t = mini_type_get_underlying_type (t);
2017 linfo->args [i].storage = LLVMArgNone;
2019 switch (ainfo->storage) {
2021 linfo->args [i].storage = LLVMArgNormal;
2023 case ArgInDoubleSSEReg:
2024 case ArgInFloatSSEReg:
2025 linfo->args [i].storage = LLVMArgNormal;
2028 if (MONO_TYPE_ISSTRUCT (t))
2029 linfo->args [i].storage = LLVMArgVtypeByVal;
2031 linfo->args [i].storage = LLVMArgNormal;
2033 case ArgValuetypeInReg:
2035 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2036 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2037 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2038 cfg->disable_llvm = TRUE;
2042 linfo->args [i].storage = LLVMArgVtypeInReg;
2043 for (j = 0; j < 2; ++j)
2044 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2046 case ArgGSharedVtInReg:
2047 case ArgGSharedVtOnStack:
2048 linfo->args [i].storage = LLVMArgGSharedVt;
2051 cfg->exception_message = g_strdup ("ainfo->storage");
2052 cfg->disable_llvm = TRUE;
2062 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2065 MonoMethodSignature *sig;
2071 sig = call->signature;
2072 n = sig->param_count + sig->hasthis;
2074 cinfo = get_call_info (cfg->mempool, sig);
2078 if (COMPILE_LLVM (cfg)) {
2079 /* We shouldn't be called in the llvm case */
2080 cfg->disable_llvm = TRUE;
2085 * Emit all arguments which are passed on the stack to prevent register
2086 * allocation problems.
2088 for (i = 0; i < n; ++i) {
2090 ainfo = cinfo->args + i;
2092 in = call->args [i];
2094 if (sig->hasthis && i == 0)
2095 t = &mono_defaults.object_class->byval_arg;
2097 t = sig->params [i - sig->hasthis];
2099 t = mini_get_underlying_type (t);
2100 //XXX what about ArgGSharedVtOnStack here?
2101 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2103 if (t->type == MONO_TYPE_R4)
2104 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2105 else if (t->type == MONO_TYPE_R8)
2106 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2108 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2110 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2112 if (cfg->compute_gc_maps) {
2115 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2121 * Emit all parameters passed in registers in non-reverse order for better readability
2122 * and to help the optimization in emit_prolog ().
2124 for (i = 0; i < n; ++i) {
2125 ainfo = cinfo->args + i;
2127 in = call->args [i];
2129 if (ainfo->storage == ArgInIReg)
2130 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2133 for (i = n - 1; i >= 0; --i) {
2136 ainfo = cinfo->args + i;
2138 in = call->args [i];
2140 if (sig->hasthis && i == 0)
2141 t = &mono_defaults.object_class->byval_arg;
2143 t = sig->params [i - sig->hasthis];
2144 t = mini_get_underlying_type (t);
2146 switch (ainfo->storage) {
2150 case ArgInFloatSSEReg:
2151 case ArgInDoubleSSEReg:
2152 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2155 case ArgValuetypeInReg:
2156 case ArgValuetypeAddrInIReg:
2157 case ArgValuetypeAddrOnStack:
2158 case ArgGSharedVtInReg:
2159 case ArgGSharedVtOnStack: {
2160 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2161 /* Already emitted above */
2163 //FIXME what about ArgGSharedVtOnStack ?
2164 if (ainfo->storage == ArgOnStack && call->tail_call) {
2165 MonoInst *call_inst = (MonoInst*)call;
2166 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2167 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2175 size = mono_type_native_stack_size (t, &align);
2178 * Other backends use mono_type_stack_size (), but that
2179 * aligns the size to 8, which is larger than the size of
2180 * the source, leading to reads of invalid memory if the
2181 * source is at the end of address space.
2183 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2186 if (size >= 10000) {
2187 /* Avoid asserts in emit_memcpy () */
2188 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2189 /* Continue normally */
2192 if (size > 0 || ainfo->pass_empty_struct) {
2193 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2194 arg->sreg1 = in->dreg;
2195 arg->klass = mono_class_from_mono_type (t);
2196 arg->backend.size = size;
2197 arg->inst_p0 = call;
2198 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2199 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2201 MONO_ADD_INS (cfg->cbb, arg);
2206 g_assert_not_reached ();
2209 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2210 /* Emit the signature cookie just before the implicit arguments */
2211 emit_sig_cookie (cfg, call, cinfo);
2214 /* Handle the case where there are no implicit arguments */
2215 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2216 emit_sig_cookie (cfg, call, cinfo);
2218 switch (cinfo->ret.storage) {
2219 case ArgValuetypeInReg:
2220 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2222 * Tell the JIT to use a more efficient calling convention: call using
2223 * OP_CALL, compute the result location after the call, and save the
2226 call->vret_in_reg = TRUE;
2228 * Nullify the instruction computing the vret addr to enable
2229 * future optimizations.
2232 NULLIFY_INS (call->vret_var);
2234 if (call->tail_call)
2237 * The valuetype is in RAX:RDX after the call, need to be copied to
2238 * the stack. Push the address here, so the call instruction can
2241 if (!cfg->arch.vret_addr_loc) {
2242 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2243 /* Prevent it from being register allocated or optimized away */
2244 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2247 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2250 case ArgValuetypeAddrInIReg:
2251 case ArgGsharedvtVariableInReg: {
2253 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2254 vtarg->sreg1 = call->vret_var->dreg;
2255 vtarg->dreg = mono_alloc_preg (cfg);
2256 MONO_ADD_INS (cfg->cbb, vtarg);
2258 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2265 if (cfg->method->save_lmf) {
2266 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2267 MONO_ADD_INS (cfg->cbb, arg);
2270 call->stack_usage = cinfo->stack_usage;
2274 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2277 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2278 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2279 int size = ins->backend.size;
2281 switch (ainfo->storage) {
2282 case ArgValuetypeInReg: {
2286 for (part = 0; part < 2; ++part) {
2287 if (ainfo->pair_storage [part] == ArgNone)
2290 if (ainfo->pass_empty_struct) {
2291 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2292 NEW_ICONST (cfg, load, 0);
2295 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2296 load->inst_basereg = src->dreg;
2297 load->inst_offset = part * sizeof(mgreg_t);
2299 switch (ainfo->pair_storage [part]) {
2301 load->dreg = mono_alloc_ireg (cfg);
2303 case ArgInDoubleSSEReg:
2304 case ArgInFloatSSEReg:
2305 load->dreg = mono_alloc_freg (cfg);
2308 g_assert_not_reached ();
2312 MONO_ADD_INS (cfg->cbb, load);
2314 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2318 case ArgValuetypeAddrInIReg:
2319 case ArgValuetypeAddrOnStack: {
2320 MonoInst *vtaddr, *load;
2322 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2324 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2326 MONO_INST_NEW (cfg, load, OP_LDADDR);
2327 cfg->has_indirection = TRUE;
2328 load->inst_p0 = vtaddr;
2329 vtaddr->flags |= MONO_INST_INDIRECT;
2330 load->type = STACK_MP;
2331 load->klass = vtaddr->klass;
2332 load->dreg = mono_alloc_ireg (cfg);
2333 MONO_ADD_INS (cfg->cbb, load);
2334 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2336 if (ainfo->pair_storage [0] == ArgInIReg) {
2337 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2338 arg->dreg = mono_alloc_ireg (cfg);
2339 arg->sreg1 = load->dreg;
2341 MONO_ADD_INS (cfg->cbb, arg);
2342 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2344 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2348 case ArgGSharedVtInReg:
2350 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2352 case ArgGSharedVtOnStack:
2353 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2357 int dreg = mono_alloc_ireg (cfg);
2359 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2360 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2361 } else if (size <= 40) {
2362 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2364 // FIXME: Code growth
2365 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2368 if (cfg->compute_gc_maps) {
2370 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2376 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2378 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2380 if (ret->type == MONO_TYPE_R4) {
2381 if (COMPILE_LLVM (cfg))
2382 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2384 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2386 } else if (ret->type == MONO_TYPE_R8) {
2387 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2391 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2394 #endif /* DISABLE_JIT */
2396 #define EMIT_COND_BRANCH(ins,cond,sign) \
2397 if (ins->inst_true_bb->native_offset) { \
2398 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2400 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2401 if ((cfg->opt & MONO_OPT_BRANCH) && \
2402 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2403 x86_branch8 (code, cond, 0, sign); \
2405 x86_branch32 (code, cond, 0, sign); \
2409 MonoMethodSignature *sig;
2414 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2418 switch (cinfo->ret.storage) {
2421 case ArgInFloatSSEReg:
2422 case ArgInDoubleSSEReg:
2423 case ArgValuetypeAddrInIReg:
2424 case ArgValuetypeInReg:
2430 for (i = 0; i < cinfo->nargs; ++i) {
2431 ArgInfo *ainfo = &cinfo->args [i];
2432 switch (ainfo->storage) {
2434 case ArgInFloatSSEReg:
2435 case ArgInDoubleSSEReg:
2436 case ArgValuetypeInReg:
2439 if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2451 * mono_arch_dyn_call_prepare:
2453 * Return a pointer to an arch-specific structure which contains information
2454 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2455 * supported for SIG.
2456 * This function is equivalent to ffi_prep_cif in libffi.
2459 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2461 ArchDynCallInfo *info;
2464 cinfo = get_call_info (NULL, sig);
2466 if (!dyn_call_supported (sig, cinfo)) {
2471 info = g_new0 (ArchDynCallInfo, 1);
2472 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2474 info->cinfo = cinfo;
2476 return (MonoDynCallInfo*)info;
2480 * mono_arch_dyn_call_free:
2482 * Free a MonoDynCallInfo structure.
2485 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2487 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2489 g_free (ainfo->cinfo);
2493 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2494 #define GREG_TO_PTR(greg) (gpointer)(greg)
2497 * mono_arch_get_start_dyn_call:
2499 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2500 * store the result into BUF.
2501 * ARGS should be an array of pointers pointing to the arguments.
2502 * RET should point to a memory buffer large enought to hold the result of the
2504 * This function should be as fast as possible, any work which does not depend
2505 * on the actual values of the arguments should be done in
2506 * mono_arch_dyn_call_prepare ().
2507 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2511 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2513 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2514 DynCallArgs *p = (DynCallArgs*)buf;
2515 int arg_index, greg, freg, i, pindex;
2516 MonoMethodSignature *sig = dinfo->sig;
2517 int buffer_offset = 0;
2518 static int param_reg_to_index [16];
2519 static gboolean param_reg_to_index_inited;
2521 if (!param_reg_to_index_inited) {
2522 for (i = 0; i < PARAM_REGS; ++i)
2523 param_reg_to_index [param_regs [i]] = i;
2524 mono_memory_barrier ();
2525 param_reg_to_index_inited = 1;
2528 g_assert (buf_len >= sizeof (DynCallArgs));
2538 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2539 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2544 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2545 p->regs [greg ++] = PTR_TO_GREG(ret);
2547 for (; pindex < sig->param_count; pindex++) {
2548 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2549 gpointer *arg = args [arg_index ++];
2550 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2553 if (ainfo->storage == ArgOnStack) {
2554 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2556 slot = param_reg_to_index [ainfo->reg];
2560 p->regs [slot] = PTR_TO_GREG(*(arg));
2566 case MONO_TYPE_STRING:
2567 case MONO_TYPE_CLASS:
2568 case MONO_TYPE_ARRAY:
2569 case MONO_TYPE_SZARRAY:
2570 case MONO_TYPE_OBJECT:
2574 #if !defined(__mono_ilp32__)
2578 p->regs [slot] = PTR_TO_GREG(*(arg));
2580 #if defined(__mono_ilp32__)
2583 p->regs [slot] = *(guint64*)(arg);
2587 p->regs [slot] = *(guint8*)(arg);
2590 p->regs [slot] = *(gint8*)(arg);
2593 p->regs [slot] = *(gint16*)(arg);
2596 p->regs [slot] = *(guint16*)(arg);
2599 p->regs [slot] = *(gint32*)(arg);
2602 p->regs [slot] = *(guint32*)(arg);
2604 case MONO_TYPE_R4: {
2607 *(float*)&d = *(float*)(arg);
2609 p->fregs [freg ++] = d;
2614 p->fregs [freg ++] = *(double*)(arg);
2616 case MONO_TYPE_GENERICINST:
2617 if (MONO_TYPE_IS_REFERENCE (t)) {
2618 p->regs [slot] = PTR_TO_GREG(*(arg));
2620 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2621 MonoClass *klass = mono_class_from_mono_type (t);
2622 guint8 *nullable_buf;
2625 size = mono_class_value_size (klass, NULL);
2626 nullable_buf = p->buffer + buffer_offset;
2627 buffer_offset += size;
2628 g_assert (buffer_offset <= 256);
2630 /* The argument pointed to by arg is either a boxed vtype or null */
2631 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2633 arg = (gpointer*)nullable_buf;
2639 case MONO_TYPE_VALUETYPE: {
2640 switch (ainfo->storage) {
2641 case ArgValuetypeInReg:
2642 for (i = 0; i < 2; ++i) {
2643 switch (ainfo->pair_storage [i]) {
2647 slot = param_reg_to_index [ainfo->pair_regs [i]];
2648 p->regs [slot] = ((mgreg_t*)(arg))[i];
2650 case ArgInDoubleSSEReg:
2652 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2655 g_assert_not_reached ();
2661 for (i = 0; i < ainfo->arg_size / 8; ++i)
2662 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2665 g_assert_not_reached ();
2671 g_assert_not_reached ();
2677 * mono_arch_finish_dyn_call:
2679 * Store the result of a dyn call into the return value buffer passed to
2680 * start_dyn_call ().
2681 * This function should be as fast as possible, any work which does not depend
2682 * on the actual values of the arguments should be done in
2683 * mono_arch_dyn_call_prepare ().
2686 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2688 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2689 MonoMethodSignature *sig = dinfo->sig;
2690 DynCallArgs *dargs = (DynCallArgs*)buf;
2691 guint8 *ret = dargs->ret;
2692 mgreg_t res = dargs->res;
2693 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2696 switch (sig_ret->type) {
2697 case MONO_TYPE_VOID:
2698 *(gpointer*)ret = NULL;
2700 case MONO_TYPE_STRING:
2701 case MONO_TYPE_CLASS:
2702 case MONO_TYPE_ARRAY:
2703 case MONO_TYPE_SZARRAY:
2704 case MONO_TYPE_OBJECT:
2708 *(gpointer*)ret = GREG_TO_PTR(res);
2714 *(guint8*)ret = res;
2717 *(gint16*)ret = res;
2720 *(guint16*)ret = res;
2723 *(gint32*)ret = res;
2726 *(guint32*)ret = res;
2729 *(gint64*)ret = res;
2732 *(guint64*)ret = res;
2735 *(float*)ret = *(float*)&(dargs->fregs [0]);
2738 *(double*)ret = dargs->fregs [0];
2740 case MONO_TYPE_GENERICINST:
2741 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2742 *(gpointer*)ret = GREG_TO_PTR(res);
2747 case MONO_TYPE_VALUETYPE:
2748 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2751 ArgInfo *ainfo = &dinfo->cinfo->ret;
2753 g_assert (ainfo->storage == ArgValuetypeInReg);
2755 for (i = 0; i < 2; ++i) {
2756 switch (ainfo->pair_storage [0]) {
2758 ((mgreg_t*)ret)[i] = res;
2760 case ArgInDoubleSSEReg:
2761 ((double*)ret)[i] = dargs->fregs [i];
2766 g_assert_not_reached ();
2773 g_assert_not_reached ();
2777 /* emit an exception if condition is fail */
2778 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2780 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2781 if (tins == NULL) { \
2782 mono_add_patch_info (cfg, code - cfg->native_code, \
2783 MONO_PATCH_INFO_EXC, exc_name); \
2784 x86_branch32 (code, cond, 0, signed); \
2786 EMIT_COND_BRANCH (tins, cond, signed); \
2790 #define EMIT_FPCOMPARE(code) do { \
2791 amd64_fcompp (code); \
2792 amd64_fnstsw (code); \
2795 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2796 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2797 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2798 amd64_ ##op (code); \
2799 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2800 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2804 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2806 gboolean no_patch = FALSE;
2809 * FIXME: Add support for thunks
2812 gboolean near_call = FALSE;
2815 * Indirect calls are expensive so try to make a near call if possible.
2816 * The caller memory is allocated by the code manager so it is
2817 * guaranteed to be at a 32 bit offset.
2820 if (patch_type != MONO_PATCH_INFO_ABS) {
2821 /* The target is in memory allocated using the code manager */
2824 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2825 if (((MonoMethod*)data)->klass->image->aot_module)
2826 /* The callee might be an AOT method */
2828 if (((MonoMethod*)data)->dynamic)
2829 /* The target is in malloc-ed memory */
2833 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2835 * The call might go directly to a native function without
2838 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2840 gconstpointer target = mono_icall_get_wrapper (mi);
2841 if ((((guint64)target) >> 32) != 0)
2847 MonoJumpInfo *jinfo = NULL;
2849 if (cfg->abs_patches)
2850 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2852 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2853 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2854 if (mi && (((guint64)mi->func) >> 32) == 0)
2859 * This is not really an optimization, but required because the
2860 * generic class init trampolines use R11 to pass the vtable.
2865 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2867 if (info->func == info->wrapper) {
2869 if ((((guint64)info->func) >> 32) == 0)
2873 /* See the comment in mono_codegen () */
2874 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2878 else if ((((guint64)data) >> 32) == 0) {
2885 if (cfg->method->dynamic)
2886 /* These methods are allocated using malloc */
2889 #ifdef MONO_ARCH_NOMAP32BIT
2892 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2893 if (optimize_for_xen)
2896 if (cfg->compile_aot) {
2903 * Align the call displacement to an address divisible by 4 so it does
2904 * not span cache lines. This is required for code patching to work on SMP
2907 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2908 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2909 amd64_padding (code, pad_size);
2911 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2912 amd64_call_code (code, 0);
2915 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2916 amd64_set_reg_template (code, GP_SCRATCH_REG);
2917 amd64_call_reg (code, GP_SCRATCH_REG);
2924 static inline guint8*
2925 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2928 if (win64_adjust_stack)
2929 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2931 code = emit_call_body (cfg, code, patch_type, data);
2933 if (win64_adjust_stack)
2934 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2941 store_membase_imm_to_store_membase_reg (int opcode)
2944 case OP_STORE_MEMBASE_IMM:
2945 return OP_STORE_MEMBASE_REG;
2946 case OP_STOREI4_MEMBASE_IMM:
2947 return OP_STOREI4_MEMBASE_REG;
2948 case OP_STOREI8_MEMBASE_IMM:
2949 return OP_STOREI8_MEMBASE_REG;
2957 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2960 * mono_arch_peephole_pass_1:
2962 * Perform peephole opts which should/can be performed before local regalloc
2965 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2969 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2970 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2972 switch (ins->opcode) {
2976 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2978 * X86_LEA is like ADD, but doesn't have the
2979 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2980 * its operand to 64 bit.
2982 ins->opcode = OP_X86_LEA_MEMBASE;
2983 ins->inst_basereg = ins->sreg1;
2988 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2992 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2993 * the latter has length 2-3 instead of 6 (reverse constant
2994 * propagation). These instruction sequences are very common
2995 * in the initlocals bblock.
2997 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2998 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2999 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3000 ins2->sreg1 = ins->dreg;
3001 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3003 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3006 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3014 case OP_COMPARE_IMM:
3015 case OP_LCOMPARE_IMM:
3016 /* OP_COMPARE_IMM (reg, 0)
3018 * OP_AMD64_TEST_NULL (reg)
3021 ins->opcode = OP_AMD64_TEST_NULL;
3023 case OP_ICOMPARE_IMM:
3025 ins->opcode = OP_X86_TEST_NULL;
3027 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3029 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3030 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3032 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3033 * OP_COMPARE_IMM reg, imm
3035 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3037 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3038 ins->inst_basereg == last_ins->inst_destbasereg &&
3039 ins->inst_offset == last_ins->inst_offset) {
3040 ins->opcode = OP_ICOMPARE_IMM;
3041 ins->sreg1 = last_ins->sreg1;
3043 /* check if we can remove cmp reg,0 with test null */
3045 ins->opcode = OP_X86_TEST_NULL;
3051 mono_peephole_ins (bb, ins);
3056 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3060 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3061 switch (ins->opcode) {
3064 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3065 /* reg = 0 -> XOR (reg, reg) */
3066 /* XOR sets cflags on x86, so we cant do it always */
3067 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3068 ins->opcode = OP_LXOR;
3069 ins->sreg1 = ins->dreg;
3070 ins->sreg2 = ins->dreg;
3078 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3079 * 0 result into 64 bits.
3081 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3082 ins->opcode = OP_IXOR;
3086 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3090 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3091 * the latter has length 2-3 instead of 6 (reverse constant
3092 * propagation). These instruction sequences are very common
3093 * in the initlocals bblock.
3095 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3096 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3097 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3098 ins2->sreg1 = ins->dreg;
3099 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3101 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3104 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3113 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3114 ins->opcode = OP_X86_INC_REG;
3117 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3118 ins->opcode = OP_X86_DEC_REG;
3122 mono_peephole_ins (bb, ins);
3126 #define NEW_INS(cfg,ins,dest,op) do { \
3127 MONO_INST_NEW ((cfg), (dest), (op)); \
3128 (dest)->cil_code = (ins)->cil_code; \
3129 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3133 * mono_arch_lowering_pass:
3135 * Converts complex opcodes into simpler ones so that each IR instruction
3136 * corresponds to one machine instruction.
3139 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3141 MonoInst *ins, *n, *temp;
3144 * FIXME: Need to add more instructions, but the current machine
3145 * description can't model some parts of the composite instructions like
3148 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3149 switch (ins->opcode) {
3153 case OP_IDIV_UN_IMM:
3154 case OP_IREM_UN_IMM:
3157 mono_decompose_op_imm (cfg, bb, ins);
3159 case OP_COMPARE_IMM:
3160 case OP_LCOMPARE_IMM:
3161 if (!amd64_use_imm32 (ins->inst_imm)) {
3162 NEW_INS (cfg, ins, temp, OP_I8CONST);
3163 temp->inst_c0 = ins->inst_imm;
3164 temp->dreg = mono_alloc_ireg (cfg);
3165 ins->opcode = OP_COMPARE;
3166 ins->sreg2 = temp->dreg;
3169 #ifndef __mono_ilp32__
3170 case OP_LOAD_MEMBASE:
3172 case OP_LOADI8_MEMBASE:
3173 /* Don't generate memindex opcodes (to simplify */
3174 /* read sandboxing) */
3175 if (!amd64_use_imm32 (ins->inst_offset)) {
3176 NEW_INS (cfg, ins, temp, OP_I8CONST);
3177 temp->inst_c0 = ins->inst_offset;
3178 temp->dreg = mono_alloc_ireg (cfg);
3179 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3180 ins->inst_indexreg = temp->dreg;
3183 #ifndef __mono_ilp32__
3184 case OP_STORE_MEMBASE_IMM:
3186 case OP_STOREI8_MEMBASE_IMM:
3187 if (!amd64_use_imm32 (ins->inst_imm)) {
3188 NEW_INS (cfg, ins, temp, OP_I8CONST);
3189 temp->inst_c0 = ins->inst_imm;
3190 temp->dreg = mono_alloc_ireg (cfg);
3191 ins->opcode = OP_STOREI8_MEMBASE_REG;
3192 ins->sreg1 = temp->dreg;
3195 #ifdef MONO_ARCH_SIMD_INTRINSICS
3196 case OP_EXPAND_I1: {
3197 int temp_reg1 = mono_alloc_ireg (cfg);
3198 int temp_reg2 = mono_alloc_ireg (cfg);
3199 int original_reg = ins->sreg1;
3201 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3202 temp->sreg1 = original_reg;
3203 temp->dreg = temp_reg1;
3205 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3206 temp->sreg1 = temp_reg1;
3207 temp->dreg = temp_reg2;
3210 NEW_INS (cfg, ins, temp, OP_LOR);
3211 temp->sreg1 = temp->dreg = temp_reg2;
3212 temp->sreg2 = temp_reg1;
3214 ins->opcode = OP_EXPAND_I2;
3215 ins->sreg1 = temp_reg2;
3224 bb->max_vreg = cfg->next_vreg;
3228 branch_cc_table [] = {
3229 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3230 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3231 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3234 /* Maps CMP_... constants to X86_CC_... constants */
3237 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3238 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3242 cc_signed_table [] = {
3243 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3244 FALSE, FALSE, FALSE, FALSE
3247 /*#include "cprop.c"*/
3249 static unsigned char*
3250 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3253 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3255 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3258 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3260 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3264 static unsigned char*
3265 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3267 int sreg = tree->sreg1;
3268 int need_touch = FALSE;
3270 #if defined(TARGET_WIN32)
3272 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3273 if (!tree->flags & MONO_INST_INIT)
3282 * If requested stack size is larger than one page,
3283 * perform stack-touch operation
3286 * Generate stack probe code.
3287 * Under Windows, it is necessary to allocate one page at a time,
3288 * "touching" stack after each successful sub-allocation. This is
3289 * because of the way stack growth is implemented - there is a
3290 * guard page before the lowest stack page that is currently commited.
3291 * Stack normally grows sequentially so OS traps access to the
3292 * guard page and commits more pages when needed.
3294 amd64_test_reg_imm (code, sreg, ~0xFFF);
3295 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3297 br[2] = code; /* loop */
3298 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3299 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3300 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3301 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3302 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3303 amd64_patch (br[3], br[2]);
3304 amd64_test_reg_reg (code, sreg, sreg);
3305 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3306 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3308 br[1] = code; x86_jump8 (code, 0);
3310 amd64_patch (br[0], code);
3311 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3312 amd64_patch (br[1], code);
3313 amd64_patch (br[4], code);
3316 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3318 if (tree->flags & MONO_INST_INIT) {
3320 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3321 amd64_push_reg (code, AMD64_RAX);
3324 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3325 amd64_push_reg (code, AMD64_RCX);
3328 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3329 amd64_push_reg (code, AMD64_RDI);
3333 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3334 if (sreg != AMD64_RCX)
3335 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3336 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3338 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3339 if (cfg->param_area)
3340 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3342 amd64_prefix (code, X86_REP_PREFIX);
3345 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3346 amd64_pop_reg (code, AMD64_RDI);
3347 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3348 amd64_pop_reg (code, AMD64_RCX);
3349 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3350 amd64_pop_reg (code, AMD64_RAX);
3356 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3361 /* Move return value to the target register */
3362 /* FIXME: do this in the local reg allocator */
3363 switch (ins->opcode) {
3366 case OP_CALL_MEMBASE:
3369 case OP_LCALL_MEMBASE:
3370 g_assert (ins->dreg == AMD64_RAX);
3374 case OP_FCALL_MEMBASE: {
3375 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3376 if (rtype->type == MONO_TYPE_R4) {
3377 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3380 if (ins->dreg != AMD64_XMM0)
3381 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3387 case OP_RCALL_MEMBASE:
3388 if (ins->dreg != AMD64_XMM0)
3389 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3393 case OP_VCALL_MEMBASE:
3396 case OP_VCALL2_MEMBASE:
3397 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3398 if (cinfo->ret.storage == ArgValuetypeInReg) {
3399 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3401 /* Load the destination address */
3402 g_assert (loc->opcode == OP_REGOFFSET);
3403 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3405 for (quad = 0; quad < 2; quad ++) {
3406 switch (cinfo->ret.pair_storage [quad]) {
3408 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3410 case ArgInFloatSSEReg:
3411 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3413 case ArgInDoubleSSEReg:
3414 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3429 #endif /* DISABLE_JIT */
3432 static int tls_gs_offset;
3436 mono_amd64_have_tls_get (void)
3439 static gboolean have_tls_get = FALSE;
3440 static gboolean inited = FALSE;
3443 return have_tls_get;
3445 #if MONO_HAVE_FAST_TLS
3446 guint8 *ins = (guint8*)pthread_getspecific;
3449 * We're looking for these two instructions:
3451 * mov %gs:[offset](,%rdi,8),%rax
3454 have_tls_get = ins [0] == 0x65 &&
3464 tls_gs_offset = ins[5];
3467 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3468 * For that version we're looking for these instructions:
3472 * mov %gs:[offset](,%rdi,8),%rax
3476 if (!have_tls_get) {
3477 have_tls_get = ins [0] == 0x55 &&
3492 tls_gs_offset = ins[9];
3498 return have_tls_get;
3499 #elif defined(TARGET_ANDROID)
3507 mono_amd64_get_tls_gs_offset (void)
3510 return tls_gs_offset;
3512 g_assert_not_reached ();
3518 * mono_amd64_emit_tls_get:
3519 * @code: buffer to store code to
3520 * @dreg: hard register where to place the result
3521 * @tls_offset: offset info
3523 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3524 * the dreg register the item in the thread local storage identified
3527 * Returns: a pointer to the end of the stored code
3530 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3533 if (tls_offset < 64) {
3534 x86_prefix (code, X86_GS_PREFIX);
3535 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3539 g_assert (tls_offset < 0x440);
3540 /* Load TEB->TlsExpansionSlots */
3541 x86_prefix (code, X86_GS_PREFIX);
3542 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3543 amd64_test_reg_reg (code, dreg, dreg);
3545 amd64_branch (code, X86_CC_EQ, code, TRUE);
3546 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3547 amd64_patch (buf [0], code);
3549 #elif defined(__APPLE__)
3550 x86_prefix (code, X86_GS_PREFIX);
3551 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3553 if (optimize_for_xen) {
3554 x86_prefix (code, X86_FS_PREFIX);
3555 amd64_mov_reg_mem (code, dreg, 0, 8);
3556 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3558 x86_prefix (code, X86_FS_PREFIX);
3559 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3567 #define MAX_TEB_TLS_SLOTS 64
3568 #define TEB_TLS_SLOTS_OFFSET 0x1480
3569 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3572 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3575 guint8 * more_than_64_slots = NULL;
3576 guint8 * empty_slot = NULL;
3577 guint8 * tls_get_reg_done = NULL;
3579 //Use temporary register for offset calculation?
3580 if (dreg == offset_reg) {
3581 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3582 amd64_push_reg (code, tmp_reg);
3583 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3584 offset_reg = tmp_reg;
3587 //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3588 amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3589 more_than_64_slots = code;
3590 amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3592 //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3593 amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3594 amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3596 //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3597 x86_prefix (code, X86_GS_PREFIX);
3598 amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3600 tls_get_reg_done = code;
3601 amd64_jump8 (code, 0);
3603 amd64_patch (more_than_64_slots, code);
3605 //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3606 x86_prefix (code, X86_GS_PREFIX);
3607 amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3609 //Check for NULL in _TEB.TlsExpansionSlots.
3610 amd64_test_reg_reg (code, dreg, dreg);
3612 amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3614 //TLS expansion slots are at index offset into the expansion array.
3615 //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3616 amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3617 amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3619 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3621 amd64_patch (empty_slot, code);
3622 amd64_patch (tls_get_reg_done, code);
3625 amd64_pop_reg (code, tmp_reg);
3633 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3635 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3637 if (dreg != offset_reg)
3638 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3639 amd64_prefix (code, X86_GS_PREFIX);
3640 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3641 #elif defined(__linux__)
3644 if (dreg == offset_reg) {
3645 /* Use a temporary reg by saving it to the redzone */
3646 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3647 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3648 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3649 offset_reg = tmpreg;
3651 x86_prefix (code, X86_FS_PREFIX);
3652 amd64_mov_reg_mem (code, dreg, 0, 8);
3653 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3655 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3656 #elif defined(TARGET_WIN32)
3657 code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3659 g_assert_not_reached ();
3665 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3668 g_assert_not_reached ();
3669 #elif defined(__APPLE__)
3670 x86_prefix (code, X86_GS_PREFIX);
3671 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3673 g_assert (!optimize_for_xen);
3674 x86_prefix (code, X86_FS_PREFIX);
3675 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3681 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3683 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3685 g_assert_not_reached ();
3686 #elif defined(__APPLE__)
3687 x86_prefix (code, X86_GS_PREFIX);
3688 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3690 x86_prefix (code, X86_FS_PREFIX);
3691 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3697 * mono_arch_translate_tls_offset:
3699 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3702 mono_arch_translate_tls_offset (int offset)
3705 return tls_gs_offset + (offset * 8);
3714 * Emit code to initialize an LMF structure at LMF_OFFSET.
3717 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3720 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3723 * sp is saved right before calls but we need to save it here too so
3724 * async stack walks would work.
3726 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3728 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3729 if (cfg->arch.omit_fp && cfa_offset != -1)
3730 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3732 /* These can't contain refs */
3733 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3734 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3735 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3736 /* These are handled automatically by the stack marking code */
3737 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3744 #define TEB_LAST_ERROR_OFFSET 0x068
3747 emit_get_last_error (guint8* code, int dreg)
3749 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3750 x86_prefix (code, X86_GS_PREFIX);
3751 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3759 emit_get_last_error (guint8* code, int dreg)
3761 g_assert_not_reached ();
3766 /* benchmark and set based on cpu */
3767 #define LOOP_ALIGNMENT 8
3768 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3772 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3777 guint8 *code = cfg->native_code + cfg->code_len;
3780 /* Fix max_offset estimate for each successor bb */
3781 if (cfg->opt & MONO_OPT_BRANCH) {
3782 int current_offset = cfg->code_len;
3783 MonoBasicBlock *current_bb;
3784 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3785 current_bb->max_offset = current_offset;
3786 current_offset += current_bb->max_length;
3790 if (cfg->opt & MONO_OPT_LOOP) {
3791 int pad, align = LOOP_ALIGNMENT;
3792 /* set alignment depending on cpu */
3793 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3795 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3796 amd64_padding (code, pad);
3797 cfg->code_len += pad;
3798 bb->native_offset = cfg->code_len;
3802 if (cfg->verbose_level > 2)
3803 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3805 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3806 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3807 g_assert (!cfg->compile_aot);
3809 cov->data [bb->dfn].cil_code = bb->cil_code;
3810 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3811 /* this is not thread save, but good enough */
3812 amd64_inc_membase (code, AMD64_R11, 0);
3815 offset = code - cfg->native_code;
3817 mono_debug_open_block (cfg, bb, offset);
3819 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3820 x86_breakpoint (code);
3822 MONO_BB_FOR_EACH_INS (bb, ins) {
3823 offset = code - cfg->native_code;
3825 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3827 #define EXTRA_CODE_SPACE (16)
3829 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3830 cfg->code_size *= 2;
3831 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3832 code = cfg->native_code + offset;
3833 cfg->stat_code_reallocs++;
3836 if (cfg->debug_info)
3837 mono_debug_record_line_number (cfg, ins, offset);
3839 switch (ins->opcode) {
3841 amd64_mul_reg (code, ins->sreg2, TRUE);
3844 amd64_mul_reg (code, ins->sreg2, FALSE);
3846 case OP_X86_SETEQ_MEMBASE:
3847 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3849 case OP_STOREI1_MEMBASE_IMM:
3850 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3852 case OP_STOREI2_MEMBASE_IMM:
3853 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3855 case OP_STOREI4_MEMBASE_IMM:
3856 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3858 case OP_STOREI1_MEMBASE_REG:
3859 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3861 case OP_STOREI2_MEMBASE_REG:
3862 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3864 /* In AMD64 NaCl, pointers are 4 bytes, */
3865 /* so STORE_* != STOREI8_*. Likewise below. */
3866 case OP_STORE_MEMBASE_REG:
3867 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3869 case OP_STOREI8_MEMBASE_REG:
3870 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3872 case OP_STOREI4_MEMBASE_REG:
3873 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3875 case OP_STORE_MEMBASE_IMM:
3876 /* In NaCl, this could be a PCONST type, which could */
3877 /* mean a pointer type was copied directly into the */
3878 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3879 /* the value would be 0x00000000FFFFFFFF which is */
3880 /* not proper for an imm32 unless you cast it. */
3881 g_assert (amd64_is_imm32 (ins->inst_imm));
3882 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3884 case OP_STOREI8_MEMBASE_IMM:
3885 g_assert (amd64_is_imm32 (ins->inst_imm));
3886 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3889 #ifdef __mono_ilp32__
3890 /* In ILP32, pointers are 4 bytes, so separate these */
3891 /* cases, use literal 8 below where we really want 8 */
3892 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3893 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3897 // FIXME: Decompose this earlier
3898 if (amd64_use_imm32 (ins->inst_imm))
3899 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3901 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3902 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3906 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3907 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3910 // FIXME: Decompose this earlier
3911 if (amd64_use_imm32 (ins->inst_imm))
3912 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3914 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3915 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3919 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3920 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3923 /* For NaCl, pointers are 4 bytes, so separate these */
3924 /* cases, use literal 8 below where we really want 8 */
3925 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3926 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3928 case OP_LOAD_MEMBASE:
3929 g_assert (amd64_is_imm32 (ins->inst_offset));
3930 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3932 case OP_LOADI8_MEMBASE:
3933 /* Use literal 8 instead of sizeof pointer or */
3934 /* register, we really want 8 for this opcode */
3935 g_assert (amd64_is_imm32 (ins->inst_offset));
3936 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3938 case OP_LOADI4_MEMBASE:
3939 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3941 case OP_LOADU4_MEMBASE:
3942 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3944 case OP_LOADU1_MEMBASE:
3945 /* The cpu zero extends the result into 64 bits */
3946 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3948 case OP_LOADI1_MEMBASE:
3949 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3951 case OP_LOADU2_MEMBASE:
3952 /* The cpu zero extends the result into 64 bits */
3953 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3955 case OP_LOADI2_MEMBASE:
3956 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3958 case OP_AMD64_LOADI8_MEMINDEX:
3959 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3961 case OP_LCONV_TO_I1:
3962 case OP_ICONV_TO_I1:
3964 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3966 case OP_LCONV_TO_I2:
3967 case OP_ICONV_TO_I2:
3969 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3971 case OP_LCONV_TO_U1:
3972 case OP_ICONV_TO_U1:
3973 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3975 case OP_LCONV_TO_U2:
3976 case OP_ICONV_TO_U2:
3977 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3980 /* Clean out the upper word */
3981 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3984 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3988 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3990 case OP_COMPARE_IMM:
3991 #if defined(__mono_ilp32__)
3992 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3993 g_assert (amd64_is_imm32 (ins->inst_imm));
3994 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3997 case OP_LCOMPARE_IMM:
3998 g_assert (amd64_is_imm32 (ins->inst_imm));
3999 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4001 case OP_X86_COMPARE_REG_MEMBASE:
4002 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4004 case OP_X86_TEST_NULL:
4005 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4007 case OP_AMD64_TEST_NULL:
4008 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4011 case OP_X86_ADD_REG_MEMBASE:
4012 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4014 case OP_X86_SUB_REG_MEMBASE:
4015 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4017 case OP_X86_AND_REG_MEMBASE:
4018 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4020 case OP_X86_OR_REG_MEMBASE:
4021 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4023 case OP_X86_XOR_REG_MEMBASE:
4024 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4027 case OP_X86_ADD_MEMBASE_IMM:
4028 /* FIXME: Make a 64 version too */
4029 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4031 case OP_X86_SUB_MEMBASE_IMM:
4032 g_assert (amd64_is_imm32 (ins->inst_imm));
4033 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4035 case OP_X86_AND_MEMBASE_IMM:
4036 g_assert (amd64_is_imm32 (ins->inst_imm));
4037 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4039 case OP_X86_OR_MEMBASE_IMM:
4040 g_assert (amd64_is_imm32 (ins->inst_imm));
4041 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4043 case OP_X86_XOR_MEMBASE_IMM:
4044 g_assert (amd64_is_imm32 (ins->inst_imm));
4045 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4047 case OP_X86_ADD_MEMBASE_REG:
4048 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4050 case OP_X86_SUB_MEMBASE_REG:
4051 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4053 case OP_X86_AND_MEMBASE_REG:
4054 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4056 case OP_X86_OR_MEMBASE_REG:
4057 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4059 case OP_X86_XOR_MEMBASE_REG:
4060 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4062 case OP_X86_INC_MEMBASE:
4063 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4065 case OP_X86_INC_REG:
4066 amd64_inc_reg_size (code, ins->dreg, 4);
4068 case OP_X86_DEC_MEMBASE:
4069 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4071 case OP_X86_DEC_REG:
4072 amd64_dec_reg_size (code, ins->dreg, 4);
4074 case OP_X86_MUL_REG_MEMBASE:
4075 case OP_X86_MUL_MEMBASE_REG:
4076 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4078 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4079 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4081 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4082 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4084 case OP_AMD64_COMPARE_MEMBASE_REG:
4085 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4087 case OP_AMD64_COMPARE_MEMBASE_IMM:
4088 g_assert (amd64_is_imm32 (ins->inst_imm));
4089 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4091 case OP_X86_COMPARE_MEMBASE8_IMM:
4092 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4094 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4095 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4097 case OP_AMD64_COMPARE_REG_MEMBASE:
4098 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4101 case OP_AMD64_ADD_REG_MEMBASE:
4102 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4104 case OP_AMD64_SUB_REG_MEMBASE:
4105 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4107 case OP_AMD64_AND_REG_MEMBASE:
4108 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4110 case OP_AMD64_OR_REG_MEMBASE:
4111 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4113 case OP_AMD64_XOR_REG_MEMBASE:
4114 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4117 case OP_AMD64_ADD_MEMBASE_REG:
4118 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4120 case OP_AMD64_SUB_MEMBASE_REG:
4121 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4123 case OP_AMD64_AND_MEMBASE_REG:
4124 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4126 case OP_AMD64_OR_MEMBASE_REG:
4127 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4129 case OP_AMD64_XOR_MEMBASE_REG:
4130 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4133 case OP_AMD64_ADD_MEMBASE_IMM:
4134 g_assert (amd64_is_imm32 (ins->inst_imm));
4135 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4137 case OP_AMD64_SUB_MEMBASE_IMM:
4138 g_assert (amd64_is_imm32 (ins->inst_imm));
4139 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4141 case OP_AMD64_AND_MEMBASE_IMM:
4142 g_assert (amd64_is_imm32 (ins->inst_imm));
4143 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4145 case OP_AMD64_OR_MEMBASE_IMM:
4146 g_assert (amd64_is_imm32 (ins->inst_imm));
4147 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4149 case OP_AMD64_XOR_MEMBASE_IMM:
4150 g_assert (amd64_is_imm32 (ins->inst_imm));
4151 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4155 amd64_breakpoint (code);
4157 case OP_RELAXED_NOP:
4158 x86_prefix (code, X86_REP_PREFIX);
4166 case OP_DUMMY_STORE:
4167 case OP_DUMMY_ICONST:
4168 case OP_DUMMY_R8CONST:
4169 case OP_NOT_REACHED:
4172 case OP_IL_SEQ_POINT:
4173 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4175 case OP_SEQ_POINT: {
4176 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4177 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4180 /* Load ss_tramp_var */
4181 /* This is equal to &ss_trampoline */
4182 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4183 /* Load the trampoline address */
4184 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4185 /* Call it if it is non-null */
4186 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4188 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4189 amd64_call_reg (code, AMD64_R11);
4190 amd64_patch (label, code);
4194 * This is the address which is saved in seq points,
4196 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4198 if (cfg->compile_aot) {
4199 guint32 offset = code - cfg->native_code;
4201 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4205 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4206 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4207 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4208 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4209 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4211 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4212 /* Call the trampoline */
4213 amd64_call_reg (code, AMD64_R11);
4214 amd64_patch (label, code);
4216 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4220 * Emit a test+branch against a constant, the constant will be overwritten
4221 * by mono_arch_set_breakpoint () to cause the test to fail.
4223 amd64_mov_reg_imm (code, AMD64_R11, 0);
4224 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4226 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4229 g_assert (var->opcode == OP_REGOFFSET);
4230 /* Load bp_tramp_var */
4231 /* This is equal to &bp_trampoline */
4232 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4233 /* Call the trampoline */
4234 amd64_call_membase (code, AMD64_R11, 0);
4235 amd64_patch (label, code);
4238 * Add an additional nop so skipping the bp doesn't cause the ip to point
4239 * to another IL offset.
4247 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4250 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4254 g_assert (amd64_is_imm32 (ins->inst_imm));
4255 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4258 g_assert (amd64_is_imm32 (ins->inst_imm));
4259 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4264 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4267 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4271 g_assert (amd64_is_imm32 (ins->inst_imm));
4272 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4275 g_assert (amd64_is_imm32 (ins->inst_imm));
4276 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4279 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4283 g_assert (amd64_is_imm32 (ins->inst_imm));
4284 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4287 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4292 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4294 switch (ins->inst_imm) {
4298 if (ins->dreg != ins->sreg1)
4299 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4300 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4303 /* LEA r1, [r2 + r2*2] */
4304 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4307 /* LEA r1, [r2 + r2*4] */
4308 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4311 /* LEA r1, [r2 + r2*2] */
4313 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4314 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4317 /* LEA r1, [r2 + r2*8] */
4318 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4321 /* LEA r1, [r2 + r2*4] */
4323 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4324 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4327 /* LEA r1, [r2 + r2*2] */
4329 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4330 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4333 /* LEA r1, [r2 + r2*4] */
4334 /* LEA r1, [r1 + r1*4] */
4335 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4336 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4339 /* LEA r1, [r2 + r2*4] */
4341 /* LEA r1, [r1 + r1*4] */
4342 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4343 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4344 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4347 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4354 /* Regalloc magic makes the div/rem cases the same */
4355 if (ins->sreg2 == AMD64_RDX) {
4356 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4358 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4361 amd64_div_reg (code, ins->sreg2, TRUE);
4366 if (ins->sreg2 == AMD64_RDX) {
4367 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4368 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4369 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4371 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4372 amd64_div_reg (code, ins->sreg2, FALSE);
4377 if (ins->sreg2 == AMD64_RDX) {
4378 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4379 amd64_cdq_size (code, 4);
4380 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4382 amd64_cdq_size (code, 4);
4383 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4388 if (ins->sreg2 == AMD64_RDX) {
4389 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4390 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4391 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4393 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4394 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4398 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4399 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4402 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4406 g_assert (amd64_is_imm32 (ins->inst_imm));
4407 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4410 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4414 g_assert (amd64_is_imm32 (ins->inst_imm));
4415 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4418 g_assert (ins->sreg2 == AMD64_RCX);
4419 amd64_shift_reg (code, X86_SHL, ins->dreg);
4422 g_assert (ins->sreg2 == AMD64_RCX);
4423 amd64_shift_reg (code, X86_SAR, ins->dreg);
4427 g_assert (amd64_is_imm32 (ins->inst_imm));
4428 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4431 g_assert (amd64_is_imm32 (ins->inst_imm));
4432 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4434 case OP_LSHR_UN_IMM:
4435 g_assert (amd64_is_imm32 (ins->inst_imm));
4436 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4439 g_assert (ins->sreg2 == AMD64_RCX);
4440 amd64_shift_reg (code, X86_SHR, ins->dreg);
4444 g_assert (amd64_is_imm32 (ins->inst_imm));
4445 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4450 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4453 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4456 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4459 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4463 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4466 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4469 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4472 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4475 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4478 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4481 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4484 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4487 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4490 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4493 amd64_neg_reg_size (code, ins->sreg1, 4);
4496 amd64_not_reg_size (code, ins->sreg1, 4);
4499 g_assert (ins->sreg2 == AMD64_RCX);
4500 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4503 g_assert (ins->sreg2 == AMD64_RCX);
4504 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4507 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4509 case OP_ISHR_UN_IMM:
4510 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4513 g_assert (ins->sreg2 == AMD64_RCX);
4514 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4517 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4520 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4523 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4524 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4526 case OP_IMUL_OVF_UN:
4527 case OP_LMUL_OVF_UN: {
4528 /* the mul operation and the exception check should most likely be split */
4529 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4530 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4531 /*g_assert (ins->sreg2 == X86_EAX);
4532 g_assert (ins->dreg == X86_EAX);*/
4533 if (ins->sreg2 == X86_EAX) {
4534 non_eax_reg = ins->sreg1;
4535 } else if (ins->sreg1 == X86_EAX) {
4536 non_eax_reg = ins->sreg2;
4538 /* no need to save since we're going to store to it anyway */
4539 if (ins->dreg != X86_EAX) {
4541 amd64_push_reg (code, X86_EAX);
4543 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4544 non_eax_reg = ins->sreg2;
4546 if (ins->dreg == X86_EDX) {
4549 amd64_push_reg (code, X86_EAX);
4553 amd64_push_reg (code, X86_EDX);
4555 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4556 /* save before the check since pop and mov don't change the flags */
4557 if (ins->dreg != X86_EAX)
4558 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4560 amd64_pop_reg (code, X86_EDX);
4562 amd64_pop_reg (code, X86_EAX);
4563 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4567 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4569 case OP_ICOMPARE_IMM:
4570 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4592 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4600 case OP_CMOV_INE_UN:
4601 case OP_CMOV_IGE_UN:
4602 case OP_CMOV_IGT_UN:
4603 case OP_CMOV_ILE_UN:
4604 case OP_CMOV_ILT_UN:
4610 case OP_CMOV_LNE_UN:
4611 case OP_CMOV_LGE_UN:
4612 case OP_CMOV_LGT_UN:
4613 case OP_CMOV_LLE_UN:
4614 case OP_CMOV_LLT_UN:
4615 g_assert (ins->dreg == ins->sreg1);
4616 /* This needs to operate on 64 bit values */
4617 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4621 amd64_not_reg (code, ins->sreg1);
4624 amd64_neg_reg (code, ins->sreg1);
4629 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4630 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4632 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4635 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4636 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4639 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4640 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4643 if (ins->dreg != ins->sreg1)
4644 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4646 case OP_AMD64_SET_XMMREG_R4: {
4648 if (ins->dreg != ins->sreg1)
4649 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4651 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4655 case OP_AMD64_SET_XMMREG_R8: {
4656 if (ins->dreg != ins->sreg1)
4657 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4661 MonoCallInst *call = (MonoCallInst*)ins;
4662 int i, save_area_offset;
4664 g_assert (!cfg->method->save_lmf);
4666 /* Restore callee saved registers */
4667 save_area_offset = cfg->arch.reg_save_area_offset;
4668 for (i = 0; i < AMD64_NREG; ++i)
4669 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4670 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4671 save_area_offset += 8;
4674 if (cfg->arch.omit_fp) {
4675 if (cfg->arch.stack_alloc_size)
4676 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4678 if (call->stack_usage)
4681 /* Copy arguments on the stack to our argument area */
4682 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4683 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4684 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4690 offset = code - cfg->native_code;
4691 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4692 if (cfg->compile_aot)
4693 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4695 amd64_set_reg_template (code, AMD64_R11);
4696 amd64_jump_reg (code, AMD64_R11);
4697 ins->flags |= MONO_INST_GC_CALLSITE;
4698 ins->backend.pc_offset = code - cfg->native_code;
4702 /* ensure ins->sreg1 is not NULL */
4703 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4706 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4707 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4717 call = (MonoCallInst*)ins;
4719 * The AMD64 ABI forces callers to know about varargs.
4721 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4722 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4723 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4725 * Since the unmanaged calling convention doesn't contain a
4726 * 'vararg' entry, we have to treat every pinvoke call as a
4727 * potential vararg call.
4731 for (i = 0; i < AMD64_XMM_NREG; ++i)
4732 if (call->used_fregs & (1 << i))
4735 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4737 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4740 if (ins->flags & MONO_INST_HAS_METHOD)
4741 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4743 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4744 ins->flags |= MONO_INST_GC_CALLSITE;
4745 ins->backend.pc_offset = code - cfg->native_code;
4746 code = emit_move_return_value (cfg, ins, code);
4753 case OP_VOIDCALL_REG:
4755 call = (MonoCallInst*)ins;
4757 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4758 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4759 ins->sreg1 = AMD64_R11;
4763 * The AMD64 ABI forces callers to know about varargs.
4765 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4766 if (ins->sreg1 == AMD64_RAX) {
4767 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4768 ins->sreg1 = AMD64_R11;
4770 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4771 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4773 * Since the unmanaged calling convention doesn't contain a
4774 * 'vararg' entry, we have to treat every pinvoke call as a
4775 * potential vararg call.
4779 for (i = 0; i < AMD64_XMM_NREG; ++i)
4780 if (call->used_fregs & (1 << i))
4782 if (ins->sreg1 == AMD64_RAX) {
4783 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4784 ins->sreg1 = AMD64_R11;
4787 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4789 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4792 amd64_call_reg (code, ins->sreg1);
4793 ins->flags |= MONO_INST_GC_CALLSITE;
4794 ins->backend.pc_offset = code - cfg->native_code;
4795 code = emit_move_return_value (cfg, ins, code);
4797 case OP_FCALL_MEMBASE:
4798 case OP_RCALL_MEMBASE:
4799 case OP_LCALL_MEMBASE:
4800 case OP_VCALL_MEMBASE:
4801 case OP_VCALL2_MEMBASE:
4802 case OP_VOIDCALL_MEMBASE:
4803 case OP_CALL_MEMBASE:
4804 call = (MonoCallInst*)ins;
4806 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4807 ins->flags |= MONO_INST_GC_CALLSITE;
4808 ins->backend.pc_offset = code - cfg->native_code;
4809 code = emit_move_return_value (cfg, ins, code);
4813 MonoInst *var = cfg->dyn_call_var;
4816 g_assert (var->opcode == OP_REGOFFSET);
4818 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4819 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4821 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4823 /* Save args buffer */
4824 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4826 /* Set fp arg regs */
4827 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4828 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4830 amd64_branch8 (code, X86_CC_Z, -1, 1);
4831 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4832 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4833 amd64_patch (label, code);
4835 /* Set stack args */
4836 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4837 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4838 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4841 /* Set argument registers */
4842 for (i = 0; i < PARAM_REGS; ++i)
4843 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4846 amd64_call_reg (code, AMD64_R10);
4848 ins->flags |= MONO_INST_GC_CALLSITE;
4849 ins->backend.pc_offset = code - cfg->native_code;
4852 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4853 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4854 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4855 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4858 case OP_AMD64_SAVE_SP_TO_LMF: {
4859 MonoInst *lmf_var = cfg->lmf_var;
4860 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4864 g_assert_not_reached ();
4865 amd64_push_reg (code, ins->sreg1);
4867 case OP_X86_PUSH_IMM:
4868 g_assert_not_reached ();
4869 g_assert (amd64_is_imm32 (ins->inst_imm));
4870 amd64_push_imm (code, ins->inst_imm);
4872 case OP_X86_PUSH_MEMBASE:
4873 g_assert_not_reached ();
4874 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4876 case OP_X86_PUSH_OBJ: {
4877 int size = ALIGN_TO (ins->inst_imm, 8);
4879 g_assert_not_reached ();
4881 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4882 amd64_push_reg (code, AMD64_RDI);
4883 amd64_push_reg (code, AMD64_RSI);
4884 amd64_push_reg (code, AMD64_RCX);
4885 if (ins->inst_offset)
4886 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4888 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4889 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4890 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4892 amd64_prefix (code, X86_REP_PREFIX);
4894 amd64_pop_reg (code, AMD64_RCX);
4895 amd64_pop_reg (code, AMD64_RSI);
4896 amd64_pop_reg (code, AMD64_RDI);
4899 case OP_GENERIC_CLASS_INIT: {
4900 static int byte_offset = -1;
4901 static guint8 bitmask;
4904 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4906 if (byte_offset < 0)
4907 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4909 amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4911 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4913 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4914 ins->flags |= MONO_INST_GC_CALLSITE;
4915 ins->backend.pc_offset = code - cfg->native_code;
4917 x86_patch (jump, code);
4922 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4924 case OP_X86_LEA_MEMBASE:
4925 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4928 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4931 /* keep alignment */
4932 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4933 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4934 code = mono_emit_stack_alloc (cfg, code, ins);
4935 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4936 if (cfg->param_area)
4937 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4939 case OP_LOCALLOC_IMM: {
4940 guint32 size = ins->inst_imm;
4941 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4943 if (ins->flags & MONO_INST_INIT) {
4947 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4948 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4950 for (i = 0; i < size; i += 8)
4951 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4952 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4954 amd64_mov_reg_imm (code, ins->dreg, size);
4955 ins->sreg1 = ins->dreg;
4957 code = mono_emit_stack_alloc (cfg, code, ins);
4958 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4961 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4962 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4964 if (cfg->param_area)
4965 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4969 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4970 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4971 (gpointer)"mono_arch_throw_exception", FALSE);
4972 ins->flags |= MONO_INST_GC_CALLSITE;
4973 ins->backend.pc_offset = code - cfg->native_code;
4977 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4978 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4979 (gpointer)"mono_arch_rethrow_exception", FALSE);
4980 ins->flags |= MONO_INST_GC_CALLSITE;
4981 ins->backend.pc_offset = code - cfg->native_code;
4984 case OP_CALL_HANDLER:
4986 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4987 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4988 amd64_call_imm (code, 0);
4989 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4990 /* Restore stack alignment */
4991 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4993 case OP_START_HANDLER: {
4994 /* Even though we're saving RSP, use sizeof */
4995 /* gpointer because spvar is of type IntPtr */
4996 /* see: mono_create_spvar_for_region */
4997 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4998 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5000 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5001 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5003 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5007 case OP_ENDFINALLY: {
5008 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5009 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5013 case OP_ENDFILTER: {
5014 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5015 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5016 /* The local allocator will put the result into RAX */
5021 if (ins->dreg != AMD64_RAX)
5022 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5025 ins->inst_c0 = code - cfg->native_code;
5028 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5029 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5031 if (ins->inst_target_bb->native_offset) {
5032 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5034 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5035 if ((cfg->opt & MONO_OPT_BRANCH) &&
5036 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5037 x86_jump8 (code, 0);
5039 x86_jump32 (code, 0);
5043 amd64_jump_reg (code, ins->sreg1);
5066 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5067 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5069 case OP_COND_EXC_EQ:
5070 case OP_COND_EXC_NE_UN:
5071 case OP_COND_EXC_LT:
5072 case OP_COND_EXC_LT_UN:
5073 case OP_COND_EXC_GT:
5074 case OP_COND_EXC_GT_UN:
5075 case OP_COND_EXC_GE:
5076 case OP_COND_EXC_GE_UN:
5077 case OP_COND_EXC_LE:
5078 case OP_COND_EXC_LE_UN:
5079 case OP_COND_EXC_IEQ:
5080 case OP_COND_EXC_INE_UN:
5081 case OP_COND_EXC_ILT:
5082 case OP_COND_EXC_ILT_UN:
5083 case OP_COND_EXC_IGT:
5084 case OP_COND_EXC_IGT_UN:
5085 case OP_COND_EXC_IGE:
5086 case OP_COND_EXC_IGE_UN:
5087 case OP_COND_EXC_ILE:
5088 case OP_COND_EXC_ILE_UN:
5089 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5091 case OP_COND_EXC_OV:
5092 case OP_COND_EXC_NO:
5094 case OP_COND_EXC_NC:
5095 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5096 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5098 case OP_COND_EXC_IOV:
5099 case OP_COND_EXC_INO:
5100 case OP_COND_EXC_IC:
5101 case OP_COND_EXC_INC:
5102 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5103 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5106 /* floating point opcodes */
5108 double d = *(double *)ins->inst_p0;
5110 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5111 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5114 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5115 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5120 float f = *(float *)ins->inst_p0;
5122 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5124 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5126 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5129 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5130 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5132 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5136 case OP_STORER8_MEMBASE_REG:
5137 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5139 case OP_LOADR8_MEMBASE:
5140 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5142 case OP_STORER4_MEMBASE_REG:
5144 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5146 /* This requires a double->single conversion */
5147 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5148 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5151 case OP_LOADR4_MEMBASE:
5153 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5155 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5156 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5159 case OP_ICONV_TO_R4:
5161 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5163 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5164 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5167 case OP_ICONV_TO_R8:
5168 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5170 case OP_LCONV_TO_R4:
5172 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5174 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5175 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5178 case OP_LCONV_TO_R8:
5179 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5181 case OP_FCONV_TO_R4:
5183 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5185 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5186 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5189 case OP_FCONV_TO_I1:
5190 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5192 case OP_FCONV_TO_U1:
5193 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5195 case OP_FCONV_TO_I2:
5196 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5198 case OP_FCONV_TO_U2:
5199 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5201 case OP_FCONV_TO_U4:
5202 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5204 case OP_FCONV_TO_I4:
5206 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5208 case OP_FCONV_TO_I8:
5209 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5212 case OP_RCONV_TO_I1:
5213 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5214 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5216 case OP_RCONV_TO_U1:
5217 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5218 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5220 case OP_RCONV_TO_I2:
5221 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5222 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5224 case OP_RCONV_TO_U2:
5225 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5226 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5228 case OP_RCONV_TO_I4:
5229 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5231 case OP_RCONV_TO_U4:
5232 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5234 case OP_RCONV_TO_I8:
5235 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5237 case OP_RCONV_TO_R8:
5238 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5240 case OP_RCONV_TO_R4:
5241 if (ins->dreg != ins->sreg1)
5242 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5245 case OP_LCONV_TO_R_UN: {
5248 /* Based on gcc code */
5249 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5250 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5253 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5254 br [1] = code; x86_jump8 (code, 0);
5255 amd64_patch (br [0], code);
5258 /* Save to the red zone */
5259 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5260 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5261 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5262 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5263 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5264 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5265 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5266 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5267 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5269 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5270 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5271 amd64_patch (br [1], code);
5274 case OP_LCONV_TO_OVF_U4:
5275 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5276 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5277 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5279 case OP_LCONV_TO_OVF_I4_UN:
5280 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5281 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5282 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5285 if (ins->dreg != ins->sreg1)
5286 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5289 if (ins->dreg != ins->sreg1)
5290 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5292 case OP_MOVE_F_TO_I4:
5294 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5296 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5297 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5300 case OP_MOVE_I4_TO_F:
5301 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5303 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5305 case OP_MOVE_F_TO_I8:
5306 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5308 case OP_MOVE_I8_TO_F:
5309 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5312 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5315 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5318 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5321 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5324 static double r8_0 = -0.0;
5326 g_assert (ins->sreg1 == ins->dreg);
5328 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5329 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5333 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5336 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5339 static guint64 d = 0x7fffffffffffffffUL;
5341 g_assert (ins->sreg1 == ins->dreg);
5343 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5344 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5348 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5352 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5355 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5358 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5361 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5364 static float r4_0 = -0.0;
5366 g_assert (ins->sreg1 == ins->dreg);
5368 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5369 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5370 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5375 g_assert (cfg->opt & MONO_OPT_CMOV);
5376 g_assert (ins->dreg == ins->sreg1);
5377 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5378 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5381 g_assert (cfg->opt & MONO_OPT_CMOV);
5382 g_assert (ins->dreg == ins->sreg1);
5383 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5384 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5387 g_assert (cfg->opt & MONO_OPT_CMOV);
5388 g_assert (ins->dreg == ins->sreg1);
5389 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5390 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5393 g_assert (cfg->opt & MONO_OPT_CMOV);
5394 g_assert (ins->dreg == ins->sreg1);
5395 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5396 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5399 g_assert (cfg->opt & MONO_OPT_CMOV);
5400 g_assert (ins->dreg == ins->sreg1);
5401 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5402 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5405 g_assert (cfg->opt & MONO_OPT_CMOV);
5406 g_assert (ins->dreg == ins->sreg1);
5407 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5408 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5411 g_assert (cfg->opt & MONO_OPT_CMOV);
5412 g_assert (ins->dreg == ins->sreg1);
5413 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5414 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5417 g_assert (cfg->opt & MONO_OPT_CMOV);
5418 g_assert (ins->dreg == ins->sreg1);
5419 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5420 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5426 * The two arguments are swapped because the fbranch instructions
5427 * depend on this for the non-sse case to work.
5429 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5433 * FIXME: Get rid of this.
5434 * The two arguments are swapped because the fbranch instructions
5435 * depend on this for the non-sse case to work.
5437 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5441 /* zeroing the register at the start results in
5442 * shorter and faster code (we can also remove the widening op)
5444 guchar *unordered_check;
5446 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5447 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5448 unordered_check = code;
5449 x86_branch8 (code, X86_CC_P, 0, FALSE);
5451 if (ins->opcode == OP_FCEQ) {
5452 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5453 amd64_patch (unordered_check, code);
5455 guchar *jump_to_end;
5456 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5458 x86_jump8 (code, 0);
5459 amd64_patch (unordered_check, code);
5460 amd64_inc_reg (code, ins->dreg);
5461 amd64_patch (jump_to_end, code);
5467 /* zeroing the register at the start results in
5468 * shorter and faster code (we can also remove the widening op)
5470 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5471 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5472 if (ins->opcode == OP_FCLT_UN) {
5473 guchar *unordered_check = code;
5474 guchar *jump_to_end;
5475 x86_branch8 (code, X86_CC_P, 0, FALSE);
5476 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5478 x86_jump8 (code, 0);
5479 amd64_patch (unordered_check, code);
5480 amd64_inc_reg (code, ins->dreg);
5481 amd64_patch (jump_to_end, code);
5483 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5488 guchar *unordered_check;
5489 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5490 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5491 unordered_check = code;
5492 x86_branch8 (code, X86_CC_P, 0, FALSE);
5493 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5494 amd64_patch (unordered_check, code);
5499 /* zeroing the register at the start results in
5500 * shorter and faster code (we can also remove the widening op)
5502 guchar *unordered_check;
5504 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5505 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5506 if (ins->opcode == OP_FCGT) {
5507 unordered_check = code;
5508 x86_branch8 (code, X86_CC_P, 0, FALSE);
5509 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5510 amd64_patch (unordered_check, code);
5512 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5517 guchar *unordered_check;
5518 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5519 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5520 unordered_check = code;
5521 x86_branch8 (code, X86_CC_P, 0, FALSE);
5522 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5523 amd64_patch (unordered_check, code);
5533 gboolean unordered = FALSE;
5535 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5536 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5538 switch (ins->opcode) {
5540 x86_cond = X86_CC_EQ;
5543 x86_cond = X86_CC_LT;
5546 x86_cond = X86_CC_GT;
5549 x86_cond = X86_CC_GT;
5553 x86_cond = X86_CC_LT;
5557 g_assert_not_reached ();
5562 guchar *unordered_check;
5563 guchar *jump_to_end;
5565 unordered_check = code;
5566 x86_branch8 (code, X86_CC_P, 0, FALSE);
5567 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5569 x86_jump8 (code, 0);
5570 amd64_patch (unordered_check, code);
5571 amd64_inc_reg (code, ins->dreg);
5572 amd64_patch (jump_to_end, code);
5574 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5578 case OP_FCLT_MEMBASE:
5579 case OP_FCGT_MEMBASE:
5580 case OP_FCLT_UN_MEMBASE:
5581 case OP_FCGT_UN_MEMBASE:
5582 case OP_FCEQ_MEMBASE: {
5583 guchar *unordered_check, *jump_to_end;
5586 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5587 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5589 switch (ins->opcode) {
5590 case OP_FCEQ_MEMBASE:
5591 x86_cond = X86_CC_EQ;
5593 case OP_FCLT_MEMBASE:
5594 case OP_FCLT_UN_MEMBASE:
5595 x86_cond = X86_CC_LT;
5597 case OP_FCGT_MEMBASE:
5598 case OP_FCGT_UN_MEMBASE:
5599 x86_cond = X86_CC_GT;
5602 g_assert_not_reached ();
5605 unordered_check = code;
5606 x86_branch8 (code, X86_CC_P, 0, FALSE);
5607 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5609 switch (ins->opcode) {
5610 case OP_FCEQ_MEMBASE:
5611 case OP_FCLT_MEMBASE:
5612 case OP_FCGT_MEMBASE:
5613 amd64_patch (unordered_check, code);
5615 case OP_FCLT_UN_MEMBASE:
5616 case OP_FCGT_UN_MEMBASE:
5618 x86_jump8 (code, 0);
5619 amd64_patch (unordered_check, code);
5620 amd64_inc_reg (code, ins->dreg);
5621 amd64_patch (jump_to_end, code);
5629 guchar *jump = code;
5630 x86_branch8 (code, X86_CC_P, 0, TRUE);
5631 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5632 amd64_patch (jump, code);
5636 /* Branch if C013 != 100 */
5637 /* branch if !ZF or (PF|CF) */
5638 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5639 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5640 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5643 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5646 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5647 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5651 if (ins->opcode == OP_FBGT) {
5654 /* skip branch if C1=1 */
5656 x86_branch8 (code, X86_CC_P, 0, FALSE);
5657 /* branch if (C0 | C3) = 1 */
5658 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5659 amd64_patch (br1, code);
5662 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5666 /* Branch if C013 == 100 or 001 */
5669 /* skip branch if C1=1 */
5671 x86_branch8 (code, X86_CC_P, 0, FALSE);
5672 /* branch if (C0 | C3) = 1 */
5673 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5674 amd64_patch (br1, code);
5678 /* Branch if C013 == 000 */
5679 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5682 /* Branch if C013=000 or 100 */
5685 /* skip branch if C1=1 */
5687 x86_branch8 (code, X86_CC_P, 0, FALSE);
5688 /* branch if C0=0 */
5689 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5690 amd64_patch (br1, code);
5694 /* Branch if C013 != 001 */
5695 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5696 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5699 /* Transfer value to the fp stack */
5700 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5701 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5702 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5704 amd64_push_reg (code, AMD64_RAX);
5706 amd64_fnstsw (code);
5707 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5708 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5709 amd64_pop_reg (code, AMD64_RAX);
5710 amd64_fstp (code, 0);
5711 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5712 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5715 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5718 case OP_TLS_GET_REG:
5719 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5722 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5725 case OP_TLS_SET_REG: {
5726 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5729 case OP_MEMORY_BARRIER: {
5730 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5734 case OP_ATOMIC_ADD_I4:
5735 case OP_ATOMIC_ADD_I8: {
5736 int dreg = ins->dreg;
5737 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5739 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5742 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5743 amd64_prefix (code, X86_LOCK_PREFIX);
5744 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5745 /* dreg contains the old value, add with sreg2 value */
5746 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5748 if (ins->dreg != dreg)
5749 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5753 case OP_ATOMIC_EXCHANGE_I4:
5754 case OP_ATOMIC_EXCHANGE_I8: {
5755 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5757 /* LOCK prefix is implied. */
5758 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5759 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5760 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5763 case OP_ATOMIC_CAS_I4:
5764 case OP_ATOMIC_CAS_I8: {
5767 if (ins->opcode == OP_ATOMIC_CAS_I8)
5773 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5774 * an explanation of how this works.
5776 g_assert (ins->sreg3 == AMD64_RAX);
5777 g_assert (ins->sreg1 != AMD64_RAX);
5778 g_assert (ins->sreg1 != ins->sreg2);
5780 amd64_prefix (code, X86_LOCK_PREFIX);
5781 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5783 if (ins->dreg != AMD64_RAX)
5784 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5787 case OP_ATOMIC_LOAD_I1: {
5788 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5791 case OP_ATOMIC_LOAD_U1: {
5792 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5795 case OP_ATOMIC_LOAD_I2: {
5796 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5799 case OP_ATOMIC_LOAD_U2: {
5800 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5803 case OP_ATOMIC_LOAD_I4: {
5804 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5807 case OP_ATOMIC_LOAD_U4:
5808 case OP_ATOMIC_LOAD_I8:
5809 case OP_ATOMIC_LOAD_U8: {
5810 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5813 case OP_ATOMIC_LOAD_R4: {
5814 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5815 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5818 case OP_ATOMIC_LOAD_R8: {
5819 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5822 case OP_ATOMIC_STORE_I1:
5823 case OP_ATOMIC_STORE_U1:
5824 case OP_ATOMIC_STORE_I2:
5825 case OP_ATOMIC_STORE_U2:
5826 case OP_ATOMIC_STORE_I4:
5827 case OP_ATOMIC_STORE_U4:
5828 case OP_ATOMIC_STORE_I8:
5829 case OP_ATOMIC_STORE_U8: {
5832 switch (ins->opcode) {
5833 case OP_ATOMIC_STORE_I1:
5834 case OP_ATOMIC_STORE_U1:
5837 case OP_ATOMIC_STORE_I2:
5838 case OP_ATOMIC_STORE_U2:
5841 case OP_ATOMIC_STORE_I4:
5842 case OP_ATOMIC_STORE_U4:
5845 case OP_ATOMIC_STORE_I8:
5846 case OP_ATOMIC_STORE_U8:
5851 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5853 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5857 case OP_ATOMIC_STORE_R4: {
5858 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5859 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5861 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5865 case OP_ATOMIC_STORE_R8: {
5868 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5872 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5876 case OP_CARD_TABLE_WBARRIER: {
5877 int ptr = ins->sreg1;
5878 int value = ins->sreg2;
5880 int nursery_shift, card_table_shift;
5881 gpointer card_table_mask;
5882 size_t nursery_size;
5884 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5885 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5886 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5888 /*If either point to the stack we can simply avoid the WB. This happens due to
5889 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5891 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5895 * We need one register we can clobber, we choose EDX and make sreg1
5896 * fixed EAX to work around limitations in the local register allocator.
5897 * sreg2 might get allocated to EDX, but that is not a problem since
5898 * we use it before clobbering EDX.
5900 g_assert (ins->sreg1 == AMD64_RAX);
5903 * This is the code we produce:
5906 * edx >>= nursery_shift
5907 * cmp edx, (nursery_start >> nursery_shift)
5910 * edx >>= card_table_shift
5916 if (mono_gc_card_table_nursery_check ()) {
5917 if (value != AMD64_RDX)
5918 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5919 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5920 if (shifted_nursery_start >> 31) {
5922 * The value we need to compare against is 64 bits, so we need
5923 * another spare register. We use RBX, which we save and
5926 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5927 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5928 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5929 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5931 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5933 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5935 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5936 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5937 if (card_table_mask)
5938 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5940 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5941 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5943 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5945 if (mono_gc_card_table_nursery_check ())
5946 x86_patch (br, code);
5949 #ifdef MONO_ARCH_SIMD_INTRINSICS
5950 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5952 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5955 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5958 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5961 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5964 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5967 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5970 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5971 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5974 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5977 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5980 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5983 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5986 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5989 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5992 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5995 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5998 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6001 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6004 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6007 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6010 case OP_PSHUFLEW_HIGH:
6011 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6012 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6014 case OP_PSHUFLEW_LOW:
6015 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6016 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6019 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6020 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6023 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6024 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6027 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6028 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6032 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6035 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6038 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6041 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6044 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6047 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6050 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6051 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6054 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6057 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6060 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6063 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6066 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6069 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6072 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6075 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6078 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6081 case OP_EXTRACT_MASK:
6082 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6086 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6089 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6092 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6096 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6099 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6102 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6105 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6109 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6112 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6115 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6118 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6122 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6125 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6128 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6132 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6135 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6138 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6142 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6145 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6149 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6152 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6155 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6159 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6162 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6165 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6169 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6172 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6175 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6178 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6182 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6185 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6188 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6191 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6194 case OP_PSUM_ABS_DIFF:
6195 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6198 case OP_UNPACK_LOWB:
6199 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6201 case OP_UNPACK_LOWW:
6202 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6204 case OP_UNPACK_LOWD:
6205 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6207 case OP_UNPACK_LOWQ:
6208 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6210 case OP_UNPACK_LOWPS:
6211 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6213 case OP_UNPACK_LOWPD:
6214 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6217 case OP_UNPACK_HIGHB:
6218 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6220 case OP_UNPACK_HIGHW:
6221 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6223 case OP_UNPACK_HIGHD:
6224 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6226 case OP_UNPACK_HIGHQ:
6227 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6229 case OP_UNPACK_HIGHPS:
6230 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6232 case OP_UNPACK_HIGHPD:
6233 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6237 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6240 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6243 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6246 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6249 case OP_PADDB_SAT_UN:
6250 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6252 case OP_PSUBB_SAT_UN:
6253 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6255 case OP_PADDW_SAT_UN:
6256 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6258 case OP_PSUBW_SAT_UN:
6259 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6263 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6266 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6269 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6272 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6276 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6279 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6282 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6284 case OP_PMULW_HIGH_UN:
6285 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6288 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6292 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6295 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6299 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6302 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6306 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6309 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6313 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6316 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6320 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6323 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6327 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6330 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6334 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6337 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6340 /*TODO: This is appart of the sse spec but not added
6342 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6345 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6350 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6353 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6356 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6359 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6362 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6365 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6368 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6371 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6374 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6377 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6381 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6384 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6388 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6389 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6391 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6396 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6398 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6399 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6403 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6405 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6406 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6407 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6411 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6413 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6416 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6418 case OP_EXTRACTX_U2:
6419 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6421 case OP_INSERTX_U1_SLOW:
6422 /*sreg1 is the extracted ireg (scratch)
6423 /sreg2 is the to be inserted ireg (scratch)
6424 /dreg is the xreg to receive the value*/
6426 /*clear the bits from the extracted word*/
6427 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6428 /*shift the value to insert if needed*/
6429 if (ins->inst_c0 & 1)
6430 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6431 /*join them together*/
6432 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6433 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6435 case OP_INSERTX_I4_SLOW:
6436 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6437 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6438 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6440 case OP_INSERTX_I8_SLOW:
6441 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6443 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6445 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6448 case OP_INSERTX_R4_SLOW:
6449 switch (ins->inst_c0) {
6452 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6454 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6457 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6459 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6461 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6462 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6465 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6467 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6469 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6470 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6473 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6475 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6477 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6478 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6482 case OP_INSERTX_R8_SLOW:
6484 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6486 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6488 case OP_STOREX_MEMBASE_REG:
6489 case OP_STOREX_MEMBASE:
6490 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6492 case OP_LOADX_MEMBASE:
6493 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6495 case OP_LOADX_ALIGNED_MEMBASE:
6496 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6498 case OP_STOREX_ALIGNED_MEMBASE_REG:
6499 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6501 case OP_STOREX_NTA_MEMBASE_REG:
6502 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6504 case OP_PREFETCH_MEMBASE:
6505 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6509 /*FIXME the peephole pass should have killed this*/
6510 if (ins->dreg != ins->sreg1)
6511 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6514 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6516 case OP_ICONV_TO_R4_RAW:
6517 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6520 case OP_FCONV_TO_R8_X:
6521 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6524 case OP_XCONV_R8_TO_I4:
6525 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6526 switch (ins->backend.source_opcode) {
6527 case OP_FCONV_TO_I1:
6528 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6530 case OP_FCONV_TO_U1:
6531 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6533 case OP_FCONV_TO_I2:
6534 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6536 case OP_FCONV_TO_U2:
6537 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6543 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6544 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6545 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6548 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6549 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6552 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6553 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6557 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6559 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6560 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6562 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6565 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6566 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6569 case OP_LIVERANGE_START: {
6570 if (cfg->verbose_level > 1)
6571 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6572 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6575 case OP_LIVERANGE_END: {
6576 if (cfg->verbose_level > 1)
6577 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6578 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6581 case OP_GC_SAFE_POINT: {
6584 g_assert (mono_threads_is_coop_enabled ());
6586 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6587 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6588 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6589 amd64_patch (br[0], code);
6593 case OP_GC_LIVENESS_DEF:
6594 case OP_GC_LIVENESS_USE:
6595 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6596 ins->backend.pc_offset = code - cfg->native_code;
6598 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6599 ins->backend.pc_offset = code - cfg->native_code;
6600 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6602 case OP_GET_LAST_ERROR:
6603 emit_get_last_error(code, ins->dreg);
6606 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6607 g_assert_not_reached ();
6610 if ((code - cfg->native_code - offset) > max_len) {
6611 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6612 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6613 g_assert_not_reached ();
6617 cfg->code_len = code - cfg->native_code;
6620 #endif /* DISABLE_JIT */
6623 mono_arch_register_lowlevel_calls (void)
6625 /* The signature doesn't matter */
6626 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6630 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6632 unsigned char *ip = ji->ip.i + code;
6635 * Debug code to help track down problems where the target of a near call is
6638 if (amd64_is_near_call (ip)) {
6639 gint64 disp = (guint8*)target - (guint8*)ip;
6641 if (!amd64_is_imm32 (disp)) {
6642 printf ("TYPE: %d\n", ji->type);
6644 case MONO_PATCH_INFO_INTERNAL_METHOD:
6645 printf ("V: %s\n", ji->data.name);
6647 case MONO_PATCH_INFO_METHOD_JUMP:
6648 case MONO_PATCH_INFO_METHOD:
6649 printf ("V: %s\n", ji->data.method->name);
6657 amd64_patch (ip, (gpointer)target);
6663 get_max_epilog_size (MonoCompile *cfg)
6665 int max_epilog_size = 16;
6667 if (cfg->method->save_lmf)
6668 max_epilog_size += 256;
6670 if (mono_jit_trace_calls != NULL)
6671 max_epilog_size += 50;
6673 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6674 max_epilog_size += 50;
6676 max_epilog_size += (AMD64_NREG * 2);
6678 return max_epilog_size;
6682 * This macro is used for testing whenever the unwinder works correctly at every point
6683 * where an async exception can happen.
6685 /* This will generate a SIGSEGV at the given point in the code */
6686 #define async_exc_point(code) do { \
6687 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6688 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6689 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6690 cfg->arch.async_point_count ++; \
6695 mono_arch_emit_prolog (MonoCompile *cfg)
6697 MonoMethod *method = cfg->method;
6699 MonoMethodSignature *sig;
6701 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6704 MonoInst *lmf_var = cfg->lmf_var;
6705 gboolean args_clobbered = FALSE;
6706 gboolean trace = FALSE;
6708 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6710 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6712 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6715 /* Amount of stack space allocated by register saving code */
6718 /* Offset between RSP and the CFA */
6722 * The prolog consists of the following parts:
6724 * - push rbp, mov rbp, rsp
6725 * - save callee saved regs using pushes
6727 * - save rgctx if needed
6728 * - save lmf if needed
6731 * - save rgctx if needed
6732 * - save lmf if needed
6733 * - save callee saved regs using moves
6738 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6739 // IP saved at CFA - 8
6740 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6741 async_exc_point (code);
6742 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6744 if (!cfg->arch.omit_fp) {
6745 amd64_push_reg (code, AMD64_RBP);
6747 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6748 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6749 async_exc_point (code);
6751 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6753 /* These are handled automatically by the stack marking code */
6754 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6756 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6757 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6758 async_exc_point (code);
6760 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6764 /* The param area is always at offset 0 from sp */
6765 /* This needs to be allocated here, since it has to come after the spill area */
6766 if (cfg->param_area) {
6767 if (cfg->arch.omit_fp)
6769 g_assert_not_reached ();
6770 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6773 if (cfg->arch.omit_fp) {
6775 * On enter, the stack is misaligned by the pushing of the return
6776 * address. It is either made aligned by the pushing of %rbp, or by
6779 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6780 if ((alloc_size % 16) == 0) {
6782 /* Mark the padding slot as NOREF */
6783 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6786 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6787 if (cfg->stack_offset != alloc_size) {
6788 /* Mark the padding slot as NOREF */
6789 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6791 cfg->arch.sp_fp_offset = alloc_size;
6795 cfg->arch.stack_alloc_size = alloc_size;
6797 /* Allocate stack frame */
6799 /* See mono_emit_stack_alloc */
6800 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6801 guint32 remaining_size = alloc_size;
6802 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6803 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6804 guint32 offset = code - cfg->native_code;
6805 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6806 while (required_code_size >= (cfg->code_size - offset))
6807 cfg->code_size *= 2;
6808 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6809 code = cfg->native_code + offset;
6810 cfg->stat_code_reallocs++;
6813 while (remaining_size >= 0x1000) {
6814 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6815 if (cfg->arch.omit_fp) {
6816 cfa_offset += 0x1000;
6817 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6819 async_exc_point (code);
6821 if (cfg->arch.omit_fp)
6822 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6825 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6826 remaining_size -= 0x1000;
6828 if (remaining_size) {
6829 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6830 if (cfg->arch.omit_fp) {
6831 cfa_offset += remaining_size;
6832 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6833 async_exc_point (code);
6836 if (cfg->arch.omit_fp)
6837 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6841 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6842 if (cfg->arch.omit_fp) {
6843 cfa_offset += alloc_size;
6844 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6845 async_exc_point (code);
6850 /* Stack alignment check */
6855 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6856 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6857 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6859 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6860 amd64_breakpoint (code);
6861 amd64_patch (buf, code);
6865 if (mini_get_debug_options ()->init_stacks) {
6866 /* Fill the stack frame with a dummy value to force deterministic behavior */
6868 /* Save registers to the red zone */
6869 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6870 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6872 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6873 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6874 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6877 amd64_prefix (code, X86_REP_PREFIX);
6880 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6881 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6885 if (method->save_lmf)
6886 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6888 /* Save callee saved registers */
6889 if (cfg->arch.omit_fp) {
6890 save_area_offset = cfg->arch.reg_save_area_offset;
6891 /* Save caller saved registers after sp is adjusted */
6892 /* The registers are saved at the bottom of the frame */
6893 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6895 /* The registers are saved just below the saved rbp */
6896 save_area_offset = cfg->arch.reg_save_area_offset;
6899 for (i = 0; i < AMD64_NREG; ++i) {
6900 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6901 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6903 if (cfg->arch.omit_fp) {
6904 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6905 /* These are handled automatically by the stack marking code */
6906 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6908 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6912 save_area_offset += 8;
6913 async_exc_point (code);
6917 /* store runtime generic context */
6918 if (cfg->rgctx_var) {
6919 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6920 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6922 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6924 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6925 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6928 /* compute max_length in order to use short forward jumps */
6929 max_epilog_size = get_max_epilog_size (cfg);
6930 if (cfg->opt & MONO_OPT_BRANCH) {
6931 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6935 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6937 /* max alignment for loops */
6938 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6939 max_length += LOOP_ALIGNMENT;
6941 MONO_BB_FOR_EACH_INS (bb, ins) {
6942 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6945 /* Take prolog and epilog instrumentation into account */
6946 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6947 max_length += max_epilog_size;
6949 bb->max_length = max_length;
6953 sig = mono_method_signature (method);
6956 cinfo = (CallInfo *)cfg->arch.cinfo;
6958 if (sig->ret->type != MONO_TYPE_VOID) {
6959 /* Save volatile arguments to the stack */
6960 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6961 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6964 /* Keep this in sync with emit_load_volatile_arguments */
6965 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6966 ArgInfo *ainfo = cinfo->args + i;
6968 ins = cfg->args [i];
6970 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6971 /* Unused arguments */
6974 /* Save volatile arguments to the stack */
6975 if (ins->opcode != OP_REGVAR) {
6976 switch (ainfo->storage) {
6982 if (stack_offset & 0x1)
6984 else if (stack_offset & 0x2)
6986 else if (stack_offset & 0x4)
6991 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6994 * Save the original location of 'this',
6995 * get_generic_info_from_stack_frame () needs this to properly look up
6996 * the argument value during the handling of async exceptions.
6998 if (ins == cfg->args [0]) {
6999 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7000 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7004 case ArgInFloatSSEReg:
7005 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7007 case ArgInDoubleSSEReg:
7008 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7010 case ArgValuetypeInReg:
7011 for (quad = 0; quad < 2; quad ++) {
7012 switch (ainfo->pair_storage [quad]) {
7014 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7016 case ArgInFloatSSEReg:
7017 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7019 case ArgInDoubleSSEReg:
7020 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7025 g_assert_not_reached ();
7029 case ArgValuetypeAddrInIReg:
7030 if (ainfo->pair_storage [0] == ArgInIReg)
7031 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7033 case ArgValuetypeAddrOnStack:
7035 case ArgGSharedVtInReg:
7036 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7042 /* Argument allocated to (non-volatile) register */
7043 switch (ainfo->storage) {
7045 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7048 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7051 g_assert_not_reached ();
7054 if (ins == cfg->args [0]) {
7055 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7056 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7061 if (cfg->method->save_lmf)
7062 args_clobbered = TRUE;
7065 args_clobbered = TRUE;
7066 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7069 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7070 args_clobbered = TRUE;
7073 * Optimize the common case of the first bblock making a call with the same
7074 * arguments as the method. This works because the arguments are still in their
7075 * original argument registers.
7076 * FIXME: Generalize this
7078 if (!args_clobbered) {
7079 MonoBasicBlock *first_bb = cfg->bb_entry;
7081 int filter = FILTER_IL_SEQ_POINT;
7083 next = mono_bb_first_inst (first_bb, filter);
7084 if (!next && first_bb->next_bb) {
7085 first_bb = first_bb->next_bb;
7086 next = mono_bb_first_inst (first_bb, filter);
7089 if (first_bb->in_count > 1)
7092 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7093 ArgInfo *ainfo = cinfo->args + i;
7094 gboolean match = FALSE;
7096 ins = cfg->args [i];
7097 if (ins->opcode != OP_REGVAR) {
7098 switch (ainfo->storage) {
7100 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7101 if (next->dreg == ainfo->reg) {
7105 next->opcode = OP_MOVE;
7106 next->sreg1 = ainfo->reg;
7107 /* Only continue if the instruction doesn't change argument regs */
7108 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7118 /* Argument allocated to (non-volatile) register */
7119 switch (ainfo->storage) {
7121 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7132 next = mono_inst_next (next, filter);
7133 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7140 if (cfg->gen_sdb_seq_points) {
7141 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7143 /* Initialize seq_point_info_var */
7144 if (cfg->compile_aot) {
7145 /* Initialize the variable from a GOT slot */
7146 /* Same as OP_AOTCONST */
7147 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7148 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7149 g_assert (info_var->opcode == OP_REGOFFSET);
7150 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7153 if (cfg->compile_aot) {
7154 /* Initialize ss_tramp_var */
7155 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7156 g_assert (ins->opcode == OP_REGOFFSET);
7158 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7159 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7160 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7162 /* Initialize ss_tramp_var */
7163 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7164 g_assert (ins->opcode == OP_REGOFFSET);
7166 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7167 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7169 /* Initialize bp_tramp_var */
7170 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7171 g_assert (ins->opcode == OP_REGOFFSET);
7173 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7174 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7178 cfg->code_len = code - cfg->native_code;
7180 g_assert (cfg->code_len < cfg->code_size);
7186 mono_arch_emit_epilog (MonoCompile *cfg)
7188 MonoMethod *method = cfg->method;
7191 int max_epilog_size;
7193 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7194 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7196 max_epilog_size = get_max_epilog_size (cfg);
7198 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7199 cfg->code_size *= 2;
7200 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7201 cfg->stat_code_reallocs++;
7203 code = cfg->native_code + cfg->code_len;
7205 cfg->has_unwind_info_for_epilog = TRUE;
7207 /* Mark the start of the epilog */
7208 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7210 /* Save the uwind state which is needed by the out-of-line code */
7211 mono_emit_unwind_op_remember_state (cfg, code);
7213 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7214 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7216 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7218 if (method->save_lmf) {
7219 /* check if we need to restore protection of the stack after a stack overflow */
7220 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7222 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7223 /* we load the value in a separate instruction: this mechanism may be
7224 * used later as a safer way to do thread interruption
7226 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7227 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7229 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7230 /* note that the call trampoline will preserve eax/edx */
7231 x86_call_reg (code, X86_ECX);
7232 x86_patch (patch, code);
7234 /* FIXME: maybe save the jit tls in the prolog */
7236 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7237 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7241 /* Restore callee saved regs */
7242 for (i = 0; i < AMD64_NREG; ++i) {
7243 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7244 /* Restore only used_int_regs, not arch.saved_iregs */
7245 #if defined(MONO_SUPPORT_TASKLETS)
7248 int restore_reg=(cfg->used_int_regs & (1 << i));
7251 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7252 mono_emit_unwind_op_same_value (cfg, code, i);
7253 async_exc_point (code);
7255 save_area_offset += 8;
7259 /* Load returned vtypes into registers if needed */
7260 cinfo = (CallInfo *)cfg->arch.cinfo;
7261 if (cinfo->ret.storage == ArgValuetypeInReg) {
7262 ArgInfo *ainfo = &cinfo->ret;
7263 MonoInst *inst = cfg->ret;
7265 for (quad = 0; quad < 2; quad ++) {
7266 switch (ainfo->pair_storage [quad]) {
7268 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7270 case ArgInFloatSSEReg:
7271 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7273 case ArgInDoubleSSEReg:
7274 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7279 g_assert_not_reached ();
7284 if (cfg->arch.omit_fp) {
7285 if (cfg->arch.stack_alloc_size) {
7286 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7290 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7292 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7293 async_exc_point (code);
7296 /* Restore the unwind state to be the same as before the epilog */
7297 mono_emit_unwind_op_restore_state (cfg, code);
7299 cfg->code_len = code - cfg->native_code;
7301 g_assert (cfg->code_len < cfg->code_size);
7305 mono_arch_emit_exceptions (MonoCompile *cfg)
7307 MonoJumpInfo *patch_info;
7310 MonoClass *exc_classes [16];
7311 guint8 *exc_throw_start [16], *exc_throw_end [16];
7312 guint32 code_size = 0;
7314 /* Compute needed space */
7315 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7316 if (patch_info->type == MONO_PATCH_INFO_EXC)
7318 if (patch_info->type == MONO_PATCH_INFO_R8)
7319 code_size += 8 + 15; /* sizeof (double) + alignment */
7320 if (patch_info->type == MONO_PATCH_INFO_R4)
7321 code_size += 4 + 15; /* sizeof (float) + alignment */
7322 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7323 code_size += 8 + 7; /*sizeof (void*) + alignment */
7326 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7327 cfg->code_size *= 2;
7328 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7329 cfg->stat_code_reallocs++;
7332 code = cfg->native_code + cfg->code_len;
7334 /* add code to raise exceptions */
7336 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7337 switch (patch_info->type) {
7338 case MONO_PATCH_INFO_EXC: {
7339 MonoClass *exc_class;
7343 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7345 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7346 throw_ip = patch_info->ip.i;
7348 //x86_breakpoint (code);
7349 /* Find a throw sequence for the same exception class */
7350 for (i = 0; i < nthrows; ++i)
7351 if (exc_classes [i] == exc_class)
7354 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7355 x86_jump_code (code, exc_throw_start [i]);
7356 patch_info->type = MONO_PATCH_INFO_NONE;
7360 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7364 exc_classes [nthrows] = exc_class;
7365 exc_throw_start [nthrows] = code;
7367 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7369 patch_info->type = MONO_PATCH_INFO_NONE;
7371 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7373 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7378 exc_throw_end [nthrows] = code;
7388 g_assert(code < cfg->native_code + cfg->code_size);
7391 /* Handle relocations with RIP relative addressing */
7392 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7393 gboolean remove = FALSE;
7394 guint8 *orig_code = code;
7396 switch (patch_info->type) {
7397 case MONO_PATCH_INFO_R8:
7398 case MONO_PATCH_INFO_R4: {
7399 guint8 *pos, *patch_pos;
7402 /* The SSE opcodes require a 16 byte alignment */
7403 code = (guint8*)ALIGN_TO (code, 16);
7405 pos = cfg->native_code + patch_info->ip.i;
7406 if (IS_REX (pos [1])) {
7407 patch_pos = pos + 5;
7408 target_pos = code - pos - 9;
7411 patch_pos = pos + 4;
7412 target_pos = code - pos - 8;
7415 if (patch_info->type == MONO_PATCH_INFO_R8) {
7416 *(double*)code = *(double*)patch_info->data.target;
7417 code += sizeof (double);
7419 *(float*)code = *(float*)patch_info->data.target;
7420 code += sizeof (float);
7423 *(guint32*)(patch_pos) = target_pos;
7428 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7431 if (cfg->compile_aot)
7434 /*loading is faster against aligned addresses.*/
7435 code = (guint8*)ALIGN_TO (code, 8);
7436 memset (orig_code, 0, code - orig_code);
7438 pos = cfg->native_code + patch_info->ip.i;
7440 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7441 if (IS_REX (pos [1]))
7442 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7444 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7446 *(gpointer*)code = (gpointer)patch_info->data.target;
7447 code += sizeof (gpointer);
7457 if (patch_info == cfg->patch_info)
7458 cfg->patch_info = patch_info->next;
7462 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7464 tmp->next = patch_info->next;
7467 g_assert (code < cfg->native_code + cfg->code_size);
7470 cfg->code_len = code - cfg->native_code;
7472 g_assert (cfg->code_len < cfg->code_size);
7476 #endif /* DISABLE_JIT */
7479 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7481 guchar *code = (guchar *)p;
7482 MonoMethodSignature *sig;
7484 int i, n, stack_area = 0;
7486 /* Keep this in sync with mono_arch_get_argument_info */
7488 if (enable_arguments) {
7489 /* Allocate a new area on the stack and save arguments there */
7490 sig = mono_method_signature (cfg->method);
7492 n = sig->param_count + sig->hasthis;
7494 stack_area = ALIGN_TO (n * 8, 16);
7496 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7498 for (i = 0; i < n; ++i) {
7499 inst = cfg->args [i];
7501 if (inst->opcode == OP_REGVAR)
7502 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7504 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7505 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7510 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7511 amd64_set_reg_template (code, AMD64_ARG_REG1);
7512 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7513 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7515 if (enable_arguments)
7516 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7530 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7532 guchar *code = (guchar *)p;
7533 int save_mode = SAVE_NONE;
7534 MonoMethod *method = cfg->method;
7535 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7538 switch (ret_type->type) {
7539 case MONO_TYPE_VOID:
7540 /* special case string .ctor icall */
7541 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7542 save_mode = SAVE_EAX;
7544 save_mode = SAVE_NONE;
7548 save_mode = SAVE_EAX;
7552 save_mode = SAVE_XMM;
7554 case MONO_TYPE_GENERICINST:
7555 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7556 save_mode = SAVE_EAX;
7560 case MONO_TYPE_VALUETYPE:
7561 save_mode = SAVE_STRUCT;
7564 save_mode = SAVE_EAX;
7568 /* Save the result and copy it into the proper argument register */
7569 switch (save_mode) {
7571 amd64_push_reg (code, AMD64_RAX);
7573 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7574 if (enable_arguments)
7575 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7579 if (enable_arguments)
7580 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7583 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7584 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7586 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7588 * The result is already in the proper argument register so no copying
7595 g_assert_not_reached ();
7598 /* Set %al since this is a varargs call */
7599 if (save_mode == SAVE_XMM)
7600 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7602 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7604 if (preserve_argument_registers) {
7605 for (i = 0; i < PARAM_REGS; ++i)
7606 amd64_push_reg (code, param_regs [i]);
7609 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7610 amd64_set_reg_template (code, AMD64_ARG_REG1);
7611 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7613 if (preserve_argument_registers) {
7614 for (i = PARAM_REGS - 1; i >= 0; --i)
7615 amd64_pop_reg (code, param_regs [i]);
7618 /* Restore result */
7619 switch (save_mode) {
7621 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7622 amd64_pop_reg (code, AMD64_RAX);
7628 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7629 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7630 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7635 g_assert_not_reached ();
7642 mono_arch_flush_icache (guint8 *code, gint size)
7648 mono_arch_flush_register_windows (void)
7653 mono_arch_is_inst_imm (gint64 imm)
7655 return amd64_use_imm32 (imm);
7659 * Determine whenever the trap whose info is in SIGINFO is caused by
7663 mono_arch_is_int_overflow (void *sigctx, void *info)
7670 mono_sigctx_to_monoctx (sigctx, &ctx);
7672 rip = (guint8*)ctx.gregs [AMD64_RIP];
7674 if (IS_REX (rip [0])) {
7675 reg = amd64_rex_b (rip [0]);
7681 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7683 reg += x86_modrm_rm (rip [1]);
7685 value = ctx.gregs [reg];
7695 mono_arch_get_patch_offset (guint8 *code)
7701 * mono_breakpoint_clean_code:
7703 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7704 * breakpoints in the original code, they are removed in the copy.
7706 * Returns TRUE if no sw breakpoint was present.
7709 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7712 * If method_start is non-NULL we need to perform bound checks, since we access memory
7713 * at code - offset we could go before the start of the method and end up in a different
7714 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7717 if (!method_start || code - offset >= method_start) {
7718 memcpy (buf, code - offset, size);
7720 int diff = code - method_start;
7721 memset (buf, 0, size);
7722 memcpy (buf + offset - diff, method_start, diff + size - offset);
7728 mono_arch_get_this_arg_reg (guint8 *code)
7730 return AMD64_ARG_REG1;
7734 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7736 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7739 #define MAX_ARCH_DELEGATE_PARAMS 10
7742 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7744 guint8 *code, *start;
7745 GSList *unwind_ops = NULL;
7748 unwind_ops = mono_arch_get_cie_program ();
7751 start = code = (guint8 *)mono_global_codeman_reserve (64);
7753 /* Replace the this argument with the target */
7754 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7755 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7756 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7758 g_assert ((code - start) < 64);
7760 start = code = (guint8 *)mono_global_codeman_reserve (64);
7762 if (param_count == 0) {
7763 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7765 /* We have to shift the arguments left */
7766 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7767 for (i = 0; i < param_count; ++i) {
7770 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7772 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7774 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7778 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7780 g_assert ((code - start) < 64);
7783 mono_arch_flush_icache (start, code - start);
7786 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7788 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7789 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7793 if (mono_jit_map_is_enabled ()) {
7796 buff = (char*)"delegate_invoke_has_target";
7798 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7799 mono_emit_jit_tramp (start, code - start, buff);
7803 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7808 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7811 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7813 guint8 *code, *start;
7818 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7821 start = code = (guint8 *)mono_global_codeman_reserve (size);
7823 unwind_ops = mono_arch_get_cie_program ();
7825 /* Replace the this argument with the target */
7826 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7827 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7830 /* Load the IMT reg */
7831 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7834 /* Load the vtable */
7835 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7836 amd64_jump_membase (code, AMD64_RAX, offset);
7837 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7839 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7840 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7841 g_free (tramp_name);
7847 * mono_arch_get_delegate_invoke_impls:
7849 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7853 mono_arch_get_delegate_invoke_impls (void)
7856 MonoTrampInfo *info;
7859 get_delegate_invoke_impl (&info, TRUE, 0);
7860 res = g_slist_prepend (res, info);
7862 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7863 get_delegate_invoke_impl (&info, FALSE, i);
7864 res = g_slist_prepend (res, info);
7867 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7868 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7869 res = g_slist_prepend (res, info);
7872 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7873 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7874 res = g_slist_prepend (res, info);
7875 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7876 res = g_slist_prepend (res, info);
7883 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7885 guint8 *code, *start;
7888 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7891 /* FIXME: Support more cases */
7892 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7896 static guint8* cached = NULL;
7901 if (mono_aot_only) {
7902 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7904 MonoTrampInfo *info;
7905 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7906 mono_tramp_info_register (info, NULL);
7909 mono_memory_barrier ();
7913 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7914 for (i = 0; i < sig->param_count; ++i)
7915 if (!mono_is_regsize_var (sig->params [i]))
7917 if (sig->param_count > 4)
7920 code = cache [sig->param_count];
7924 if (mono_aot_only) {
7925 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7926 start = (guint8 *)mono_aot_get_trampoline (name);
7929 MonoTrampInfo *info;
7930 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7931 mono_tramp_info_register (info, NULL);
7934 mono_memory_barrier ();
7936 cache [sig->param_count] = start;
7943 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7945 MonoTrampInfo *info;
7948 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7950 mono_tramp_info_register (info, NULL);
7955 mono_arch_finish_init (void)
7957 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7958 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7963 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7967 #define CMP_SIZE (6 + 1)
7968 #define CMP_REG_REG_SIZE (4 + 1)
7969 #define BR_SMALL_SIZE 2
7970 #define BR_LARGE_SIZE 6
7971 #define MOV_REG_IMM_SIZE 10
7972 #define MOV_REG_IMM_32BIT_SIZE 6
7973 #define JUMP_REG_SIZE (2 + 1)
7976 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7978 int i, distance = 0;
7979 for (i = start; i < target; ++i)
7980 distance += imt_entries [i]->chunk_size;
7985 * LOCKING: called with the domain lock held
7988 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7989 gpointer fail_tramp)
7993 guint8 *code, *start;
7994 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7997 for (i = 0; i < count; ++i) {
7998 MonoIMTCheckItem *item = imt_entries [i];
7999 if (item->is_equals) {
8000 if (item->check_target_idx) {
8001 if (!item->compare_done) {
8002 if (amd64_use_imm32 ((gint64)item->key))
8003 item->chunk_size += CMP_SIZE;
8005 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8007 if (item->has_target_code) {
8008 item->chunk_size += MOV_REG_IMM_SIZE;
8010 if (vtable_is_32bit)
8011 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8013 item->chunk_size += MOV_REG_IMM_SIZE;
8015 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8018 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8019 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8021 if (vtable_is_32bit)
8022 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8024 item->chunk_size += MOV_REG_IMM_SIZE;
8025 item->chunk_size += JUMP_REG_SIZE;
8026 /* with assert below:
8027 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8032 if (amd64_use_imm32 ((gint64)item->key))
8033 item->chunk_size += CMP_SIZE;
8035 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8036 item->chunk_size += BR_LARGE_SIZE;
8037 imt_entries [item->check_target_idx]->compare_done = TRUE;
8039 size += item->chunk_size;
8042 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8044 code = (guint8 *)mono_domain_code_reserve (domain, size);
8047 unwind_ops = mono_arch_get_cie_program ();
8049 for (i = 0; i < count; ++i) {
8050 MonoIMTCheckItem *item = imt_entries [i];
8051 item->code_target = code;
8052 if (item->is_equals) {
8053 gboolean fail_case = !item->check_target_idx && fail_tramp;
8055 if (item->check_target_idx || fail_case) {
8056 if (!item->compare_done || fail_case) {
8057 if (amd64_use_imm32 ((gint64)item->key))
8058 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8060 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8061 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8064 item->jmp_code = code;
8065 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8066 if (item->has_target_code) {
8067 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8068 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8070 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8071 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8075 amd64_patch (item->jmp_code, code);
8076 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8077 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8078 item->jmp_code = NULL;
8081 /* enable the commented code to assert on wrong method */
8083 if (amd64_is_imm32 (item->key))
8084 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8086 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8087 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8089 item->jmp_code = code;
8090 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8091 /* See the comment below about R10 */
8092 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8093 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8094 amd64_patch (item->jmp_code, code);
8095 amd64_breakpoint (code);
8096 item->jmp_code = NULL;
8098 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8099 needs to be preserved. R10 needs
8100 to be preserved for calls which
8101 require a runtime generic context,
8102 but interface calls don't. */
8103 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8104 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8108 if (amd64_use_imm32 ((gint64)item->key))
8109 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8111 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8112 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8114 item->jmp_code = code;
8115 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8116 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8118 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8120 g_assert (code - item->code_target <= item->chunk_size);
8122 /* patch the branches to get to the target items */
8123 for (i = 0; i < count; ++i) {
8124 MonoIMTCheckItem *item = imt_entries [i];
8125 if (item->jmp_code) {
8126 if (item->check_target_idx) {
8127 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8133 mono_stats.imt_thunks_size += code - start;
8134 g_assert (code - start <= size);
8136 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8138 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8144 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8146 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8150 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8152 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8156 mono_arch_get_cie_program (void)
8160 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8161 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8169 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8171 MonoInst *ins = NULL;
8174 if (cmethod->klass == mono_defaults.math_class) {
8175 if (strcmp (cmethod->name, "Sin") == 0) {
8177 } else if (strcmp (cmethod->name, "Cos") == 0) {
8179 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8181 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8185 if (opcode && fsig->param_count == 1) {
8186 MONO_INST_NEW (cfg, ins, opcode);
8187 ins->type = STACK_R8;
8188 ins->dreg = mono_alloc_freg (cfg);
8189 ins->sreg1 = args [0]->dreg;
8190 MONO_ADD_INS (cfg->cbb, ins);
8194 if (cfg->opt & MONO_OPT_CMOV) {
8195 if (strcmp (cmethod->name, "Min") == 0) {
8196 if (fsig->params [0]->type == MONO_TYPE_I4)
8198 if (fsig->params [0]->type == MONO_TYPE_U4)
8199 opcode = OP_IMIN_UN;
8200 else if (fsig->params [0]->type == MONO_TYPE_I8)
8202 else if (fsig->params [0]->type == MONO_TYPE_U8)
8203 opcode = OP_LMIN_UN;
8204 } else if (strcmp (cmethod->name, "Max") == 0) {
8205 if (fsig->params [0]->type == MONO_TYPE_I4)
8207 if (fsig->params [0]->type == MONO_TYPE_U4)
8208 opcode = OP_IMAX_UN;
8209 else if (fsig->params [0]->type == MONO_TYPE_I8)
8211 else if (fsig->params [0]->type == MONO_TYPE_U8)
8212 opcode = OP_LMAX_UN;
8216 if (opcode && fsig->param_count == 2) {
8217 MONO_INST_NEW (cfg, ins, opcode);
8218 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8219 ins->dreg = mono_alloc_ireg (cfg);
8220 ins->sreg1 = args [0]->dreg;
8221 ins->sreg2 = args [1]->dreg;
8222 MONO_ADD_INS (cfg->cbb, ins);
8226 /* OP_FREM is not IEEE compatible */
8227 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8228 MONO_INST_NEW (cfg, ins, OP_FREM);
8229 ins->inst_i0 = args [0];
8230 ins->inst_i1 = args [1];
8240 mono_arch_print_tree (MonoInst *tree, int arity)
8246 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8248 return ctx->gregs [reg];
8252 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8254 ctx->gregs [reg] = val;
8258 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8260 gpointer *sp, old_value;
8264 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8265 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8268 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8277 * mono_arch_emit_load_aotconst:
8279 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8280 * TARGET from the mscorlib GOT in full-aot code.
8281 * On AMD64, the result is placed into R11.
8284 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8286 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8287 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8293 * mono_arch_get_trampolines:
8295 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8299 mono_arch_get_trampolines (gboolean aot)
8301 return mono_amd64_get_exception_trampolines (aot);
8304 /* Soft Debug support */
8305 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8308 * mono_arch_set_breakpoint:
8310 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8311 * The location should contain code emitted by OP_SEQ_POINT.
8314 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8319 guint32 native_offset = ip - (guint8*)ji->code_start;
8320 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8322 g_assert (info->bp_addrs [native_offset] == 0);
8323 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8325 /* ip points to a mov r11, 0 */
8326 g_assert (code [0] == 0x41);
8327 g_assert (code [1] == 0xbb);
8328 amd64_mov_reg_imm (code, AMD64_R11, 1);
8333 * mono_arch_clear_breakpoint:
8335 * Clear the breakpoint at IP.
8338 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8343 guint32 native_offset = ip - (guint8*)ji->code_start;
8344 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8346 info->bp_addrs [native_offset] = NULL;
8348 amd64_mov_reg_imm (code, AMD64_R11, 0);
8353 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8355 /* We use soft breakpoints on amd64 */
8360 * mono_arch_skip_breakpoint:
8362 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8363 * we resume, the instruction is not executed again.
8366 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8368 g_assert_not_reached ();
8372 * mono_arch_start_single_stepping:
8374 * Start single stepping.
8377 mono_arch_start_single_stepping (void)
8379 ss_trampoline = mini_get_single_step_trampoline ();
8383 * mono_arch_stop_single_stepping:
8385 * Stop single stepping.
8388 mono_arch_stop_single_stepping (void)
8390 ss_trampoline = NULL;
8394 * mono_arch_is_single_step_event:
8396 * Return whenever the machine state in SIGCTX corresponds to a single
8400 mono_arch_is_single_step_event (void *info, void *sigctx)
8402 /* We use soft breakpoints on amd64 */
8407 * mono_arch_skip_single_step:
8409 * Modify CTX so the ip is placed after the single step trigger instruction,
8410 * we resume, the instruction is not executed again.
8413 mono_arch_skip_single_step (MonoContext *ctx)
8415 g_assert_not_reached ();
8419 * mono_arch_create_seq_point_info:
8421 * Return a pointer to a data structure which is used by the sequence
8422 * point implementation in AOTed code.
8425 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8430 // FIXME: Add a free function
8432 mono_domain_lock (domain);
8433 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8435 mono_domain_unlock (domain);
8438 ji = mono_jit_info_table_find (domain, (char*)code);
8441 // FIXME: Optimize the size
8442 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8444 info->ss_tramp_addr = &ss_trampoline;
8446 mono_domain_lock (domain);
8447 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8449 mono_domain_unlock (domain);
8456 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8458 ext->lmf.previous_lmf = prev_lmf;
8459 /* Mark that this is a MonoLMFExt */
8460 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8461 ext->lmf.rsp = (gssize)ext;
8467 mono_arch_opcode_supported (int opcode)
8470 case OP_ATOMIC_ADD_I4:
8471 case OP_ATOMIC_ADD_I8:
8472 case OP_ATOMIC_EXCHANGE_I4:
8473 case OP_ATOMIC_EXCHANGE_I8:
8474 case OP_ATOMIC_CAS_I4:
8475 case OP_ATOMIC_CAS_I8:
8476 case OP_ATOMIC_LOAD_I1:
8477 case OP_ATOMIC_LOAD_I2:
8478 case OP_ATOMIC_LOAD_I4:
8479 case OP_ATOMIC_LOAD_I8:
8480 case OP_ATOMIC_LOAD_U1:
8481 case OP_ATOMIC_LOAD_U2:
8482 case OP_ATOMIC_LOAD_U4:
8483 case OP_ATOMIC_LOAD_U8:
8484 case OP_ATOMIC_LOAD_R4:
8485 case OP_ATOMIC_LOAD_R8:
8486 case OP_ATOMIC_STORE_I1:
8487 case OP_ATOMIC_STORE_I2:
8488 case OP_ATOMIC_STORE_I4:
8489 case OP_ATOMIC_STORE_I8:
8490 case OP_ATOMIC_STORE_U1:
8491 case OP_ATOMIC_STORE_U2:
8492 case OP_ATOMIC_STORE_U4:
8493 case OP_ATOMIC_STORE_U8:
8494 case OP_ATOMIC_STORE_R4:
8495 case OP_ATOMIC_STORE_R8:
8503 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8505 return get_call_info (mp, sig);