mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  16  */
  17 #include "mini.h"
  18 #include <string.h>
  19 #include <math.h>
  20 #ifdef HAVE_UNISTD_H
  21 #include <unistd.h>
  22 #endif
  23
  24 #include <mono/metadata/abi-details.h>
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/metadata/threads.h>
  28 #include <mono/metadata/profiler-private.h>
  29 #include <mono/metadata/mono-debug.h>
  30 #include <mono/metadata/gc-internals.h>
  31 #include <mono/utils/mono-math.h>
  32 #include <mono/utils/mono-mmap.h>
  33 #include <mono/utils/mono-memory-model.h>
  34 #include <mono/utils/mono-tls.h>
  35 #include <mono/utils/mono-hwcap-x86.h>
  36 #include <mono/utils/mono-threads.h>
  37
  38 #include "trace.h"
  39 #include "ir-emit.h"
  40 #include "mini-amd64.h"
  41 #include "cpu-amd64.h"
  42 #include "debugger-agent.h"
  43 #include "mini-gc.h"
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef TARGET_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  67 static mono_mutex_t mini_arch_mutex;
  68
  69 /* The single step trampoline */
  70 static gpointer ss_trampoline;
  71
  72 /* The breakpoint trampoline */
  73 static gpointer bp_trampoline;
  74
  75 /* Offset between fp and the first argument in the callee */
  76 #define ARGS_OFFSET 16
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return mono_debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline gboolean
 169 amd64_use_imm32 (gint64 val)
 170 {
 171         if (mini_get_debug_options()->single_imm_size)
 172                 return FALSE;
 173
 174         return amd64_is_imm32 (val);
 175 }
 176
 177 static void
 178 amd64_patch (unsigned char* code, gpointer target)
 179 {
 180         guint8 rex = 0;
 181
 182         /* Skip REX */
 183         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 184                 rex = code [0];
 185                 code += 1;
 186         }
 187
 188         if ((code [0] & 0xf8) == 0xb8) {
 189                 /* amd64_set_reg_template */
 190                 *(guint64*)(code + 1) = (guint64)target;
 191         }
 192         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 193                 /* mov 0(%rip), %dreg */
 194                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 195         }
 196         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 197                 /* call *<OFFSET>(%rip) */
 198                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 199         }
 200         else if (code [0] == 0xe8) {
 201                 /* call <DISP> */
 202                 gint64 disp = (guint8*)target - (guint8*)code;
 203                 g_assert (amd64_is_imm32 (disp));
 204                 x86_patch (code, (unsigned char*)target);
 205         }
 206         else
 207                 x86_patch (code, (unsigned char*)target);
 208 }
 209
 210 void
 211 mono_amd64_patch (unsigned char* code, gpointer target)
 212 {
 213         amd64_patch (code, target);
 214 }
 215
 216 #define DEBUG(a) if (cfg->verbose_level > 1) a
 217
 218 static void inline
 219 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 ainfo->arg_size = sizeof (mgreg_t);
 226                 /* Since the same stack slot size is used for all arg */
 227                 /*  types, it needs to be big enough to hold them all */
 228                 (*stack_size) += sizeof(mgreg_t);
 229     }
 230     else {
 231                 ainfo->storage = ArgInIReg;
 232                 ainfo->reg = param_regs [*gr];
 233                 (*gr) ++;
 234     }
 235 }
 236
 237 static void inline
 238 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 239 {
 240     ainfo->offset = *stack_size;
 241
 242     if (*gr >= FLOAT_PARAM_REGS) {
 243                 ainfo->storage = ArgOnStack;
 244                 ainfo->arg_size = sizeof (mgreg_t);
 245                 /* Since the same stack slot size is used for both float */
 246                 /*  types, it needs to be big enough to hold them both */
 247                 (*stack_size) += sizeof(mgreg_t);
 248     }
 249     else {
 250                 /* A double register */
 251                 if (is_double)
 252                         ainfo->storage = ArgInDoubleSSEReg;
 253                 else
 254                         ainfo->storage = ArgInFloatSSEReg;
 255                 ainfo->reg = *gr;
 256                 (*gr) += 1;
 257     }
 258 }
 259
 260 typedef enum ArgumentClass {
 261         ARG_CLASS_NO_CLASS,
 262         ARG_CLASS_MEMORY,
 263         ARG_CLASS_INTEGER,
 264         ARG_CLASS_SSE
 265 } ArgumentClass;
 266
 267 static ArgumentClass
 268 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 269 {
 270         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 271         MonoType *ptype;
 272
 273         ptype = mini_get_underlying_type (type);
 274         switch (ptype->type) {
 275         case MONO_TYPE_I1:
 276         case MONO_TYPE_U1:
 277         case MONO_TYPE_I2:
 278         case MONO_TYPE_U2:
 279         case MONO_TYPE_I4:
 280         case MONO_TYPE_U4:
 281         case MONO_TYPE_I:
 282         case MONO_TYPE_U:
 283         case MONO_TYPE_STRING:
 284         case MONO_TYPE_OBJECT:
 285         case MONO_TYPE_CLASS:
 286         case MONO_TYPE_SZARRAY:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_ARRAY:
 290         case MONO_TYPE_I8:
 291         case MONO_TYPE_U8:
 292                 class2 = ARG_CLASS_INTEGER;
 293                 break;
 294         case MONO_TYPE_R4:
 295         case MONO_TYPE_R8:
 296 #ifdef TARGET_WIN32
 297                 class2 = ARG_CLASS_INTEGER;
 298 #else
 299                 class2 = ARG_CLASS_SSE;
 300 #endif
 301                 break;
 302
 303         case MONO_TYPE_TYPEDBYREF:
 304                 g_assert_not_reached ();
 305
 306         case MONO_TYPE_GENERICINST:
 307                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 308                         class2 = ARG_CLASS_INTEGER;
 309                         break;
 310                 }
 311                 /* fall through */
 312         case MONO_TYPE_VALUETYPE: {
 313                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 314                 int i;
 315
 316                 for (i = 0; i < info->num_fields; ++i) {
 317                         class2 = class1;
 318                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 319                 }
 320                 break;
 321         }
 322         default:
 323                 g_assert_not_reached ();
 324         }
 325
 326         /* Merge */
 327         if (class1 == class2)
 328                 ;
 329         else if (class1 == ARG_CLASS_NO_CLASS)
 330                 class1 = class2;
 331         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 332                 class1 = ARG_CLASS_MEMORY;
 333         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 334                 class1 = ARG_CLASS_INTEGER;
 335         else
 336                 class1 = ARG_CLASS_SSE;
 337
 338         return class1;
 339 }
 340
 341 static int
 342 count_fields_nested (MonoClass *klass)
 343 {
 344         MonoMarshalType *info;
 345         int i, count;
 346
 347         info = mono_marshal_load_type_info (klass);
 348         g_assert(info);
 349         count = 0;
 350         for (i = 0; i < info->num_fields; ++i) {
 351                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 352                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 353                 else
 354                         count ++;
 355         }
 356         return count;
 357 }
 358
 359 static int
 360 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 361 {
 362         MonoMarshalType *info;
 363         int i;
 364
 365         info = mono_marshal_load_type_info (klass);
 366         g_assert(info);
 367         for (i = 0; i < info->num_fields; ++i) {
 368                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 369                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 370                 } else {
 371                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 372                         fields [index].offset += offset;
 373                         index ++;
 374                 }
 375         }
 376         return index;
 377 }
 378
 379 #ifdef TARGET_WIN32
 380 static void
 381 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 382                                          gboolean is_return,
 383                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 384 {
 385         guint32 size, i, nfields;
 386         guint32 argsize = 8;
 387         ArgumentClass arg_class;
 388         MonoMarshalType *info = NULL;
 389         MonoMarshalField *fields = NULL;
 390         MonoClass *klass;
 391         gboolean pass_on_stack = FALSE;
 392
 393         klass = mono_class_from_mono_type (type);
 394         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 395         if (!sig->pinvoke)
 396                 pass_on_stack = TRUE;
 397
 398         /* If this struct can't be split up naturally into 8-byte */
 399         /* chunks (registers), pass it on the stack.              */
 400         if (sig->pinvoke && !pass_on_stack) {
 401                 guint32 align;
 402                 guint32 field_size;
 403
 404                 info = mono_marshal_load_type_info (klass);
 405                 g_assert (info);
 406
 407                 /*
 408                  * Collect field information recursively to be able to
 409                  * handle nested structures.
 410                  */
 411                 nfields = count_fields_nested (klass);
 412                 fields = g_new0 (MonoMarshalField, nfields);
 413                 collect_field_info_nested (klass, fields, 0, 0);
 414
 415                 for (i = 0; i < nfields; ++i) {
 416                         field_size = mono_marshal_type_size (fields [i].field->type,
 417                                                            fields [i].mspec,
 418                                                            &align, TRUE, klass->unicode);
 419                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 420                                 pass_on_stack = TRUE;
 421                                 break;
 422                         }
 423                 }
 424         }
 425
 426         if (pass_on_stack) {
 427                 /* Allways pass in memory */
 428                 ainfo->offset = *stack_size;
 429                 *stack_size += ALIGN_TO (size, 8);
 430                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 431                 if (!is_return)
 432                         ainfo->arg_size = ALIGN_TO (size, 8);
 433
 434                 g_free (fields);
 435                 return;
 436         }
 437
 438         if (!sig->pinvoke) {
 439                 int n = mono_class_value_size (klass, NULL);
 440
 441                 argsize = n;
 442
 443                 if (n > 8)
 444                         arg_class = ARG_CLASS_MEMORY;
 445                 else
 446                         /* Always pass in 1 integer register */
 447                         arg_class = ARG_CLASS_INTEGER;
 448         } else {
 449                 g_assert (info);
 450
 451                 if (!fields) {
 452                         ainfo->storage = ArgValuetypeInReg;
 453                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 454                         return;
 455                 }
 456
 457                 switch (info->native_size) {
 458                 case 1: case 2: case 4: case 8:
 459                         break;
 460                 default:
 461                         if (is_return) {
 462                                 ainfo->storage = ArgValuetypeAddrInIReg;
 463                                 ainfo->offset = *stack_size;
 464                                 *stack_size += ALIGN_TO (info->native_size, 8);
 465                         }
 466                         else {
 467                                 ainfo->storage = ArgValuetypeAddrInIReg;
 468
 469                                 if (*gr < PARAM_REGS) {
 470                                         ainfo->pair_storage [0] = ArgInIReg;
 471                                         ainfo->pair_regs [0] = param_regs [*gr];
 472                                         (*gr) ++;
 473                                 }
 474                                 else {
 475                                         ainfo->pair_storage [0] = ArgOnStack;
 476                                         ainfo->offset = *stack_size;
 477                                         ainfo->arg_size = sizeof (mgreg_t);
 478                                         *stack_size += 8;
 479                                 }
 480                         }
 481
 482                         g_free (fields);
 483                         return;
 484                 }
 485
 486                 int size;
 487                 guint32 align;
 488                 ArgumentClass class1;
 489
 490                 if (nfields == 0)
 491                         class1 = ARG_CLASS_MEMORY;
 492                 else
 493                         class1 = ARG_CLASS_NO_CLASS;
 494                 for (i = 0; i < nfields; ++i) {
 495                         size = mono_marshal_type_size (fields [i].field->type,
 496                                                                                    fields [i].mspec,
 497                                                                                    &align, TRUE, klass->unicode);
 498                         /* How far into this quad this data extends.*/
 499                         /* (8 is size of quad) */
 500                         argsize = fields [i].offset + size;
 501
 502                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 503                 }
 504                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 505                 arg_class = class1;
 506         }
 507
 508         g_free (fields);
 509
 510         /* Allocate registers */
 511         {
 512                 int orig_gr = *gr;
 513                 int orig_fr = *fr;
 514
 515                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 516                         argsize ++;
 517
 518                 ainfo->storage = ArgValuetypeInReg;
 519                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 520                 ainfo->pair_size [0] = argsize;
 521                 ainfo->pair_size [1] = 0;
 522                 ainfo->nregs = 1;
 523                 switch (arg_class) {
 524                 case ARG_CLASS_INTEGER:
 525                         if (*gr >= PARAM_REGS)
 526                                 arg_class = ARG_CLASS_MEMORY;
 527                         else {
 528                                 ainfo->pair_storage [0] = ArgInIReg;
 529                                 if (is_return)
 530                                         ainfo->pair_regs [0] = return_regs [*gr];
 531                                 else
 532                                         ainfo->pair_regs [0] = param_regs [*gr];
 533                                 (*gr) ++;
 534                         }
 535                         break;
 536                 case ARG_CLASS_SSE:
 537                         if (*fr >= FLOAT_PARAM_REGS)
 538                                 arg_class = ARG_CLASS_MEMORY;
 539                         else {
 540                                 if (argsize <= 4)
 541                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 542                                 else
 543                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 544                                 ainfo->pair_regs [0] = *fr;
 545                                 (*fr) ++;
 546                         }
 547                         break;
 548                 case ARG_CLASS_MEMORY:
 549                         break;
 550                 default:
 551                         g_assert_not_reached ();
 552                 }
 553
 554                 if (arg_class == ARG_CLASS_MEMORY) {
 555                         /* Revert possible register assignments */
 556                         *gr = orig_gr;
 557                         *fr = orig_fr;
 558
 559                         ainfo->offset = *stack_size;
 560                         *stack_size += sizeof (mgreg_t);
 561                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 562                         if (!is_return)
 563                                 ainfo->arg_size = sizeof (mgreg_t);
 564                 }
 565         }
 566 }
 567 #endif /* TARGET_WIN32 */
 568
 569 static void
 570 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 571                            gboolean is_return,
 572                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 573 {
 574 #ifdef TARGET_WIN32
 575         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 576 #else
 577         guint32 size, quad, nquads, i, nfields;
 578         /* Keep track of the size used in each quad so we can */
 579         /* use the right size when copying args/return vars.  */
 580         guint32 quadsize [2] = {8, 8};
 581         ArgumentClass args [2];
 582         MonoMarshalType *info = NULL;
 583         MonoMarshalField *fields = NULL;
 584         MonoClass *klass;
 585         gboolean pass_on_stack = FALSE;
 586
 587         klass = mono_class_from_mono_type (type);
 588         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 589         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 590                 /* We pass and return vtypes of size 8 in a register */
 591         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 592                 pass_on_stack = TRUE;
 593         }
 594
 595         /* If this struct can't be split up naturally into 8-byte */
 596         /* chunks (registers), pass it on the stack.              */
 597         if (sig->pinvoke && !pass_on_stack) {
 598                 guint32 align;
 599                 guint32 field_size;
 600
 601                 info = mono_marshal_load_type_info (klass);
 602                 g_assert (info);
 603
 604                 /*
 605                  * Collect field information recursively to be able to
 606                  * handle nested structures.
 607                  */
 608                 nfields = count_fields_nested (klass);
 609                 fields = g_new0 (MonoMarshalField, nfields);
 610                 collect_field_info_nested (klass, fields, 0, 0);
 611
 612                 for (i = 0; i < nfields; ++i) {
 613                         field_size = mono_marshal_type_size (fields [i].field->type,
 614                                                            fields [i].mspec,
 615                                                            &align, TRUE, klass->unicode);
 616                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 617                                 pass_on_stack = TRUE;
 618                                 break;
 619                         }
 620                 }
 621         }
 622
 623         if (size == 0) {
 624                 ainfo->storage = ArgValuetypeInReg;
 625                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 626                 return;
 627         }
 628
 629         if (pass_on_stack) {
 630                 /* Allways pass in memory */
 631                 ainfo->offset = *stack_size;
 632                 *stack_size += ALIGN_TO (size, 8);
 633                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 634                 if (!is_return)
 635                         ainfo->arg_size = ALIGN_TO (size, 8);
 636
 637                 g_free (fields);
 638                 return;
 639         }
 640
 641         if (size > 8)
 642                 nquads = 2;
 643         else
 644                 nquads = 1;
 645
 646         if (!sig->pinvoke) {
 647                 int n = mono_class_value_size (klass, NULL);
 648
 649                 quadsize [0] = n >= 8 ? 8 : n;
 650                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 651
 652                 /* Always pass in 1 or 2 integer registers */
 653                 args [0] = ARG_CLASS_INTEGER;
 654                 args [1] = ARG_CLASS_INTEGER;
 655                 /* Only the simplest cases are supported */
 656                 if (is_return && nquads != 1) {
 657                         args [0] = ARG_CLASS_MEMORY;
 658                         args [1] = ARG_CLASS_MEMORY;
 659                 }
 660         } else {
 661                 /*
 662                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 663                  * The X87 and SSEUP stuff is left out since there are no such types in
 664                  * the CLR.
 665                  */
 666                 g_assert (info);
 667
 668                 if (!fields) {
 669                         ainfo->storage = ArgValuetypeInReg;
 670                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 671                         return;
 672                 }
 673
 674                 if (info->native_size > 16) {
 675                         ainfo->offset = *stack_size;
 676                         *stack_size += ALIGN_TO (info->native_size, 8);
 677                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 678                         if (!is_return)
 679                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
 680
 681                         g_free (fields);
 682                         return;
 683                 }
 684
 685                 args [0] = ARG_CLASS_NO_CLASS;
 686                 args [1] = ARG_CLASS_NO_CLASS;
 687                 for (quad = 0; quad < nquads; ++quad) {
 688                         int size;
 689                         guint32 align;
 690                         ArgumentClass class1;
 691
 692                         if (nfields == 0)
 693                                 class1 = ARG_CLASS_MEMORY;
 694                         else
 695                                 class1 = ARG_CLASS_NO_CLASS;
 696                         for (i = 0; i < nfields; ++i) {
 697                                 size = mono_marshal_type_size (fields [i].field->type,
 698                                                                                            fields [i].mspec,
 699                                                                                            &align, TRUE, klass->unicode);
 700                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 701                                         /* Unaligned field */
 702                                         NOT_IMPLEMENTED;
 703                                 }
 704
 705                                 /* Skip fields in other quad */
 706                                 if ((quad == 0) && (fields [i].offset >= 8))
 707                                         continue;
 708                                 if ((quad == 1) && (fields [i].offset < 8))
 709                                         continue;
 710
 711                                 /* How far into this quad this data extends.*/
 712                                 /* (8 is size of quad) */
 713                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 714
 715                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 716                         }
 717                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 718                         args [quad] = class1;
 719                 }
 720         }
 721
 722         g_free (fields);
 723
 724         /* Post merger cleanup */
 725         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 726                 args [0] = args [1] = ARG_CLASS_MEMORY;
 727
 728         /* Allocate registers */
 729         {
 730                 int orig_gr = *gr;
 731                 int orig_fr = *fr;
 732
 733                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 734                         quadsize [0] ++;
 735                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 736                         quadsize [1] ++;
 737
 738                 ainfo->storage = ArgValuetypeInReg;
 739                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 740                 g_assert (quadsize [0] <= 8);
 741                 g_assert (quadsize [1] <= 8);
 742                 ainfo->pair_size [0] = quadsize [0];
 743                 ainfo->pair_size [1] = quadsize [1];
 744                 ainfo->nregs = nquads;
 745                 for (quad = 0; quad < nquads; ++quad) {
 746                         switch (args [quad]) {
 747                         case ARG_CLASS_INTEGER:
 748                                 if (*gr >= PARAM_REGS)
 749                                         args [quad] = ARG_CLASS_MEMORY;
 750                                 else {
 751                                         ainfo->pair_storage [quad] = ArgInIReg;
 752                                         if (is_return)
 753                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 754                                         else
 755                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 756                                         (*gr) ++;
 757                                 }
 758                                 break;
 759                         case ARG_CLASS_SSE:
 760                                 if (*fr >= FLOAT_PARAM_REGS)
 761                                         args [quad] = ARG_CLASS_MEMORY;
 762                                 else {
 763                                         if (quadsize[quad] <= 4)
 764                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 765                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 766                                         ainfo->pair_regs [quad] = *fr;
 767                                         (*fr) ++;
 768                                 }
 769                                 break;
 770                         case ARG_CLASS_MEMORY:
 771                                 break;
 772                         default:
 773                                 g_assert_not_reached ();
 774                         }
 775                 }
 776
 777                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 778                         int arg_size;
 779                         /* Revert possible register assignments */
 780                         *gr = orig_gr;
 781                         *fr = orig_fr;
 782
 783                         ainfo->offset = *stack_size;
 784                         if (sig->pinvoke)
 785                                 arg_size = ALIGN_TO (info->native_size, 8);
 786                         else
 787                                 arg_size = nquads * sizeof(mgreg_t);
 788                         *stack_size += arg_size;
 789                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 790                         if (!is_return)
 791                                 ainfo->arg_size = arg_size;
 792                 }
 793         }
 794 #endif /* !TARGET_WIN32 */
 795 }
 796
 797 /*
 798  * get_call_info:
 799  *
 800  *  Obtain information about a call according to the calling convention.
 801  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 802  * Draft Version 0.23" document for more information.
 803  */
 804 static CallInfo*
 805 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 806 {
 807         guint32 i, gr, fr, pstart;
 808         MonoType *ret_type;
 809         int n = sig->hasthis + sig->param_count;
 810         guint32 stack_size = 0;
 811         CallInfo *cinfo;
 812         gboolean is_pinvoke = sig->pinvoke;
 813
 814         if (mp)
 815                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 816         else
 817                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 818
 819         cinfo->nargs = n;
 820         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 821
 822         gr = 0;
 823         fr = 0;
 824
 825 #ifdef TARGET_WIN32
 826         /* Reserve space where the callee can save the argument registers */
 827         stack_size = 4 * sizeof (mgreg_t);
 828 #endif
 829
 830         /* return value */
 831         ret_type = mini_get_underlying_type (sig->ret);
 832         switch (ret_type->type) {
 833         case MONO_TYPE_I1:
 834         case MONO_TYPE_U1:
 835         case MONO_TYPE_I2:
 836         case MONO_TYPE_U2:
 837         case MONO_TYPE_I4:
 838         case MONO_TYPE_U4:
 839         case MONO_TYPE_I:
 840         case MONO_TYPE_U:
 841         case MONO_TYPE_PTR:
 842         case MONO_TYPE_FNPTR:
 843         case MONO_TYPE_CLASS:
 844         case MONO_TYPE_OBJECT:
 845         case MONO_TYPE_SZARRAY:
 846         case MONO_TYPE_ARRAY:
 847         case MONO_TYPE_STRING:
 848                 cinfo->ret.storage = ArgInIReg;
 849                 cinfo->ret.reg = AMD64_RAX;
 850                 break;
 851         case MONO_TYPE_U8:
 852         case MONO_TYPE_I8:
 853                 cinfo->ret.storage = ArgInIReg;
 854                 cinfo->ret.reg = AMD64_RAX;
 855                 break;
 856         case MONO_TYPE_R4:
 857                 cinfo->ret.storage = ArgInFloatSSEReg;
 858                 cinfo->ret.reg = AMD64_XMM0;
 859                 break;
 860         case MONO_TYPE_R8:
 861                 cinfo->ret.storage = ArgInDoubleSSEReg;
 862                 cinfo->ret.reg = AMD64_XMM0;
 863                 break;
 864         case MONO_TYPE_GENERICINST:
 865                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 866                         cinfo->ret.storage = ArgInIReg;
 867                         cinfo->ret.reg = AMD64_RAX;
 868                         break;
 869                 }
 870                 if (mini_is_gsharedvt_type (ret_type)) {
 871                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 872                         break;
 873                 }
 874                 /* fall through */
 875         case MONO_TYPE_VALUETYPE:
 876         case MONO_TYPE_TYPEDBYREF: {
 877                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 878
 879                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 880                 g_assert (cinfo->ret.storage != ArgInIReg);
 881                 break;
 882         }
 883         case MONO_TYPE_VAR:
 884         case MONO_TYPE_MVAR:
 885                 g_assert (mini_is_gsharedvt_type (ret_type));
 886                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 887                 break;
 888         case MONO_TYPE_VOID:
 889                 break;
 890         default:
 891                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 892         }
 893
 894         pstart = 0;
 895         /*
 896          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 897          * the first argument, allowing 'this' to be always passed in the first arg reg.
 898          * Also do this if the first argument is a reference type, since virtual calls
 899          * are sometimes made using calli without sig->hasthis set, like in the delegate
 900          * invoke wrappers.
 901          */
 902         ArgStorage ret_storage = cinfo->ret.storage;
 903         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 904                 if (sig->hasthis) {
 905                         add_general (&gr, &stack_size, cinfo->args + 0);
 906                 } else {
 907                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 908                         pstart = 1;
 909                 }
 910                 add_general (&gr, &stack_size, &cinfo->ret);
 911                 cinfo->ret.storage = ret_storage;
 912                 cinfo->vret_arg_index = 1;
 913         } else {
 914                 /* this */
 915                 if (sig->hasthis)
 916                         add_general (&gr, &stack_size, cinfo->args + 0);
 917
 918                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 919                         add_general (&gr, &stack_size, &cinfo->ret);
 920                         cinfo->ret.storage = ret_storage;
 921                 }
 922         }
 923
 924         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 925                 gr = PARAM_REGS;
 926                 fr = FLOAT_PARAM_REGS;
 927
 928                 /* Emit the signature cookie just before the implicit arguments */
 929                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 930         }
 931
 932         for (i = pstart; i < sig->param_count; ++i) {
 933                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 934                 MonoType *ptype;
 935
 936 #ifdef TARGET_WIN32
 937                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 938                 if (gr > fr)
 939                         fr = gr;
 940                 else if (fr > gr)
 941                         gr = fr;
 942 #endif
 943
 944                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 945                         /* We allways pass the sig cookie on the stack for simplicity */
 946                         /*
 947                          * Prevent implicit arguments + the sig cookie from being passed
 948                          * in registers.
 949                          */
 950                         gr = PARAM_REGS;
 951                         fr = FLOAT_PARAM_REGS;
 952
 953                         /* Emit the signature cookie just before the implicit arguments */
 954                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 955                 }
 956
 957                 ptype = mini_get_underlying_type (sig->params [i]);
 958                 switch (ptype->type) {
 959                 case MONO_TYPE_I1:
 960                 case MONO_TYPE_U1:
 961                         add_general (&gr, &stack_size, ainfo);
 962                         break;
 963                 case MONO_TYPE_I2:
 964                 case MONO_TYPE_U2:
 965                         add_general (&gr, &stack_size, ainfo);
 966                         break;
 967                 case MONO_TYPE_I4:
 968                 case MONO_TYPE_U4:
 969                         add_general (&gr, &stack_size, ainfo);
 970                         break;
 971                 case MONO_TYPE_I:
 972                 case MONO_TYPE_U:
 973                 case MONO_TYPE_PTR:
 974                 case MONO_TYPE_FNPTR:
 975                 case MONO_TYPE_CLASS:
 976                 case MONO_TYPE_OBJECT:
 977                 case MONO_TYPE_STRING:
 978                 case MONO_TYPE_SZARRAY:
 979                 case MONO_TYPE_ARRAY:
 980                         add_general (&gr, &stack_size, ainfo);
 981                         break;
 982                 case MONO_TYPE_GENERICINST:
 983                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 984                                 add_general (&gr, &stack_size, ainfo);
 985                                 break;
 986                         }
 987                         if (mini_is_gsharedvt_variable_type (ptype)) {
 988                                 /* gsharedvt arguments are passed by ref */
 989                                 add_general (&gr, &stack_size, ainfo);
 990                                 if (ainfo->storage == ArgInIReg)
 991                                         ainfo->storage = ArgGSharedVtInReg;
 992                                 else
 993                                         ainfo->storage = ArgGSharedVtOnStack;
 994                                 break;
 995                         }
 996                         /* fall through */
 997                 case MONO_TYPE_VALUETYPE:
 998                 case MONO_TYPE_TYPEDBYREF:
 999                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1000                         break;
1001                 case MONO_TYPE_U8:
1002
1003                 case MONO_TYPE_I8:
1004                         add_general (&gr, &stack_size, ainfo);
1005                         break;
1006                 case MONO_TYPE_R4:
1007                         add_float (&fr, &stack_size, ainfo, FALSE);
1008                         break;
1009                 case MONO_TYPE_R8:
1010                         add_float (&fr, &stack_size, ainfo, TRUE);
1011                         break;
1012                 case MONO_TYPE_VAR:
1013                 case MONO_TYPE_MVAR:
1014                         /* gsharedvt arguments are passed by ref */
1015                         g_assert (mini_is_gsharedvt_type (ptype));
1016                         add_general (&gr, &stack_size, ainfo);
1017                         if (ainfo->storage == ArgInIReg)
1018                                 ainfo->storage = ArgGSharedVtInReg;
1019                         else
1020                                 ainfo->storage = ArgGSharedVtOnStack;
1021                         break;
1022                 default:
1023                         g_assert_not_reached ();
1024                 }
1025         }
1026
1027         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1028                 gr = PARAM_REGS;
1029                 fr = FLOAT_PARAM_REGS;
1030
1031                 /* Emit the signature cookie just before the implicit arguments */
1032                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1033         }
1034
1035         cinfo->stack_usage = stack_size;
1036         cinfo->reg_usage = gr;
1037         cinfo->freg_usage = fr;
1038         return cinfo;
1039 }
1040
1041 /*
1042  * mono_arch_get_argument_info:
1043  * @csig:  a method signature
1044  * @param_count: the number of parameters to consider
1045  * @arg_info: an array to store the result infos
1046  *
1047  * Gathers information on parameters such as size, alignment and
1048  * padding. arg_info should be large enought to hold param_count + 1 entries.
1049  *
1050  * Returns the size of the argument area on the stack.
1051  */
1052 int
1053 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1054 {
1055         int k;
1056         CallInfo *cinfo = get_call_info (NULL, csig);
1057         guint32 args_size = cinfo->stack_usage;
1058
1059         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1060         if (csig->hasthis) {
1061                 arg_info [0].offset = 0;
1062         }
1063
1064         for (k = 0; k < param_count; k++) {
1065                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1066                 /* FIXME: */
1067                 arg_info [k + 1].size = 0;
1068         }
1069
1070         g_free (cinfo);
1071
1072         return args_size;
1073 }
1074
1075 gboolean
1076 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1077 {
1078         CallInfo *c1, *c2;
1079         gboolean res;
1080         MonoType *callee_ret;
1081
1082         c1 = get_call_info (NULL, caller_sig);
1083         c2 = get_call_info (NULL, callee_sig);
1084         res = c1->stack_usage >= c2->stack_usage;
1085         callee_ret = mini_get_underlying_type (callee_sig->ret);
1086         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1087                 /* An address on the callee's stack is passed as the first argument */
1088                 res = FALSE;
1089
1090         g_free (c1);
1091         g_free (c2);
1092
1093         return res;
1094 }
1095
1096 /*
1097  * Initialize the cpu to execute managed code.
1098  */
1099 void
1100 mono_arch_cpu_init (void)
1101 {
1102 #ifndef _MSC_VER
1103         guint16 fpcw;
1104
1105         /* spec compliance requires running with double precision */
1106         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1107         fpcw &= ~X86_FPCW_PRECC_MASK;
1108         fpcw |= X86_FPCW_PREC_DOUBLE;
1109         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1110         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1111 #else
1112         /* TODO: This is crashing on Win64 right now.
1113         * _control87 (_PC_53, MCW_PC);
1114         */
1115 #endif
1116 }
1117
1118 /*
1119  * Initialize architecture specific code.
1120  */
1121 void
1122 mono_arch_init (void)
1123 {
1124         mono_os_mutex_init_recursive (&mini_arch_mutex);
1125
1126         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1127         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1128         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1129         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1130 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1131         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1132 #endif
1133
1134         if (!mono_aot_only)
1135                 bp_trampoline = mini_get_breakpoint_trampoline ();
1136 }
1137
1138 /*
1139  * Cleanup architecture specific code.
1140  */
1141 void
1142 mono_arch_cleanup (void)
1143 {
1144         mono_os_mutex_destroy (&mini_arch_mutex);
1145 }
1146
1147 /*
1148  * This function returns the optimizations supported on this cpu.
1149  */
1150 guint32
1151 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1152 {
1153         guint32 opts = 0;
1154
1155         *exclude_mask = 0;
1156
1157         if (mono_hwcap_x86_has_cmov) {
1158                 opts |= MONO_OPT_CMOV;
1159
1160                 if (mono_hwcap_x86_has_fcmov)
1161                         opts |= MONO_OPT_FCMOV;
1162                 else
1163                         *exclude_mask |= MONO_OPT_FCMOV;
1164         } else {
1165                 *exclude_mask |= MONO_OPT_CMOV;
1166         }
1167
1168         return opts;
1169 }
1170
1171 /*
1172  * This function test for all SSE functions supported.
1173  *
1174  * Returns a bitmask corresponding to all supported versions.
1175  *
1176  */
1177 guint32
1178 mono_arch_cpu_enumerate_simd_versions (void)
1179 {
1180         guint32 sse_opts = 0;
1181
1182         if (mono_hwcap_x86_has_sse1)
1183                 sse_opts |= SIMD_VERSION_SSE1;
1184
1185         if (mono_hwcap_x86_has_sse2)
1186                 sse_opts |= SIMD_VERSION_SSE2;
1187
1188         if (mono_hwcap_x86_has_sse3)
1189                 sse_opts |= SIMD_VERSION_SSE3;
1190
1191         if (mono_hwcap_x86_has_ssse3)
1192                 sse_opts |= SIMD_VERSION_SSSE3;
1193
1194         if (mono_hwcap_x86_has_sse41)
1195                 sse_opts |= SIMD_VERSION_SSE41;
1196
1197         if (mono_hwcap_x86_has_sse42)
1198                 sse_opts |= SIMD_VERSION_SSE42;
1199
1200         if (mono_hwcap_x86_has_sse4a)
1201                 sse_opts |= SIMD_VERSION_SSE4a;
1202
1203         return sse_opts;
1204 }
1205
1206 #ifndef DISABLE_JIT
1207
1208 GList *
1209 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1210 {
1211         GList *vars = NULL;
1212         int i;
1213
1214         for (i = 0; i < cfg->num_varinfo; i++) {
1215                 MonoInst *ins = cfg->varinfo [i];
1216                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1217
1218                 /* unused vars */
1219                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1220                         continue;
1221
1222                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1223                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1224                         continue;
1225
1226                 if (mono_is_regsize_var (ins->inst_vtype)) {
1227                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1228                         g_assert (i == vmv->idx);
1229                         vars = g_list_prepend (vars, vmv);
1230                 }
1231         }
1232
1233         vars = mono_varlist_sort (cfg, vars, 0);
1234
1235         return vars;
1236 }
1237
1238 /**
1239  * mono_arch_compute_omit_fp:
1240  *
1241  *   Determine whenever the frame pointer can be eliminated.
1242  */
1243 static void
1244 mono_arch_compute_omit_fp (MonoCompile *cfg)
1245 {
1246         MonoMethodSignature *sig;
1247         MonoMethodHeader *header;
1248         int i, locals_size;
1249         CallInfo *cinfo;
1250
1251         if (cfg->arch.omit_fp_computed)
1252                 return;
1253
1254         header = cfg->header;
1255
1256         sig = mono_method_signature (cfg->method);
1257
1258         if (!cfg->arch.cinfo)
1259                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1260         cinfo = (CallInfo *)cfg->arch.cinfo;
1261
1262         /*
1263          * FIXME: Remove some of the restrictions.
1264          */
1265         cfg->arch.omit_fp = TRUE;
1266         cfg->arch.omit_fp_computed = TRUE;
1267
1268         if (cfg->disable_omit_fp)
1269                 cfg->arch.omit_fp = FALSE;
1270
1271         if (!debug_omit_fp ())
1272                 cfg->arch.omit_fp = FALSE;
1273         /*
1274         if (cfg->method->save_lmf)
1275                 cfg->arch.omit_fp = FALSE;
1276         */
1277         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1278                 cfg->arch.omit_fp = FALSE;
1279         if (header->num_clauses)
1280                 cfg->arch.omit_fp = FALSE;
1281         if (cfg->param_area)
1282                 cfg->arch.omit_fp = FALSE;
1283         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1284                 cfg->arch.omit_fp = FALSE;
1285         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1286                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1287                 cfg->arch.omit_fp = FALSE;
1288         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1289                 ArgInfo *ainfo = &cinfo->args [i];
1290
1291                 if (ainfo->storage == ArgOnStack) {
1292                         /*
1293                          * The stack offset can only be determined when the frame
1294                          * size is known.
1295                          */
1296                         cfg->arch.omit_fp = FALSE;
1297                 }
1298         }
1299
1300         locals_size = 0;
1301         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1302                 MonoInst *ins = cfg->varinfo [i];
1303                 int ialign;
1304
1305                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1306         }
1307 }
1308
1309 GList *
1310 mono_arch_get_global_int_regs (MonoCompile *cfg)
1311 {
1312         GList *regs = NULL;
1313
1314         mono_arch_compute_omit_fp (cfg);
1315
1316         if (cfg->arch.omit_fp)
1317                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1318
1319         /* We use the callee saved registers for global allocation */
1320         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1321         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1322         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1323         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1324         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1325 #ifdef TARGET_WIN32
1326         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1327         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1328 #endif
1329
1330         return regs;
1331 }
1332
1333 GList*
1334 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1335 {
1336         GList *regs = NULL;
1337         int i;
1338
1339         /* All XMM registers */
1340         for (i = 0; i < 16; ++i)
1341                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1342
1343         return regs;
1344 }
1345
1346 GList*
1347 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1348 {
1349         static GList *r = NULL;
1350
1351         if (r == NULL) {
1352                 GList *regs = NULL;
1353
1354                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1355                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1356                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1357                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1358                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1359                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1360
1361                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1362                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1363                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1364                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1365                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1366                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1367                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1368                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1369
1370                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1371         }
1372
1373         return r;
1374 }
1375
1376 GList*
1377 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1378 {
1379         int i;
1380         static GList *r = NULL;
1381
1382         if (r == NULL) {
1383                 GList *regs = NULL;
1384
1385                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1386                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1387
1388                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1389         }
1390
1391         return r;
1392 }
1393
1394 /*
1395  * mono_arch_regalloc_cost:
1396  *
1397  *  Return the cost, in number of memory references, of the action of
1398  * allocating the variable VMV into a register during global register
1399  * allocation.
1400  */
1401 guint32
1402 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1403 {
1404         MonoInst *ins = cfg->varinfo [vmv->idx];
1405
1406         if (cfg->method->save_lmf)
1407                 /* The register is already saved */
1408                 /* substract 1 for the invisible store in the prolog */
1409                 return (ins->opcode == OP_ARG) ? 0 : 1;
1410         else
1411                 /* push+pop */
1412                 return (ins->opcode == OP_ARG) ? 1 : 2;
1413 }
1414
1415 /*
1416  * mono_arch_fill_argument_info:
1417  *
1418  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1419  * of the method.
1420  */
1421 void
1422 mono_arch_fill_argument_info (MonoCompile *cfg)
1423 {
1424         MonoType *sig_ret;
1425         MonoMethodSignature *sig;
1426         MonoInst *ins;
1427         int i;
1428         CallInfo *cinfo;
1429
1430         sig = mono_method_signature (cfg->method);
1431
1432         cinfo = (CallInfo *)cfg->arch.cinfo;
1433         sig_ret = mini_get_underlying_type (sig->ret);
1434
1435         /*
1436          * Contrary to mono_arch_allocate_vars (), the information should describe
1437          * where the arguments are at the beginning of the method, not where they can be
1438          * accessed during the execution of the method. The later makes no sense for the
1439          * global register allocator, since a variable can be in more than one location.
1440          */
1441         switch (cinfo->ret.storage) {
1442         case ArgInIReg:
1443         case ArgInFloatSSEReg:
1444         case ArgInDoubleSSEReg:
1445                 cfg->ret->opcode = OP_REGVAR;
1446                 cfg->ret->inst_c0 = cinfo->ret.reg;
1447                 break;
1448         case ArgValuetypeInReg:
1449                 cfg->ret->opcode = OP_REGOFFSET;
1450                 cfg->ret->inst_basereg = -1;
1451                 cfg->ret->inst_offset = -1;
1452                 break;
1453         case ArgNone:
1454                 break;
1455         default:
1456                 g_assert_not_reached ();
1457         }
1458
1459         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1460                 ArgInfo *ainfo = &cinfo->args [i];
1461
1462                 ins = cfg->args [i];
1463
1464                 switch (ainfo->storage) {
1465                 case ArgInIReg:
1466                 case ArgInFloatSSEReg:
1467                 case ArgInDoubleSSEReg:
1468                         ins->opcode = OP_REGVAR;
1469                         ins->inst_c0 = ainfo->reg;
1470                         break;
1471                 case ArgOnStack:
1472                         ins->opcode = OP_REGOFFSET;
1473                         ins->inst_basereg = -1;
1474                         ins->inst_offset = -1;
1475                         break;
1476                 case ArgValuetypeInReg:
1477                         /* Dummy */
1478                         ins->opcode = OP_NOP;
1479                         break;
1480                 default:
1481                         g_assert_not_reached ();
1482                 }
1483         }
1484 }
1485
1486 void
1487 mono_arch_allocate_vars (MonoCompile *cfg)
1488 {
1489         MonoType *sig_ret;
1490         MonoMethodSignature *sig;
1491         MonoInst *ins;
1492         int i, offset;
1493         guint32 locals_stack_size, locals_stack_align;
1494         gint32 *offsets;
1495         CallInfo *cinfo;
1496
1497         sig = mono_method_signature (cfg->method);
1498
1499         cinfo = (CallInfo *)cfg->arch.cinfo;
1500         sig_ret = mini_get_underlying_type (sig->ret);
1501
1502         mono_arch_compute_omit_fp (cfg);
1503
1504         /*
1505          * We use the ABI calling conventions for managed code as well.
1506          * Exception: valuetypes are only sometimes passed or returned in registers.
1507          */
1508
1509         /*
1510          * The stack looks like this:
1511          * <incoming arguments passed on the stack>
1512          * <return value>
1513          * <lmf/caller saved registers>
1514          * <locals>
1515          * <spill area>
1516          * <localloc area>  -> grows dynamically
1517          * <params area>
1518          */
1519
1520         if (cfg->arch.omit_fp) {
1521                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1522                 cfg->frame_reg = AMD64_RSP;
1523                 offset = 0;
1524         } else {
1525                 /* Locals are allocated backwards from %fp */
1526                 cfg->frame_reg = AMD64_RBP;
1527                 offset = 0;
1528         }
1529
1530         cfg->arch.saved_iregs = cfg->used_int_regs;
1531         if (cfg->method->save_lmf)
1532                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1533                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1534
1535         if (cfg->arch.omit_fp)
1536                 cfg->arch.reg_save_area_offset = offset;
1537         /* Reserve space for callee saved registers */
1538         for (i = 0; i < AMD64_NREG; ++i)
1539                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1540                         offset += sizeof(mgreg_t);
1541                 }
1542         if (!cfg->arch.omit_fp)
1543                 cfg->arch.reg_save_area_offset = -offset;
1544
1545         if (sig_ret->type != MONO_TYPE_VOID) {
1546                 switch (cinfo->ret.storage) {
1547                 case ArgInIReg:
1548                 case ArgInFloatSSEReg:
1549                 case ArgInDoubleSSEReg:
1550                         cfg->ret->opcode = OP_REGVAR;
1551                         cfg->ret->inst_c0 = cinfo->ret.reg;
1552                         cfg->ret->dreg = cinfo->ret.reg;
1553                         break;
1554                 case ArgValuetypeAddrInIReg:
1555                 case ArgGsharedvtVariableInReg:
1556                         /* The register is volatile */
1557                         cfg->vret_addr->opcode = OP_REGOFFSET;
1558                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1559                         if (cfg->arch.omit_fp) {
1560                                 cfg->vret_addr->inst_offset = offset;
1561                                 offset += 8;
1562                         } else {
1563                                 offset += 8;
1564                                 cfg->vret_addr->inst_offset = -offset;
1565                         }
1566                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1567                                 printf ("vret_addr =");
1568                                 mono_print_ins (cfg->vret_addr);
1569                         }
1570                         break;
1571                 case ArgValuetypeInReg:
1572                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1573                         cfg->ret->opcode = OP_REGOFFSET;
1574                         cfg->ret->inst_basereg = cfg->frame_reg;
1575                         if (cfg->arch.omit_fp) {
1576                                 cfg->ret->inst_offset = offset;
1577                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1578                         } else {
1579                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1580                                 cfg->ret->inst_offset = - offset;
1581                         }
1582                         break;
1583                 default:
1584                         g_assert_not_reached ();
1585                 }
1586         }
1587
1588         /* Allocate locals */
1589         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1590         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1591                 char *mname = mono_method_full_name (cfg->method, TRUE);
1592                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1593                 g_free (mname);
1594                 return;
1595         }
1596
1597         if (locals_stack_align) {
1598                 offset += (locals_stack_align - 1);
1599                 offset &= ~(locals_stack_align - 1);
1600         }
1601         if (cfg->arch.omit_fp) {
1602                 cfg->locals_min_stack_offset = offset;
1603                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1604         } else {
1605                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1606                 cfg->locals_max_stack_offset = - offset;
1607         }
1608
1609         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1610                 if (offsets [i] != -1) {
1611                         MonoInst *ins = cfg->varinfo [i];
1612                         ins->opcode = OP_REGOFFSET;
1613                         ins->inst_basereg = cfg->frame_reg;
1614                         if (cfg->arch.omit_fp)
1615                                 ins->inst_offset = (offset + offsets [i]);
1616                         else
1617                                 ins->inst_offset = - (offset + offsets [i]);
1618                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1619                 }
1620         }
1621         offset += locals_stack_size;
1622
1623         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1624                 g_assert (!cfg->arch.omit_fp);
1625                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1626                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1627         }
1628
1629         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1630                 ins = cfg->args [i];
1631                 if (ins->opcode != OP_REGVAR) {
1632                         ArgInfo *ainfo = &cinfo->args [i];
1633                         gboolean inreg = TRUE;
1634
1635                         /* FIXME: Allocate volatile arguments to registers */
1636                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1637                                 inreg = FALSE;
1638
1639                         /*
1640                          * Under AMD64, all registers used to pass arguments to functions
1641                          * are volatile across calls.
1642                          * FIXME: Optimize this.
1643                          */
1644                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1645                                 inreg = FALSE;
1646
1647                         ins->opcode = OP_REGOFFSET;
1648
1649                         switch (ainfo->storage) {
1650                         case ArgInIReg:
1651                         case ArgInFloatSSEReg:
1652                         case ArgInDoubleSSEReg:
1653                         case ArgGSharedVtInReg:
1654                                 if (inreg) {
1655                                         ins->opcode = OP_REGVAR;
1656                                         ins->dreg = ainfo->reg;
1657                                 }
1658                                 break;
1659                         case ArgOnStack:
1660                         case ArgGSharedVtOnStack:
1661                                 g_assert (!cfg->arch.omit_fp);
1662                                 ins->opcode = OP_REGOFFSET;
1663                                 ins->inst_basereg = cfg->frame_reg;
1664                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1665                                 break;
1666                         case ArgValuetypeInReg:
1667                                 break;
1668                         case ArgValuetypeAddrInIReg: {
1669                                 MonoInst *indir;
1670                                 g_assert (!cfg->arch.omit_fp);
1671
1672                                 MONO_INST_NEW (cfg, indir, 0);
1673                                 indir->opcode = OP_REGOFFSET;
1674                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1675                                         indir->inst_basereg = cfg->frame_reg;
1676                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1677                                         offset += (sizeof (gpointer));
1678                                         indir->inst_offset = - offset;
1679                                 }
1680                                 else {
1681                                         indir->inst_basereg = cfg->frame_reg;
1682                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1683                                 }
1684
1685                                 ins->opcode = OP_VTARG_ADDR;
1686                                 ins->inst_left = indir;
1687
1688                                 break;
1689                         }
1690                         default:
1691                                 NOT_IMPLEMENTED;
1692                         }
1693
1694                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
1695                                 ins->opcode = OP_REGOFFSET;
1696                                 ins->inst_basereg = cfg->frame_reg;
1697                                 /* These arguments are saved to the stack in the prolog */
1698                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1699                                 if (cfg->arch.omit_fp) {
1700                                         ins->inst_offset = offset;
1701                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1702                                         // Arguments are yet supported by the stack map creation code
1703                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1704                                 } else {
1705                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1706                                         ins->inst_offset = - offset;
1707                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1708                                 }
1709                         }
1710                 }
1711         }
1712
1713         cfg->stack_offset = offset;
1714 }
1715
1716 void
1717 mono_arch_create_vars (MonoCompile *cfg)
1718 {
1719         MonoMethodSignature *sig;
1720         CallInfo *cinfo;
1721         MonoType *sig_ret;
1722
1723         sig = mono_method_signature (cfg->method);
1724
1725         if (!cfg->arch.cinfo)
1726                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1727         cinfo = (CallInfo *)cfg->arch.cinfo;
1728
1729         if (cinfo->ret.storage == ArgValuetypeInReg)
1730                 cfg->ret_var_is_local = TRUE;
1731
1732         sig_ret = mini_get_underlying_type (sig->ret);
1733         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1734                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1735                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1736                         printf ("vret_addr = ");
1737                         mono_print_ins (cfg->vret_addr);
1738                 }
1739         }
1740
1741         if (cfg->gen_sdb_seq_points) {
1742                 MonoInst *ins;
1743
1744                 if (cfg->compile_aot) {
1745                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1746                         ins->flags |= MONO_INST_VOLATILE;
1747                         cfg->arch.seq_point_info_var = ins;
1748                 }
1749                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1750                 ins->flags |= MONO_INST_VOLATILE;
1751                 cfg->arch.ss_tramp_var = ins;
1752
1753                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1754                 ins->flags |= MONO_INST_VOLATILE;
1755                 cfg->arch.bp_tramp_var = ins;
1756         }
1757
1758         if (cfg->method->save_lmf)
1759                 cfg->create_lmf_var = TRUE;
1760
1761         if (cfg->method->save_lmf) {
1762                 cfg->lmf_ir = TRUE;
1763 #if !defined(TARGET_WIN32)
1764                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1765                         cfg->lmf_ir_mono_lmf = TRUE;
1766 #endif
1767         }
1768 }
1769
1770 static void
1771 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1772 {
1773         MonoInst *ins;
1774
1775         switch (storage) {
1776         case ArgInIReg:
1777                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1778                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1779                 ins->sreg1 = tree->dreg;
1780                 MONO_ADD_INS (cfg->cbb, ins);
1781                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1782                 break;
1783         case ArgInFloatSSEReg:
1784                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1785                 ins->dreg = mono_alloc_freg (cfg);
1786                 ins->sreg1 = tree->dreg;
1787                 MONO_ADD_INS (cfg->cbb, ins);
1788
1789                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1790                 break;
1791         case ArgInDoubleSSEReg:
1792                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1793                 ins->dreg = mono_alloc_freg (cfg);
1794                 ins->sreg1 = tree->dreg;
1795                 MONO_ADD_INS (cfg->cbb, ins);
1796
1797                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1798
1799                 break;
1800         default:
1801                 g_assert_not_reached ();
1802         }
1803 }
1804
1805 static int
1806 arg_storage_to_load_membase (ArgStorage storage)
1807 {
1808         switch (storage) {
1809         case ArgInIReg:
1810 #if defined(__mono_ilp32__)
1811                 return OP_LOADI8_MEMBASE;
1812 #else
1813                 return OP_LOAD_MEMBASE;
1814 #endif
1815         case ArgInDoubleSSEReg:
1816                 return OP_LOADR8_MEMBASE;
1817         case ArgInFloatSSEReg:
1818                 return OP_LOADR4_MEMBASE;
1819         default:
1820                 g_assert_not_reached ();
1821         }
1822
1823         return -1;
1824 }
1825
1826 static void
1827 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1828 {
1829         MonoMethodSignature *tmp_sig;
1830         int sig_reg;
1831
1832         if (call->tail_call)
1833                 NOT_IMPLEMENTED;
1834
1835         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1836
1837         /*
1838          * mono_ArgIterator_Setup assumes the signature cookie is
1839          * passed first and all the arguments which were before it are
1840          * passed on the stack after the signature. So compensate by
1841          * passing a different signature.
1842          */
1843         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1844         tmp_sig->param_count -= call->signature->sentinelpos;
1845         tmp_sig->sentinelpos = 0;
1846         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1847
1848         sig_reg = mono_alloc_ireg (cfg);
1849         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1850
1851         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1852 }
1853
1854 #ifdef ENABLE_LLVM
1855 static inline LLVMArgStorage
1856 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1857 {
1858         switch (storage) {
1859         case ArgInIReg:
1860                 return LLVMArgInIReg;
1861         case ArgNone:
1862                 return LLVMArgNone;
1863         case ArgGSharedVtInReg:
1864         case ArgGSharedVtOnStack:
1865                 return LLVMArgGSharedVt;
1866         default:
1867                 g_assert_not_reached ();
1868                 return LLVMArgNone;
1869         }
1870 }
1871
1872 LLVMCallInfo*
1873 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1874 {
1875         int i, n;
1876         CallInfo *cinfo;
1877         ArgInfo *ainfo;
1878         int j;
1879         LLVMCallInfo *linfo;
1880         MonoType *t, *sig_ret;
1881
1882         n = sig->param_count + sig->hasthis;
1883         sig_ret = mini_get_underlying_type (sig->ret);
1884
1885         cinfo = get_call_info (cfg->mempool, sig);
1886
1887         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1888
1889         /*
1890          * LLVM always uses the native ABI while we use our own ABI, the
1891          * only difference is the handling of vtypes:
1892          * - we only pass/receive them in registers in some cases, and only
1893          *   in 1 or 2 integer registers.
1894          */
1895         switch (cinfo->ret.storage) {
1896         case ArgNone:
1897                 linfo->ret.storage = LLVMArgNone;
1898                 break;
1899         case ArgInIReg:
1900         case ArgInFloatSSEReg:
1901         case ArgInDoubleSSEReg:
1902                 linfo->ret.storage = LLVMArgNormal;
1903                 break;
1904         case ArgValuetypeInReg: {
1905                 ainfo = &cinfo->ret;
1906
1907                 if (sig->pinvoke &&
1908                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1909                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1910                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1911                         cfg->disable_llvm = TRUE;
1912                         return linfo;
1913                 }
1914
1915                 linfo->ret.storage = LLVMArgVtypeInReg;
1916                 for (j = 0; j < 2; ++j)
1917                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1918                 break;
1919         }
1920         case ArgValuetypeAddrInIReg:
1921         case ArgGsharedvtVariableInReg:
1922                 /* Vtype returned using a hidden argument */
1923                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1924                 linfo->vret_arg_index = cinfo->vret_arg_index;
1925                 break;
1926         default:
1927                 g_assert_not_reached ();
1928                 break;
1929         }
1930
1931         for (i = 0; i < n; ++i) {
1932                 ainfo = cinfo->args + i;
1933
1934                 if (i >= sig->hasthis)
1935                         t = sig->params [i - sig->hasthis];
1936                 else
1937                         t = &mono_defaults.int_class->byval_arg;
1938
1939                 linfo->args [i].storage = LLVMArgNone;
1940
1941                 switch (ainfo->storage) {
1942                 case ArgInIReg:
1943                         linfo->args [i].storage = LLVMArgNormal;
1944                         break;
1945                 case ArgInDoubleSSEReg:
1946                 case ArgInFloatSSEReg:
1947                         linfo->args [i].storage = LLVMArgNormal;
1948                         break;
1949                 case ArgOnStack:
1950                         if (MONO_TYPE_ISSTRUCT (t))
1951                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1952                         else
1953                                 linfo->args [i].storage = LLVMArgNormal;
1954                         break;
1955                 case ArgValuetypeInReg:
1956                         if (sig->pinvoke &&
1957                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1958                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1959                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1960                                 cfg->disable_llvm = TRUE;
1961                                 return linfo;
1962                         }
1963
1964                         linfo->args [i].storage = LLVMArgVtypeInReg;
1965                         for (j = 0; j < 2; ++j)
1966                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1967                         break;
1968                 case ArgGSharedVtInReg:
1969                 case ArgGSharedVtOnStack:
1970                         linfo->args [i].storage = LLVMArgGSharedVt;
1971                         break;
1972                 default:
1973                         cfg->exception_message = g_strdup ("ainfo->storage");
1974                         cfg->disable_llvm = TRUE;
1975                         break;
1976                 }
1977         }
1978
1979         return linfo;
1980 }
1981 #endif
1982
1983 void
1984 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1985 {
1986         MonoInst *arg, *in;
1987         MonoMethodSignature *sig;
1988         MonoType *sig_ret;
1989         int i, n;
1990         CallInfo *cinfo;
1991         ArgInfo *ainfo;
1992
1993         sig = call->signature;
1994         n = sig->param_count + sig->hasthis;
1995
1996         cinfo = get_call_info (cfg->mempool, sig);
1997
1998         sig_ret = sig->ret;
1999
2000         if (COMPILE_LLVM (cfg)) {
2001                 /* We shouldn't be called in the llvm case */
2002                 cfg->disable_llvm = TRUE;
2003                 return;
2004         }
2005
2006         /*
2007          * Emit all arguments which are passed on the stack to prevent register
2008          * allocation problems.
2009          */
2010         for (i = 0; i < n; ++i) {
2011                 MonoType *t;
2012                 ainfo = cinfo->args + i;
2013
2014                 in = call->args [i];
2015
2016                 if (sig->hasthis && i == 0)
2017                         t = &mono_defaults.object_class->byval_arg;
2018                 else
2019                         t = sig->params [i - sig->hasthis];
2020
2021                 t = mini_get_underlying_type (t);
2022                 //XXX what about ArgGSharedVtOnStack here?
2023                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2024                         if (!t->byref) {
2025                                 if (t->type == MONO_TYPE_R4)
2026                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2027                                 else if (t->type == MONO_TYPE_R8)
2028                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2029                                 else
2030                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2031                         } else {
2032                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2033                         }
2034                         if (cfg->compute_gc_maps) {
2035                                 MonoInst *def;
2036
2037                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2038                         }
2039                 }
2040         }
2041
2042         /*
2043          * Emit all parameters passed in registers in non-reverse order for better readability
2044          * and to help the optimization in emit_prolog ().
2045          */
2046         for (i = 0; i < n; ++i) {
2047                 ainfo = cinfo->args + i;
2048
2049                 in = call->args [i];
2050
2051                 if (ainfo->storage == ArgInIReg)
2052                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2053         }
2054
2055         for (i = n - 1; i >= 0; --i) {
2056                 MonoType *t;
2057
2058                 ainfo = cinfo->args + i;
2059
2060                 in = call->args [i];
2061
2062                 if (sig->hasthis && i == 0)
2063                         t = &mono_defaults.object_class->byval_arg;
2064                 else
2065                         t = sig->params [i - sig->hasthis];
2066                 t = mini_get_underlying_type (t);
2067
2068                 switch (ainfo->storage) {
2069                 case ArgInIReg:
2070                         /* Already done */
2071                         break;
2072                 case ArgInFloatSSEReg:
2073                 case ArgInDoubleSSEReg:
2074                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2075                         break;
2076                 case ArgOnStack:
2077                 case ArgValuetypeInReg:
2078                 case ArgValuetypeAddrInIReg:
2079                 case ArgGSharedVtInReg:
2080                 case ArgGSharedVtOnStack: {
2081                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2082                                 /* Already emitted above */
2083                                 break;
2084                         //FIXME what about ArgGSharedVtOnStack ?
2085                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2086                                 MonoInst *call_inst = (MonoInst*)call;
2087                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2088                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2089                                 break;
2090                         }
2091
2092                         guint32 align;
2093                         guint32 size;
2094
2095                         if (sig->pinvoke)
2096                                 size = mono_type_native_stack_size (t, &align);
2097                         else {
2098                                 /*
2099                                  * Other backends use mono_type_stack_size (), but that
2100                                  * aligns the size to 8, which is larger than the size of
2101                                  * the source, leading to reads of invalid memory if the
2102                                  * source is at the end of address space.
2103                                  */
2104                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2105                         }
2106
2107                         if (size >= 10000) {
2108                                 /* Avoid asserts in emit_memcpy () */
2109                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2110                                 /* Continue normally */
2111                         }
2112
2113                         if (size > 0) {
2114                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2115                                 arg->sreg1 = in->dreg;
2116                                 arg->klass = mono_class_from_mono_type (t);
2117                                 arg->backend.size = size;
2118                                 arg->inst_p0 = call;
2119                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2120                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2121
2122                                 MONO_ADD_INS (cfg->cbb, arg);
2123                         }
2124                         break;
2125                 }
2126                 default:
2127                         g_assert_not_reached ();
2128                 }
2129
2130                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2131                         /* Emit the signature cookie just before the implicit arguments */
2132                         emit_sig_cookie (cfg, call, cinfo);
2133         }
2134
2135         /* Handle the case where there are no implicit arguments */
2136         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2137                 emit_sig_cookie (cfg, call, cinfo);
2138
2139         switch (cinfo->ret.storage) {
2140         case ArgValuetypeInReg:
2141                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2142                         /*
2143                          * Tell the JIT to use a more efficient calling convention: call using
2144                          * OP_CALL, compute the result location after the call, and save the
2145                          * result there.
2146                          */
2147                         call->vret_in_reg = TRUE;
2148                         /*
2149                          * Nullify the instruction computing the vret addr to enable
2150                          * future optimizations.
2151                          */
2152                         if (call->vret_var)
2153                                 NULLIFY_INS (call->vret_var);
2154                 } else {
2155                         if (call->tail_call)
2156                                 NOT_IMPLEMENTED;
2157                         /*
2158                          * The valuetype is in RAX:RDX after the call, need to be copied to
2159                          * the stack. Push the address here, so the call instruction can
2160                          * access it.
2161                          */
2162                         if (!cfg->arch.vret_addr_loc) {
2163                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2164                                 /* Prevent it from being register allocated or optimized away */
2165                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2166                         }
2167
2168                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2169                 }
2170                 break;
2171         case ArgValuetypeAddrInIReg:
2172         case ArgGsharedvtVariableInReg: {
2173                 MonoInst *vtarg;
2174                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2175                 vtarg->sreg1 = call->vret_var->dreg;
2176                 vtarg->dreg = mono_alloc_preg (cfg);
2177                 MONO_ADD_INS (cfg->cbb, vtarg);
2178
2179                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2180                 break;
2181         }
2182         default:
2183                 break;
2184         }
2185
2186         if (cfg->method->save_lmf) {
2187                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2188                 MONO_ADD_INS (cfg->cbb, arg);
2189         }
2190
2191         call->stack_usage = cinfo->stack_usage;
2192 }
2193
2194 void
2195 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2196 {
2197         MonoInst *arg;
2198         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2199         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2200         int size = ins->backend.size;
2201
2202         switch (ainfo->storage) {
2203         case ArgValuetypeInReg: {
2204                 MonoInst *load;
2205                 int part;
2206
2207                 for (part = 0; part < 2; ++part) {
2208                         if (ainfo->pair_storage [part] == ArgNone)
2209                                 continue;
2210
2211                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2212                         load->inst_basereg = src->dreg;
2213                         load->inst_offset = part * sizeof(mgreg_t);
2214
2215                         switch (ainfo->pair_storage [part]) {
2216                         case ArgInIReg:
2217                                 load->dreg = mono_alloc_ireg (cfg);
2218                                 break;
2219                         case ArgInDoubleSSEReg:
2220                         case ArgInFloatSSEReg:
2221                                 load->dreg = mono_alloc_freg (cfg);
2222                                 break;
2223                         default:
2224                                 g_assert_not_reached ();
2225                         }
2226                         MONO_ADD_INS (cfg->cbb, load);
2227
2228                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2229                 }
2230                 break;
2231         }
2232         case ArgValuetypeAddrInIReg: {
2233                 MonoInst *vtaddr, *load;
2234                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2235
2236                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2237                 cfg->has_indirection = TRUE;
2238                 load->inst_p0 = vtaddr;
2239                 vtaddr->flags |= MONO_INST_INDIRECT;
2240                 load->type = STACK_MP;
2241                 load->klass = vtaddr->klass;
2242                 load->dreg = mono_alloc_ireg (cfg);
2243                 MONO_ADD_INS (cfg->cbb, load);
2244                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2245
2246                 if (ainfo->pair_storage [0] == ArgInIReg) {
2247                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2248                         arg->dreg = mono_alloc_ireg (cfg);
2249                         arg->sreg1 = load->dreg;
2250                         arg->inst_imm = 0;
2251                         MONO_ADD_INS (cfg->cbb, arg);
2252                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2253                 } else {
2254                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2255                 }
2256                 break;
2257         }
2258         case ArgGSharedVtInReg:
2259                 /* Pass by addr */
2260                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2261                 break;
2262         case ArgGSharedVtOnStack:
2263                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2264                 break;
2265         default:
2266                 if (size == 8) {
2267                         int dreg = mono_alloc_ireg (cfg);
2268
2269                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2270                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2271                 } else if (size <= 40) {
2272                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2273                 } else {
2274                         // FIXME: Code growth
2275                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2276                 }
2277
2278                 if (cfg->compute_gc_maps) {
2279                         MonoInst *def;
2280                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2281                 }
2282         }
2283 }
2284
2285 void
2286 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2287 {
2288         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2289
2290         if (ret->type == MONO_TYPE_R4) {
2291                 if (COMPILE_LLVM (cfg))
2292                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2293                 else
2294                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2295                 return;
2296         } else if (ret->type == MONO_TYPE_R8) {
2297                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2298                 return;
2299         }
2300
2301         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2302 }
2303
2304 #endif /* DISABLE_JIT */
2305
2306 #define EMIT_COND_BRANCH(ins,cond,sign) \
2307         if (ins->inst_true_bb->native_offset) { \
2308                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2309         } else { \
2310                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2311                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2312             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2313                         x86_branch8 (code, cond, 0, sign); \
2314                 else \
2315                         x86_branch32 (code, cond, 0, sign); \
2316 }
2317
2318 typedef struct {
2319         MonoMethodSignature *sig;
2320         CallInfo *cinfo;
2321 } ArchDynCallInfo;
2322
2323 static gboolean
2324 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2325 {
2326         int i;
2327
2328 #ifdef HOST_WIN32
2329         return FALSE;
2330 #endif
2331
2332         switch (cinfo->ret.storage) {
2333         case ArgNone:
2334         case ArgInIReg:
2335         case ArgInFloatSSEReg:
2336         case ArgInDoubleSSEReg:
2337                 break;
2338         case ArgValuetypeInReg: {
2339                 ArgInfo *ainfo = &cinfo->ret;
2340
2341                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2342                         return FALSE;
2343                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2344                         return FALSE;
2345                 break;
2346         }
2347         default:
2348                 return FALSE;
2349         }
2350
2351         for (i = 0; i < cinfo->nargs; ++i) {
2352                 ArgInfo *ainfo = &cinfo->args [i];
2353                 switch (ainfo->storage) {
2354                 case ArgInIReg:
2355                 case ArgInFloatSSEReg:
2356                 case ArgInDoubleSSEReg:
2357                         break;
2358                 case ArgValuetypeInReg:
2359                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2360                                 return FALSE;
2361                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2362                                 return FALSE;
2363                         break;
2364                 default:
2365                         return FALSE;
2366                 }
2367         }
2368
2369         return TRUE;
2370 }
2371
2372 /*
2373  * mono_arch_dyn_call_prepare:
2374  *
2375  *   Return a pointer to an arch-specific structure which contains information
2376  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2377  * supported for SIG.
2378  * This function is equivalent to ffi_prep_cif in libffi.
2379  */
2380 MonoDynCallInfo*
2381 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2382 {
2383         ArchDynCallInfo *info;
2384         CallInfo *cinfo;
2385
2386         cinfo = get_call_info (NULL, sig);
2387
2388         if (!dyn_call_supported (sig, cinfo)) {
2389                 g_free (cinfo);
2390                 return NULL;
2391         }
2392
2393         info = g_new0 (ArchDynCallInfo, 1);
2394         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2395         info->sig = sig;
2396         info->cinfo = cinfo;
2397
2398         return (MonoDynCallInfo*)info;
2399 }
2400
2401 /*
2402  * mono_arch_dyn_call_free:
2403  *
2404  *   Free a MonoDynCallInfo structure.
2405  */
2406 void
2407 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2408 {
2409         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2410
2411         g_free (ainfo->cinfo);
2412         g_free (ainfo);
2413 }
2414
2415 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2416 #define GREG_TO_PTR(greg) (gpointer)(greg)
2417
2418 /*
2419  * mono_arch_get_start_dyn_call:
2420  *
2421  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2422  * store the result into BUF.
2423  * ARGS should be an array of pointers pointing to the arguments.
2424  * RET should point to a memory buffer large enought to hold the result of the
2425  * call.
2426  * This function should be as fast as possible, any work which does not depend
2427  * on the actual values of the arguments should be done in
2428  * mono_arch_dyn_call_prepare ().
2429  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2430  * libffi.
2431  */
2432 void
2433 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2434 {
2435         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2436         DynCallArgs *p = (DynCallArgs*)buf;
2437         int arg_index, greg, freg, i, pindex;
2438         MonoMethodSignature *sig = dinfo->sig;
2439         int buffer_offset = 0;
2440
2441         g_assert (buf_len >= sizeof (DynCallArgs));
2442
2443         p->res = 0;
2444         p->ret = ret;
2445
2446         arg_index = 0;
2447         greg = 0;
2448         freg = 0;
2449         pindex = 0;
2450
2451         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2452                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2453                 if (!sig->hasthis)
2454                         pindex = 1;
2455         }
2456
2457         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2458                 p->regs [greg ++] = PTR_TO_GREG(ret);
2459
2460         for (i = pindex; i < sig->param_count; i++) {
2461                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2462                 gpointer *arg = args [arg_index ++];
2463
2464                 if (t->byref) {
2465                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2466                         continue;
2467                 }
2468
2469                 switch (t->type) {
2470                 case MONO_TYPE_STRING:
2471                 case MONO_TYPE_CLASS:
2472                 case MONO_TYPE_ARRAY:
2473                 case MONO_TYPE_SZARRAY:
2474                 case MONO_TYPE_OBJECT:
2475                 case MONO_TYPE_PTR:
2476                 case MONO_TYPE_I:
2477                 case MONO_TYPE_U:
2478 #if !defined(__mono_ilp32__)
2479                 case MONO_TYPE_I8:
2480                 case MONO_TYPE_U8:
2481 #endif
2482                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2483                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2484                         break;
2485 #if defined(__mono_ilp32__)
2486                 case MONO_TYPE_I8:
2487                 case MONO_TYPE_U8:
2488                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2489                         p->regs [greg ++] = *(guint64*)(arg);
2490                         break;
2491 #endif
2492                 case MONO_TYPE_U1:
2493                         p->regs [greg ++] = *(guint8*)(arg);
2494                         break;
2495                 case MONO_TYPE_I1:
2496                         p->regs [greg ++] = *(gint8*)(arg);
2497                         break;
2498                 case MONO_TYPE_I2:
2499                         p->regs [greg ++] = *(gint16*)(arg);
2500                         break;
2501                 case MONO_TYPE_U2:
2502                         p->regs [greg ++] = *(guint16*)(arg);
2503                         break;
2504                 case MONO_TYPE_I4:
2505                         p->regs [greg ++] = *(gint32*)(arg);
2506                         break;
2507                 case MONO_TYPE_U4:
2508                         p->regs [greg ++] = *(guint32*)(arg);
2509                         break;
2510                 case MONO_TYPE_R4: {
2511                         double d;
2512
2513                         *(float*)&d = *(float*)(arg);
2514                         p->has_fp = 1;
2515                         p->fregs [freg ++] = d;
2516                         break;
2517                 }
2518                 case MONO_TYPE_R8:
2519                         p->has_fp = 1;
2520                         p->fregs [freg ++] = *(double*)(arg);
2521                         break;
2522                 case MONO_TYPE_GENERICINST:
2523                     if (MONO_TYPE_IS_REFERENCE (t)) {
2524                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2525                                 break;
2526                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2527                                         MonoClass *klass = mono_class_from_mono_type (t);
2528                                         guint8 *nullable_buf;
2529                                         int size;
2530
2531                                         size = mono_class_value_size (klass, NULL);
2532                                         nullable_buf = p->buffer + buffer_offset;
2533                                         buffer_offset += size;
2534                                         g_assert (buffer_offset <= 256);
2535
2536                                         /* The argument pointed to by arg is either a boxed vtype or null */
2537                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2538
2539                                         arg = (gpointer*)nullable_buf;
2540                                         /* Fall though */
2541
2542                         } else {
2543                                 /* Fall through */
2544                         }
2545                 case MONO_TYPE_VALUETYPE: {
2546                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2547
2548                         g_assert (ainfo->storage == ArgValuetypeInReg);
2549                         if (ainfo->pair_storage [0] != ArgNone) {
2550                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2551                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2552                         }
2553                         if (ainfo->pair_storage [1] != ArgNone) {
2554                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2555                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2556                         }
2557                         break;
2558                 }
2559                 default:
2560                         g_assert_not_reached ();
2561                 }
2562         }
2563
2564         g_assert (greg <= PARAM_REGS);
2565 }
2566
2567 /*
2568  * mono_arch_finish_dyn_call:
2569  *
2570  *   Store the result of a dyn call into the return value buffer passed to
2571  * start_dyn_call ().
2572  * This function should be as fast as possible, any work which does not depend
2573  * on the actual values of the arguments should be done in
2574  * mono_arch_dyn_call_prepare ().
2575  */
2576 void
2577 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2578 {
2579         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2580         MonoMethodSignature *sig = dinfo->sig;
2581         DynCallArgs *dargs = (DynCallArgs*)buf;
2582         guint8 *ret = dargs->ret;
2583         mgreg_t res = dargs->res;
2584         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2585
2586         switch (sig_ret->type) {
2587         case MONO_TYPE_VOID:
2588                 *(gpointer*)ret = NULL;
2589                 break;
2590         case MONO_TYPE_STRING:
2591         case MONO_TYPE_CLASS:
2592         case MONO_TYPE_ARRAY:
2593         case MONO_TYPE_SZARRAY:
2594         case MONO_TYPE_OBJECT:
2595         case MONO_TYPE_I:
2596         case MONO_TYPE_U:
2597         case MONO_TYPE_PTR:
2598                 *(gpointer*)ret = GREG_TO_PTR(res);
2599                 break;
2600         case MONO_TYPE_I1:
2601                 *(gint8*)ret = res;
2602                 break;
2603         case MONO_TYPE_U1:
2604                 *(guint8*)ret = res;
2605                 break;
2606         case MONO_TYPE_I2:
2607                 *(gint16*)ret = res;
2608                 break;
2609         case MONO_TYPE_U2:
2610                 *(guint16*)ret = res;
2611                 break;
2612         case MONO_TYPE_I4:
2613                 *(gint32*)ret = res;
2614                 break;
2615         case MONO_TYPE_U4:
2616                 *(guint32*)ret = res;
2617                 break;
2618         case MONO_TYPE_I8:
2619                 *(gint64*)ret = res;
2620                 break;
2621         case MONO_TYPE_U8:
2622                 *(guint64*)ret = res;
2623                 break;
2624         case MONO_TYPE_R4:
2625                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2626                 break;
2627         case MONO_TYPE_R8:
2628                 *(double*)ret = dargs->fregs [0];
2629                 break;
2630         case MONO_TYPE_GENERICINST:
2631                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2632                         *(gpointer*)ret = GREG_TO_PTR(res);
2633                         break;
2634                 } else {
2635                         /* Fall through */
2636                 }
2637         case MONO_TYPE_VALUETYPE:
2638                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2639                         /* Nothing to do */
2640                 } else {
2641                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2642
2643                         g_assert (ainfo->storage == ArgValuetypeInReg);
2644
2645                         if (ainfo->pair_storage [0] != ArgNone) {
2646                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2647                                 ((mgreg_t*)ret)[0] = res;
2648                         }
2649
2650                         g_assert (ainfo->pair_storage [1] == ArgNone);
2651                 }
2652                 break;
2653         default:
2654                 g_assert_not_reached ();
2655         }
2656 }
2657
2658 /* emit an exception if condition is fail */
2659 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2660         do {                                                        \
2661                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2662                 if (tins == NULL) {                                                                             \
2663                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2664                                         MONO_PATCH_INFO_EXC, exc_name);  \
2665                         x86_branch32 (code, cond, 0, signed);               \
2666                 } else {        \
2667                         EMIT_COND_BRANCH (tins, cond, signed);  \
2668                 }                       \
2669         } while (0);
2670
2671 #define EMIT_FPCOMPARE(code) do { \
2672         amd64_fcompp (code); \
2673         amd64_fnstsw (code); \
2674 } while (0);
2675
2676 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2677     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2678         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2679         amd64_ ##op (code); \
2680         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2681         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2682 } while (0);
2683
2684 static guint8*
2685 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2686 {
2687         gboolean no_patch = FALSE;
2688
2689         /*
2690          * FIXME: Add support for thunks
2691          */
2692         {
2693                 gboolean near_call = FALSE;
2694
2695                 /*
2696                  * Indirect calls are expensive so try to make a near call if possible.
2697                  * The caller memory is allocated by the code manager so it is
2698                  * guaranteed to be at a 32 bit offset.
2699                  */
2700
2701                 if (patch_type != MONO_PATCH_INFO_ABS) {
2702                         /* The target is in memory allocated using the code manager */
2703                         near_call = TRUE;
2704
2705                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2706                                 if (((MonoMethod*)data)->klass->image->aot_module)
2707                                         /* The callee might be an AOT method */
2708                                         near_call = FALSE;
2709                                 if (((MonoMethod*)data)->dynamic)
2710                                         /* The target is in malloc-ed memory */
2711                                         near_call = FALSE;
2712                         }
2713
2714                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2715                                 /*
2716                                  * The call might go directly to a native function without
2717                                  * the wrapper.
2718                                  */
2719                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2720                                 if (mi) {
2721                                         gconstpointer target = mono_icall_get_wrapper (mi);
2722                                         if ((((guint64)target) >> 32) != 0)
2723                                                 near_call = FALSE;
2724                                 }
2725                         }
2726                 }
2727                 else {
2728                         MonoJumpInfo *jinfo = NULL;
2729
2730                         if (cfg->abs_patches)
2731                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2732                         if (jinfo) {
2733                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2734                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2735                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2736                                                 near_call = TRUE;
2737                                         no_patch = TRUE;
2738                                 } else {
2739                                         /*
2740                                          * This is not really an optimization, but required because the
2741                                          * generic class init trampolines use R11 to pass the vtable.
2742                                          */
2743                                         near_call = TRUE;
2744                                 }
2745                         } else {
2746                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2747                                 if (info) {
2748                                         if (info->func == info->wrapper) {
2749                                                 /* No wrapper */
2750                                                 if ((((guint64)info->func) >> 32) == 0)
2751                                                         near_call = TRUE;
2752                                         }
2753                                         else {
2754                                                 /* See the comment in mono_codegen () */
2755                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2756                                                         near_call = TRUE;
2757                                         }
2758                                 }
2759                                 else if ((((guint64)data) >> 32) == 0) {
2760                                         near_call = TRUE;
2761                                         no_patch = TRUE;
2762                                 }
2763                         }
2764                 }
2765
2766                 if (cfg->method->dynamic)
2767                         /* These methods are allocated using malloc */
2768                         near_call = FALSE;
2769
2770 #ifdef MONO_ARCH_NOMAP32BIT
2771                 near_call = FALSE;
2772 #endif
2773                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2774                 if (optimize_for_xen)
2775                         near_call = FALSE;
2776
2777                 if (cfg->compile_aot) {
2778                         near_call = TRUE;
2779                         no_patch = TRUE;
2780                 }
2781
2782                 if (near_call) {
2783                         /*
2784                          * Align the call displacement to an address divisible by 4 so it does
2785                          * not span cache lines. This is required for code patching to work on SMP
2786                          * systems.
2787                          */
2788                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2789                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2790                                 amd64_padding (code, pad_size);
2791                         }
2792                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2793                         amd64_call_code (code, 0);
2794                 }
2795                 else {
2796                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2797                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2798                         amd64_call_reg (code, GP_SCRATCH_REG);
2799                 }
2800         }
2801
2802         return code;
2803 }
2804
2805 static inline guint8*
2806 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2807 {
2808 #ifdef TARGET_WIN32
2809         if (win64_adjust_stack)
2810                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2811 #endif
2812         code = emit_call_body (cfg, code, patch_type, data);
2813 #ifdef TARGET_WIN32
2814         if (win64_adjust_stack)
2815                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2816 #endif
2817
2818         return code;
2819 }
2820
2821 static inline int
2822 store_membase_imm_to_store_membase_reg (int opcode)
2823 {
2824         switch (opcode) {
2825         case OP_STORE_MEMBASE_IMM:
2826                 return OP_STORE_MEMBASE_REG;
2827         case OP_STOREI4_MEMBASE_IMM:
2828                 return OP_STOREI4_MEMBASE_REG;
2829         case OP_STOREI8_MEMBASE_IMM:
2830                 return OP_STOREI8_MEMBASE_REG;
2831         }
2832
2833         return -1;
2834 }
2835
2836 #ifndef DISABLE_JIT
2837
2838 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2839
2840 /*
2841  * mono_arch_peephole_pass_1:
2842  *
2843  *   Perform peephole opts which should/can be performed before local regalloc
2844  */
2845 void
2846 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2847 {
2848         MonoInst *ins, *n;
2849
2850         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2851                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2852
2853                 switch (ins->opcode) {
2854                 case OP_ADD_IMM:
2855                 case OP_IADD_IMM:
2856                 case OP_LADD_IMM:
2857                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2858                                 /*
2859                                  * X86_LEA is like ADD, but doesn't have the
2860                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2861                                  * its operand to 64 bit.
2862                                  */
2863                                 ins->opcode = OP_X86_LEA_MEMBASE;
2864                                 ins->inst_basereg = ins->sreg1;
2865                         }
2866                         break;
2867                 case OP_LXOR:
2868                 case OP_IXOR:
2869                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2870                                 MonoInst *ins2;
2871
2872                                 /*
2873                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2874                                  * the latter has length 2-3 instead of 6 (reverse constant
2875                                  * propagation). These instruction sequences are very common
2876                                  * in the initlocals bblock.
2877                                  */
2878                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2879                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2880                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2881                                                 ins2->sreg1 = ins->dreg;
2882                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2883                                                 /* Continue */
2884                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2885                                                 NULLIFY_INS (ins2);
2886                                                 /* Continue */
2887                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2888                                                 /* Continue */
2889                                         } else {
2890                                                 break;
2891                                         }
2892                                 }
2893                         }
2894                         break;
2895                 case OP_COMPARE_IMM:
2896                 case OP_LCOMPARE_IMM:
2897                         /* OP_COMPARE_IMM (reg, 0)
2898                          * -->
2899                          * OP_AMD64_TEST_NULL (reg)
2900                          */
2901                         if (!ins->inst_imm)
2902                                 ins->opcode = OP_AMD64_TEST_NULL;
2903                         break;
2904                 case OP_ICOMPARE_IMM:
2905                         if (!ins->inst_imm)
2906                                 ins->opcode = OP_X86_TEST_NULL;
2907                         break;
2908                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2909                         /*
2910                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2911                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2912                          * -->
2913                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2914                          * OP_COMPARE_IMM reg, imm
2915                          *
2916                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2917                          */
2918                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2919                             ins->inst_basereg == last_ins->inst_destbasereg &&
2920                             ins->inst_offset == last_ins->inst_offset) {
2921                                         ins->opcode = OP_ICOMPARE_IMM;
2922                                         ins->sreg1 = last_ins->sreg1;
2923
2924                                         /* check if we can remove cmp reg,0 with test null */
2925                                         if (!ins->inst_imm)
2926                                                 ins->opcode = OP_X86_TEST_NULL;
2927                                 }
2928
2929                         break;
2930                 }
2931
2932                 mono_peephole_ins (bb, ins);
2933         }
2934 }
2935
2936 void
2937 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2938 {
2939         MonoInst *ins, *n;
2940
2941         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2942                 switch (ins->opcode) {
2943                 case OP_ICONST:
2944                 case OP_I8CONST: {
2945                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
2946                         /* reg = 0 -> XOR (reg, reg) */
2947                         /* XOR sets cflags on x86, so we cant do it always */
2948                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
2949                                 ins->opcode = OP_LXOR;
2950                                 ins->sreg1 = ins->dreg;
2951                                 ins->sreg2 = ins->dreg;
2952                                 /* Fall through */
2953                         } else {
2954                                 break;
2955                         }
2956                 }
2957                 case OP_LXOR:
2958                         /*
2959                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2960                          * 0 result into 64 bits.
2961                          */
2962                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2963                                 ins->opcode = OP_IXOR;
2964                         }
2965                         /* Fall through */
2966                 case OP_IXOR:
2967                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2968                                 MonoInst *ins2;
2969
2970                                 /*
2971                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2972                                  * the latter has length 2-3 instead of 6 (reverse constant
2973                                  * propagation). These instruction sequences are very common
2974                                  * in the initlocals bblock.
2975                                  */
2976                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2977                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2978                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2979                                                 ins2->sreg1 = ins->dreg;
2980                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
2981                                                 /* Continue */
2982                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2983                                                 NULLIFY_INS (ins2);
2984                                                 /* Continue */
2985                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2986                                                 /* Continue */
2987                                         } else {
2988                                                 break;
2989                                         }
2990                                 }
2991                         }
2992                         break;
2993                 case OP_IADD_IMM:
2994                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2995                                 ins->opcode = OP_X86_INC_REG;
2996                         break;
2997                 case OP_ISUB_IMM:
2998                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2999                                 ins->opcode = OP_X86_DEC_REG;
3000                         break;
3001                 }
3002
3003                 mono_peephole_ins (bb, ins);
3004         }
3005 }
3006
3007 #define NEW_INS(cfg,ins,dest,op) do {   \
3008                 MONO_INST_NEW ((cfg), (dest), (op)); \
3009         (dest)->cil_code = (ins)->cil_code; \
3010         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3011         } while (0)
3012
3013 /*
3014  * mono_arch_lowering_pass:
3015  *
3016  *  Converts complex opcodes into simpler ones so that each IR instruction
3017  * corresponds to one machine instruction.
3018  */
3019 void
3020 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3021 {
3022         MonoInst *ins, *n, *temp;
3023
3024         /*
3025          * FIXME: Need to add more instructions, but the current machine
3026          * description can't model some parts of the composite instructions like
3027          * cdq.
3028          */
3029         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3030                 switch (ins->opcode) {
3031                 case OP_DIV_IMM:
3032                 case OP_REM_IMM:
3033                 case OP_IDIV_IMM:
3034                 case OP_IDIV_UN_IMM:
3035                 case OP_IREM_UN_IMM:
3036                 case OP_LREM_IMM:
3037                 case OP_IREM_IMM:
3038                         mono_decompose_op_imm (cfg, bb, ins);
3039                         break;
3040                 case OP_COMPARE_IMM:
3041                 case OP_LCOMPARE_IMM:
3042                         if (!amd64_use_imm32 (ins->inst_imm)) {
3043                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3044                                 temp->inst_c0 = ins->inst_imm;
3045                                 temp->dreg = mono_alloc_ireg (cfg);
3046                                 ins->opcode = OP_COMPARE;
3047                                 ins->sreg2 = temp->dreg;
3048                         }
3049                         break;
3050 #ifndef __mono_ilp32__
3051                 case OP_LOAD_MEMBASE:
3052 #endif
3053                 case OP_LOADI8_MEMBASE:
3054                 /*  Don't generate memindex opcodes (to simplify */
3055                 /*  read sandboxing) */
3056                         if (!amd64_use_imm32 (ins->inst_offset)) {
3057                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3058                                 temp->inst_c0 = ins->inst_offset;
3059                                 temp->dreg = mono_alloc_ireg (cfg);
3060                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3061                                 ins->inst_indexreg = temp->dreg;
3062                         }
3063                         break;
3064 #ifndef __mono_ilp32__
3065                 case OP_STORE_MEMBASE_IMM:
3066 #endif
3067                 case OP_STOREI8_MEMBASE_IMM:
3068                         if (!amd64_use_imm32 (ins->inst_imm)) {
3069                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3070                                 temp->inst_c0 = ins->inst_imm;
3071                                 temp->dreg = mono_alloc_ireg (cfg);
3072                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3073                                 ins->sreg1 = temp->dreg;
3074                         }
3075                         break;
3076 #ifdef MONO_ARCH_SIMD_INTRINSICS
3077                 case OP_EXPAND_I1: {
3078                                 int temp_reg1 = mono_alloc_ireg (cfg);
3079                                 int temp_reg2 = mono_alloc_ireg (cfg);
3080                                 int original_reg = ins->sreg1;
3081
3082                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3083                                 temp->sreg1 = original_reg;
3084                                 temp->dreg = temp_reg1;
3085
3086                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3087                                 temp->sreg1 = temp_reg1;
3088                                 temp->dreg = temp_reg2;
3089                                 temp->inst_imm = 8;
3090
3091                                 NEW_INS (cfg, ins, temp, OP_LOR);
3092                                 temp->sreg1 = temp->dreg = temp_reg2;
3093                                 temp->sreg2 = temp_reg1;
3094
3095                                 ins->opcode = OP_EXPAND_I2;
3096                                 ins->sreg1 = temp_reg2;
3097                         }
3098                         break;
3099 #endif
3100                 default:
3101                         break;
3102                 }
3103         }
3104
3105         bb->max_vreg = cfg->next_vreg;
3106 }
3107
3108 static const int
3109 branch_cc_table [] = {
3110         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3111         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3112         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3113 };
3114
3115 /* Maps CMP_... constants to X86_CC_... constants */
3116 static const int
3117 cc_table [] = {
3118         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3119         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3120 };
3121
3122 static const int
3123 cc_signed_table [] = {
3124         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3125         FALSE, FALSE, FALSE, FALSE
3126 };
3127
3128 /*#include "cprop.c"*/
3129
3130 static unsigned char*
3131 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3132 {
3133         if (size == 8)
3134                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3135         else
3136                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3137
3138         if (size == 1)
3139                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3140         else if (size == 2)
3141                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3142         return code;
3143 }
3144
3145 static unsigned char*
3146 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3147 {
3148         int sreg = tree->sreg1;
3149         int need_touch = FALSE;
3150
3151 #if defined(TARGET_WIN32)
3152         need_touch = TRUE;
3153 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3154         if (!tree->flags & MONO_INST_INIT)
3155                 need_touch = TRUE;
3156 #endif
3157
3158         if (need_touch) {
3159                 guint8* br[5];
3160
3161                 /*
3162                  * Under Windows:
3163                  * If requested stack size is larger than one page,
3164                  * perform stack-touch operation
3165                  */
3166                 /*
3167                  * Generate stack probe code.
3168                  * Under Windows, it is necessary to allocate one page at a time,
3169                  * "touching" stack after each successful sub-allocation. This is
3170                  * because of the way stack growth is implemented - there is a
3171                  * guard page before the lowest stack page that is currently commited.
3172                  * Stack normally grows sequentially so OS traps access to the
3173                  * guard page and commits more pages when needed.
3174                  */
3175                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3176                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3177
3178                 br[2] = code; /* loop */
3179                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3180                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3181                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3182                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3183                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3184                 amd64_patch (br[3], br[2]);
3185                 amd64_test_reg_reg (code, sreg, sreg);
3186                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3187                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3188
3189                 br[1] = code; x86_jump8 (code, 0);
3190
3191                 amd64_patch (br[0], code);
3192                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3193                 amd64_patch (br[1], code);
3194                 amd64_patch (br[4], code);
3195         }
3196         else
3197                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3198
3199         if (tree->flags & MONO_INST_INIT) {
3200                 int offset = 0;
3201                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3202                         amd64_push_reg (code, AMD64_RAX);
3203                         offset += 8;
3204                 }
3205                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3206                         amd64_push_reg (code, AMD64_RCX);
3207                         offset += 8;
3208                 }
3209                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3210                         amd64_push_reg (code, AMD64_RDI);
3211                         offset += 8;
3212                 }
3213
3214                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3215                 if (sreg != AMD64_RCX)
3216                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3217                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3218
3219                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3220                 if (cfg->param_area)
3221                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3222                 amd64_cld (code);
3223                 amd64_prefix (code, X86_REP_PREFIX);
3224                 amd64_stosl (code);
3225
3226                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3227                         amd64_pop_reg (code, AMD64_RDI);
3228                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3229                         amd64_pop_reg (code, AMD64_RCX);
3230                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3231                         amd64_pop_reg (code, AMD64_RAX);
3232         }
3233         return code;
3234 }
3235
3236 static guint8*
3237 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3238 {
3239         CallInfo *cinfo;
3240         guint32 quad;
3241
3242         /* Move return value to the target register */
3243         /* FIXME: do this in the local reg allocator */
3244         switch (ins->opcode) {
3245         case OP_CALL:
3246         case OP_CALL_REG:
3247         case OP_CALL_MEMBASE:
3248         case OP_LCALL:
3249         case OP_LCALL_REG:
3250         case OP_LCALL_MEMBASE:
3251                 g_assert (ins->dreg == AMD64_RAX);
3252                 break;
3253         case OP_FCALL:
3254         case OP_FCALL_REG:
3255         case OP_FCALL_MEMBASE: {
3256                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3257                 if (rtype->type == MONO_TYPE_R4) {
3258                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3259                 }
3260                 else {
3261                         if (ins->dreg != AMD64_XMM0)
3262                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3263                 }
3264                 break;
3265         }
3266         case OP_RCALL:
3267         case OP_RCALL_REG:
3268         case OP_RCALL_MEMBASE:
3269                 if (ins->dreg != AMD64_XMM0)
3270                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3271                 break;
3272         case OP_VCALL:
3273         case OP_VCALL_REG:
3274         case OP_VCALL_MEMBASE:
3275         case OP_VCALL2:
3276         case OP_VCALL2_REG:
3277         case OP_VCALL2_MEMBASE:
3278                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3279                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3280                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3281
3282                         /* Load the destination address */
3283                         g_assert (loc->opcode == OP_REGOFFSET);
3284                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3285
3286                         for (quad = 0; quad < 2; quad ++) {
3287                                 switch (cinfo->ret.pair_storage [quad]) {
3288                                 case ArgInIReg:
3289                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3290                                         break;
3291                                 case ArgInFloatSSEReg:
3292                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3293                                         break;
3294                                 case ArgInDoubleSSEReg:
3295                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3296                                         break;
3297                                 case ArgNone:
3298                                         break;
3299                                 default:
3300                                         NOT_IMPLEMENTED;
3301                                 }
3302                         }
3303                 }
3304                 break;
3305         }
3306
3307         return code;
3308 }
3309
3310 #endif /* DISABLE_JIT */
3311
3312 #ifdef __APPLE__
3313 static int tls_gs_offset;
3314 #endif
3315
3316 gboolean
3317 mono_amd64_have_tls_get (void)
3318 {
3319 #ifdef TARGET_MACH
3320         static gboolean have_tls_get = FALSE;
3321         static gboolean inited = FALSE;
3322
3323         if (inited)
3324                 return have_tls_get;
3325
3326 #if MONO_HAVE_FAST_TLS
3327         guint8 *ins = (guint8*)pthread_getspecific;
3328
3329         /*
3330          * We're looking for these two instructions:
3331          *
3332          * mov    %gs:[offset](,%rdi,8),%rax
3333          * retq
3334          */
3335         have_tls_get = ins [0] == 0x65 &&
3336                        ins [1] == 0x48 &&
3337                        ins [2] == 0x8b &&
3338                        ins [3] == 0x04 &&
3339                        ins [4] == 0xfd &&
3340                        ins [6] == 0x00 &&
3341                        ins [7] == 0x00 &&
3342                        ins [8] == 0x00 &&
3343                        ins [9] == 0xc3;
3344
3345         tls_gs_offset = ins[5];
3346
3347         /*
3348          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3349          * For that version we're looking for these instructions:
3350          *
3351          * pushq  %rbp
3352          * movq   %rsp, %rbp
3353          * mov    %gs:[offset](,%rdi,8),%rax
3354          * popq   %rbp
3355          * retq
3356          */
3357         if (!have_tls_get) {
3358                 have_tls_get = ins [0] == 0x55 &&
3359                                ins [1] == 0x48 &&
3360                                ins [2] == 0x89 &&
3361                                ins [3] == 0xe5 &&
3362                                ins [4] == 0x65 &&
3363                                ins [5] == 0x48 &&
3364                                ins [6] == 0x8b &&
3365                                ins [7] == 0x04 &&
3366                                ins [8] == 0xfd &&
3367                                ins [10] == 0x00 &&
3368                                ins [11] == 0x00 &&
3369                                ins [12] == 0x00 &&
3370                                ins [13] == 0x5d &&
3371                                ins [14] == 0xc3;
3372
3373                 tls_gs_offset = ins[9];
3374         }
3375 #endif
3376
3377         inited = TRUE;
3378
3379         return have_tls_get;
3380 #elif defined(TARGET_ANDROID)
3381         return FALSE;
3382 #else
3383         return TRUE;
3384 #endif
3385 }
3386
3387 int
3388 mono_amd64_get_tls_gs_offset (void)
3389 {
3390 #ifdef TARGET_OSX
3391         return tls_gs_offset;
3392 #else
3393         g_assert_not_reached ();
3394         return -1;
3395 #endif
3396 }
3397
3398 /*
3399  * mono_amd64_emit_tls_get:
3400  * @code: buffer to store code to
3401  * @dreg: hard register where to place the result
3402  * @tls_offset: offset info
3403  *
3404  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3405  * the dreg register the item in the thread local storage identified
3406  * by tls_offset.
3407  *
3408  * Returns: a pointer to the end of the stored code
3409  */
3410 guint8*
3411 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3412 {
3413 #ifdef TARGET_WIN32
3414         if (tls_offset < 64) {
3415                 x86_prefix (code, X86_GS_PREFIX);
3416                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3417         } else {
3418                 guint8 *buf [16];
3419
3420                 g_assert (tls_offset < 0x440);
3421                 /* Load TEB->TlsExpansionSlots */
3422                 x86_prefix (code, X86_GS_PREFIX);
3423                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3424                 amd64_test_reg_reg (code, dreg, dreg);
3425                 buf [0] = code;
3426                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3427                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3428                 amd64_patch (buf [0], code);
3429         }
3430 #elif defined(__APPLE__)
3431         x86_prefix (code, X86_GS_PREFIX);
3432         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3433 #else
3434         if (optimize_for_xen) {
3435                 x86_prefix (code, X86_FS_PREFIX);
3436                 amd64_mov_reg_mem (code, dreg, 0, 8);
3437                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3438         } else {
3439                 x86_prefix (code, X86_FS_PREFIX);
3440                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3441         }
3442 #endif
3443         return code;
3444 }
3445
3446 #ifdef TARGET_WIN32
3447
3448 #define MAX_TEB_TLS_SLOTS 64
3449 #define TEB_TLS_SLOTS_OFFSET 0x1480
3450 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3451
3452 static guint8*
3453 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3454 {
3455         int tmp_reg = -1;
3456         guint8 * more_than_64_slots = NULL;
3457         guint8 * empty_slot = NULL;
3458         guint8 * tls_get_reg_done = NULL;
3459
3460         //Use temporary register for offset calculation?
3461         if (dreg == offset_reg) {
3462                 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3463                 amd64_push_reg (code, tmp_reg);
3464                 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3465                 offset_reg = tmp_reg;
3466         }
3467
3468         //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3469         amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3470         more_than_64_slots = code;
3471         amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3472
3473         //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3474         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3475         amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3476
3477         //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3478         x86_prefix (code, X86_GS_PREFIX);
3479         amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3480
3481         tls_get_reg_done = code;
3482         amd64_jump8 (code, 0);
3483
3484         amd64_patch (more_than_64_slots, code);
3485
3486         //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3487         x86_prefix (code, X86_GS_PREFIX);
3488         amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3489
3490         //Check for NULL in _TEB.TlsExpansionSlots.
3491         amd64_test_reg_reg (code, dreg, dreg);
3492         empty_slot = code;
3493         amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3494
3495         //TLS expansion slots are at index offset into the expansion array.
3496         //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3497         amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3498         amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3499
3500         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3501
3502         amd64_patch (empty_slot, code);
3503         amd64_patch (tls_get_reg_done, code);
3504
3505         if (tmp_reg != -1)
3506                 amd64_pop_reg (code, tmp_reg);
3507
3508         return code;
3509 }
3510
3511 #endif
3512
3513 static guint8*
3514 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3515 {
3516         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3517 #ifdef TARGET_OSX
3518         if (dreg != offset_reg)
3519                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3520         amd64_prefix (code, X86_GS_PREFIX);
3521         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3522 #elif defined(__linux__)
3523         int tmpreg = -1;
3524
3525         if (dreg == offset_reg) {
3526                 /* Use a temporary reg by saving it to the redzone */
3527                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3528                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3529                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3530                 offset_reg = tmpreg;
3531         }
3532         x86_prefix (code, X86_FS_PREFIX);
3533         amd64_mov_reg_mem (code, dreg, 0, 8);
3534         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3535         if (tmpreg != -1)
3536                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3537 #elif defined(TARGET_WIN32)
3538         code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3539 #else
3540         g_assert_not_reached ();
3541 #endif
3542         return code;
3543 }
3544
3545 static guint8*
3546 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3547 {
3548 #ifdef TARGET_WIN32
3549         g_assert_not_reached ();
3550 #elif defined(__APPLE__)
3551         x86_prefix (code, X86_GS_PREFIX);
3552         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3553 #else
3554         g_assert (!optimize_for_xen);
3555         x86_prefix (code, X86_FS_PREFIX);
3556         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3557 #endif
3558         return code;
3559 }
3560
3561 static guint8*
3562 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3563 {
3564         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3565 #ifdef TARGET_WIN32
3566         g_assert_not_reached ();
3567 #elif defined(__APPLE__)
3568         x86_prefix (code, X86_GS_PREFIX);
3569         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3570 #else
3571         x86_prefix (code, X86_FS_PREFIX);
3572         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3573 #endif
3574         return code;
3575 }
3576
3577  /*
3578  * mono_arch_translate_tls_offset:
3579  *
3580  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3581  */
3582 int
3583 mono_arch_translate_tls_offset (int offset)
3584 {
3585 #ifdef __APPLE__
3586         return tls_gs_offset + (offset * 8);
3587 #else
3588         return offset;
3589 #endif
3590 }
3591
3592 /*
3593  * emit_setup_lmf:
3594  *
3595  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3596  */
3597 static guint8*
3598 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3599 {
3600         /*
3601          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3602          */
3603         /*
3604          * sp is saved right before calls but we need to save it here too so
3605          * async stack walks would work.
3606          */
3607         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3608         /* Save rbp */
3609         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3610         if (cfg->arch.omit_fp && cfa_offset != -1)
3611                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3612
3613         /* These can't contain refs */
3614         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3615         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3616         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3617         /* These are handled automatically by the stack marking code */
3618         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3619
3620         return code;
3621 }
3622
3623 /* benchmark and set based on cpu */
3624 #define LOOP_ALIGNMENT 8
3625 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3626
3627 #ifndef DISABLE_JIT
3628 void
3629 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3630 {
3631         MonoInst *ins;
3632         MonoCallInst *call;
3633         guint offset;
3634         guint8 *code = cfg->native_code + cfg->code_len;
3635         int max_len;
3636
3637         /* Fix max_offset estimate for each successor bb */
3638         if (cfg->opt & MONO_OPT_BRANCH) {
3639                 int current_offset = cfg->code_len;
3640                 MonoBasicBlock *current_bb;
3641                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3642                         current_bb->max_offset = current_offset;
3643                         current_offset += current_bb->max_length;
3644                 }
3645         }
3646
3647         if (cfg->opt & MONO_OPT_LOOP) {
3648                 int pad, align = LOOP_ALIGNMENT;
3649                 /* set alignment depending on cpu */
3650                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3651                         pad = align - pad;
3652                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3653                         amd64_padding (code, pad);
3654                         cfg->code_len += pad;
3655                         bb->native_offset = cfg->code_len;
3656                 }
3657         }
3658
3659         if (cfg->verbose_level > 2)
3660                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3661
3662         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3663                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3664                 g_assert (!cfg->compile_aot);
3665
3666                 cov->data [bb->dfn].cil_code = bb->cil_code;
3667                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3668                 /* this is not thread save, but good enough */
3669                 amd64_inc_membase (code, AMD64_R11, 0);
3670         }
3671
3672         offset = code - cfg->native_code;
3673
3674         mono_debug_open_block (cfg, bb, offset);
3675
3676     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3677                 x86_breakpoint (code);
3678
3679         MONO_BB_FOR_EACH_INS (bb, ins) {
3680                 offset = code - cfg->native_code;
3681
3682                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3683
3684 #define EXTRA_CODE_SPACE (16)
3685
3686                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3687                         cfg->code_size *= 2;
3688                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3689                         code = cfg->native_code + offset;
3690                         cfg->stat_code_reallocs++;
3691                 }
3692
3693                 if (cfg->debug_info)
3694                         mono_debug_record_line_number (cfg, ins, offset);
3695
3696                 switch (ins->opcode) {
3697                 case OP_BIGMUL:
3698                         amd64_mul_reg (code, ins->sreg2, TRUE);
3699                         break;
3700                 case OP_BIGMUL_UN:
3701                         amd64_mul_reg (code, ins->sreg2, FALSE);
3702                         break;
3703                 case OP_X86_SETEQ_MEMBASE:
3704                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3705                         break;
3706                 case OP_STOREI1_MEMBASE_IMM:
3707                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3708                         break;
3709                 case OP_STOREI2_MEMBASE_IMM:
3710                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3711                         break;
3712                 case OP_STOREI4_MEMBASE_IMM:
3713                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3714                         break;
3715                 case OP_STOREI1_MEMBASE_REG:
3716                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3717                         break;
3718                 case OP_STOREI2_MEMBASE_REG:
3719                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3720                         break;
3721                 /* In AMD64 NaCl, pointers are 4 bytes, */
3722                 /*  so STORE_* != STOREI8_*. Likewise below. */
3723                 case OP_STORE_MEMBASE_REG:
3724                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3725                         break;
3726                 case OP_STOREI8_MEMBASE_REG:
3727                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3728                         break;
3729                 case OP_STOREI4_MEMBASE_REG:
3730                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3731                         break;
3732                 case OP_STORE_MEMBASE_IMM:
3733                         /* In NaCl, this could be a PCONST type, which could */
3734                         /* mean a pointer type was copied directly into the  */
3735                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3736                         /* the value would be 0x00000000FFFFFFFF which is    */
3737                         /* not proper for an imm32 unless you cast it.       */
3738                         g_assert (amd64_is_imm32 (ins->inst_imm));
3739                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3740                         break;
3741                 case OP_STOREI8_MEMBASE_IMM:
3742                         g_assert (amd64_is_imm32 (ins->inst_imm));
3743                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3744                         break;
3745                 case OP_LOAD_MEM:
3746 #ifdef __mono_ilp32__
3747                         /* In ILP32, pointers are 4 bytes, so separate these */
3748                         /* cases, use literal 8 below where we really want 8 */
3749                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3750                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3751                         break;
3752 #endif
3753                 case OP_LOADI8_MEM:
3754                         // FIXME: Decompose this earlier
3755                         if (amd64_use_imm32 (ins->inst_imm))
3756                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3757                         else {
3758                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3759                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3760                         }
3761                         break;
3762                 case OP_LOADI4_MEM:
3763                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3764                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3765                         break;
3766                 case OP_LOADU4_MEM:
3767                         // FIXME: Decompose this earlier
3768                         if (amd64_use_imm32 (ins->inst_imm))
3769                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3770                         else {
3771                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3772                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3773                         }
3774                         break;
3775                 case OP_LOADU1_MEM:
3776                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3777                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3778                         break;
3779                 case OP_LOADU2_MEM:
3780                         /* For NaCl, pointers are 4 bytes, so separate these */
3781                         /* cases, use literal 8 below where we really want 8 */
3782                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3783                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3784                         break;
3785                 case OP_LOAD_MEMBASE:
3786                         g_assert (amd64_is_imm32 (ins->inst_offset));
3787                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3788                         break;
3789                 case OP_LOADI8_MEMBASE:
3790                         /* Use literal 8 instead of sizeof pointer or */
3791                         /* register, we really want 8 for this opcode */
3792                         g_assert (amd64_is_imm32 (ins->inst_offset));
3793                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3794                         break;
3795                 case OP_LOADI4_MEMBASE:
3796                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3797                         break;
3798                 case OP_LOADU4_MEMBASE:
3799                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3800                         break;
3801                 case OP_LOADU1_MEMBASE:
3802                         /* The cpu zero extends the result into 64 bits */
3803                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3804                         break;
3805                 case OP_LOADI1_MEMBASE:
3806                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3807                         break;
3808                 case OP_LOADU2_MEMBASE:
3809                         /* The cpu zero extends the result into 64 bits */
3810                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3811                         break;
3812                 case OP_LOADI2_MEMBASE:
3813                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3814                         break;
3815                 case OP_AMD64_LOADI8_MEMINDEX:
3816                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3817                         break;
3818                 case OP_LCONV_TO_I1:
3819                 case OP_ICONV_TO_I1:
3820                 case OP_SEXT_I1:
3821                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3822                         break;
3823                 case OP_LCONV_TO_I2:
3824                 case OP_ICONV_TO_I2:
3825                 case OP_SEXT_I2:
3826                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3827                         break;
3828                 case OP_LCONV_TO_U1:
3829                 case OP_ICONV_TO_U1:
3830                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3831                         break;
3832                 case OP_LCONV_TO_U2:
3833                 case OP_ICONV_TO_U2:
3834                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3835                         break;
3836                 case OP_ZEXT_I4:
3837                         /* Clean out the upper word */
3838                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3839                         break;
3840                 case OP_SEXT_I4:
3841                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3842                         break;
3843                 case OP_COMPARE:
3844                 case OP_LCOMPARE:
3845                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3846                         break;
3847                 case OP_COMPARE_IMM:
3848 #if defined(__mono_ilp32__)
3849                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3850                         g_assert (amd64_is_imm32 (ins->inst_imm));
3851                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3852                         break;
3853 #endif
3854                 case OP_LCOMPARE_IMM:
3855                         g_assert (amd64_is_imm32 (ins->inst_imm));
3856                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3857                         break;
3858                 case OP_X86_COMPARE_REG_MEMBASE:
3859                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3860                         break;
3861                 case OP_X86_TEST_NULL:
3862                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3863                         break;
3864                 case OP_AMD64_TEST_NULL:
3865                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3866                         break;
3867
3868                 case OP_X86_ADD_REG_MEMBASE:
3869                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3870                         break;
3871                 case OP_X86_SUB_REG_MEMBASE:
3872                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3873                         break;
3874                 case OP_X86_AND_REG_MEMBASE:
3875                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3876                         break;
3877                 case OP_X86_OR_REG_MEMBASE:
3878                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3879                         break;
3880                 case OP_X86_XOR_REG_MEMBASE:
3881                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3882                         break;
3883
3884                 case OP_X86_ADD_MEMBASE_IMM:
3885                         /* FIXME: Make a 64 version too */
3886                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3887                         break;
3888                 case OP_X86_SUB_MEMBASE_IMM:
3889                         g_assert (amd64_is_imm32 (ins->inst_imm));
3890                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3891                         break;
3892                 case OP_X86_AND_MEMBASE_IMM:
3893                         g_assert (amd64_is_imm32 (ins->inst_imm));
3894                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3895                         break;
3896                 case OP_X86_OR_MEMBASE_IMM:
3897                         g_assert (amd64_is_imm32 (ins->inst_imm));
3898                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3899                         break;
3900                 case OP_X86_XOR_MEMBASE_IMM:
3901                         g_assert (amd64_is_imm32 (ins->inst_imm));
3902                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3903                         break;
3904                 case OP_X86_ADD_MEMBASE_REG:
3905                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3906                         break;
3907                 case OP_X86_SUB_MEMBASE_REG:
3908                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3909                         break;
3910                 case OP_X86_AND_MEMBASE_REG:
3911                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3912                         break;
3913                 case OP_X86_OR_MEMBASE_REG:
3914                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3915                         break;
3916                 case OP_X86_XOR_MEMBASE_REG:
3917                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3918                         break;
3919                 case OP_X86_INC_MEMBASE:
3920                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3921                         break;
3922                 case OP_X86_INC_REG:
3923                         amd64_inc_reg_size (code, ins->dreg, 4);
3924                         break;
3925                 case OP_X86_DEC_MEMBASE:
3926                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3927                         break;
3928                 case OP_X86_DEC_REG:
3929                         amd64_dec_reg_size (code, ins->dreg, 4);
3930                         break;
3931                 case OP_X86_MUL_REG_MEMBASE:
3932                 case OP_X86_MUL_MEMBASE_REG:
3933                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3934                         break;
3935                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3936                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3937                         break;
3938                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3939                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3940                         break;
3941                 case OP_AMD64_COMPARE_MEMBASE_REG:
3942                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3943                         break;
3944                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3945                         g_assert (amd64_is_imm32 (ins->inst_imm));
3946                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3947                         break;
3948                 case OP_X86_COMPARE_MEMBASE8_IMM:
3949                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3950                         break;
3951                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3952                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3953                         break;
3954                 case OP_AMD64_COMPARE_REG_MEMBASE:
3955                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3956                         break;
3957
3958                 case OP_AMD64_ADD_REG_MEMBASE:
3959                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3960                         break;
3961                 case OP_AMD64_SUB_REG_MEMBASE:
3962                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3963                         break;
3964                 case OP_AMD64_AND_REG_MEMBASE:
3965                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3966                         break;
3967                 case OP_AMD64_OR_REG_MEMBASE:
3968                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3969                         break;
3970                 case OP_AMD64_XOR_REG_MEMBASE:
3971                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3972                         break;
3973
3974                 case OP_AMD64_ADD_MEMBASE_REG:
3975                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3976                         break;
3977                 case OP_AMD64_SUB_MEMBASE_REG:
3978                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3979                         break;
3980                 case OP_AMD64_AND_MEMBASE_REG:
3981                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3982                         break;
3983                 case OP_AMD64_OR_MEMBASE_REG:
3984                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3985                         break;
3986                 case OP_AMD64_XOR_MEMBASE_REG:
3987                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3988                         break;
3989
3990                 case OP_AMD64_ADD_MEMBASE_IMM:
3991                         g_assert (amd64_is_imm32 (ins->inst_imm));
3992                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3993                         break;
3994                 case OP_AMD64_SUB_MEMBASE_IMM:
3995                         g_assert (amd64_is_imm32 (ins->inst_imm));
3996                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3997                         break;
3998                 case OP_AMD64_AND_MEMBASE_IMM:
3999                         g_assert (amd64_is_imm32 (ins->inst_imm));
4000                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4001                         break;
4002                 case OP_AMD64_OR_MEMBASE_IMM:
4003                         g_assert (amd64_is_imm32 (ins->inst_imm));
4004                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4005                         break;
4006                 case OP_AMD64_XOR_MEMBASE_IMM:
4007                         g_assert (amd64_is_imm32 (ins->inst_imm));
4008                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4009                         break;
4010
4011                 case OP_BREAK:
4012                         amd64_breakpoint (code);
4013                         break;
4014                 case OP_RELAXED_NOP:
4015                         x86_prefix (code, X86_REP_PREFIX);
4016                         x86_nop (code);
4017                         break;
4018                 case OP_HARD_NOP:
4019                         x86_nop (code);
4020                         break;
4021                 case OP_NOP:
4022                 case OP_DUMMY_USE:
4023                 case OP_DUMMY_STORE:
4024                 case OP_DUMMY_ICONST:
4025                 case OP_DUMMY_R8CONST:
4026                 case OP_NOT_REACHED:
4027                 case OP_NOT_NULL:
4028                         break;
4029                 case OP_IL_SEQ_POINT:
4030                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4031                         break;
4032                 case OP_SEQ_POINT: {
4033                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4034                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4035                                 guint8 *label;
4036
4037                                 /* Load ss_tramp_var */
4038                                 /* This is equal to &ss_trampoline */
4039                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4040                                 /* Load the trampoline address */
4041                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4042                                 /* Call it if it is non-null */
4043                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4044                                 label = code;
4045                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4046                                 amd64_call_reg (code, AMD64_R11);
4047                                 amd64_patch (label, code);
4048                         }
4049
4050                         /*
4051                          * This is the address which is saved in seq points,
4052                          */
4053                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4054
4055                         if (cfg->compile_aot) {
4056                                 guint32 offset = code - cfg->native_code;
4057                                 guint32 val;
4058                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4059                                 guint8 *label;
4060
4061                                 /* Load info var */
4062                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4063                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4064                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4065                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4066                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4067                                 label = code;
4068                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4069                                 /* Call the trampoline */
4070                                 amd64_call_reg (code, AMD64_R11);
4071                                 amd64_patch (label, code);
4072                         } else {
4073                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4074                                 guint8 *label;
4075
4076                                 /*
4077                                  * Emit a test+branch against a constant, the constant will be overwritten
4078                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4079                                  */
4080                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4081                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4082                                 label = code;
4083                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4084
4085                                 g_assert (var);
4086                                 g_assert (var->opcode == OP_REGOFFSET);
4087                                 /* Load bp_tramp_var */
4088                                 /* This is equal to &bp_trampoline */
4089                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4090                                 /* Call the trampoline */
4091                                 amd64_call_membase (code, AMD64_R11, 0);
4092                                 amd64_patch (label, code);
4093                         }
4094                         /*
4095                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4096                          * to another IL offset.
4097                          */
4098                         x86_nop (code);
4099                         break;
4100                 }
4101                 case OP_ADDCC:
4102                 case OP_LADDCC:
4103                 case OP_LADD:
4104                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4105                         break;
4106                 case OP_ADC:
4107                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4108                         break;
4109                 case OP_ADD_IMM:
4110                 case OP_LADD_IMM:
4111                         g_assert (amd64_is_imm32 (ins->inst_imm));
4112                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4113                         break;
4114                 case OP_ADC_IMM:
4115                         g_assert (amd64_is_imm32 (ins->inst_imm));
4116                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4117                         break;
4118                 case OP_SUBCC:
4119                 case OP_LSUBCC:
4120                 case OP_LSUB:
4121                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4122                         break;
4123                 case OP_SBB:
4124                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4125                         break;
4126                 case OP_SUB_IMM:
4127                 case OP_LSUB_IMM:
4128                         g_assert (amd64_is_imm32 (ins->inst_imm));
4129                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4130                         break;
4131                 case OP_SBB_IMM:
4132                         g_assert (amd64_is_imm32 (ins->inst_imm));
4133                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4134                         break;
4135                 case OP_LAND:
4136                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4137                         break;
4138                 case OP_AND_IMM:
4139                 case OP_LAND_IMM:
4140                         g_assert (amd64_is_imm32 (ins->inst_imm));
4141                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4142                         break;
4143                 case OP_LMUL:
4144                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4145                         break;
4146                 case OP_MUL_IMM:
4147                 case OP_LMUL_IMM:
4148                 case OP_IMUL_IMM: {
4149                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4150
4151                         switch (ins->inst_imm) {
4152                         case 2:
4153                                 /* MOV r1, r2 */
4154                                 /* ADD r1, r1 */
4155                                 if (ins->dreg != ins->sreg1)
4156                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4157                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4158                                 break;
4159                         case 3:
4160                                 /* LEA r1, [r2 + r2*2] */
4161                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4162                                 break;
4163                         case 5:
4164                                 /* LEA r1, [r2 + r2*4] */
4165                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4166                                 break;
4167                         case 6:
4168                                 /* LEA r1, [r2 + r2*2] */
4169                                 /* ADD r1, r1          */
4170                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4171                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4172                                 break;
4173                         case 9:
4174                                 /* LEA r1, [r2 + r2*8] */
4175                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4176                                 break;
4177                         case 10:
4178                                 /* LEA r1, [r2 + r2*4] */
4179                                 /* ADD r1, r1          */
4180                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4181                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4182                                 break;
4183                         case 12:
4184                                 /* LEA r1, [r2 + r2*2] */
4185                                 /* SHL r1, 2           */
4186                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4187                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4188                                 break;
4189                         case 25:
4190                                 /* LEA r1, [r2 + r2*4] */
4191                                 /* LEA r1, [r1 + r1*4] */
4192                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4193                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4194                                 break;
4195                         case 100:
4196                                 /* LEA r1, [r2 + r2*4] */
4197                                 /* SHL r1, 2           */
4198                                 /* LEA r1, [r1 + r1*4] */
4199                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4200                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4201                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4202                                 break;
4203                         default:
4204                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4205                                 break;
4206                         }
4207                         break;
4208                 }
4209                 case OP_LDIV:
4210                 case OP_LREM:
4211                         /* Regalloc magic makes the div/rem cases the same */
4212                         if (ins->sreg2 == AMD64_RDX) {
4213                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4214                                 amd64_cdq (code);
4215                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4216                         } else {
4217                                 amd64_cdq (code);
4218                                 amd64_div_reg (code, ins->sreg2, TRUE);
4219                         }
4220                         break;
4221                 case OP_LDIV_UN:
4222                 case OP_LREM_UN:
4223                         if (ins->sreg2 == AMD64_RDX) {
4224                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4225                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4226                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4227                         } else {
4228                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4229                                 amd64_div_reg (code, ins->sreg2, FALSE);
4230                         }
4231                         break;
4232                 case OP_IDIV:
4233                 case OP_IREM:
4234                         if (ins->sreg2 == AMD64_RDX) {
4235                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4236                                 amd64_cdq_size (code, 4);
4237                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4238                         } else {
4239                                 amd64_cdq_size (code, 4);
4240                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4241                         }
4242                         break;
4243                 case OP_IDIV_UN:
4244                 case OP_IREM_UN:
4245                         if (ins->sreg2 == AMD64_RDX) {
4246                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4247                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4248                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4249                         } else {
4250                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4251                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4252                         }
4253                         break;
4254                 case OP_LMUL_OVF:
4255                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4256                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4257                         break;
4258                 case OP_LOR:
4259                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4260                         break;
4261                 case OP_OR_IMM:
4262                 case OP_LOR_IMM:
4263                         g_assert (amd64_is_imm32 (ins->inst_imm));
4264                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4265                         break;
4266                 case OP_LXOR:
4267                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4268                         break;
4269                 case OP_XOR_IMM:
4270                 case OP_LXOR_IMM:
4271                         g_assert (amd64_is_imm32 (ins->inst_imm));
4272                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4273                         break;
4274                 case OP_LSHL:
4275                         g_assert (ins->sreg2 == AMD64_RCX);
4276                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4277                         break;
4278                 case OP_LSHR:
4279                         g_assert (ins->sreg2 == AMD64_RCX);
4280                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4281                         break;
4282                 case OP_SHR_IMM:
4283                 case OP_LSHR_IMM:
4284                         g_assert (amd64_is_imm32 (ins->inst_imm));
4285                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4286                         break;
4287                 case OP_SHR_UN_IMM:
4288                         g_assert (amd64_is_imm32 (ins->inst_imm));
4289                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4290                         break;
4291                 case OP_LSHR_UN_IMM:
4292                         g_assert (amd64_is_imm32 (ins->inst_imm));
4293                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4294                         break;
4295                 case OP_LSHR_UN:
4296                         g_assert (ins->sreg2 == AMD64_RCX);
4297                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4298                         break;
4299                 case OP_SHL_IMM:
4300                 case OP_LSHL_IMM:
4301                         g_assert (amd64_is_imm32 (ins->inst_imm));
4302                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4303                         break;
4304
4305                 case OP_IADDCC:
4306                 case OP_IADD:
4307                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4308                         break;
4309                 case OP_IADC:
4310                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4311                         break;
4312                 case OP_IADD_IMM:
4313                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4314                         break;
4315                 case OP_IADC_IMM:
4316                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4317                         break;
4318                 case OP_ISUBCC:
4319                 case OP_ISUB:
4320                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4321                         break;
4322                 case OP_ISBB:
4323                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4324                         break;
4325                 case OP_ISUB_IMM:
4326                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4327                         break;
4328                 case OP_ISBB_IMM:
4329                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4330                         break;
4331                 case OP_IAND:
4332                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4333                         break;
4334                 case OP_IAND_IMM:
4335                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4336                         break;
4337                 case OP_IOR:
4338                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4339                         break;
4340                 case OP_IOR_IMM:
4341                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4342                         break;
4343                 case OP_IXOR:
4344                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4345                         break;
4346                 case OP_IXOR_IMM:
4347                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4348                         break;
4349                 case OP_INEG:
4350                         amd64_neg_reg_size (code, ins->sreg1, 4);
4351                         break;
4352                 case OP_INOT:
4353                         amd64_not_reg_size (code, ins->sreg1, 4);
4354                         break;
4355                 case OP_ISHL:
4356                         g_assert (ins->sreg2 == AMD64_RCX);
4357                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4358                         break;
4359                 case OP_ISHR:
4360                         g_assert (ins->sreg2 == AMD64_RCX);
4361                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4362                         break;
4363                 case OP_ISHR_IMM:
4364                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4365                         break;
4366                 case OP_ISHR_UN_IMM:
4367                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4368                         break;
4369                 case OP_ISHR_UN:
4370                         g_assert (ins->sreg2 == AMD64_RCX);
4371                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4372                         break;
4373                 case OP_ISHL_IMM:
4374                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4375                         break;
4376                 case OP_IMUL:
4377                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4378                         break;
4379                 case OP_IMUL_OVF:
4380                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4381                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4382                         break;
4383                 case OP_IMUL_OVF_UN:
4384                 case OP_LMUL_OVF_UN: {
4385                         /* the mul operation and the exception check should most likely be split */
4386                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4387                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4388                         /*g_assert (ins->sreg2 == X86_EAX);
4389                         g_assert (ins->dreg == X86_EAX);*/
4390                         if (ins->sreg2 == X86_EAX) {
4391                                 non_eax_reg = ins->sreg1;
4392                         } else if (ins->sreg1 == X86_EAX) {
4393                                 non_eax_reg = ins->sreg2;
4394                         } else {
4395                                 /* no need to save since we're going to store to it anyway */
4396                                 if (ins->dreg != X86_EAX) {
4397                                         saved_eax = TRUE;
4398                                         amd64_push_reg (code, X86_EAX);
4399                                 }
4400                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4401                                 non_eax_reg = ins->sreg2;
4402                         }
4403                         if (ins->dreg == X86_EDX) {
4404                                 if (!saved_eax) {
4405                                         saved_eax = TRUE;
4406                                         amd64_push_reg (code, X86_EAX);
4407                                 }
4408                         } else {
4409                                 saved_edx = TRUE;
4410                                 amd64_push_reg (code, X86_EDX);
4411                         }
4412                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4413                         /* save before the check since pop and mov don't change the flags */
4414                         if (ins->dreg != X86_EAX)
4415                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4416                         if (saved_edx)
4417                                 amd64_pop_reg (code, X86_EDX);
4418                         if (saved_eax)
4419                                 amd64_pop_reg (code, X86_EAX);
4420                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4421                         break;
4422                 }
4423                 case OP_ICOMPARE:
4424                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4425                         break;
4426                 case OP_ICOMPARE_IMM:
4427                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4428                         break;
4429                 case OP_IBEQ:
4430                 case OP_IBLT:
4431                 case OP_IBGT:
4432                 case OP_IBGE:
4433                 case OP_IBLE:
4434                 case OP_LBEQ:
4435                 case OP_LBLT:
4436                 case OP_LBGT:
4437                 case OP_LBGE:
4438                 case OP_LBLE:
4439                 case OP_IBNE_UN:
4440                 case OP_IBLT_UN:
4441                 case OP_IBGT_UN:
4442                 case OP_IBGE_UN:
4443                 case OP_IBLE_UN:
4444                 case OP_LBNE_UN:
4445                 case OP_LBLT_UN:
4446                 case OP_LBGT_UN:
4447                 case OP_LBGE_UN:
4448                 case OP_LBLE_UN:
4449                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4450                         break;
4451
4452                 case OP_CMOV_IEQ:
4453                 case OP_CMOV_IGE:
4454                 case OP_CMOV_IGT:
4455                 case OP_CMOV_ILE:
4456                 case OP_CMOV_ILT:
4457                 case OP_CMOV_INE_UN:
4458                 case OP_CMOV_IGE_UN:
4459                 case OP_CMOV_IGT_UN:
4460                 case OP_CMOV_ILE_UN:
4461                 case OP_CMOV_ILT_UN:
4462                 case OP_CMOV_LEQ:
4463                 case OP_CMOV_LGE:
4464                 case OP_CMOV_LGT:
4465                 case OP_CMOV_LLE:
4466                 case OP_CMOV_LLT:
4467                 case OP_CMOV_LNE_UN:
4468                 case OP_CMOV_LGE_UN:
4469                 case OP_CMOV_LGT_UN:
4470                 case OP_CMOV_LLE_UN:
4471                 case OP_CMOV_LLT_UN:
4472                         g_assert (ins->dreg == ins->sreg1);
4473                         /* This needs to operate on 64 bit values */
4474                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4475                         break;
4476
4477                 case OP_LNOT:
4478                         amd64_not_reg (code, ins->sreg1);
4479                         break;
4480                 case OP_LNEG:
4481                         amd64_neg_reg (code, ins->sreg1);
4482                         break;
4483
4484                 case OP_ICONST:
4485                 case OP_I8CONST:
4486                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4487                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4488                         else
4489                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4490                         break;
4491                 case OP_AOTCONST:
4492                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4493                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4494                         break;
4495                 case OP_JUMP_TABLE:
4496                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4497                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4498                         break;
4499                 case OP_MOVE:
4500                         if (ins->dreg != ins->sreg1)
4501                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4502                         break;
4503                 case OP_AMD64_SET_XMMREG_R4: {
4504                         if (cfg->r4fp) {
4505                                 if (ins->dreg != ins->sreg1)
4506                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4507                         } else {
4508                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4509                         }
4510                         break;
4511                 }
4512                 case OP_AMD64_SET_XMMREG_R8: {
4513                         if (ins->dreg != ins->sreg1)
4514                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4515                         break;
4516                 }
4517                 case OP_TAILCALL: {
4518                         MonoCallInst *call = (MonoCallInst*)ins;
4519                         int i, save_area_offset;
4520
4521                         g_assert (!cfg->method->save_lmf);
4522
4523                         /* Restore callee saved registers */
4524                         save_area_offset = cfg->arch.reg_save_area_offset;
4525                         for (i = 0; i < AMD64_NREG; ++i)
4526                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4527                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4528                                         save_area_offset += 8;
4529                                 }
4530
4531                         if (cfg->arch.omit_fp) {
4532                                 if (cfg->arch.stack_alloc_size)
4533                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4534                                 // FIXME:
4535                                 if (call->stack_usage)
4536                                         NOT_IMPLEMENTED;
4537                         } else {
4538                                 /* Copy arguments on the stack to our argument area */
4539                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4540                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4541                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4542                                 }
4543
4544                                 amd64_leave (code);
4545                         }
4546
4547                         offset = code - cfg->native_code;
4548                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4549                         if (cfg->compile_aot)
4550                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4551                         else
4552                                 amd64_set_reg_template (code, AMD64_R11);
4553                         amd64_jump_reg (code, AMD64_R11);
4554                         ins->flags |= MONO_INST_GC_CALLSITE;
4555                         ins->backend.pc_offset = code - cfg->native_code;
4556                         break;
4557                 }
4558                 case OP_CHECK_THIS:
4559                         /* ensure ins->sreg1 is not NULL */
4560                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4561                         break;
4562                 case OP_ARGLIST: {
4563                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4564                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4565                         break;
4566                 }
4567                 case OP_CALL:
4568                 case OP_FCALL:
4569                 case OP_RCALL:
4570                 case OP_LCALL:
4571                 case OP_VCALL:
4572                 case OP_VCALL2:
4573                 case OP_VOIDCALL:
4574                         call = (MonoCallInst*)ins;
4575                         /*
4576                          * The AMD64 ABI forces callers to know about varargs.
4577                          */
4578                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4579                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4580                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4581                                 /*
4582                                  * Since the unmanaged calling convention doesn't contain a
4583                                  * 'vararg' entry, we have to treat every pinvoke call as a
4584                                  * potential vararg call.
4585                                  */
4586                                 guint32 nregs, i;
4587                                 nregs = 0;
4588                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4589                                         if (call->used_fregs & (1 << i))
4590                                                 nregs ++;
4591                                 if (!nregs)
4592                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4593                                 else
4594                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4595                         }
4596
4597                         if (ins->flags & MONO_INST_HAS_METHOD)
4598                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4599                         else
4600                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4601                         ins->flags |= MONO_INST_GC_CALLSITE;
4602                         ins->backend.pc_offset = code - cfg->native_code;
4603                         code = emit_move_return_value (cfg, ins, code);
4604                         break;
4605                 case OP_FCALL_REG:
4606                 case OP_RCALL_REG:
4607                 case OP_LCALL_REG:
4608                 case OP_VCALL_REG:
4609                 case OP_VCALL2_REG:
4610                 case OP_VOIDCALL_REG:
4611                 case OP_CALL_REG:
4612                         call = (MonoCallInst*)ins;
4613
4614                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4615                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4616                                 ins->sreg1 = AMD64_R11;
4617                         }
4618
4619                         /*
4620                          * The AMD64 ABI forces callers to know about varargs.
4621                          */
4622                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4623                                 if (ins->sreg1 == AMD64_RAX) {
4624                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4625                                         ins->sreg1 = AMD64_R11;
4626                                 }
4627                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4628                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4629                                 /*
4630                                  * Since the unmanaged calling convention doesn't contain a
4631                                  * 'vararg' entry, we have to treat every pinvoke call as a
4632                                  * potential vararg call.
4633                                  */
4634                                 guint32 nregs, i;
4635                                 nregs = 0;
4636                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4637                                         if (call->used_fregs & (1 << i))
4638                                                 nregs ++;
4639                                 if (ins->sreg1 == AMD64_RAX) {
4640                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4641                                         ins->sreg1 = AMD64_R11;
4642                                 }
4643                                 if (!nregs)
4644                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4645                                 else
4646                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4647                         }
4648
4649                         amd64_call_reg (code, ins->sreg1);
4650                         ins->flags |= MONO_INST_GC_CALLSITE;
4651                         ins->backend.pc_offset = code - cfg->native_code;
4652                         code = emit_move_return_value (cfg, ins, code);
4653                         break;
4654                 case OP_FCALL_MEMBASE:
4655                 case OP_RCALL_MEMBASE:
4656                 case OP_LCALL_MEMBASE:
4657                 case OP_VCALL_MEMBASE:
4658                 case OP_VCALL2_MEMBASE:
4659                 case OP_VOIDCALL_MEMBASE:
4660                 case OP_CALL_MEMBASE:
4661                         call = (MonoCallInst*)ins;
4662
4663                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4664                         ins->flags |= MONO_INST_GC_CALLSITE;
4665                         ins->backend.pc_offset = code - cfg->native_code;
4666                         code = emit_move_return_value (cfg, ins, code);
4667                         break;
4668                 case OP_DYN_CALL: {
4669                         int i;
4670                         MonoInst *var = cfg->dyn_call_var;
4671                         guint8 *label;
4672
4673                         g_assert (var->opcode == OP_REGOFFSET);
4674
4675                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4676                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4677                         /* r10 = ftn */
4678                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4679
4680                         /* Save args buffer */
4681                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4682
4683                         /* Set fp arg regs */
4684                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4685                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4686                         label = code;
4687                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4688                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4689                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4690                         amd64_patch (label, code);
4691
4692                         /* Set argument registers */
4693                         for (i = 0; i < PARAM_REGS; ++i)
4694                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4695
4696                         /* Make the call */
4697                         amd64_call_reg (code, AMD64_R10);
4698
4699                         ins->flags |= MONO_INST_GC_CALLSITE;
4700                         ins->backend.pc_offset = code - cfg->native_code;
4701
4702                         /* Save result */
4703                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4704                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4705                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4706                         break;
4707                 }
4708                 case OP_AMD64_SAVE_SP_TO_LMF: {
4709                         MonoInst *lmf_var = cfg->lmf_var;
4710                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4711                         break;
4712                 }
4713                 case OP_X86_PUSH:
4714                         g_assert_not_reached ();
4715                         amd64_push_reg (code, ins->sreg1);
4716                         break;
4717                 case OP_X86_PUSH_IMM:
4718                         g_assert_not_reached ();
4719                         g_assert (amd64_is_imm32 (ins->inst_imm));
4720                         amd64_push_imm (code, ins->inst_imm);
4721                         break;
4722                 case OP_X86_PUSH_MEMBASE:
4723                         g_assert_not_reached ();
4724                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4725                         break;
4726                 case OP_X86_PUSH_OBJ: {
4727                         int size = ALIGN_TO (ins->inst_imm, 8);
4728
4729                         g_assert_not_reached ();
4730
4731                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4732                         amd64_push_reg (code, AMD64_RDI);
4733                         amd64_push_reg (code, AMD64_RSI);
4734                         amd64_push_reg (code, AMD64_RCX);
4735                         if (ins->inst_offset)
4736                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4737                         else
4738                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4739                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4740                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4741                         amd64_cld (code);
4742                         amd64_prefix (code, X86_REP_PREFIX);
4743                         amd64_movsd (code);
4744                         amd64_pop_reg (code, AMD64_RCX);
4745                         amd64_pop_reg (code, AMD64_RSI);
4746                         amd64_pop_reg (code, AMD64_RDI);
4747                         break;
4748                 }
4749                 case OP_GENERIC_CLASS_INIT: {
4750                         static int byte_offset = -1;
4751                         static guint8 bitmask;
4752                         guint8 *jump;
4753
4754                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4755
4756                         if (byte_offset < 0)
4757                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4758
4759                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4760                         jump = code;
4761                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4762
4763                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4764                         ins->flags |= MONO_INST_GC_CALLSITE;
4765                         ins->backend.pc_offset = code - cfg->native_code;
4766
4767                         x86_patch (jump, code);
4768                         break;
4769                 }
4770
4771                 case OP_X86_LEA:
4772                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4773                         break;
4774                 case OP_X86_LEA_MEMBASE:
4775                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4776                         break;
4777                 case OP_X86_XCHG:
4778                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4779                         break;
4780                 case OP_LOCALLOC:
4781                         /* keep alignment */
4782                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4783                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4784                         code = mono_emit_stack_alloc (cfg, code, ins);
4785                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4786                         if (cfg->param_area)
4787                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4788                         break;
4789                 case OP_LOCALLOC_IMM: {
4790                         guint32 size = ins->inst_imm;
4791                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4792
4793                         if (ins->flags & MONO_INST_INIT) {
4794                                 if (size < 64) {
4795                                         int i;
4796
4797                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4798                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4799
4800                                         for (i = 0; i < size; i += 8)
4801                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4802                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4803                                 } else {
4804                                         amd64_mov_reg_imm (code, ins->dreg, size);
4805                                         ins->sreg1 = ins->dreg;
4806
4807                                         code = mono_emit_stack_alloc (cfg, code, ins);
4808                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4809                                 }
4810                         } else {
4811                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4812                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4813                         }
4814                         if (cfg->param_area)
4815                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4816                         break;
4817                 }
4818                 case OP_THROW: {
4819                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4820                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4821                                              (gpointer)"mono_arch_throw_exception", FALSE);
4822                         ins->flags |= MONO_INST_GC_CALLSITE;
4823                         ins->backend.pc_offset = code - cfg->native_code;
4824                         break;
4825                 }
4826                 case OP_RETHROW: {
4827                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4828                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4829                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4830                         ins->flags |= MONO_INST_GC_CALLSITE;
4831                         ins->backend.pc_offset = code - cfg->native_code;
4832                         break;
4833                 }
4834                 case OP_CALL_HANDLER:
4835                         /* Align stack */
4836                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4837                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4838                         amd64_call_imm (code, 0);
4839                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4840                         /* Restore stack alignment */
4841                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4842                         break;
4843                 case OP_START_HANDLER: {
4844                         /* Even though we're saving RSP, use sizeof */
4845                         /* gpointer because spvar is of type IntPtr */
4846                         /* see: mono_create_spvar_for_region */
4847                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4848                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4849
4850                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4851                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4852                                 cfg->param_area) {
4853                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4854                         }
4855                         break;
4856                 }
4857                 case OP_ENDFINALLY: {
4858                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4859                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4860                         amd64_ret (code);
4861                         break;
4862                 }
4863                 case OP_ENDFILTER: {
4864                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4865                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4866                         /* The local allocator will put the result into RAX */
4867                         amd64_ret (code);
4868                         break;
4869                 }
4870                 case OP_GET_EX_OBJ:
4871                         if (ins->dreg != AMD64_RAX)
4872                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4873                         break;
4874                 case OP_LABEL:
4875                         ins->inst_c0 = code - cfg->native_code;
4876                         break;
4877                 case OP_BR:
4878                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4879                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4880                         //break;
4881                                 if (ins->inst_target_bb->native_offset) {
4882                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4883                                 } else {
4884                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4885                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4886                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4887                                                 x86_jump8 (code, 0);
4888                                         else
4889                                                 x86_jump32 (code, 0);
4890                         }
4891                         break;
4892                 case OP_BR_REG:
4893                         amd64_jump_reg (code, ins->sreg1);
4894                         break;
4895                 case OP_ICNEQ:
4896                 case OP_ICGE:
4897                 case OP_ICLE:
4898                 case OP_ICGE_UN:
4899                 case OP_ICLE_UN:
4900
4901                 case OP_CEQ:
4902                 case OP_LCEQ:
4903                 case OP_ICEQ:
4904                 case OP_CLT:
4905                 case OP_LCLT:
4906                 case OP_ICLT:
4907                 case OP_CGT:
4908                 case OP_ICGT:
4909                 case OP_LCGT:
4910                 case OP_CLT_UN:
4911                 case OP_LCLT_UN:
4912                 case OP_ICLT_UN:
4913                 case OP_CGT_UN:
4914                 case OP_LCGT_UN:
4915                 case OP_ICGT_UN:
4916                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4917                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4918                         break;
4919                 case OP_COND_EXC_EQ:
4920                 case OP_COND_EXC_NE_UN:
4921                 case OP_COND_EXC_LT:
4922                 case OP_COND_EXC_LT_UN:
4923                 case OP_COND_EXC_GT:
4924                 case OP_COND_EXC_GT_UN:
4925                 case OP_COND_EXC_GE:
4926                 case OP_COND_EXC_GE_UN:
4927                 case OP_COND_EXC_LE:
4928                 case OP_COND_EXC_LE_UN:
4929                 case OP_COND_EXC_IEQ:
4930                 case OP_COND_EXC_INE_UN:
4931                 case OP_COND_EXC_ILT:
4932                 case OP_COND_EXC_ILT_UN:
4933                 case OP_COND_EXC_IGT:
4934                 case OP_COND_EXC_IGT_UN:
4935                 case OP_COND_EXC_IGE:
4936                 case OP_COND_EXC_IGE_UN:
4937                 case OP_COND_EXC_ILE:
4938                 case OP_COND_EXC_ILE_UN:
4939                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4940                         break;
4941                 case OP_COND_EXC_OV:
4942                 case OP_COND_EXC_NO:
4943                 case OP_COND_EXC_C:
4944                 case OP_COND_EXC_NC:
4945                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4946                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4947                         break;
4948                 case OP_COND_EXC_IOV:
4949                 case OP_COND_EXC_INO:
4950                 case OP_COND_EXC_IC:
4951                 case OP_COND_EXC_INC:
4952                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4953                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4954                         break;
4955
4956                 /* floating point opcodes */
4957                 case OP_R8CONST: {
4958                         double d = *(double *)ins->inst_p0;
4959
4960                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4961                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4962                         }
4963                         else {
4964                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4965                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4966                         }
4967                         break;
4968                 }
4969                 case OP_R4CONST: {
4970                         float f = *(float *)ins->inst_p0;
4971
4972                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4973                                 if (cfg->r4fp)
4974                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4975                                 else
4976                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4977                         }
4978                         else {
4979                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4980                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4981                                 if (!cfg->r4fp)
4982                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4983                         }
4984                         break;
4985                 }
4986                 case OP_STORER8_MEMBASE_REG:
4987                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4988                         break;
4989                 case OP_LOADR8_MEMBASE:
4990                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4991                         break;
4992                 case OP_STORER4_MEMBASE_REG:
4993                         if (cfg->r4fp) {
4994                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4995                         } else {
4996                                 /* This requires a double->single conversion */
4997                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4998                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4999                         }
5000                         break;
5001                 case OP_LOADR4_MEMBASE:
5002                         if (cfg->r4fp) {
5003                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5004                         } else {
5005                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5006                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5007                         }
5008                         break;
5009                 case OP_ICONV_TO_R4:
5010                         if (cfg->r4fp) {
5011                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5012                         } else {
5013                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5014                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5015                         }
5016                         break;
5017                 case OP_ICONV_TO_R8:
5018                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5019                         break;
5020                 case OP_LCONV_TO_R4:
5021                         if (cfg->r4fp) {
5022                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5023                         } else {
5024                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5025                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5026                         }
5027                         break;
5028                 case OP_LCONV_TO_R8:
5029                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5030                         break;
5031                 case OP_FCONV_TO_R4:
5032                         if (cfg->r4fp) {
5033                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5034                         } else {
5035                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5036                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5037                         }
5038                         break;
5039                 case OP_FCONV_TO_I1:
5040                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5041                         break;
5042                 case OP_FCONV_TO_U1:
5043                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5044                         break;
5045                 case OP_FCONV_TO_I2:
5046                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5047                         break;
5048                 case OP_FCONV_TO_U2:
5049                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5050                         break;
5051                 case OP_FCONV_TO_U4:
5052                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5053                         break;
5054                 case OP_FCONV_TO_I4:
5055                 case OP_FCONV_TO_I:
5056                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5057                         break;
5058                 case OP_FCONV_TO_I8:
5059                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5060                         break;
5061
5062                 case OP_RCONV_TO_I1:
5063                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5064                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5065                         break;
5066                 case OP_RCONV_TO_U1:
5067                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5068                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5069                         break;
5070                 case OP_RCONV_TO_I2:
5071                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5072                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5073                         break;
5074                 case OP_RCONV_TO_U2:
5075                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5076                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5077                         break;
5078                 case OP_RCONV_TO_I4:
5079                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5080                         break;
5081                 case OP_RCONV_TO_U4:
5082                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5083                         break;
5084                 case OP_RCONV_TO_I8:
5085                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5086                         break;
5087                 case OP_RCONV_TO_R8:
5088                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5089                         break;
5090                 case OP_RCONV_TO_R4:
5091                         if (ins->dreg != ins->sreg1)
5092                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5093                         break;
5094
5095                 case OP_LCONV_TO_R_UN: {
5096                         guint8 *br [2];
5097
5098                         /* Based on gcc code */
5099                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5100                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5101
5102                         /* Positive case */
5103                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5104                         br [1] = code; x86_jump8 (code, 0);
5105                         amd64_patch (br [0], code);
5106
5107                         /* Negative case */
5108                         /* Save to the red zone */
5109                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5110                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5111                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5112                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5113                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5114                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5115                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5116                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5117                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5118                         /* Restore */
5119                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5120                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5121                         amd64_patch (br [1], code);
5122                         break;
5123                 }
5124                 case OP_LCONV_TO_OVF_U4:
5125                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5126                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5127                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5128                         break;
5129                 case OP_LCONV_TO_OVF_I4_UN:
5130                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5131                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5132                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5133                         break;
5134                 case OP_FMOVE:
5135                         if (ins->dreg != ins->sreg1)
5136                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5137                         break;
5138                 case OP_RMOVE:
5139                         if (ins->dreg != ins->sreg1)
5140                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5141                         break;
5142                 case OP_MOVE_F_TO_I4:
5143                         if (cfg->r4fp) {
5144                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5145                         } else {
5146                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5147                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5148                         }
5149                         break;
5150                 case OP_MOVE_I4_TO_F:
5151                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5152                         if (!cfg->r4fp)
5153                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5154                         break;
5155                 case OP_MOVE_F_TO_I8:
5156                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5157                         break;
5158                 case OP_MOVE_I8_TO_F:
5159                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5160                         break;
5161                 case OP_FADD:
5162                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5163                         break;
5164                 case OP_FSUB:
5165                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5166                         break;
5167                 case OP_FMUL:
5168                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5169                         break;
5170                 case OP_FDIV:
5171                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5172                         break;
5173                 case OP_FNEG: {
5174                         static double r8_0 = -0.0;
5175
5176                         g_assert (ins->sreg1 == ins->dreg);
5177
5178                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5179                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5180                         break;
5181                 }
5182                 case OP_SIN:
5183                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5184                         break;
5185                 case OP_COS:
5186                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5187                         break;
5188                 case OP_ABS: {
5189                         static guint64 d = 0x7fffffffffffffffUL;
5190
5191                         g_assert (ins->sreg1 == ins->dreg);
5192
5193                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5194                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5195                         break;
5196                 }
5197                 case OP_SQRT:
5198                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5199                         break;
5200
5201                 case OP_RADD:
5202                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5203                         break;
5204                 case OP_RSUB:
5205                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5206                         break;
5207                 case OP_RMUL:
5208                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5209                         break;
5210                 case OP_RDIV:
5211                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5212                         break;
5213                 case OP_RNEG: {
5214                         static float r4_0 = -0.0;
5215
5216                         g_assert (ins->sreg1 == ins->dreg);
5217
5218                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5219                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5220                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5221                         break;
5222                 }
5223
5224                 case OP_IMIN:
5225                         g_assert (cfg->opt & MONO_OPT_CMOV);
5226                         g_assert (ins->dreg == ins->sreg1);
5227                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5228                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5229                         break;
5230                 case OP_IMIN_UN:
5231                         g_assert (cfg->opt & MONO_OPT_CMOV);
5232                         g_assert (ins->dreg == ins->sreg1);
5233                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5234                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5235                         break;
5236                 case OP_IMAX:
5237                         g_assert (cfg->opt & MONO_OPT_CMOV);
5238                         g_assert (ins->dreg == ins->sreg1);
5239                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5240                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5241                         break;
5242                 case OP_IMAX_UN:
5243                         g_assert (cfg->opt & MONO_OPT_CMOV);
5244                         g_assert (ins->dreg == ins->sreg1);
5245                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5246                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5247                         break;
5248                 case OP_LMIN:
5249                         g_assert (cfg->opt & MONO_OPT_CMOV);
5250                         g_assert (ins->dreg == ins->sreg1);
5251                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5252                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5253                         break;
5254                 case OP_LMIN_UN:
5255                         g_assert (cfg->opt & MONO_OPT_CMOV);
5256                         g_assert (ins->dreg == ins->sreg1);
5257                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5258                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5259                         break;
5260                 case OP_LMAX:
5261                         g_assert (cfg->opt & MONO_OPT_CMOV);
5262                         g_assert (ins->dreg == ins->sreg1);
5263                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5264                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5265                         break;
5266                 case OP_LMAX_UN:
5267                         g_assert (cfg->opt & MONO_OPT_CMOV);
5268                         g_assert (ins->dreg == ins->sreg1);
5269                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5270                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5271                         break;
5272                 case OP_X86_FPOP:
5273                         break;
5274                 case OP_FCOMPARE:
5275                         /*
5276                          * The two arguments are swapped because the fbranch instructions
5277                          * depend on this for the non-sse case to work.
5278                          */
5279                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5280                         break;
5281                 case OP_RCOMPARE:
5282                         /*
5283                          * FIXME: Get rid of this.
5284                          * The two arguments are swapped because the fbranch instructions
5285                          * depend on this for the non-sse case to work.
5286                          */
5287                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5288                         break;
5289                 case OP_FCNEQ:
5290                 case OP_FCEQ: {
5291                         /* zeroing the register at the start results in
5292                          * shorter and faster code (we can also remove the widening op)
5293                          */
5294                         guchar *unordered_check;
5295
5296                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5297                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5298                         unordered_check = code;
5299                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5300
5301                         if (ins->opcode == OP_FCEQ) {
5302                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5303                                 amd64_patch (unordered_check, code);
5304                         } else {
5305                                 guchar *jump_to_end;
5306                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5307                                 jump_to_end = code;
5308                                 x86_jump8 (code, 0);
5309                                 amd64_patch (unordered_check, code);
5310                                 amd64_inc_reg (code, ins->dreg);
5311                                 amd64_patch (jump_to_end, code);
5312                         }
5313                         break;
5314                 }
5315                 case OP_FCLT:
5316                 case OP_FCLT_UN: {
5317                         /* zeroing the register at the start results in
5318                          * shorter and faster code (we can also remove the widening op)
5319                          */
5320                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5321                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5322                         if (ins->opcode == OP_FCLT_UN) {
5323                                 guchar *unordered_check = code;
5324                                 guchar *jump_to_end;
5325                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5326                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5327                                 jump_to_end = code;
5328                                 x86_jump8 (code, 0);
5329                                 amd64_patch (unordered_check, code);
5330                                 amd64_inc_reg (code, ins->dreg);
5331                                 amd64_patch (jump_to_end, code);
5332                         } else {
5333                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5334                         }
5335                         break;
5336                 }
5337                 case OP_FCLE: {
5338                         guchar *unordered_check;
5339                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5340                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5341                         unordered_check = code;
5342                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5343                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5344                         amd64_patch (unordered_check, code);
5345                         break;
5346                 }
5347                 case OP_FCGT:
5348                 case OP_FCGT_UN: {
5349                         /* zeroing the register at the start results in
5350                          * shorter and faster code (we can also remove the widening op)
5351                          */
5352                         guchar *unordered_check;
5353
5354                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5355                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5356                         if (ins->opcode == OP_FCGT) {
5357                                 unordered_check = code;
5358                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5359                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5360                                 amd64_patch (unordered_check, code);
5361                         } else {
5362                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5363                         }
5364                         break;
5365                 }
5366                 case OP_FCGE: {
5367                         guchar *unordered_check;
5368                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5369                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5370                         unordered_check = code;
5371                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5372                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5373                         amd64_patch (unordered_check, code);
5374                         break;
5375                 }
5376
5377                 case OP_RCEQ:
5378                 case OP_RCGT:
5379                 case OP_RCLT:
5380                 case OP_RCLT_UN:
5381                 case OP_RCGT_UN: {
5382                         int x86_cond;
5383                         gboolean unordered = FALSE;
5384
5385                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5386                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5387
5388                         switch (ins->opcode) {
5389                         case OP_RCEQ:
5390                                 x86_cond = X86_CC_EQ;
5391                                 break;
5392                         case OP_RCGT:
5393                                 x86_cond = X86_CC_LT;
5394                                 break;
5395                         case OP_RCLT:
5396                                 x86_cond = X86_CC_GT;
5397                                 break;
5398                         case OP_RCLT_UN:
5399                                 x86_cond = X86_CC_GT;
5400                                 unordered = TRUE;
5401                                 break;
5402                         case OP_RCGT_UN:
5403                                 x86_cond = X86_CC_LT;
5404                                 unordered = TRUE;
5405                                 break;
5406                         default:
5407                                 g_assert_not_reached ();
5408                                 break;
5409                         }
5410
5411                         if (unordered) {
5412                                 guchar *unordered_check;
5413                                 guchar *jump_to_end;
5414
5415                                 unordered_check = code;
5416                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5417                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5418                                 jump_to_end = code;
5419                                 x86_jump8 (code, 0);
5420                                 amd64_patch (unordered_check, code);
5421                                 amd64_inc_reg (code, ins->dreg);
5422                                 amd64_patch (jump_to_end, code);
5423                         } else {
5424                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5425                         }
5426                         break;
5427                 }
5428                 case OP_FCLT_MEMBASE:
5429                 case OP_FCGT_MEMBASE:
5430                 case OP_FCLT_UN_MEMBASE:
5431                 case OP_FCGT_UN_MEMBASE:
5432                 case OP_FCEQ_MEMBASE: {
5433                         guchar *unordered_check, *jump_to_end;
5434                         int x86_cond;
5435
5436                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5437                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5438
5439                         switch (ins->opcode) {
5440                         case OP_FCEQ_MEMBASE:
5441                                 x86_cond = X86_CC_EQ;
5442                                 break;
5443                         case OP_FCLT_MEMBASE:
5444                         case OP_FCLT_UN_MEMBASE:
5445                                 x86_cond = X86_CC_LT;
5446                                 break;
5447                         case OP_FCGT_MEMBASE:
5448                         case OP_FCGT_UN_MEMBASE:
5449                                 x86_cond = X86_CC_GT;
5450                                 break;
5451                         default:
5452                                 g_assert_not_reached ();
5453                         }
5454
5455                         unordered_check = code;
5456                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5457                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5458
5459                         switch (ins->opcode) {
5460                         case OP_FCEQ_MEMBASE:
5461                         case OP_FCLT_MEMBASE:
5462                         case OP_FCGT_MEMBASE:
5463                                 amd64_patch (unordered_check, code);
5464                                 break;
5465                         case OP_FCLT_UN_MEMBASE:
5466                         case OP_FCGT_UN_MEMBASE:
5467                                 jump_to_end = code;
5468                                 x86_jump8 (code, 0);
5469                                 amd64_patch (unordered_check, code);
5470                                 amd64_inc_reg (code, ins->dreg);
5471                                 amd64_patch (jump_to_end, code);
5472                                 break;
5473                         default:
5474                                 break;
5475                         }
5476                         break;
5477                 }
5478                 case OP_FBEQ: {
5479                         guchar *jump = code;
5480                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5481                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5482                         amd64_patch (jump, code);
5483                         break;
5484                 }
5485                 case OP_FBNE_UN:
5486                         /* Branch if C013 != 100 */
5487                         /* branch if !ZF or (PF|CF) */
5488                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5489                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5490                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5491                         break;
5492                 case OP_FBLT:
5493                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5494                         break;
5495                 case OP_FBLT_UN:
5496                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5497                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5498                         break;
5499                 case OP_FBGT:
5500                 case OP_FBGT_UN:
5501                         if (ins->opcode == OP_FBGT) {
5502                                 guchar *br1;
5503
5504                                 /* skip branch if C1=1 */
5505                                 br1 = code;
5506                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5507                                 /* branch if (C0 | C3) = 1 */
5508                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5509                                 amd64_patch (br1, code);
5510                                 break;
5511                         } else {
5512                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5513                         }
5514                         break;
5515                 case OP_FBGE: {
5516                         /* Branch if C013 == 100 or 001 */
5517                         guchar *br1;
5518
5519                         /* skip branch if C1=1 */
5520                         br1 = code;
5521                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5522                         /* branch if (C0 | C3) = 1 */
5523                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5524                         amd64_patch (br1, code);
5525                         break;
5526                 }
5527                 case OP_FBGE_UN:
5528                         /* Branch if C013 == 000 */
5529                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5530                         break;
5531                 case OP_FBLE: {
5532                         /* Branch if C013=000 or 100 */
5533                         guchar *br1;
5534
5535                         /* skip branch if C1=1 */
5536                         br1 = code;
5537                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5538                         /* branch if C0=0 */
5539                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5540                         amd64_patch (br1, code);
5541                         break;
5542                 }
5543                 case OP_FBLE_UN:
5544                         /* Branch if C013 != 001 */
5545                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5546                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5547                         break;
5548                 case OP_CKFINITE:
5549                         /* Transfer value to the fp stack */
5550                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5551                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5552                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5553
5554                         amd64_push_reg (code, AMD64_RAX);
5555                         amd64_fxam (code);
5556                         amd64_fnstsw (code);
5557                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5558                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5559                         amd64_pop_reg (code, AMD64_RAX);
5560                         amd64_fstp (code, 0);
5561                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5562                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5563                         break;
5564                 case OP_TLS_GET: {
5565                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5566                         break;
5567                 }
5568                 case OP_TLS_GET_REG:
5569                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5570                         break;
5571                 case OP_TLS_SET: {
5572                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5573                         break;
5574                 }
5575                 case OP_TLS_SET_REG: {
5576                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5577                         break;
5578                 }
5579                 case OP_MEMORY_BARRIER: {
5580                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5581                                 x86_mfence (code);
5582                         break;
5583                 }
5584                 case OP_ATOMIC_ADD_I4:
5585                 case OP_ATOMIC_ADD_I8: {
5586                         int dreg = ins->dreg;
5587                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5588
5589                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5590                                 dreg = AMD64_R11;
5591
5592                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5593                         amd64_prefix (code, X86_LOCK_PREFIX);
5594                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5595                         /* dreg contains the old value, add with sreg2 value */
5596                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5597
5598                         if (ins->dreg != dreg)
5599                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5600
5601                         break;
5602                 }
5603                 case OP_ATOMIC_EXCHANGE_I4:
5604                 case OP_ATOMIC_EXCHANGE_I8: {
5605                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5606
5607                         /* LOCK prefix is implied. */
5608                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5609                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5610                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5611                         break;
5612                 }
5613                 case OP_ATOMIC_CAS_I4:
5614                 case OP_ATOMIC_CAS_I8: {
5615                         guint32 size;
5616
5617                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5618                                 size = 8;
5619                         else
5620                                 size = 4;
5621
5622                         /*
5623                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5624                          * an explanation of how this works.
5625                          */
5626                         g_assert (ins->sreg3 == AMD64_RAX);
5627                         g_assert (ins->sreg1 != AMD64_RAX);
5628                         g_assert (ins->sreg1 != ins->sreg2);
5629
5630                         amd64_prefix (code, X86_LOCK_PREFIX);
5631                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5632
5633                         if (ins->dreg != AMD64_RAX)
5634                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5635                         break;
5636                 }
5637                 case OP_ATOMIC_LOAD_I1: {
5638                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5639                         break;
5640                 }
5641                 case OP_ATOMIC_LOAD_U1: {
5642                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5643                         break;
5644                 }
5645                 case OP_ATOMIC_LOAD_I2: {
5646                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5647                         break;
5648                 }
5649                 case OP_ATOMIC_LOAD_U2: {
5650                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5651                         break;
5652                 }
5653                 case OP_ATOMIC_LOAD_I4: {
5654                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5655                         break;
5656                 }
5657                 case OP_ATOMIC_LOAD_U4:
5658                 case OP_ATOMIC_LOAD_I8:
5659                 case OP_ATOMIC_LOAD_U8: {
5660                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5661                         break;
5662                 }
5663                 case OP_ATOMIC_LOAD_R4: {
5664                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5665                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5666                         break;
5667                 }
5668                 case OP_ATOMIC_LOAD_R8: {
5669                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5670                         break;
5671                 }
5672                 case OP_ATOMIC_STORE_I1:
5673                 case OP_ATOMIC_STORE_U1:
5674                 case OP_ATOMIC_STORE_I2:
5675                 case OP_ATOMIC_STORE_U2:
5676                 case OP_ATOMIC_STORE_I4:
5677                 case OP_ATOMIC_STORE_U4:
5678                 case OP_ATOMIC_STORE_I8:
5679                 case OP_ATOMIC_STORE_U8: {
5680                         int size;
5681
5682                         switch (ins->opcode) {
5683                         case OP_ATOMIC_STORE_I1:
5684                         case OP_ATOMIC_STORE_U1:
5685                                 size = 1;
5686                                 break;
5687                         case OP_ATOMIC_STORE_I2:
5688                         case OP_ATOMIC_STORE_U2:
5689                                 size = 2;
5690                                 break;
5691                         case OP_ATOMIC_STORE_I4:
5692                         case OP_ATOMIC_STORE_U4:
5693                                 size = 4;
5694                                 break;
5695                         case OP_ATOMIC_STORE_I8:
5696                         case OP_ATOMIC_STORE_U8:
5697                                 size = 8;
5698                                 break;
5699                         }
5700
5701                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5702
5703                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5704                                 x86_mfence (code);
5705                         break;
5706                 }
5707                 case OP_ATOMIC_STORE_R4: {
5708                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5709                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5710
5711                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5712                                 x86_mfence (code);
5713                         break;
5714                 }
5715                 case OP_ATOMIC_STORE_R8: {
5716                         x86_nop (code);
5717                         x86_nop (code);
5718                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5719                         x86_nop (code);
5720                         x86_nop (code);
5721
5722                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5723                                 x86_mfence (code);
5724                         break;
5725                 }
5726                 case OP_CARD_TABLE_WBARRIER: {
5727                         int ptr = ins->sreg1;
5728                         int value = ins->sreg2;
5729                         guchar *br = 0;
5730                         int nursery_shift, card_table_shift;
5731                         gpointer card_table_mask;
5732                         size_t nursery_size;
5733
5734                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5735                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5736                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5737
5738                         /*If either point to the stack we can simply avoid the WB. This happens due to
5739                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5740                          */
5741                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5742                                 continue;
5743
5744                         /*
5745                          * We need one register we can clobber, we choose EDX and make sreg1
5746                          * fixed EAX to work around limitations in the local register allocator.
5747                          * sreg2 might get allocated to EDX, but that is not a problem since
5748                          * we use it before clobbering EDX.
5749                          */
5750                         g_assert (ins->sreg1 == AMD64_RAX);
5751
5752                         /*
5753                          * This is the code we produce:
5754                          *
5755                          *   edx = value
5756                          *   edx >>= nursery_shift
5757                          *   cmp edx, (nursery_start >> nursery_shift)
5758                          *   jne done
5759                          *   edx = ptr
5760                          *   edx >>= card_table_shift
5761                          *   edx += cardtable
5762                          *   [edx] = 1
5763                          * done:
5764                          */
5765
5766                         if (mono_gc_card_table_nursery_check ()) {
5767                                 if (value != AMD64_RDX)
5768                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5769                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5770                                 if (shifted_nursery_start >> 31) {
5771                                         /*
5772                                          * The value we need to compare against is 64 bits, so we need
5773                                          * another spare register.  We use RBX, which we save and
5774                                          * restore.
5775                                          */
5776                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5777                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5778                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5779                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5780                                 } else {
5781                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5782                                 }
5783                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5784                         }
5785                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5786                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5787                         if (card_table_mask)
5788                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5789
5790                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5791                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5792
5793                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5794
5795                         if (mono_gc_card_table_nursery_check ())
5796                                 x86_patch (br, code);
5797                         break;
5798                 }
5799 #ifdef MONO_ARCH_SIMD_INTRINSICS
5800                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5801                 case OP_ADDPS:
5802                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5803                         break;
5804                 case OP_DIVPS:
5805                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5806                         break;
5807                 case OP_MULPS:
5808                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5809                         break;
5810                 case OP_SUBPS:
5811                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5812                         break;
5813                 case OP_MAXPS:
5814                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5815                         break;
5816                 case OP_MINPS:
5817                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5818                         break;
5819                 case OP_COMPPS:
5820                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5821                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5822                         break;
5823                 case OP_ANDPS:
5824                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5825                         break;
5826                 case OP_ANDNPS:
5827                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5828                         break;
5829                 case OP_ORPS:
5830                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5831                         break;
5832                 case OP_XORPS:
5833                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5834                         break;
5835                 case OP_SQRTPS:
5836                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5837                         break;
5838                 case OP_RSQRTPS:
5839                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5840                         break;
5841                 case OP_RCPPS:
5842                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5843                         break;
5844                 case OP_ADDSUBPS:
5845                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5846                         break;
5847                 case OP_HADDPS:
5848                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5849                         break;
5850                 case OP_HSUBPS:
5851                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5852                         break;
5853                 case OP_DUPPS_HIGH:
5854                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5855                         break;
5856                 case OP_DUPPS_LOW:
5857                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5858                         break;
5859
5860                 case OP_PSHUFLEW_HIGH:
5861                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5862                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5863                         break;
5864                 case OP_PSHUFLEW_LOW:
5865                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5866                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5867                         break;
5868                 case OP_PSHUFLED:
5869                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5870                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5871                         break;
5872                 case OP_SHUFPS:
5873                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5874                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5875                         break;
5876                 case OP_SHUFPD:
5877                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5878                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5879                         break;
5880
5881                 case OP_ADDPD:
5882                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5883                         break;
5884                 case OP_DIVPD:
5885                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_MULPD:
5888                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_SUBPD:
5891                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_MAXPD:
5894                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5895                         break;
5896                 case OP_MINPD:
5897                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5898                         break;
5899                 case OP_COMPPD:
5900                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5901                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5902                         break;
5903                 case OP_ANDPD:
5904                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906                 case OP_ANDNPD:
5907                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909                 case OP_ORPD:
5910                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_XORPD:
5913                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_SQRTPD:
5916                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5917                         break;
5918                 case OP_ADDSUBPD:
5919                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921                 case OP_HADDPD:
5922                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5923                         break;
5924                 case OP_HSUBPD:
5925                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5926                         break;
5927                 case OP_DUPPD:
5928                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5929                         break;
5930
5931                 case OP_EXTRACT_MASK:
5932                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5933                         break;
5934
5935                 case OP_PAND:
5936                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_POR:
5939                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941                 case OP_PXOR:
5942                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944
5945                 case OP_PADDB:
5946                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_PADDW:
5949                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_PADDD:
5952                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954                 case OP_PADDQ:
5955                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5956                         break;
5957
5958                 case OP_PSUBB:
5959                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961                 case OP_PSUBW:
5962                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5963                         break;
5964                 case OP_PSUBD:
5965                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5966                         break;
5967                 case OP_PSUBQ:
5968                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5969                         break;
5970
5971                 case OP_PMAXB_UN:
5972                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5973                         break;
5974                 case OP_PMAXW_UN:
5975                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5976                         break;
5977                 case OP_PMAXD_UN:
5978                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5979                         break;
5980
5981                 case OP_PMAXB:
5982                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_PMAXW:
5985                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_PMAXD:
5988                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990
5991                 case OP_PAVGB_UN:
5992                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994                 case OP_PAVGW_UN:
5995                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997
5998                 case OP_PMINB_UN:
5999                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_PMINW_UN:
6002                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004                 case OP_PMIND_UN:
6005                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007
6008                 case OP_PMINB:
6009                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_PMINW:
6012                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_PMIND:
6015                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017
6018                 case OP_PCMPEQB:
6019                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_PCMPEQW:
6022                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_PCMPEQD:
6025                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_PCMPEQQ:
6028                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030
6031                 case OP_PCMPGTB:
6032                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_PCMPGTW:
6035                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_PCMPGTD:
6038                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_PCMPGTQ:
6041                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043
6044                 case OP_PSUM_ABS_DIFF:
6045                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047
6048                 case OP_UNPACK_LOWB:
6049                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_UNPACK_LOWW:
6052                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_UNPACK_LOWD:
6055                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_UNPACK_LOWQ:
6058                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_UNPACK_LOWPS:
6061                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063                 case OP_UNPACK_LOWPD:
6064                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066
6067                 case OP_UNPACK_HIGHB:
6068                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_UNPACK_HIGHW:
6071                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_UNPACK_HIGHD:
6074                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_UNPACK_HIGHQ:
6077                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_UNPACK_HIGHPS:
6080                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_UNPACK_HIGHPD:
6083                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085
6086                 case OP_PACKW:
6087                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PACKD:
6090                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PACKW_UN:
6093                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PACKD_UN:
6096                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098
6099                 case OP_PADDB_SAT_UN:
6100                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PSUBB_SAT_UN:
6103                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PADDW_SAT_UN:
6106                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_PSUBW_SAT_UN:
6109                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111
6112                 case OP_PADDB_SAT:
6113                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PSUBB_SAT:
6116                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_PADDW_SAT:
6119                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121                 case OP_PSUBW_SAT:
6122                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124
6125                 case OP_PMULW:
6126                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_PMULD:
6129                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_PMULQ:
6132                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_PMULW_HIGH_UN:
6135                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137                 case OP_PMULW_HIGH:
6138                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6139                         break;
6140
6141                 case OP_PSHRW:
6142                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6143                         break;
6144                 case OP_PSHRW_REG:
6145                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6146                         break;
6147
6148                 case OP_PSARW:
6149                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6150                         break;
6151                 case OP_PSARW_REG:
6152                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6153                         break;
6154
6155                 case OP_PSHLW:
6156                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6157                         break;
6158                 case OP_PSHLW_REG:
6159                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6160                         break;
6161
6162                 case OP_PSHRD:
6163                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6164                         break;
6165                 case OP_PSHRD_REG:
6166                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6167                         break;
6168
6169                 case OP_PSARD:
6170                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6171                         break;
6172                 case OP_PSARD_REG:
6173                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6174                         break;
6175
6176                 case OP_PSHLD:
6177                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6178                         break;
6179                 case OP_PSHLD_REG:
6180                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6181                         break;
6182
6183                 case OP_PSHRQ:
6184                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6185                         break;
6186                 case OP_PSHRQ_REG:
6187                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6188                         break;
6189
6190                 /*TODO: This is appart of the sse spec but not added
6191                 case OP_PSARQ:
6192                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6193                         break;
6194                 case OP_PSARQ_REG:
6195                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6196                         break;
6197                 */
6198
6199                 case OP_PSHLQ:
6200                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6201                         break;
6202                 case OP_PSHLQ_REG:
6203                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6204                         break;
6205                 case OP_CVTDQ2PD:
6206                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6207                         break;
6208                 case OP_CVTDQ2PS:
6209                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6210                         break;
6211                 case OP_CVTPD2DQ:
6212                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6213                         break;
6214                 case OP_CVTPD2PS:
6215                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6216                         break;
6217                 case OP_CVTPS2DQ:
6218                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6219                         break;
6220                 case OP_CVTPS2PD:
6221                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6222                         break;
6223                 case OP_CVTTPD2DQ:
6224                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6225                         break;
6226                 case OP_CVTTPS2DQ:
6227                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6228                         break;
6229
6230                 case OP_ICONV_TO_X:
6231                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6232                         break;
6233                 case OP_EXTRACT_I4:
6234                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6235                         break;
6236                 case OP_EXTRACT_I8:
6237                         if (ins->inst_c0) {
6238                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6239                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6240                         } else {
6241                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6242                         }
6243                         break;
6244                 case OP_EXTRACT_I1:
6245                 case OP_EXTRACT_U1:
6246                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6247                         if (ins->inst_c0)
6248                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6249                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6250                         break;
6251                 case OP_EXTRACT_I2:
6252                 case OP_EXTRACT_U2:
6253                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6254                         if (ins->inst_c0)
6255                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6256                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6257                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6258                         break;
6259                 case OP_EXTRACT_R8:
6260                         if (ins->inst_c0)
6261                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6262                         else
6263                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6264                         break;
6265                 case OP_INSERT_I2:
6266                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6267                         break;
6268                 case OP_EXTRACTX_U2:
6269                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6270                         break;
6271                 case OP_INSERTX_U1_SLOW:
6272                         /*sreg1 is the extracted ireg (scratch)
6273                         /sreg2 is the to be inserted ireg (scratch)
6274                         /dreg is the xreg to receive the value*/
6275
6276                         /*clear the bits from the extracted word*/
6277                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6278                         /*shift the value to insert if needed*/
6279                         if (ins->inst_c0 & 1)
6280                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6281                         /*join them together*/
6282                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6283                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6284                         break;
6285                 case OP_INSERTX_I4_SLOW:
6286                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6287                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6288                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6289                         break;
6290                 case OP_INSERTX_I8_SLOW:
6291                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6292                         if (ins->inst_c0)
6293                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6294                         else
6295                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6296                         break;
6297
6298                 case OP_INSERTX_R4_SLOW:
6299                         switch (ins->inst_c0) {
6300                         case 0:
6301                                 if (cfg->r4fp)
6302                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6303                                 else
6304                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6305                                 break;
6306                         case 1:
6307                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6308                                 if (cfg->r4fp)
6309                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6310                                 else
6311                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6312                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6313                                 break;
6314                         case 2:
6315                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6316                                 if (cfg->r4fp)
6317                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6318                                 else
6319                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6320                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6321                                 break;
6322                         case 3:
6323                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6324                                 if (cfg->r4fp)
6325                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6326                                 else
6327                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6328                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6329                                 break;
6330                         }
6331                         break;
6332                 case OP_INSERTX_R8_SLOW:
6333                         if (ins->inst_c0)
6334                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6335                         else
6336                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6337                         break;
6338                 case OP_STOREX_MEMBASE_REG:
6339                 case OP_STOREX_MEMBASE:
6340                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6341                         break;
6342                 case OP_LOADX_MEMBASE:
6343                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6344                         break;
6345                 case OP_LOADX_ALIGNED_MEMBASE:
6346                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6347                         break;
6348                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6349                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6350                         break;
6351                 case OP_STOREX_NTA_MEMBASE_REG:
6352                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6353                         break;
6354                 case OP_PREFETCH_MEMBASE:
6355                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6356                         break;
6357
6358                 case OP_XMOVE:
6359                         /*FIXME the peephole pass should have killed this*/
6360                         if (ins->dreg != ins->sreg1)
6361                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6362                         break;
6363                 case OP_XZERO:
6364                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6365                         break;
6366                 case OP_ICONV_TO_R4_RAW:
6367                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6368                         break;
6369
6370                 case OP_FCONV_TO_R8_X:
6371                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6372                         break;
6373
6374                 case OP_XCONV_R8_TO_I4:
6375                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6376                         switch (ins->backend.source_opcode) {
6377                         case OP_FCONV_TO_I1:
6378                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6379                                 break;
6380                         case OP_FCONV_TO_U1:
6381                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6382                                 break;
6383                         case OP_FCONV_TO_I2:
6384                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6385                                 break;
6386                         case OP_FCONV_TO_U2:
6387                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6388                                 break;
6389                         }
6390                         break;
6391
6392                 case OP_EXPAND_I2:
6393                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6394                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6395                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6396                         break;
6397                 case OP_EXPAND_I4:
6398                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6399                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6400                         break;
6401                 case OP_EXPAND_I8:
6402                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6403                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6404                         break;
6405                 case OP_EXPAND_R4:
6406                         if (cfg->r4fp) {
6407                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6408                         } else {
6409                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6410                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6411                         }
6412                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6413                         break;
6414                 case OP_EXPAND_R8:
6415                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6416                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6417                         break;
6418 #endif
6419                 case OP_LIVERANGE_START: {
6420                         if (cfg->verbose_level > 1)
6421                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6422                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6423                         break;
6424                 }
6425                 case OP_LIVERANGE_END: {
6426                         if (cfg->verbose_level > 1)
6427                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6428                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6429                         break;
6430                 }
6431                 case OP_GC_SAFE_POINT: {
6432                         guint8 *br [1];
6433
6434                         g_assert (mono_threads_is_coop_enabled ());
6435
6436                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6437                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6438                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6439                         amd64_patch (br[0], code);
6440                         break;
6441                 }
6442
6443                 case OP_GC_LIVENESS_DEF:
6444                 case OP_GC_LIVENESS_USE:
6445                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6446                         ins->backend.pc_offset = code - cfg->native_code;
6447                         break;
6448                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6449                         ins->backend.pc_offset = code - cfg->native_code;
6450                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6451                         break;
6452                 default:
6453                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6454                         g_assert_not_reached ();
6455                 }
6456
6457                 if ((code - cfg->native_code - offset) > max_len) {
6458                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6459                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6460                         g_assert_not_reached ();
6461                 }
6462         }
6463
6464         cfg->code_len = code - cfg->native_code;
6465 }
6466
6467 #endif /* DISABLE_JIT */
6468
6469 void
6470 mono_arch_register_lowlevel_calls (void)
6471 {
6472         /* The signature doesn't matter */
6473         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6474 }
6475
6476 void
6477 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6478 {
6479         unsigned char *ip = ji->ip.i + code;
6480
6481         /*
6482          * Debug code to help track down problems where the target of a near call is
6483          * is not valid.
6484          */
6485         if (amd64_is_near_call (ip)) {
6486                 gint64 disp = (guint8*)target - (guint8*)ip;
6487
6488                 if (!amd64_is_imm32 (disp)) {
6489                         printf ("TYPE: %d\n", ji->type);
6490                         switch (ji->type) {
6491                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6492                                 printf ("V: %s\n", ji->data.name);
6493                                 break;
6494                         case MONO_PATCH_INFO_METHOD_JUMP:
6495                         case MONO_PATCH_INFO_METHOD:
6496                                 printf ("V: %s\n", ji->data.method->name);
6497                                 break;
6498                         default:
6499                                 break;
6500                         }
6501                 }
6502         }
6503
6504         amd64_patch (ip, (gpointer)target);
6505 }
6506
6507 #ifndef DISABLE_JIT
6508
6509 static int
6510 get_max_epilog_size (MonoCompile *cfg)
6511 {
6512         int max_epilog_size = 16;
6513
6514         if (cfg->method->save_lmf)
6515                 max_epilog_size += 256;
6516
6517         if (mono_jit_trace_calls != NULL)
6518                 max_epilog_size += 50;
6519
6520         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6521                 max_epilog_size += 50;
6522
6523         max_epilog_size += (AMD64_NREG * 2);
6524
6525         return max_epilog_size;
6526 }
6527
6528 /*
6529  * This macro is used for testing whenever the unwinder works correctly at every point
6530  * where an async exception can happen.
6531  */
6532 /* This will generate a SIGSEGV at the given point in the code */
6533 #define async_exc_point(code) do { \
6534     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6535          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6536              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6537          cfg->arch.async_point_count ++; \
6538     } \
6539 } while (0)
6540
6541 guint8 *
6542 mono_arch_emit_prolog (MonoCompile *cfg)
6543 {
6544         MonoMethod *method = cfg->method;
6545         MonoBasicBlock *bb;
6546         MonoMethodSignature *sig;
6547         MonoInst *ins;
6548         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6549         guint8 *code;
6550         CallInfo *cinfo;
6551         MonoInst *lmf_var = cfg->lmf_var;
6552         gboolean args_clobbered = FALSE;
6553         gboolean trace = FALSE;
6554
6555         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6556
6557         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6558
6559         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6560                 trace = TRUE;
6561
6562         /* Amount of stack space allocated by register saving code */
6563         pos = 0;
6564
6565         /* Offset between RSP and the CFA */
6566         cfa_offset = 0;
6567
6568         /*
6569          * The prolog consists of the following parts:
6570          * FP present:
6571          * - push rbp, mov rbp, rsp
6572          * - save callee saved regs using pushes
6573          * - allocate frame
6574          * - save rgctx if needed
6575          * - save lmf if needed
6576          * FP not present:
6577          * - allocate frame
6578          * - save rgctx if needed
6579          * - save lmf if needed
6580          * - save callee saved regs using moves
6581          */
6582
6583         // CFA = sp + 8
6584         cfa_offset = 8;
6585         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6586         // IP saved at CFA - 8
6587         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6588         async_exc_point (code);
6589         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6590
6591         if (!cfg->arch.omit_fp) {
6592                 amd64_push_reg (code, AMD64_RBP);
6593                 cfa_offset += 8;
6594                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6595                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6596                 async_exc_point (code);
6597 #ifdef TARGET_WIN32
6598                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6599 #endif
6600                 /* These are handled automatically by the stack marking code */
6601                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6602
6603                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6604                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6605                 async_exc_point (code);
6606 #ifdef TARGET_WIN32
6607                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6608 #endif
6609         }
6610
6611         /* The param area is always at offset 0 from sp */
6612         /* This needs to be allocated here, since it has to come after the spill area */
6613         if (cfg->param_area) {
6614                 if (cfg->arch.omit_fp)
6615                         // FIXME:
6616                         g_assert_not_reached ();
6617                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6618         }
6619
6620         if (cfg->arch.omit_fp) {
6621                 /*
6622                  * On enter, the stack is misaligned by the pushing of the return
6623                  * address. It is either made aligned by the pushing of %rbp, or by
6624                  * this.
6625                  */
6626                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6627                 if ((alloc_size % 16) == 0) {
6628                         alloc_size += 8;
6629                         /* Mark the padding slot as NOREF */
6630                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6631                 }
6632         } else {
6633                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6634                 if (cfg->stack_offset != alloc_size) {
6635                         /* Mark the padding slot as NOREF */
6636                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6637                 }
6638                 cfg->arch.sp_fp_offset = alloc_size;
6639                 alloc_size -= pos;
6640         }
6641
6642         cfg->arch.stack_alloc_size = alloc_size;
6643
6644         /* Allocate stack frame */
6645         if (alloc_size) {
6646                 /* See mono_emit_stack_alloc */
6647 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6648                 guint32 remaining_size = alloc_size;
6649                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6650                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6651                 guint32 offset = code - cfg->native_code;
6652                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6653                         while (required_code_size >= (cfg->code_size - offset))
6654                                 cfg->code_size *= 2;
6655                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6656                         code = cfg->native_code + offset;
6657                         cfg->stat_code_reallocs++;
6658                 }
6659
6660                 while (remaining_size >= 0x1000) {
6661                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6662                         if (cfg->arch.omit_fp) {
6663                                 cfa_offset += 0x1000;
6664                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6665                         }
6666                         async_exc_point (code);
6667 #ifdef TARGET_WIN32
6668                         if (cfg->arch.omit_fp)
6669                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6670 #endif
6671
6672                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6673                         remaining_size -= 0x1000;
6674                 }
6675                 if (remaining_size) {
6676                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6677                         if (cfg->arch.omit_fp) {
6678                                 cfa_offset += remaining_size;
6679                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6680                                 async_exc_point (code);
6681                         }
6682 #ifdef TARGET_WIN32
6683                         if (cfg->arch.omit_fp)
6684                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6685 #endif
6686                 }
6687 #else
6688                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6689                 if (cfg->arch.omit_fp) {
6690                         cfa_offset += alloc_size;
6691                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6692                         async_exc_point (code);
6693                 }
6694 #endif
6695         }
6696
6697         /* Stack alignment check */
6698 #if 0
6699         {
6700                 guint8 *buf;
6701
6702                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6703                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6704                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6705                 buf = code;
6706                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6707                 amd64_breakpoint (code);
6708                 amd64_patch (buf, code);
6709         }
6710 #endif
6711
6712         if (mini_get_debug_options ()->init_stacks) {
6713                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6714
6715                 /* Save registers to the red zone */
6716                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6717                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6718
6719                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6720                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6721                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6722
6723                 amd64_cld (code);
6724                 amd64_prefix (code, X86_REP_PREFIX);
6725                 amd64_stosl (code);
6726
6727                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6728                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6729         }
6730
6731         /* Save LMF */
6732         if (method->save_lmf)
6733                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6734
6735         /* Save callee saved registers */
6736         if (cfg->arch.omit_fp) {
6737                 save_area_offset = cfg->arch.reg_save_area_offset;
6738                 /* Save caller saved registers after sp is adjusted */
6739                 /* The registers are saved at the bottom of the frame */
6740                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6741         } else {
6742                 /* The registers are saved just below the saved rbp */
6743                 save_area_offset = cfg->arch.reg_save_area_offset;
6744         }
6745
6746         for (i = 0; i < AMD64_NREG; ++i) {
6747                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6748                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6749
6750                         if (cfg->arch.omit_fp) {
6751                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6752                                 /* These are handled automatically by the stack marking code */
6753                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6754                         } else {
6755                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6756                                 // FIXME: GC
6757                         }
6758
6759                         save_area_offset += 8;
6760                         async_exc_point (code);
6761                 }
6762         }
6763
6764         /* store runtime generic context */
6765         if (cfg->rgctx_var) {
6766                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6767                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6768
6769                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6770
6771                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6772                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6773         }
6774
6775         /* compute max_length in order to use short forward jumps */
6776         max_epilog_size = get_max_epilog_size (cfg);
6777         if (cfg->opt & MONO_OPT_BRANCH) {
6778                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6779                         MonoInst *ins;
6780                         int max_length = 0;
6781
6782                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6783                                 max_length += 6;
6784                         /* max alignment for loops */
6785                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6786                                 max_length += LOOP_ALIGNMENT;
6787
6788                         MONO_BB_FOR_EACH_INS (bb, ins) {
6789                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6790                         }
6791
6792                         /* Take prolog and epilog instrumentation into account */
6793                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6794                                 max_length += max_epilog_size;
6795
6796                         bb->max_length = max_length;
6797                 }
6798         }
6799
6800         sig = mono_method_signature (method);
6801         pos = 0;
6802
6803         cinfo = (CallInfo *)cfg->arch.cinfo;
6804
6805         if (sig->ret->type != MONO_TYPE_VOID) {
6806                 /* Save volatile arguments to the stack */
6807                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6808                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6809         }
6810
6811         /* Keep this in sync with emit_load_volatile_arguments */
6812         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6813                 ArgInfo *ainfo = cinfo->args + i;
6814
6815                 ins = cfg->args [i];
6816
6817                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6818                         /* Unused arguments */
6819                         continue;
6820
6821                 /* Save volatile arguments to the stack */
6822                 if (ins->opcode != OP_REGVAR) {
6823                         switch (ainfo->storage) {
6824                         case ArgInIReg: {
6825                                 guint32 size = 8;
6826
6827                                 /* FIXME: I1 etc */
6828                                 /*
6829                                 if (stack_offset & 0x1)
6830                                         size = 1;
6831                                 else if (stack_offset & 0x2)
6832                                         size = 2;
6833                                 else if (stack_offset & 0x4)
6834                                         size = 4;
6835                                 else
6836                                         size = 8;
6837                                 */
6838                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6839
6840                                 /*
6841                                  * Save the original location of 'this',
6842                                  * get_generic_info_from_stack_frame () needs this to properly look up
6843                                  * the argument value during the handling of async exceptions.
6844                                  */
6845                                 if (ins == cfg->args [0]) {
6846                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6847                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6848                                 }
6849                                 break;
6850                         }
6851                         case ArgInFloatSSEReg:
6852                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6853                                 break;
6854                         case ArgInDoubleSSEReg:
6855                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6856                                 break;
6857                         case ArgValuetypeInReg:
6858                                 for (quad = 0; quad < 2; quad ++) {
6859                                         switch (ainfo->pair_storage [quad]) {
6860                                         case ArgInIReg:
6861                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6862                                                 break;
6863                                         case ArgInFloatSSEReg:
6864                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6865                                                 break;
6866                                         case ArgInDoubleSSEReg:
6867                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6868                                                 break;
6869                                         case ArgNone:
6870                                                 break;
6871                                         default:
6872                                                 g_assert_not_reached ();
6873                                         }
6874                                 }
6875                                 break;
6876                         case ArgValuetypeAddrInIReg:
6877                                 if (ainfo->pair_storage [0] == ArgInIReg)
6878                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6879                                 break;
6880                         case ArgGSharedVtInReg:
6881                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6882                                 break;
6883                         default:
6884                                 break;
6885                         }
6886                 } else {
6887                         /* Argument allocated to (non-volatile) register */
6888                         switch (ainfo->storage) {
6889                         case ArgInIReg:
6890                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6891                                 break;
6892                         case ArgOnStack:
6893                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6894                                 break;
6895                         default:
6896                                 g_assert_not_reached ();
6897                         }
6898
6899                         if (ins == cfg->args [0]) {
6900                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6901                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6902                         }
6903                 }
6904         }
6905
6906         if (cfg->method->save_lmf)
6907                 args_clobbered = TRUE;
6908
6909         if (trace) {
6910                 args_clobbered = TRUE;
6911                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6912         }
6913
6914         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6915                 args_clobbered = TRUE;
6916
6917         /*
6918          * Optimize the common case of the first bblock making a call with the same
6919          * arguments as the method. This works because the arguments are still in their
6920          * original argument registers.
6921          * FIXME: Generalize this
6922          */
6923         if (!args_clobbered) {
6924                 MonoBasicBlock *first_bb = cfg->bb_entry;
6925                 MonoInst *next;
6926                 int filter = FILTER_IL_SEQ_POINT;
6927
6928                 next = mono_bb_first_inst (first_bb, filter);
6929                 if (!next && first_bb->next_bb) {
6930                         first_bb = first_bb->next_bb;
6931                         next = mono_bb_first_inst (first_bb, filter);
6932                 }
6933
6934                 if (first_bb->in_count > 1)
6935                         next = NULL;
6936
6937                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6938                         ArgInfo *ainfo = cinfo->args + i;
6939                         gboolean match = FALSE;
6940
6941                         ins = cfg->args [i];
6942                         if (ins->opcode != OP_REGVAR) {
6943                                 switch (ainfo->storage) {
6944                                 case ArgInIReg: {
6945                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6946                                                 if (next->dreg == ainfo->reg) {
6947                                                         NULLIFY_INS (next);
6948                                                         match = TRUE;
6949                                                 } else {
6950                                                         next->opcode = OP_MOVE;
6951                                                         next->sreg1 = ainfo->reg;
6952                                                         /* Only continue if the instruction doesn't change argument regs */
6953                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6954                                                                 match = TRUE;
6955                                                 }
6956                                         }
6957                                         break;
6958                                 }
6959                                 default:
6960                                         break;
6961                                 }
6962                         } else {
6963                                 /* Argument allocated to (non-volatile) register */
6964                                 switch (ainfo->storage) {
6965                                 case ArgInIReg:
6966                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6967                                                 NULLIFY_INS (next);
6968                                                 match = TRUE;
6969                                         }
6970                                         break;
6971                                 default:
6972                                         break;
6973                                 }
6974                         }
6975
6976                         if (match) {
6977                                 next = mono_inst_next (next, filter);
6978                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6979                                 if (!next)
6980                                         break;
6981                         }
6982                 }
6983         }
6984
6985         if (cfg->gen_sdb_seq_points) {
6986                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
6987
6988                 /* Initialize seq_point_info_var */
6989                 if (cfg->compile_aot) {
6990                         /* Initialize the variable from a GOT slot */
6991                         /* Same as OP_AOTCONST */
6992                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6993                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
6994                         g_assert (info_var->opcode == OP_REGOFFSET);
6995                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
6996                 }
6997
6998                 if (cfg->compile_aot) {
6999                         /* Initialize ss_tramp_var */
7000                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7001                         g_assert (ins->opcode == OP_REGOFFSET);
7002
7003                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7004                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7005                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7006                 } else {
7007                         /* Initialize ss_tramp_var */
7008                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7009                         g_assert (ins->opcode == OP_REGOFFSET);
7010
7011                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7012                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7013
7014                         /* Initialize bp_tramp_var */
7015                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7016                         g_assert (ins->opcode == OP_REGOFFSET);
7017
7018                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7019                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7020                 }
7021         }
7022
7023         cfg->code_len = code - cfg->native_code;
7024
7025         g_assert (cfg->code_len < cfg->code_size);
7026
7027         return code;
7028 }
7029
7030 void
7031 mono_arch_emit_epilog (MonoCompile *cfg)
7032 {
7033         MonoMethod *method = cfg->method;
7034         int quad, i;
7035         guint8 *code;
7036         int max_epilog_size;
7037         CallInfo *cinfo;
7038         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7039         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7040
7041         max_epilog_size = get_max_epilog_size (cfg);
7042
7043         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7044                 cfg->code_size *= 2;
7045                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7046                 cfg->stat_code_reallocs++;
7047         }
7048         code = cfg->native_code + cfg->code_len;
7049
7050         cfg->has_unwind_info_for_epilog = TRUE;
7051
7052         /* Mark the start of the epilog */
7053         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7054
7055         /* Save the uwind state which is needed by the out-of-line code */
7056         mono_emit_unwind_op_remember_state (cfg, code);
7057
7058         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7059                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7060
7061         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7062
7063         if (method->save_lmf) {
7064                 /* check if we need to restore protection of the stack after a stack overflow */
7065                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7066                         guint8 *patch;
7067                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7068                         /* we load the value in a separate instruction: this mechanism may be
7069                          * used later as a safer way to do thread interruption
7070                          */
7071                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7072                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7073                         patch = code;
7074                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7075                         /* note that the call trampoline will preserve eax/edx */
7076                         x86_call_reg (code, X86_ECX);
7077                         x86_patch (patch, code);
7078                 } else {
7079                         /* FIXME: maybe save the jit tls in the prolog */
7080                 }
7081                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7082                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7083                 }
7084         }
7085
7086         /* Restore callee saved regs */
7087         for (i = 0; i < AMD64_NREG; ++i) {
7088                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7089                         /* Restore only used_int_regs, not arch.saved_iregs */
7090                         if (cfg->used_int_regs & (1 << i)) {
7091                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7092                                 mono_emit_unwind_op_same_value (cfg, code, i);
7093                                 async_exc_point (code);
7094                         }
7095                         save_area_offset += 8;
7096                 }
7097         }
7098
7099         /* Load returned vtypes into registers if needed */
7100         cinfo = (CallInfo *)cfg->arch.cinfo;
7101         if (cinfo->ret.storage == ArgValuetypeInReg) {
7102                 ArgInfo *ainfo = &cinfo->ret;
7103                 MonoInst *inst = cfg->ret;
7104
7105                 for (quad = 0; quad < 2; quad ++) {
7106                         switch (ainfo->pair_storage [quad]) {
7107                         case ArgInIReg:
7108                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7109                                 break;
7110                         case ArgInFloatSSEReg:
7111                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7112                                 break;
7113                         case ArgInDoubleSSEReg:
7114                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7115                                 break;
7116                         case ArgNone:
7117                                 break;
7118                         default:
7119                                 g_assert_not_reached ();
7120                         }
7121                 }
7122         }
7123
7124         if (cfg->arch.omit_fp) {
7125                 if (cfg->arch.stack_alloc_size) {
7126                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7127                 }
7128         } else {
7129                 amd64_leave (code);
7130                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7131         }
7132         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7133         async_exc_point (code);
7134         amd64_ret (code);
7135
7136         /* Restore the unwind state to be the same as before the epilog */
7137         mono_emit_unwind_op_restore_state (cfg, code);
7138
7139         cfg->code_len = code - cfg->native_code;
7140
7141         g_assert (cfg->code_len < cfg->code_size);
7142 }
7143
7144 void
7145 mono_arch_emit_exceptions (MonoCompile *cfg)
7146 {
7147         MonoJumpInfo *patch_info;
7148         int nthrows, i;
7149         guint8 *code;
7150         MonoClass *exc_classes [16];
7151         guint8 *exc_throw_start [16], *exc_throw_end [16];
7152         guint32 code_size = 0;
7153
7154         /* Compute needed space */
7155         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7156                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7157                         code_size += 40;
7158                 if (patch_info->type == MONO_PATCH_INFO_R8)
7159                         code_size += 8 + 15; /* sizeof (double) + alignment */
7160                 if (patch_info->type == MONO_PATCH_INFO_R4)
7161                         code_size += 4 + 15; /* sizeof (float) + alignment */
7162                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7163                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7164         }
7165
7166         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7167                 cfg->code_size *= 2;
7168                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7169                 cfg->stat_code_reallocs++;
7170         }
7171
7172         code = cfg->native_code + cfg->code_len;
7173
7174         /* add code to raise exceptions */
7175         nthrows = 0;
7176         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7177                 switch (patch_info->type) {
7178                 case MONO_PATCH_INFO_EXC: {
7179                         MonoClass *exc_class;
7180                         guint8 *buf, *buf2;
7181                         guint32 throw_ip;
7182
7183                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7184
7185                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7186                         throw_ip = patch_info->ip.i;
7187
7188                         //x86_breakpoint (code);
7189                         /* Find a throw sequence for the same exception class */
7190                         for (i = 0; i < nthrows; ++i)
7191                                 if (exc_classes [i] == exc_class)
7192                                         break;
7193                         if (i < nthrows) {
7194                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7195                                 x86_jump_code (code, exc_throw_start [i]);
7196                                 patch_info->type = MONO_PATCH_INFO_NONE;
7197                         }
7198                         else {
7199                                 buf = code;
7200                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7201                                 buf2 = code;
7202
7203                                 if (nthrows < 16) {
7204                                         exc_classes [nthrows] = exc_class;
7205                                         exc_throw_start [nthrows] = code;
7206                                 }
7207                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7208
7209                                 patch_info->type = MONO_PATCH_INFO_NONE;
7210
7211                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7212
7213                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7214                                 while (buf < buf2)
7215                                         x86_nop (buf);
7216
7217                                 if (nthrows < 16) {
7218                                         exc_throw_end [nthrows] = code;
7219                                         nthrows ++;
7220                                 }
7221                         }
7222                         break;
7223                 }
7224                 default:
7225                         /* do nothing */
7226                         break;
7227                 }
7228                 g_assert(code < cfg->native_code + cfg->code_size);
7229         }
7230
7231         /* Handle relocations with RIP relative addressing */
7232         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7233                 gboolean remove = FALSE;
7234                 guint8 *orig_code = code;
7235
7236                 switch (patch_info->type) {
7237                 case MONO_PATCH_INFO_R8:
7238                 case MONO_PATCH_INFO_R4: {
7239                         guint8 *pos, *patch_pos;
7240                         guint32 target_pos;
7241
7242                         /* The SSE opcodes require a 16 byte alignment */
7243                         code = (guint8*)ALIGN_TO (code, 16);
7244
7245                         pos = cfg->native_code + patch_info->ip.i;
7246                         if (IS_REX (pos [1])) {
7247                                 patch_pos = pos + 5;
7248                                 target_pos = code - pos - 9;
7249                         }
7250                         else {
7251                                 patch_pos = pos + 4;
7252                                 target_pos = code - pos - 8;
7253                         }
7254
7255                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7256                                 *(double*)code = *(double*)patch_info->data.target;
7257                                 code += sizeof (double);
7258                         } else {
7259                                 *(float*)code = *(float*)patch_info->data.target;
7260                                 code += sizeof (float);
7261                         }
7262
7263                         *(guint32*)(patch_pos) = target_pos;
7264
7265                         remove = TRUE;
7266                         break;
7267                 }
7268                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7269                         guint8 *pos;
7270
7271                         if (cfg->compile_aot)
7272                                 continue;
7273
7274                         /*loading is faster against aligned addresses.*/
7275                         code = (guint8*)ALIGN_TO (code, 8);
7276                         memset (orig_code, 0, code - orig_code);
7277
7278                         pos = cfg->native_code + patch_info->ip.i;
7279
7280                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7281                         if (IS_REX (pos [1]))
7282                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7283                         else
7284                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7285
7286                         *(gpointer*)code = (gpointer)patch_info->data.target;
7287                         code += sizeof (gpointer);
7288
7289                         remove = TRUE;
7290                         break;
7291                 }
7292                 default:
7293                         break;
7294                 }
7295
7296                 if (remove) {
7297                         if (patch_info == cfg->patch_info)
7298                                 cfg->patch_info = patch_info->next;
7299                         else {
7300                                 MonoJumpInfo *tmp;
7301
7302                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7303                                         ;
7304                                 tmp->next = patch_info->next;
7305                         }
7306                 }
7307                 g_assert (code < cfg->native_code + cfg->code_size);
7308         }
7309
7310         cfg->code_len = code - cfg->native_code;
7311
7312         g_assert (cfg->code_len < cfg->code_size);
7313
7314 }
7315
7316 #endif /* DISABLE_JIT */
7317
7318 void*
7319 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7320 {
7321         guchar *code = (guchar *)p;
7322         MonoMethodSignature *sig;
7323         MonoInst *inst;
7324         int i, n, stack_area = 0;
7325
7326         /* Keep this in sync with mono_arch_get_argument_info */
7327
7328         if (enable_arguments) {
7329                 /* Allocate a new area on the stack and save arguments there */
7330                 sig = mono_method_signature (cfg->method);
7331
7332                 n = sig->param_count + sig->hasthis;
7333
7334                 stack_area = ALIGN_TO (n * 8, 16);
7335
7336                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7337
7338                 for (i = 0; i < n; ++i) {
7339                         inst = cfg->args [i];
7340
7341                         if (inst->opcode == OP_REGVAR)
7342                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7343                         else {
7344                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7345                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7346                         }
7347                 }
7348         }
7349
7350         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7351         amd64_set_reg_template (code, AMD64_ARG_REG1);
7352         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7353         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7354
7355         if (enable_arguments)
7356                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7357
7358         return code;
7359 }
7360
7361 enum {
7362         SAVE_NONE,
7363         SAVE_STRUCT,
7364         SAVE_EAX,
7365         SAVE_EAX_EDX,
7366         SAVE_XMM
7367 };
7368
7369 void*
7370 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7371 {
7372         guchar *code = (guchar *)p;
7373         int save_mode = SAVE_NONE;
7374         MonoMethod *method = cfg->method;
7375         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7376         int i;
7377
7378         switch (ret_type->type) {
7379         case MONO_TYPE_VOID:
7380                 /* special case string .ctor icall */
7381                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7382                         save_mode = SAVE_EAX;
7383                 else
7384                         save_mode = SAVE_NONE;
7385                 break;
7386         case MONO_TYPE_I8:
7387         case MONO_TYPE_U8:
7388                 save_mode = SAVE_EAX;
7389                 break;
7390         case MONO_TYPE_R4:
7391         case MONO_TYPE_R8:
7392                 save_mode = SAVE_XMM;
7393                 break;
7394         case MONO_TYPE_GENERICINST:
7395                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7396                         save_mode = SAVE_EAX;
7397                         break;
7398                 }
7399                 /* Fall through */
7400         case MONO_TYPE_VALUETYPE:
7401                 save_mode = SAVE_STRUCT;
7402                 break;
7403         default:
7404                 save_mode = SAVE_EAX;
7405                 break;
7406         }
7407
7408         /* Save the result and copy it into the proper argument register */
7409         switch (save_mode) {
7410         case SAVE_EAX:
7411                 amd64_push_reg (code, AMD64_RAX);
7412                 /* Align stack */
7413                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7414                 if (enable_arguments)
7415                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7416                 break;
7417         case SAVE_STRUCT:
7418                 /* FIXME: */
7419                 if (enable_arguments)
7420                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7421                 break;
7422         case SAVE_XMM:
7423                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7424                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7425                 /* Align stack */
7426                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7427                 /*
7428                  * The result is already in the proper argument register so no copying
7429                  * needed.
7430                  */
7431                 break;
7432         case SAVE_NONE:
7433                 break;
7434         default:
7435                 g_assert_not_reached ();
7436         }
7437
7438         /* Set %al since this is a varargs call */
7439         if (save_mode == SAVE_XMM)
7440                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7441         else
7442                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7443
7444         if (preserve_argument_registers) {
7445                 for (i = 0; i < PARAM_REGS; ++i)
7446                         amd64_push_reg (code, param_regs [i]);
7447         }
7448
7449         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7450         amd64_set_reg_template (code, AMD64_ARG_REG1);
7451         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7452
7453         if (preserve_argument_registers) {
7454                 for (i = PARAM_REGS - 1; i >= 0; --i)
7455                         amd64_pop_reg (code, param_regs [i]);
7456         }
7457
7458         /* Restore result */
7459         switch (save_mode) {
7460         case SAVE_EAX:
7461                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7462                 amd64_pop_reg (code, AMD64_RAX);
7463                 break;
7464         case SAVE_STRUCT:
7465                 /* FIXME: */
7466                 break;
7467         case SAVE_XMM:
7468                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7469                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7470                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7471                 break;
7472         case SAVE_NONE:
7473                 break;
7474         default:
7475                 g_assert_not_reached ();
7476         }
7477
7478         return code;
7479 }
7480
7481 void
7482 mono_arch_flush_icache (guint8 *code, gint size)
7483 {
7484         /* Not needed */
7485 }
7486
7487 void
7488 mono_arch_flush_register_windows (void)
7489 {
7490 }
7491
7492 gboolean
7493 mono_arch_is_inst_imm (gint64 imm)
7494 {
7495         return amd64_use_imm32 (imm);
7496 }
7497
7498 /*
7499  * Determine whenever the trap whose info is in SIGINFO is caused by
7500  * integer overflow.
7501  */
7502 gboolean
7503 mono_arch_is_int_overflow (void *sigctx, void *info)
7504 {
7505         MonoContext ctx;
7506         guint8* rip;
7507         int reg;
7508         gint64 value;
7509
7510         mono_sigctx_to_monoctx (sigctx, &ctx);
7511
7512         rip = (guint8*)ctx.gregs [AMD64_RIP];
7513
7514         if (IS_REX (rip [0])) {
7515                 reg = amd64_rex_b (rip [0]);
7516                 rip ++;
7517         }
7518         else
7519                 reg = 0;
7520
7521         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7522                 /* idiv REG */
7523                 reg += x86_modrm_rm (rip [1]);
7524
7525                 value = ctx.gregs [reg];
7526
7527                 if (value == -1)
7528                         return TRUE;
7529         }
7530
7531         return FALSE;
7532 }
7533
7534 guint32
7535 mono_arch_get_patch_offset (guint8 *code)
7536 {
7537         return 3;
7538 }
7539
7540 /**
7541  * mono_breakpoint_clean_code:
7542  *
7543  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7544  * breakpoints in the original code, they are removed in the copy.
7545  *
7546  * Returns TRUE if no sw breakpoint was present.
7547  */
7548 gboolean
7549 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7550 {
7551         /*
7552          * If method_start is non-NULL we need to perform bound checks, since we access memory
7553          * at code - offset we could go before the start of the method and end up in a different
7554          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7555          * instead.
7556          */
7557         if (!method_start || code - offset >= method_start) {
7558                 memcpy (buf, code - offset, size);
7559         } else {
7560                 int diff = code - method_start;
7561                 memset (buf, 0, size);
7562                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7563         }
7564         return TRUE;
7565 }
7566
7567 int
7568 mono_arch_get_this_arg_reg (guint8 *code)
7569 {
7570         return AMD64_ARG_REG1;
7571 }
7572
7573 gpointer
7574 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7575 {
7576         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7577 }
7578
7579 #define MAX_ARCH_DELEGATE_PARAMS 10
7580
7581 static gpointer
7582 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7583 {
7584         guint8 *code, *start;
7585         GSList *unwind_ops = NULL;
7586         int i;
7587
7588         unwind_ops = mono_arch_get_cie_program ();
7589
7590         if (has_target) {
7591                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7592
7593                 /* Replace the this argument with the target */
7594                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7595                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7596                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7597
7598                 g_assert ((code - start) < 64);
7599         } else {
7600                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7601
7602                 if (param_count == 0) {
7603                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7604                 } else {
7605                         /* We have to shift the arguments left */
7606                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7607                         for (i = 0; i < param_count; ++i) {
7608 #ifdef TARGET_WIN32
7609                                 if (i < 3)
7610                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7611                                 else
7612                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7613 #else
7614                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7615 #endif
7616                         }
7617
7618                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7619                 }
7620                 g_assert ((code - start) < 64);
7621         }
7622
7623         mono_arch_flush_icache (start, code - start);
7624
7625         if (has_target) {
7626                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7627         } else {
7628                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7629                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7630                 g_free (name);
7631         }
7632
7633         if (mono_jit_map_is_enabled ()) {
7634                 char *buff;
7635                 if (has_target)
7636                         buff = (char*)"delegate_invoke_has_target";
7637                 else
7638                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7639                 mono_emit_jit_tramp (start, code - start, buff);
7640                 if (!has_target)
7641                         g_free (buff);
7642         }
7643         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7644
7645         return start;
7646 }
7647
7648 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7649
7650 static gpointer
7651 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7652 {
7653         guint8 *code, *start;
7654         int size = 20;
7655         char *tramp_name;
7656         GSList *unwind_ops;
7657
7658         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7659                 return NULL;
7660
7661         start = code = (guint8 *)mono_global_codeman_reserve (size);
7662
7663         unwind_ops = mono_arch_get_cie_program ();
7664
7665         /* Replace the this argument with the target */
7666         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7667         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7668
7669         if (load_imt_reg) {
7670                 /* Load the IMT reg */
7671                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7672         }
7673
7674         /* Load the vtable */
7675         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7676         amd64_jump_membase (code, AMD64_RAX, offset);
7677         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7678
7679         if (load_imt_reg)
7680                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7681         else
7682                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7683         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7684         g_free (tramp_name);
7685
7686         return start;
7687 }
7688
7689 /*
7690  * mono_arch_get_delegate_invoke_impls:
7691  *
7692  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7693  * trampolines.
7694  */
7695 GSList*
7696 mono_arch_get_delegate_invoke_impls (void)
7697 {
7698         GSList *res = NULL;
7699         MonoTrampInfo *info;
7700         int i;
7701
7702         get_delegate_invoke_impl (&info, TRUE, 0);
7703         res = g_slist_prepend (res, info);
7704
7705         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7706                 get_delegate_invoke_impl (&info, FALSE, i);
7707                 res = g_slist_prepend (res, info);
7708         }
7709
7710         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7711                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7712                 res = g_slist_prepend (res, info);
7713
7714                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7715                 res = g_slist_prepend (res, info);
7716         }
7717
7718         return res;
7719 }
7720
7721 gpointer
7722 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7723 {
7724         guint8 *code, *start;
7725         int i;
7726
7727         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7728                 return NULL;
7729
7730         /* FIXME: Support more cases */
7731         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7732                 return NULL;
7733
7734         if (has_target) {
7735                 static guint8* cached = NULL;
7736
7737                 if (cached)
7738                         return cached;
7739
7740                 if (mono_aot_only) {
7741                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7742                 } else {
7743                         MonoTrampInfo *info;
7744                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7745                         mono_tramp_info_register (info, NULL);
7746                 }
7747
7748                 mono_memory_barrier ();
7749
7750                 cached = start;
7751         } else {
7752                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7753                 for (i = 0; i < sig->param_count; ++i)
7754                         if (!mono_is_regsize_var (sig->params [i]))
7755                                 return NULL;
7756                 if (sig->param_count > 4)
7757                         return NULL;
7758
7759                 code = cache [sig->param_count];
7760                 if (code)
7761                         return code;
7762
7763                 if (mono_aot_only) {
7764                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7765                         start = (guint8 *)mono_aot_get_trampoline (name);
7766                         g_free (name);
7767                 } else {
7768                         MonoTrampInfo *info;
7769                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7770                         mono_tramp_info_register (info, NULL);
7771                 }
7772
7773                 mono_memory_barrier ();
7774
7775                 cache [sig->param_count] = start;
7776         }
7777
7778         return start;
7779 }
7780
7781 gpointer
7782 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7783 {
7784         MonoTrampInfo *info;
7785         gpointer code;
7786
7787         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7788         if (code)
7789                 mono_tramp_info_register (info, NULL);
7790         return code;
7791 }
7792
7793 void
7794 mono_arch_finish_init (void)
7795 {
7796 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7797         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7798 #endif
7799 }
7800
7801 void
7802 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7803 {
7804 }
7805
7806 #define CMP_SIZE (6 + 1)
7807 #define CMP_REG_REG_SIZE (4 + 1)
7808 #define BR_SMALL_SIZE 2
7809 #define BR_LARGE_SIZE 6
7810 #define MOV_REG_IMM_SIZE 10
7811 #define MOV_REG_IMM_32BIT_SIZE 6
7812 #define JUMP_REG_SIZE (2 + 1)
7813
7814 static int
7815 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7816 {
7817         int i, distance = 0;
7818         for (i = start; i < target; ++i)
7819                 distance += imt_entries [i]->chunk_size;
7820         return distance;
7821 }
7822
7823 /*
7824  * LOCKING: called with the domain lock held
7825  */
7826 gpointer
7827 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7828         gpointer fail_tramp)
7829 {
7830         int i;
7831         int size = 0;
7832         guint8 *code, *start;
7833         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7834         GSList *unwind_ops;
7835
7836         for (i = 0; i < count; ++i) {
7837                 MonoIMTCheckItem *item = imt_entries [i];
7838                 if (item->is_equals) {
7839                         if (item->check_target_idx) {
7840                                 if (!item->compare_done) {
7841                                         if (amd64_use_imm32 ((gint64)item->key))
7842                                                 item->chunk_size += CMP_SIZE;
7843                                         else
7844                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7845                                 }
7846                                 if (item->has_target_code) {
7847                                         item->chunk_size += MOV_REG_IMM_SIZE;
7848                                 } else {
7849                                         if (vtable_is_32bit)
7850                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7851                                         else
7852                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7853                                 }
7854                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7855                         } else {
7856                                 if (fail_tramp) {
7857                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7858                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7859                                 } else {
7860                                         if (vtable_is_32bit)
7861                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7862                                         else
7863                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7864                                         item->chunk_size += JUMP_REG_SIZE;
7865                                         /* with assert below:
7866                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7867                                          */
7868                                 }
7869                         }
7870                 } else {
7871                         if (amd64_use_imm32 ((gint64)item->key))
7872                                 item->chunk_size += CMP_SIZE;
7873                         else
7874                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7875                         item->chunk_size += BR_LARGE_SIZE;
7876                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7877                 }
7878                 size += item->chunk_size;
7879         }
7880         if (fail_tramp)
7881                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
7882         else
7883                 code = (guint8 *)mono_domain_code_reserve (domain, size);
7884         start = code;
7885
7886         unwind_ops = mono_arch_get_cie_program ();
7887
7888         for (i = 0; i < count; ++i) {
7889                 MonoIMTCheckItem *item = imt_entries [i];
7890                 item->code_target = code;
7891                 if (item->is_equals) {
7892                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7893
7894                         if (item->check_target_idx || fail_case) {
7895                                 if (!item->compare_done || fail_case) {
7896                                         if (amd64_use_imm32 ((gint64)item->key))
7897                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7898                                         else {
7899                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7900                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7901                                         }
7902                                 }
7903                                 item->jmp_code = code;
7904                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7905                                 if (item->has_target_code) {
7906                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7907                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7908                                 } else {
7909                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7910                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7911                                 }
7912
7913                                 if (fail_case) {
7914                                         amd64_patch (item->jmp_code, code);
7915                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7916                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7917                                         item->jmp_code = NULL;
7918                                 }
7919                         } else {
7920                                 /* enable the commented code to assert on wrong method */
7921 #if 0
7922                                 if (amd64_is_imm32 (item->key))
7923                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7924                                 else {
7925                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7926                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7927                                 }
7928                                 item->jmp_code = code;
7929                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7930                                 /* See the comment below about R10 */
7931                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7932                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7933                                 amd64_patch (item->jmp_code, code);
7934                                 amd64_breakpoint (code);
7935                                 item->jmp_code = NULL;
7936 #else
7937                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7938                                    needs to be preserved.  R10 needs
7939                                    to be preserved for calls which
7940                                    require a runtime generic context,
7941                                    but interface calls don't. */
7942                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7943                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7944 #endif
7945                         }
7946                 } else {
7947                         if (amd64_use_imm32 ((gint64)item->key))
7948                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7949                         else {
7950                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7951                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7952                         }
7953                         item->jmp_code = code;
7954                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7955                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7956                         else
7957                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7958                 }
7959                 g_assert (code - item->code_target <= item->chunk_size);
7960         }
7961         /* patch the branches to get to the target items */
7962         for (i = 0; i < count; ++i) {
7963                 MonoIMTCheckItem *item = imt_entries [i];
7964                 if (item->jmp_code) {
7965                         if (item->check_target_idx) {
7966                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7967                         }
7968                 }
7969         }
7970
7971         if (!fail_tramp)
7972                 mono_stats.imt_thunks_size += code - start;
7973         g_assert (code - start <= size);
7974
7975         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7976
7977         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
7978
7979         return start;
7980 }
7981
7982 MonoMethod*
7983 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7984 {
7985         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7986 }
7987
7988 MonoVTable*
7989 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7990 {
7991         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7992 }
7993
7994 GSList*
7995 mono_arch_get_cie_program (void)
7996 {
7997         GSList *l = NULL;
7998
7999         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8000         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8001
8002         return l;
8003 }
8004
8005 #ifndef DISABLE_JIT
8006
8007 MonoInst*
8008 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8009 {
8010         MonoInst *ins = NULL;
8011         int opcode = 0;
8012
8013         if (cmethod->klass == mono_defaults.math_class) {
8014                 if (strcmp (cmethod->name, "Sin") == 0) {
8015                         opcode = OP_SIN;
8016                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8017                         opcode = OP_COS;
8018                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8019                         opcode = OP_SQRT;
8020                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8021                         opcode = OP_ABS;
8022                 }
8023
8024                 if (opcode && fsig->param_count == 1) {
8025                         MONO_INST_NEW (cfg, ins, opcode);
8026                         ins->type = STACK_R8;
8027                         ins->dreg = mono_alloc_freg (cfg);
8028                         ins->sreg1 = args [0]->dreg;
8029                         MONO_ADD_INS (cfg->cbb, ins);
8030                 }
8031
8032                 opcode = 0;
8033                 if (cfg->opt & MONO_OPT_CMOV) {
8034                         if (strcmp (cmethod->name, "Min") == 0) {
8035                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8036                                         opcode = OP_IMIN;
8037                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8038                                         opcode = OP_IMIN_UN;
8039                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8040                                         opcode = OP_LMIN;
8041                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8042                                         opcode = OP_LMIN_UN;
8043                         } else if (strcmp (cmethod->name, "Max") == 0) {
8044                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8045                                         opcode = OP_IMAX;
8046                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8047                                         opcode = OP_IMAX_UN;
8048                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8049                                         opcode = OP_LMAX;
8050                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8051                                         opcode = OP_LMAX_UN;
8052                         }
8053                 }
8054
8055                 if (opcode && fsig->param_count == 2) {
8056                         MONO_INST_NEW (cfg, ins, opcode);
8057                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8058                         ins->dreg = mono_alloc_ireg (cfg);
8059                         ins->sreg1 = args [0]->dreg;
8060                         ins->sreg2 = args [1]->dreg;
8061                         MONO_ADD_INS (cfg->cbb, ins);
8062                 }
8063
8064 #if 0
8065                 /* OP_FREM is not IEEE compatible */
8066                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8067                         MONO_INST_NEW (cfg, ins, OP_FREM);
8068                         ins->inst_i0 = args [0];
8069                         ins->inst_i1 = args [1];
8070                 }
8071 #endif
8072         }
8073
8074         return ins;
8075 }
8076 #endif
8077
8078 gboolean
8079 mono_arch_print_tree (MonoInst *tree, int arity)
8080 {
8081         return 0;
8082 }
8083
8084 mgreg_t
8085 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8086 {
8087         return ctx->gregs [reg];
8088 }
8089
8090 void
8091 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8092 {
8093         ctx->gregs [reg] = val;
8094 }
8095
8096 gpointer
8097 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8098 {
8099         gpointer *sp, old_value;
8100         char *bp;
8101
8102         /*Load the spvar*/
8103         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8104         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8105
8106         old_value = *sp;
8107         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8108                 return old_value;
8109
8110         *sp = new_value;
8111
8112         return old_value;
8113 }
8114
8115 /*
8116  * mono_arch_emit_load_aotconst:
8117  *
8118  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8119  * TARGET from the mscorlib GOT in full-aot code.
8120  * On AMD64, the result is placed into R11.
8121  */
8122 guint8*
8123 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8124 {
8125         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8126         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8127
8128         return code;
8129 }
8130
8131 /*
8132  * mono_arch_get_trampolines:
8133  *
8134  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8135  * for AOT.
8136  */
8137 GSList *
8138 mono_arch_get_trampolines (gboolean aot)
8139 {
8140         return mono_amd64_get_exception_trampolines (aot);
8141 }
8142
8143 /* Soft Debug support */
8144 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8145
8146 /*
8147  * mono_arch_set_breakpoint:
8148  *
8149  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8150  * The location should contain code emitted by OP_SEQ_POINT.
8151  */
8152 void
8153 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8154 {
8155         guint8 *code = ip;
8156
8157         if (ji->from_aot) {
8158                 guint32 native_offset = ip - (guint8*)ji->code_start;
8159                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8160
8161                 g_assert (info->bp_addrs [native_offset] == 0);
8162                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8163         } else {
8164                 /* ip points to a mov r11, 0 */
8165                 g_assert (code [0] == 0x41);
8166                 g_assert (code [1] == 0xbb);
8167                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8168         }
8169 }
8170
8171 /*
8172  * mono_arch_clear_breakpoint:
8173  *
8174  *   Clear the breakpoint at IP.
8175  */
8176 void
8177 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8178 {
8179         guint8 *code = ip;
8180
8181         if (ji->from_aot) {
8182                 guint32 native_offset = ip - (guint8*)ji->code_start;
8183                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8184
8185                 info->bp_addrs [native_offset] = NULL;
8186         } else {
8187                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8188         }
8189 }
8190
8191 gboolean
8192 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8193 {
8194         /* We use soft breakpoints on amd64 */
8195         return FALSE;
8196 }
8197
8198 /*
8199  * mono_arch_skip_breakpoint:
8200  *
8201  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8202  * we resume, the instruction is not executed again.
8203  */
8204 void
8205 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8206 {
8207         g_assert_not_reached ();
8208 }
8209
8210 /*
8211  * mono_arch_start_single_stepping:
8212  *
8213  *   Start single stepping.
8214  */
8215 void
8216 mono_arch_start_single_stepping (void)
8217 {
8218         ss_trampoline = mini_get_single_step_trampoline ();
8219 }
8220
8221 /*
8222  * mono_arch_stop_single_stepping:
8223  *
8224  *   Stop single stepping.
8225  */
8226 void
8227 mono_arch_stop_single_stepping (void)
8228 {
8229         ss_trampoline = NULL;
8230 }
8231
8232 /*
8233  * mono_arch_is_single_step_event:
8234  *
8235  *   Return whenever the machine state in SIGCTX corresponds to a single
8236  * step event.
8237  */
8238 gboolean
8239 mono_arch_is_single_step_event (void *info, void *sigctx)
8240 {
8241         /* We use soft breakpoints on amd64 */
8242         return FALSE;
8243 }
8244
8245 /*
8246  * mono_arch_skip_single_step:
8247  *
8248  *   Modify CTX so the ip is placed after the single step trigger instruction,
8249  * we resume, the instruction is not executed again.
8250  */
8251 void
8252 mono_arch_skip_single_step (MonoContext *ctx)
8253 {
8254         g_assert_not_reached ();
8255 }
8256
8257 /*
8258  * mono_arch_create_seq_point_info:
8259  *
8260  *   Return a pointer to a data structure which is used by the sequence
8261  * point implementation in AOTed code.
8262  */
8263 gpointer
8264 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8265 {
8266         SeqPointInfo *info;
8267         MonoJitInfo *ji;
8268
8269         // FIXME: Add a free function
8270
8271         mono_domain_lock (domain);
8272         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8273                                                                 code);
8274         mono_domain_unlock (domain);
8275
8276         if (!info) {
8277                 ji = mono_jit_info_table_find (domain, (char*)code);
8278                 g_assert (ji);
8279
8280                 // FIXME: Optimize the size
8281                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8282
8283                 info->ss_tramp_addr = &ss_trampoline;
8284
8285                 mono_domain_lock (domain);
8286                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8287                                                          code, info);
8288                 mono_domain_unlock (domain);
8289         }
8290
8291         return info;
8292 }
8293
8294 void
8295 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8296 {
8297         ext->lmf.previous_lmf = prev_lmf;
8298         /* Mark that this is a MonoLMFExt */
8299         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8300         ext->lmf.rsp = (gssize)ext;
8301 }
8302
8303 #endif
8304
8305 gboolean
8306 mono_arch_opcode_supported (int opcode)
8307 {
8308         switch (opcode) {
8309         case OP_ATOMIC_ADD_I4:
8310         case OP_ATOMIC_ADD_I8:
8311         case OP_ATOMIC_EXCHANGE_I4:
8312         case OP_ATOMIC_EXCHANGE_I8:
8313         case OP_ATOMIC_CAS_I4:
8314         case OP_ATOMIC_CAS_I8:
8315         case OP_ATOMIC_LOAD_I1:
8316         case OP_ATOMIC_LOAD_I2:
8317         case OP_ATOMIC_LOAD_I4:
8318         case OP_ATOMIC_LOAD_I8:
8319         case OP_ATOMIC_LOAD_U1:
8320         case OP_ATOMIC_LOAD_U2:
8321         case OP_ATOMIC_LOAD_U4:
8322         case OP_ATOMIC_LOAD_U8:
8323         case OP_ATOMIC_LOAD_R4:
8324         case OP_ATOMIC_LOAD_R8:
8325         case OP_ATOMIC_STORE_I1:
8326         case OP_ATOMIC_STORE_I2:
8327         case OP_ATOMIC_STORE_I4:
8328         case OP_ATOMIC_STORE_I8:
8329         case OP_ATOMIC_STORE_U1:
8330         case OP_ATOMIC_STORE_U2:
8331         case OP_ATOMIC_STORE_U4:
8332         case OP_ATOMIC_STORE_U8:
8333         case OP_ATOMIC_STORE_R4:
8334         case OP_ATOMIC_STORE_R8:
8335                 return TRUE;
8336         default:
8337                 return FALSE;
8338         }
8339 }
8340
8341 CallInfo*
8342 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8343 {
8344         return get_call_info (mp, sig);
8345 }