mono/mini/mini-amd64.c

   1 /**
   2  * \file
   3  * AMD64 backend for the Mono code generator
   4  *
   5  * Based on mini-x86.c.
   6  *
   7  * Authors:
   8  *   Paolo Molaro (lupus@ximian.com)
   9  *   Dietmar Maurer (dietmar@ximian.com)
  10  *   Patrik Torstensson
  11  *   Zoltan Varga (vargaz@gmail.com)
  12  *   Johan Lorensson (lateralusx.github@gmail.com)
  13  *
  14  * (C) 2003 Ximian, Inc.
  15  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  16  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  17  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  18  */
  19 #include "mini.h"
  20 #include <string.h>
  21 #include <math.h>
  22 #include <assert.h>
  23 #ifdef HAVE_UNISTD_H
  24 #include <unistd.h>
  25 #endif
  26
  27 #include <mono/metadata/abi-details.h>
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/threads.h>
  31 #include <mono/metadata/profiler-private.h>
  32 #include <mono/metadata/mono-debug.h>
  33 #include <mono/metadata/gc-internals.h>
  34 #include <mono/utils/mono-math.h>
  35 #include <mono/utils/mono-mmap.h>
  36 #include <mono/utils/mono-memory-model.h>
  37 #include <mono/utils/mono-tls.h>
  38 #include <mono/utils/mono-hwcap.h>
  39 #include <mono/utils/mono-threads.h>
  40
  41 #include "trace.h"
  42 #include "ir-emit.h"
  43 #include "mini-amd64.h"
  44 #include "cpu-amd64.h"
  45 #include "debugger-agent.h"
  46 #include "mini-gc.h"
  47
  48 #ifdef MONO_XEN_OPT
  49 static gboolean optimize_for_xen = TRUE;
  50 #else
  51 #define optimize_for_xen 0
  52 #endif
  53
  54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  55
  56 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  57
  58 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  59
  60 #ifdef TARGET_WIN32
  61 /* Under windows, the calling convention is never stdcall */
  62 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  63 #else
  64 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  65 #endif
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  70 static mono_mutex_t mini_arch_mutex;
  71
  72 /* The single step trampoline */
  73 static gpointer ss_trampoline;
  74
  75 /* The breakpoint trampoline */
  76 static gpointer bp_trampoline;
  77
  78 /* Offset between fp and the first argument in the callee */
  79 #define ARGS_OFFSET 16
  80 #define GP_SCRATCH_REG AMD64_R11
  81
  82 /*
  83  * AMD64 register usage:
  84  * - callee saved registers are used for global register allocation
  85  * - %r11 is used for materializing 64 bit constants in opcodes
  86  * - the rest is used for local allocation
  87  */
  88
  89 /*
  90  * Floating point comparison results:
  91  *                  ZF PF CF
  92  * A > B            0  0  0
  93  * A < B            0  0  1
  94  * A = B            1  0  0
  95  * A > B            0  0  0
  96  * UNORDERED        1  1  1
  97  */
  98
  99 const char*
 100 mono_arch_regname (int reg)
 101 {
 102         switch (reg) {
 103         case AMD64_RAX: return "%rax";
 104         case AMD64_RBX: return "%rbx";
 105         case AMD64_RCX: return "%rcx";
 106         case AMD64_RDX: return "%rdx";
 107         case AMD64_RSP: return "%rsp";
 108         case AMD64_RBP: return "%rbp";
 109         case AMD64_RDI: return "%rdi";
 110         case AMD64_RSI: return "%rsi";
 111         case AMD64_R8: return "%r8";
 112         case AMD64_R9: return "%r9";
 113         case AMD64_R10: return "%r10";
 114         case AMD64_R11: return "%r11";
 115         case AMD64_R12: return "%r12";
 116         case AMD64_R13: return "%r13";
 117         case AMD64_R14: return "%r14";
 118         case AMD64_R15: return "%r15";
 119         }
 120         return "unknown";
 121 }
 122
 123 static const char * packed_xmmregs [] = {
 124         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 125         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 126 };
 127
 128 static const char * single_xmmregs [] = {
 129         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 130         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 131 };
 132
 133 const char*
 134 mono_arch_fregname (int reg)
 135 {
 136         if (reg < AMD64_XMM_NREG)
 137                 return single_xmmregs [reg];
 138         else
 139                 return "unknown";
 140 }
 141
 142 const char *
 143 mono_arch_xregname (int reg)
 144 {
 145         if (reg < AMD64_XMM_NREG)
 146                 return packed_xmmregs [reg];
 147         else
 148                 return "unknown";
 149 }
 150
 151 static gboolean
 152 debug_omit_fp (void)
 153 {
 154 #if 0
 155         return mono_debug_count ();
 156 #else
 157         return TRUE;
 158 #endif
 159 }
 160
 161 static inline gboolean
 162 amd64_is_near_call (guint8 *code)
 163 {
 164         /* Skip REX */
 165         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 166                 code += 1;
 167
 168         return code [0] == 0xe8;
 169 }
 170
 171 static inline gboolean
 172 amd64_use_imm32 (gint64 val)
 173 {
 174         if (mini_get_debug_options()->single_imm_size)
 175                 return FALSE;
 176
 177         return amd64_is_imm32 (val);
 178 }
 179
 180 static void
 181 amd64_patch (unsigned char* code, gpointer target)
 182 {
 183         guint8 rex = 0;
 184
 185         /* Skip REX */
 186         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 187                 rex = code [0];
 188                 code += 1;
 189         }
 190
 191         if ((code [0] & 0xf8) == 0xb8) {
 192                 /* amd64_set_reg_template */
 193                 *(guint64*)(code + 1) = (guint64)target;
 194         }
 195         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 196                 /* mov 0(%rip), %dreg */
 197                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 198         }
 199         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 200                 /* call *<OFFSET>(%rip) */
 201                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 202         }
 203         else if (code [0] == 0xe8) {
 204                 /* call <DISP> */
 205                 gint64 disp = (guint8*)target - (guint8*)code;
 206                 g_assert (amd64_is_imm32 (disp));
 207                 x86_patch (code, (unsigned char*)target);
 208         }
 209         else
 210                 x86_patch (code, (unsigned char*)target);
 211 }
 212
 213 void
 214 mono_amd64_patch (unsigned char* code, gpointer target)
 215 {
 216         amd64_patch (code, target);
 217 }
 218
 219 #define DEBUG(a) if (cfg->verbose_level > 1) a
 220
 221 static void inline
 222 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 223 {
 224     ainfo->offset = *stack_size;
 225
 226     if (*gr >= PARAM_REGS) {
 227                 ainfo->storage = ArgOnStack;
 228                 ainfo->arg_size = sizeof (mgreg_t);
 229                 /* Since the same stack slot size is used for all arg */
 230                 /*  types, it needs to be big enough to hold them all */
 231                 (*stack_size) += sizeof(mgreg_t);
 232     }
 233     else {
 234                 ainfo->storage = ArgInIReg;
 235                 ainfo->reg = param_regs [*gr];
 236                 (*gr) ++;
 237     }
 238 }
 239
 240 static void inline
 241 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 242 {
 243     ainfo->offset = *stack_size;
 244
 245     if (*gr >= FLOAT_PARAM_REGS) {
 246                 ainfo->storage = ArgOnStack;
 247                 ainfo->arg_size = sizeof (mgreg_t);
 248                 /* Since the same stack slot size is used for both float */
 249                 /*  types, it needs to be big enough to hold them both */
 250                 (*stack_size) += sizeof(mgreg_t);
 251     }
 252     else {
 253                 /* A double register */
 254                 if (is_double)
 255                         ainfo->storage = ArgInDoubleSSEReg;
 256                 else
 257                         ainfo->storage = ArgInFloatSSEReg;
 258                 ainfo->reg = *gr;
 259                 (*gr) += 1;
 260     }
 261 }
 262
 263 typedef enum ArgumentClass {
 264         ARG_CLASS_NO_CLASS,
 265         ARG_CLASS_MEMORY,
 266         ARG_CLASS_INTEGER,
 267         ARG_CLASS_SSE
 268 } ArgumentClass;
 269
 270 static ArgumentClass
 271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 272 {
 273         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 274         MonoType *ptype;
 275
 276         ptype = mini_get_underlying_type (type);
 277         switch (ptype->type) {
 278         case MONO_TYPE_I1:
 279         case MONO_TYPE_U1:
 280         case MONO_TYPE_I2:
 281         case MONO_TYPE_U2:
 282         case MONO_TYPE_I4:
 283         case MONO_TYPE_U4:
 284         case MONO_TYPE_I:
 285         case MONO_TYPE_U:
 286         case MONO_TYPE_OBJECT:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_I8:
 290         case MONO_TYPE_U8:
 291                 class2 = ARG_CLASS_INTEGER;
 292                 break;
 293         case MONO_TYPE_R4:
 294         case MONO_TYPE_R8:
 295 #ifdef TARGET_WIN32
 296                 class2 = ARG_CLASS_INTEGER;
 297 #else
 298                 class2 = ARG_CLASS_SSE;
 299 #endif
 300                 break;
 301
 302         case MONO_TYPE_TYPEDBYREF:
 303                 g_assert_not_reached ();
 304
 305         case MONO_TYPE_GENERICINST:
 306                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 307                         class2 = ARG_CLASS_INTEGER;
 308                         break;
 309                 }
 310                 /* fall through */
 311         case MONO_TYPE_VALUETYPE: {
 312                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 313                 int i;
 314
 315                 for (i = 0; i < info->num_fields; ++i) {
 316                         class2 = class1;
 317                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 318                 }
 319                 break;
 320         }
 321         default:
 322                 g_assert_not_reached ();
 323         }
 324
 325         /* Merge */
 326         if (class1 == class2)
 327                 ;
 328         else if (class1 == ARG_CLASS_NO_CLASS)
 329                 class1 = class2;
 330         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 331                 class1 = ARG_CLASS_MEMORY;
 332         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 333                 class1 = ARG_CLASS_INTEGER;
 334         else
 335                 class1 = ARG_CLASS_SSE;
 336
 337         return class1;
 338 }
 339
 340 typedef struct {
 341         MonoType *type;
 342         int size, offset;
 343 } StructFieldInfo;
 344
 345 /*
 346  * collect_field_info_nested:
 347  *
 348  *   Collect field info from KLASS recursively into FIELDS.
 349  */
 350 static void
 351 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 352 {
 353         MonoMarshalType *info;
 354         int i;
 355
 356         if (pinvoke) {
 357                 info = mono_marshal_load_type_info (klass);
 358                 g_assert(info);
 359                 for (i = 0; i < info->num_fields; ++i) {
 360                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 361                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 362                         } else {
 363                                 guint32 align;
 364                                 StructFieldInfo f;
 365
 366                                 f.type = info->fields [i].field->type;
 367                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 368                                                                                                                            info->fields [i].mspec,
 369                                                                                                                            &align, TRUE, unicode);
 370                                 f.offset = offset + info->fields [i].offset;
 371                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 372                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 373                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 374                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 375                                                 g_array_append_val (fields_array, f);
 376                                                 while (f.size + f.offset < info->native_size) {
 377                                                         f.offset += f.size;
 378                                                         g_array_append_val (fields_array, f);
 379                                                 }
 380                                         } else {
 381                                                 f.size = info->native_size - f.offset;
 382                                                 g_array_append_val (fields_array, f);
 383                                         }
 384                                 } else {
 385                                         g_array_append_val (fields_array, f);
 386                                 }
 387                         }
 388                 }
 389         } else {
 390                 gpointer iter;
 391                 MonoClassField *field;
 392
 393                 iter = NULL;
 394                 while ((field = mono_class_get_fields (klass, &iter))) {
 395                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 396                                 continue;
 397                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 398                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 399                         } else {
 400                                 int align;
 401                                 StructFieldInfo f;
 402
 403                                 f.type = field->type;
 404                                 f.size = mono_type_size (field->type, &align);
 405                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 406
 407                                 g_array_append_val (fields_array, f);
 408                         }
 409                 }
 410         }
 411 }
 412
 413 #ifdef TARGET_WIN32
 414
 415 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 416 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 417
 418 static gboolean
 419 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 420 {
 421         gboolean result = FALSE;
 422
 423         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 424         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 425
 426         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 427         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 428         arg_info->pair_size [0] = 0;
 429         arg_info->pair_size [1] = 0;
 430         arg_info->nregs = 0;
 431
 432         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 433                 /* Pass parameter in integer register. */
 434                 arg_info->pair_storage [0] = ArgInIReg;
 435                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 436                 (*current_int_reg) ++;
 437                 result = TRUE;
 438         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 439                 /* Pass parameter in float register. */
 440                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 441                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 442                 (*current_float_reg) ++;
 443                 result = TRUE;
 444         }
 445
 446         if (result == TRUE) {
 447                 arg_info->pair_size [0] = arg_size;
 448                 arg_info->nregs = 1;
 449         }
 450
 451         return result;
 452 }
 453
 454 static inline gboolean
 455 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 456 {
 457         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 458 }
 459
 460 static inline gboolean
 461 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 462 {
 463         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 464 }
 465
 466 static void
 467 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 468                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 469 {
 470         /* Windows x64 value type ABI.
 471         *
 472         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 473         *
 474         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 475         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 476         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 477         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 478         *
 479         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 480         *
 481         * Integers/Float types smaller than or equal to 8 bytes
 482         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 483         * Properly sized struct/unions (1,2,4,8)
 484         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 485         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 486         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 487         */
 488
 489         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 490
 491         if (!is_return) {
 492
 493                 /* Parameter cases. */
 494                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 495                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 496
 497                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 498                         arg_info->storage = ArgValuetypeInReg;
 499                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 500                                 /* No more registers, fallback passing parameter on stack as value. */
 501                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 502
 503                                 /* Passing value directly on stack, so use size of value. */
 504                                 arg_info->storage = ArgOnStack;
 505                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 506                                 arg_info->offset = *stack_size;
 507                                 arg_info->arg_size = arg_size;
 508                                 *stack_size += arg_size;
 509                         }
 510                 } else {
 511                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 512                         arg_info->storage = ArgValuetypeAddrInIReg;
 513                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 514                                 /* No more registers, fallback passing address to parameter on stack. */
 515                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 516
 517                                 /* Passing an address to value on stack, so use size of register as argument size. */
 518                                 arg_info->storage = ArgValuetypeAddrOnStack;
 519                                 arg_size = sizeof (mgreg_t);
 520                                 arg_info->offset = *stack_size;
 521                                 arg_info->arg_size = arg_size;
 522                                 *stack_size += arg_size;
 523                         }
 524                 }
 525         } else {
 526                 /* Return value cases. */
 527                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 528                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 529
 530                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 531                         arg_info->storage = ArgValuetypeInReg;
 532                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 533
 534                         /* Only RAX/XMM0 should be used to return valuetype. */
 535                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 536                 } else {
 537                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 538                         arg_info->storage = ArgValuetypeAddrInIReg;
 539                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 540
 541                         /* Only RAX should be used to return valuetype address. */
 542                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 543
 544                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 545                         arg_info->offset = *stack_size;
 546                         *stack_size += arg_size;
 547                 }
 548         }
 549 }
 550
 551 static void
 552 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 553 {
 554         *arg_size = 0;
 555         *arg_class = ARG_CLASS_NO_CLASS;
 556
 557         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 558
 559         if (pinvoke) {
 560                 /* Calculate argument class type and size of marshalled type. */
 561                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 562                 *arg_size = info->native_size;
 563         } else {
 564                 /* Calculate argument class type and size of managed type. */
 565                 *arg_size = mono_class_value_size (klass, NULL);
 566         }
 567
 568         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 569         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 570
 571         if (*arg_class == ARG_CLASS_MEMORY) {
 572                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 573                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 574         }
 575
 576         /*
 577         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 578         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 579         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 580         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 581         * it must be represented in call and cannot be dropped.
 582         */
 583         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 584                 arg_info->pass_empty_struct = TRUE;
 585                 *arg_size = SIZEOF_REGISTER;
 586                 *arg_class = ARG_CLASS_INTEGER;
 587         }
 588
 589         assert (*arg_class != ARG_CLASS_NO_CLASS);
 590 }
 591
 592 static void
 593 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 594                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 595 {
 596         guint32 arg_size = SIZEOF_REGISTER;
 597         MonoClass *klass = NULL;
 598         ArgumentClass arg_class;
 599
 600         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 601
 602         klass = mono_class_from_mono_type (type);
 603         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 604
 605         /* Only drop value type if its not an empty struct as input that must be represented in call */
 606         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 607                 arg_info->storage = ArgValuetypeInReg;
 608                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 609         } else {
 610                 /* Alocate storage for value type. */
 611                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 612         }
 613 }
 614
 615 #endif /* TARGET_WIN32 */
 616
 617 static void
 618 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 619                            gboolean is_return,
 620                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 621 {
 622 #ifdef TARGET_WIN32
 623         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 624 #else
 625         guint32 size, quad, nquads, i, nfields;
 626         /* Keep track of the size used in each quad so we can */
 627         /* use the right size when copying args/return vars.  */
 628         guint32 quadsize [2] = {8, 8};
 629         ArgumentClass args [2];
 630         StructFieldInfo *fields = NULL;
 631         GArray *fields_array;
 632         MonoClass *klass;
 633         gboolean pass_on_stack = FALSE;
 634         int struct_size;
 635
 636         klass = mono_class_from_mono_type (type);
 637         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 638
 639         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 640                 /* We pass and return vtypes of size 8 in a register */
 641         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 642                 pass_on_stack = TRUE;
 643         }
 644
 645         /* If this struct can't be split up naturally into 8-byte */
 646         /* chunks (registers), pass it on the stack.              */
 647         if (sig->pinvoke) {
 648                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 649                 g_assert (info);
 650                 struct_size = info->native_size;
 651         } else {
 652                 struct_size = mono_class_value_size (klass, NULL);
 653         }
 654         /*
 655          * Collect field information recursively to be able to
 656          * handle nested structures.
 657          */
 658         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 659         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 660         fields = (StructFieldInfo*)fields_array->data;
 661         nfields = fields_array->len;
 662
 663         for (i = 0; i < nfields; ++i) {
 664                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 665                         pass_on_stack = TRUE;
 666                         break;
 667                 }
 668         }
 669
 670         if (size == 0) {
 671                 ainfo->storage = ArgValuetypeInReg;
 672                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 673                 return;
 674         }
 675
 676         if (pass_on_stack) {
 677                 /* Allways pass in memory */
 678                 ainfo->offset = *stack_size;
 679                 *stack_size += ALIGN_TO (size, 8);
 680                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 681                 if (!is_return)
 682                         ainfo->arg_size = ALIGN_TO (size, 8);
 683
 684                 g_array_free (fields_array, TRUE);
 685                 return;
 686         }
 687
 688         if (size > 8)
 689                 nquads = 2;
 690         else
 691                 nquads = 1;
 692
 693         if (!sig->pinvoke) {
 694                 int n = mono_class_value_size (klass, NULL);
 695
 696                 quadsize [0] = n >= 8 ? 8 : n;
 697                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 698
 699                 /* Always pass in 1 or 2 integer registers */
 700                 args [0] = ARG_CLASS_INTEGER;
 701                 args [1] = ARG_CLASS_INTEGER;
 702                 /* Only the simplest cases are supported */
 703                 if (is_return && nquads != 1) {
 704                         args [0] = ARG_CLASS_MEMORY;
 705                         args [1] = ARG_CLASS_MEMORY;
 706                 }
 707         } else {
 708                 /*
 709                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 710                  * The X87 and SSEUP stuff is left out since there are no such types in
 711                  * the CLR.
 712                  */
 713                 if (!nfields) {
 714                         ainfo->storage = ArgValuetypeInReg;
 715                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 716                         return;
 717                 }
 718
 719                 if (struct_size > 16) {
 720                         ainfo->offset = *stack_size;
 721                         *stack_size += ALIGN_TO (struct_size, 8);
 722                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 723                         if (!is_return)
 724                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 725
 726                         g_array_free (fields_array, TRUE);
 727                         return;
 728                 }
 729
 730                 args [0] = ARG_CLASS_NO_CLASS;
 731                 args [1] = ARG_CLASS_NO_CLASS;
 732                 for (quad = 0; quad < nquads; ++quad) {
 733                         ArgumentClass class1;
 734
 735                         if (nfields == 0)
 736                                 class1 = ARG_CLASS_MEMORY;
 737                         else
 738                                 class1 = ARG_CLASS_NO_CLASS;
 739                         for (i = 0; i < nfields; ++i) {
 740                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 741                                         /* Unaligned field */
 742                                         NOT_IMPLEMENTED;
 743                                 }
 744
 745                                 /* Skip fields in other quad */
 746                                 if ((quad == 0) && (fields [i].offset >= 8))
 747                                         continue;
 748                                 if ((quad == 1) && (fields [i].offset < 8))
 749                                         continue;
 750
 751                                 /* How far into this quad this data extends.*/
 752                                 /* (8 is size of quad) */
 753                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 754
 755                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 756                         }
 757                         /* Empty structs have a nonzero size, causing this assert to be hit */
 758                         if (sig->pinvoke)
 759                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 760                         args [quad] = class1;
 761                 }
 762         }
 763
 764         g_array_free (fields_array, TRUE);
 765
 766         /* Post merger cleanup */
 767         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 768                 args [0] = args [1] = ARG_CLASS_MEMORY;
 769
 770         /* Allocate registers */
 771         {
 772                 int orig_gr = *gr;
 773                 int orig_fr = *fr;
 774
 775                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 776                         quadsize [0] ++;
 777                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 778                         quadsize [1] ++;
 779
 780                 ainfo->storage = ArgValuetypeInReg;
 781                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 782                 g_assert (quadsize [0] <= 8);
 783                 g_assert (quadsize [1] <= 8);
 784                 ainfo->pair_size [0] = quadsize [0];
 785                 ainfo->pair_size [1] = quadsize [1];
 786                 ainfo->nregs = nquads;
 787                 for (quad = 0; quad < nquads; ++quad) {
 788                         switch (args [quad]) {
 789                         case ARG_CLASS_INTEGER:
 790                                 if (*gr >= PARAM_REGS)
 791                                         args [quad] = ARG_CLASS_MEMORY;
 792                                 else {
 793                                         ainfo->pair_storage [quad] = ArgInIReg;
 794                                         if (is_return)
 795                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 796                                         else
 797                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 798                                         (*gr) ++;
 799                                 }
 800                                 break;
 801                         case ARG_CLASS_SSE:
 802                                 if (*fr >= FLOAT_PARAM_REGS)
 803                                         args [quad] = ARG_CLASS_MEMORY;
 804                                 else {
 805                                         if (quadsize[quad] <= 4)
 806                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 807                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 808                                         ainfo->pair_regs [quad] = *fr;
 809                                         (*fr) ++;
 810                                 }
 811                                 break;
 812                         case ARG_CLASS_MEMORY:
 813                                 break;
 814                         case ARG_CLASS_NO_CLASS:
 815                                 break;
 816                         default:
 817                                 g_assert_not_reached ();
 818                         }
 819                 }
 820
 821                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 822                         int arg_size;
 823                         /* Revert possible register assignments */
 824                         *gr = orig_gr;
 825                         *fr = orig_fr;
 826
 827                         ainfo->offset = *stack_size;
 828                         if (sig->pinvoke)
 829                                 arg_size = ALIGN_TO (struct_size, 8);
 830                         else
 831                                 arg_size = nquads * sizeof(mgreg_t);
 832                         *stack_size += arg_size;
 833                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 834                         if (!is_return)
 835                                 ainfo->arg_size = arg_size;
 836                 }
 837         }
 838 #endif /* !TARGET_WIN32 */
 839 }
 840
 841 /*
 842  * get_call_info:
 843  *
 844  * Obtain information about a call according to the calling convention.
 845  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 846  * Draft Version 0.23" document for more information.
 847  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 848  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 849  */
 850 static CallInfo*
 851 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 852 {
 853         guint32 i, gr, fr, pstart;
 854         MonoType *ret_type;
 855         int n = sig->hasthis + sig->param_count;
 856         guint32 stack_size = 0;
 857         CallInfo *cinfo;
 858         gboolean is_pinvoke = sig->pinvoke;
 859
 860         if (mp)
 861                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 862         else
 863                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 864
 865         cinfo->nargs = n;
 866         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 867
 868         gr = 0;
 869         fr = 0;
 870
 871 #ifdef TARGET_WIN32
 872         /* Reserve space where the callee can save the argument registers */
 873         stack_size = 4 * sizeof (mgreg_t);
 874 #endif
 875
 876         /* return value */
 877         ret_type = mini_get_underlying_type (sig->ret);
 878         switch (ret_type->type) {
 879         case MONO_TYPE_I1:
 880         case MONO_TYPE_U1:
 881         case MONO_TYPE_I2:
 882         case MONO_TYPE_U2:
 883         case MONO_TYPE_I4:
 884         case MONO_TYPE_U4:
 885         case MONO_TYPE_I:
 886         case MONO_TYPE_U:
 887         case MONO_TYPE_PTR:
 888         case MONO_TYPE_FNPTR:
 889         case MONO_TYPE_OBJECT:
 890                 cinfo->ret.storage = ArgInIReg;
 891                 cinfo->ret.reg = AMD64_RAX;
 892                 break;
 893         case MONO_TYPE_U8:
 894         case MONO_TYPE_I8:
 895                 cinfo->ret.storage = ArgInIReg;
 896                 cinfo->ret.reg = AMD64_RAX;
 897                 break;
 898         case MONO_TYPE_R4:
 899                 cinfo->ret.storage = ArgInFloatSSEReg;
 900                 cinfo->ret.reg = AMD64_XMM0;
 901                 break;
 902         case MONO_TYPE_R8:
 903                 cinfo->ret.storage = ArgInDoubleSSEReg;
 904                 cinfo->ret.reg = AMD64_XMM0;
 905                 break;
 906         case MONO_TYPE_GENERICINST:
 907                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 908                         cinfo->ret.storage = ArgInIReg;
 909                         cinfo->ret.reg = AMD64_RAX;
 910                         break;
 911                 }
 912                 if (mini_is_gsharedvt_type (ret_type)) {
 913                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 914                         break;
 915                 }
 916                 /* fall through */
 917         case MONO_TYPE_VALUETYPE:
 918         case MONO_TYPE_TYPEDBYREF: {
 919                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 920
 921                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 922                 g_assert (cinfo->ret.storage != ArgInIReg);
 923                 break;
 924         }
 925         case MONO_TYPE_VAR:
 926         case MONO_TYPE_MVAR:
 927                 g_assert (mini_is_gsharedvt_type (ret_type));
 928                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 929                 break;
 930         case MONO_TYPE_VOID:
 931                 break;
 932         default:
 933                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 934         }
 935
 936         pstart = 0;
 937         /*
 938          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 939          * the first argument, allowing 'this' to be always passed in the first arg reg.
 940          * Also do this if the first argument is a reference type, since virtual calls
 941          * are sometimes made using calli without sig->hasthis set, like in the delegate
 942          * invoke wrappers.
 943          */
 944         ArgStorage ret_storage = cinfo->ret.storage;
 945         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 946                 if (sig->hasthis) {
 947                         add_general (&gr, &stack_size, cinfo->args + 0);
 948                 } else {
 949                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 950                         pstart = 1;
 951                 }
 952                 add_general (&gr, &stack_size, &cinfo->ret);
 953                 cinfo->ret.storage = ret_storage;
 954                 cinfo->vret_arg_index = 1;
 955         } else {
 956                 /* this */
 957                 if (sig->hasthis)
 958                         add_general (&gr, &stack_size, cinfo->args + 0);
 959
 960                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 961                         add_general (&gr, &stack_size, &cinfo->ret);
 962                         cinfo->ret.storage = ret_storage;
 963                 }
 964         }
 965
 966         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 967                 gr = PARAM_REGS;
 968                 fr = FLOAT_PARAM_REGS;
 969
 970                 /* Emit the signature cookie just before the implicit arguments */
 971                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 972         }
 973
 974         for (i = pstart; i < sig->param_count; ++i) {
 975                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 976                 MonoType *ptype;
 977
 978 #ifdef TARGET_WIN32
 979                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 980                 if (gr > fr)
 981                         fr = gr;
 982                 else if (fr > gr)
 983                         gr = fr;
 984 #endif
 985
 986                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 987                         /* We allways pass the sig cookie on the stack for simplicity */
 988                         /*
 989                          * Prevent implicit arguments + the sig cookie from being passed
 990                          * in registers.
 991                          */
 992                         gr = PARAM_REGS;
 993                         fr = FLOAT_PARAM_REGS;
 994
 995                         /* Emit the signature cookie just before the implicit arguments */
 996                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 997                 }
 998
 999                 ptype = mini_get_underlying_type (sig->params [i]);
1000                 switch (ptype->type) {
1001                 case MONO_TYPE_I1:
1002                 case MONO_TYPE_U1:
1003                         add_general (&gr, &stack_size, ainfo);
1004                         ainfo->byte_arg_size = 1;
1005                         break;
1006                 case MONO_TYPE_I2:
1007                 case MONO_TYPE_U2:
1008                         add_general (&gr, &stack_size, ainfo);
1009                         ainfo->byte_arg_size = 2;
1010                         break;
1011                 case MONO_TYPE_I4:
1012                 case MONO_TYPE_U4:
1013                         add_general (&gr, &stack_size, ainfo);
1014                         ainfo->byte_arg_size = 4;
1015                         break;
1016                 case MONO_TYPE_I:
1017                 case MONO_TYPE_U:
1018                 case MONO_TYPE_PTR:
1019                 case MONO_TYPE_FNPTR:
1020                 case MONO_TYPE_OBJECT:
1021                         add_general (&gr, &stack_size, ainfo);
1022                         break;
1023                 case MONO_TYPE_GENERICINST:
1024                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1025                                 add_general (&gr, &stack_size, ainfo);
1026                                 break;
1027                         }
1028                         if (mini_is_gsharedvt_variable_type (ptype)) {
1029                                 /* gsharedvt arguments are passed by ref */
1030                                 add_general (&gr, &stack_size, ainfo);
1031                                 if (ainfo->storage == ArgInIReg)
1032                                         ainfo->storage = ArgGSharedVtInReg;
1033                                 else
1034                                         ainfo->storage = ArgGSharedVtOnStack;
1035                                 break;
1036                         }
1037                         /* fall through */
1038                 case MONO_TYPE_VALUETYPE:
1039                 case MONO_TYPE_TYPEDBYREF:
1040                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1041                         break;
1042                 case MONO_TYPE_U8:
1043
1044                 case MONO_TYPE_I8:
1045                         add_general (&gr, &stack_size, ainfo);
1046                         break;
1047                 case MONO_TYPE_R4:
1048                         add_float (&fr, &stack_size, ainfo, FALSE);
1049                         break;
1050                 case MONO_TYPE_R8:
1051                         add_float (&fr, &stack_size, ainfo, TRUE);
1052                         break;
1053                 case MONO_TYPE_VAR:
1054                 case MONO_TYPE_MVAR:
1055                         /* gsharedvt arguments are passed by ref */
1056                         g_assert (mini_is_gsharedvt_type (ptype));
1057                         add_general (&gr, &stack_size, ainfo);
1058                         if (ainfo->storage == ArgInIReg)
1059                                 ainfo->storage = ArgGSharedVtInReg;
1060                         else
1061                                 ainfo->storage = ArgGSharedVtOnStack;
1062                         break;
1063                 default:
1064                         g_assert_not_reached ();
1065                 }
1066         }
1067
1068         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1069                 gr = PARAM_REGS;
1070                 fr = FLOAT_PARAM_REGS;
1071
1072                 /* Emit the signature cookie just before the implicit arguments */
1073                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1074         }
1075
1076         cinfo->stack_usage = stack_size;
1077         cinfo->reg_usage = gr;
1078         cinfo->freg_usage = fr;
1079         return cinfo;
1080 }
1081
1082 /*
1083  * mono_arch_get_argument_info:
1084  * @csig:  a method signature
1085  * @param_count: the number of parameters to consider
1086  * @arg_info: an array to store the result infos
1087  *
1088  * Gathers information on parameters such as size, alignment and
1089  * padding. arg_info should be large enought to hold param_count + 1 entries.
1090  *
1091  * Returns the size of the argument area on the stack.
1092  */
1093 int
1094 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1095 {
1096         int k;
1097         CallInfo *cinfo = get_call_info (NULL, csig);
1098         guint32 args_size = cinfo->stack_usage;
1099
1100         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1101         if (csig->hasthis) {
1102                 arg_info [0].offset = 0;
1103         }
1104
1105         for (k = 0; k < param_count; k++) {
1106                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1107                 /* FIXME: */
1108                 arg_info [k + 1].size = 0;
1109         }
1110
1111         g_free (cinfo);
1112
1113         return args_size;
1114 }
1115
1116 gboolean
1117 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1118 {
1119         CallInfo *c1, *c2;
1120         gboolean res;
1121         MonoType *callee_ret;
1122
1123         c1 = get_call_info (NULL, caller_sig);
1124         c2 = get_call_info (NULL, callee_sig);
1125         res = c1->stack_usage >= c2->stack_usage;
1126         callee_ret = mini_get_underlying_type (callee_sig->ret);
1127         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1128                 /* An address on the callee's stack is passed as the first argument */
1129                 res = FALSE;
1130
1131         g_free (c1);
1132         g_free (c2);
1133
1134         return res;
1135 }
1136
1137 /*
1138  * Initialize the cpu to execute managed code.
1139  */
1140 void
1141 mono_arch_cpu_init (void)
1142 {
1143 #ifndef _MSC_VER
1144         guint16 fpcw;
1145
1146         /* spec compliance requires running with double precision */
1147         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1148         fpcw &= ~X86_FPCW_PRECC_MASK;
1149         fpcw |= X86_FPCW_PREC_DOUBLE;
1150         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1151         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1152 #else
1153         /* TODO: This is crashing on Win64 right now.
1154         * _control87 (_PC_53, MCW_PC);
1155         */
1156 #endif
1157 }
1158
1159 /*
1160  * Initialize architecture specific code.
1161  */
1162 void
1163 mono_arch_init (void)
1164 {
1165         mono_os_mutex_init_recursive (&mini_arch_mutex);
1166
1167         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1168         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1169         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1170         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1171
1172 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1173         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1174 #endif
1175
1176         if (!mono_aot_only)
1177                 bp_trampoline = mini_get_breakpoint_trampoline ();
1178 }
1179
1180 /*
1181  * Cleanup architecture specific code.
1182  */
1183 void
1184 mono_arch_cleanup (void)
1185 {
1186         mono_os_mutex_destroy (&mini_arch_mutex);
1187 }
1188
1189 /*
1190  * This function returns the optimizations supported on this cpu.
1191  */
1192 guint32
1193 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1194 {
1195         guint32 opts = 0;
1196
1197         *exclude_mask = 0;
1198
1199         if (mono_hwcap_x86_has_cmov) {
1200                 opts |= MONO_OPT_CMOV;
1201
1202                 if (mono_hwcap_x86_has_fcmov)
1203                         opts |= MONO_OPT_FCMOV;
1204                 else
1205                         *exclude_mask |= MONO_OPT_FCMOV;
1206         } else {
1207                 *exclude_mask |= MONO_OPT_CMOV;
1208         }
1209
1210 #ifdef TARGET_WIN32
1211         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1212         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1213         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1214         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1215         /* will now have a reference to an argument that won't be fully decomposed. */
1216         *exclude_mask |= MONO_OPT_SIMD;
1217 #endif
1218
1219         return opts;
1220 }
1221
1222 /*
1223  * This function test for all SSE functions supported.
1224  *
1225  * Returns a bitmask corresponding to all supported versions.
1226  *
1227  */
1228 guint32
1229 mono_arch_cpu_enumerate_simd_versions (void)
1230 {
1231         guint32 sse_opts = 0;
1232
1233         if (mono_hwcap_x86_has_sse1)
1234                 sse_opts |= SIMD_VERSION_SSE1;
1235
1236         if (mono_hwcap_x86_has_sse2)
1237                 sse_opts |= SIMD_VERSION_SSE2;
1238
1239         if (mono_hwcap_x86_has_sse3)
1240                 sse_opts |= SIMD_VERSION_SSE3;
1241
1242         if (mono_hwcap_x86_has_ssse3)
1243                 sse_opts |= SIMD_VERSION_SSSE3;
1244
1245         if (mono_hwcap_x86_has_sse41)
1246                 sse_opts |= SIMD_VERSION_SSE41;
1247
1248         if (mono_hwcap_x86_has_sse42)
1249                 sse_opts |= SIMD_VERSION_SSE42;
1250
1251         if (mono_hwcap_x86_has_sse4a)
1252                 sse_opts |= SIMD_VERSION_SSE4a;
1253
1254         return sse_opts;
1255 }
1256
1257 #ifndef DISABLE_JIT
1258
1259 GList *
1260 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1261 {
1262         GList *vars = NULL;
1263         int i;
1264
1265         for (i = 0; i < cfg->num_varinfo; i++) {
1266                 MonoInst *ins = cfg->varinfo [i];
1267                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1268
1269                 /* unused vars */
1270                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1271                         continue;
1272
1273                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1274                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1275                         continue;
1276
1277                 if (mono_is_regsize_var (ins->inst_vtype)) {
1278                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1279                         g_assert (i == vmv->idx);
1280                         vars = g_list_prepend (vars, vmv);
1281                 }
1282         }
1283
1284         vars = mono_varlist_sort (cfg, vars, 0);
1285
1286         return vars;
1287 }
1288
1289 /**
1290  * mono_arch_compute_omit_fp:
1291  * Determine whether the frame pointer can be eliminated.
1292  */
1293 static void
1294 mono_arch_compute_omit_fp (MonoCompile *cfg)
1295 {
1296         MonoMethodSignature *sig;
1297         MonoMethodHeader *header;
1298         int i, locals_size;
1299         CallInfo *cinfo;
1300
1301         if (cfg->arch.omit_fp_computed)
1302                 return;
1303
1304         header = cfg->header;
1305
1306         sig = mono_method_signature (cfg->method);
1307
1308         if (!cfg->arch.cinfo)
1309                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1310         cinfo = (CallInfo *)cfg->arch.cinfo;
1311
1312         /*
1313          * FIXME: Remove some of the restrictions.
1314          */
1315         cfg->arch.omit_fp = TRUE;
1316         cfg->arch.omit_fp_computed = TRUE;
1317
1318         if (cfg->disable_omit_fp)
1319                 cfg->arch.omit_fp = FALSE;
1320
1321         if (!debug_omit_fp ())
1322                 cfg->arch.omit_fp = FALSE;
1323         /*
1324         if (cfg->method->save_lmf)
1325                 cfg->arch.omit_fp = FALSE;
1326         */
1327         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1328                 cfg->arch.omit_fp = FALSE;
1329         if (header->num_clauses)
1330                 cfg->arch.omit_fp = FALSE;
1331         if (cfg->param_area)
1332                 cfg->arch.omit_fp = FALSE;
1333         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1334                 cfg->arch.omit_fp = FALSE;
1335         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1336                 cfg->arch.omit_fp = FALSE;
1337         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1338                 ArgInfo *ainfo = &cinfo->args [i];
1339
1340                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1341                         /*
1342                          * The stack offset can only be determined when the frame
1343                          * size is known.
1344                          */
1345                         cfg->arch.omit_fp = FALSE;
1346                 }
1347         }
1348
1349         locals_size = 0;
1350         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1351                 MonoInst *ins = cfg->varinfo [i];
1352                 int ialign;
1353
1354                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1355         }
1356 }
1357
1358 GList *
1359 mono_arch_get_global_int_regs (MonoCompile *cfg)
1360 {
1361         GList *regs = NULL;
1362
1363         mono_arch_compute_omit_fp (cfg);
1364
1365         if (cfg->arch.omit_fp)
1366                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1367
1368         /* We use the callee saved registers for global allocation */
1369         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1370         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1371         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1372         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1373         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1374 #ifdef TARGET_WIN32
1375         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1376         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1377 #endif
1378
1379         return regs;
1380 }
1381
1382 GList*
1383 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1384 {
1385         GList *regs = NULL;
1386         int i;
1387
1388         /* All XMM registers */
1389         for (i = 0; i < 16; ++i)
1390                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1391
1392         return regs;
1393 }
1394
1395 GList*
1396 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1397 {
1398         static GList *r = NULL;
1399
1400         if (r == NULL) {
1401                 GList *regs = NULL;
1402
1403                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1404                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1405                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1406                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1407                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1408                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1409
1410                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1411                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1412                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1417                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1418
1419                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1420         }
1421
1422         return r;
1423 }
1424
1425 GList*
1426 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1427 {
1428         int i;
1429         static GList *r = NULL;
1430
1431         if (r == NULL) {
1432                 GList *regs = NULL;
1433
1434                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1435                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1436
1437                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1438         }
1439
1440         return r;
1441 }
1442
1443 /*
1444  * mono_arch_regalloc_cost:
1445  *
1446  *  Return the cost, in number of memory references, of the action of
1447  * allocating the variable VMV into a register during global register
1448  * allocation.
1449  */
1450 guint32
1451 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1452 {
1453         MonoInst *ins = cfg->varinfo [vmv->idx];
1454
1455         if (cfg->method->save_lmf)
1456                 /* The register is already saved */
1457                 /* substract 1 for the invisible store in the prolog */
1458                 return (ins->opcode == OP_ARG) ? 0 : 1;
1459         else
1460                 /* push+pop */
1461                 return (ins->opcode == OP_ARG) ? 1 : 2;
1462 }
1463
1464 /*
1465  * mono_arch_fill_argument_info:
1466  *
1467  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1468  * of the method.
1469  */
1470 void
1471 mono_arch_fill_argument_info (MonoCompile *cfg)
1472 {
1473         MonoType *sig_ret;
1474         MonoMethodSignature *sig;
1475         MonoInst *ins;
1476         int i;
1477         CallInfo *cinfo;
1478
1479         sig = mono_method_signature (cfg->method);
1480
1481         cinfo = (CallInfo *)cfg->arch.cinfo;
1482         sig_ret = mini_get_underlying_type (sig->ret);
1483
1484         /*
1485          * Contrary to mono_arch_allocate_vars (), the information should describe
1486          * where the arguments are at the beginning of the method, not where they can be
1487          * accessed during the execution of the method. The later makes no sense for the
1488          * global register allocator, since a variable can be in more than one location.
1489          */
1490         switch (cinfo->ret.storage) {
1491         case ArgInIReg:
1492         case ArgInFloatSSEReg:
1493         case ArgInDoubleSSEReg:
1494                 cfg->ret->opcode = OP_REGVAR;
1495                 cfg->ret->inst_c0 = cinfo->ret.reg;
1496                 break;
1497         case ArgValuetypeInReg:
1498                 cfg->ret->opcode = OP_REGOFFSET;
1499                 cfg->ret->inst_basereg = -1;
1500                 cfg->ret->inst_offset = -1;
1501                 break;
1502         case ArgNone:
1503                 break;
1504         default:
1505                 g_assert_not_reached ();
1506         }
1507
1508         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1509                 ArgInfo *ainfo = &cinfo->args [i];
1510
1511                 ins = cfg->args [i];
1512
1513                 switch (ainfo->storage) {
1514                 case ArgInIReg:
1515                 case ArgInFloatSSEReg:
1516                 case ArgInDoubleSSEReg:
1517                         ins->opcode = OP_REGVAR;
1518                         ins->inst_c0 = ainfo->reg;
1519                         break;
1520                 case ArgOnStack:
1521                         ins->opcode = OP_REGOFFSET;
1522                         ins->inst_basereg = -1;
1523                         ins->inst_offset = -1;
1524                         break;
1525                 case ArgValuetypeInReg:
1526                         /* Dummy */
1527                         ins->opcode = OP_NOP;
1528                         break;
1529                 default:
1530                         g_assert_not_reached ();
1531                 }
1532         }
1533 }
1534
1535 void
1536 mono_arch_allocate_vars (MonoCompile *cfg)
1537 {
1538         MonoType *sig_ret;
1539         MonoMethodSignature *sig;
1540         MonoInst *ins;
1541         int i, offset;
1542         guint32 locals_stack_size, locals_stack_align;
1543         gint32 *offsets;
1544         CallInfo *cinfo;
1545
1546         sig = mono_method_signature (cfg->method);
1547
1548         cinfo = (CallInfo *)cfg->arch.cinfo;
1549         sig_ret = mini_get_underlying_type (sig->ret);
1550
1551         mono_arch_compute_omit_fp (cfg);
1552
1553         /*
1554          * We use the ABI calling conventions for managed code as well.
1555          * Exception: valuetypes are only sometimes passed or returned in registers.
1556          */
1557
1558         /*
1559          * The stack looks like this:
1560          * <incoming arguments passed on the stack>
1561          * <return value>
1562          * <lmf/caller saved registers>
1563          * <locals>
1564          * <spill area>
1565          * <localloc area>  -> grows dynamically
1566          * <params area>
1567          */
1568
1569         if (cfg->arch.omit_fp) {
1570                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1571                 cfg->frame_reg = AMD64_RSP;
1572                 offset = 0;
1573         } else {
1574                 /* Locals are allocated backwards from %fp */
1575                 cfg->frame_reg = AMD64_RBP;
1576                 offset = 0;
1577         }
1578
1579         cfg->arch.saved_iregs = cfg->used_int_regs;
1580         if (cfg->method->save_lmf) {
1581                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1582                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1583                 cfg->arch.saved_iregs |= iregs_to_save;
1584         }
1585
1586         if (cfg->arch.omit_fp)
1587                 cfg->arch.reg_save_area_offset = offset;
1588         /* Reserve space for callee saved registers */
1589         for (i = 0; i < AMD64_NREG; ++i)
1590                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1591                         offset += sizeof(mgreg_t);
1592                 }
1593         if (!cfg->arch.omit_fp)
1594                 cfg->arch.reg_save_area_offset = -offset;
1595
1596         if (sig_ret->type != MONO_TYPE_VOID) {
1597                 switch (cinfo->ret.storage) {
1598                 case ArgInIReg:
1599                 case ArgInFloatSSEReg:
1600                 case ArgInDoubleSSEReg:
1601                         cfg->ret->opcode = OP_REGVAR;
1602                         cfg->ret->inst_c0 = cinfo->ret.reg;
1603                         cfg->ret->dreg = cinfo->ret.reg;
1604                         break;
1605                 case ArgValuetypeAddrInIReg:
1606                 case ArgGsharedvtVariableInReg:
1607                         /* The register is volatile */
1608                         cfg->vret_addr->opcode = OP_REGOFFSET;
1609                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1610                         if (cfg->arch.omit_fp) {
1611                                 cfg->vret_addr->inst_offset = offset;
1612                                 offset += 8;
1613                         } else {
1614                                 offset += 8;
1615                                 cfg->vret_addr->inst_offset = -offset;
1616                         }
1617                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1618                                 printf ("vret_addr =");
1619                                 mono_print_ins (cfg->vret_addr);
1620                         }
1621                         break;
1622                 case ArgValuetypeInReg:
1623                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1624                         cfg->ret->opcode = OP_REGOFFSET;
1625                         cfg->ret->inst_basereg = cfg->frame_reg;
1626                         if (cfg->arch.omit_fp) {
1627                                 cfg->ret->inst_offset = offset;
1628                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1629                         } else {
1630                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1631                                 cfg->ret->inst_offset = - offset;
1632                         }
1633                         break;
1634                 default:
1635                         g_assert_not_reached ();
1636                 }
1637         }
1638
1639         /* Allocate locals */
1640         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1641         if (locals_stack_align) {
1642                 offset += (locals_stack_align - 1);
1643                 offset &= ~(locals_stack_align - 1);
1644         }
1645         if (cfg->arch.omit_fp) {
1646                 cfg->locals_min_stack_offset = offset;
1647                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1648         } else {
1649                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1650                 cfg->locals_max_stack_offset = - offset;
1651         }
1652
1653         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1654                 if (offsets [i] != -1) {
1655                         MonoInst *ins = cfg->varinfo [i];
1656                         ins->opcode = OP_REGOFFSET;
1657                         ins->inst_basereg = cfg->frame_reg;
1658                         if (cfg->arch.omit_fp)
1659                                 ins->inst_offset = (offset + offsets [i]);
1660                         else
1661                                 ins->inst_offset = - (offset + offsets [i]);
1662                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1663                 }
1664         }
1665         offset += locals_stack_size;
1666
1667         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1668                 g_assert (!cfg->arch.omit_fp);
1669                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1670                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1671         }
1672
1673         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1674                 ins = cfg->args [i];
1675                 if (ins->opcode != OP_REGVAR) {
1676                         ArgInfo *ainfo = &cinfo->args [i];
1677                         gboolean inreg = TRUE;
1678
1679                         /* FIXME: Allocate volatile arguments to registers */
1680                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1681                                 inreg = FALSE;
1682
1683                         /*
1684                          * Under AMD64, all registers used to pass arguments to functions
1685                          * are volatile across calls.
1686                          * FIXME: Optimize this.
1687                          */
1688                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1689                                 inreg = FALSE;
1690
1691                         ins->opcode = OP_REGOFFSET;
1692
1693                         switch (ainfo->storage) {
1694                         case ArgInIReg:
1695                         case ArgInFloatSSEReg:
1696                         case ArgInDoubleSSEReg:
1697                         case ArgGSharedVtInReg:
1698                                 if (inreg) {
1699                                         ins->opcode = OP_REGVAR;
1700                                         ins->dreg = ainfo->reg;
1701                                 }
1702                                 break;
1703                         case ArgOnStack:
1704                         case ArgGSharedVtOnStack:
1705                                 g_assert (!cfg->arch.omit_fp);
1706                                 ins->opcode = OP_REGOFFSET;
1707                                 ins->inst_basereg = cfg->frame_reg;
1708                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1709                                 break;
1710                         case ArgValuetypeInReg:
1711                                 break;
1712                         case ArgValuetypeAddrInIReg:
1713                         case ArgValuetypeAddrOnStack: {
1714                                 MonoInst *indir;
1715                                 g_assert (!cfg->arch.omit_fp);
1716                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1717                                 MONO_INST_NEW (cfg, indir, 0);
1718
1719                                 indir->opcode = OP_REGOFFSET;
1720                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1721                                         indir->inst_basereg = cfg->frame_reg;
1722                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1723                                         offset += (sizeof (gpointer));
1724                                         indir->inst_offset = - offset;
1725                                 }
1726                                 else {
1727                                         indir->inst_basereg = cfg->frame_reg;
1728                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1729                                 }
1730
1731                                 ins->opcode = OP_VTARG_ADDR;
1732                                 ins->inst_left = indir;
1733
1734                                 break;
1735                         }
1736                         default:
1737                                 NOT_IMPLEMENTED;
1738                         }
1739
1740                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1741                                 ins->opcode = OP_REGOFFSET;
1742                                 ins->inst_basereg = cfg->frame_reg;
1743                                 /* These arguments are saved to the stack in the prolog */
1744                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1745                                 if (cfg->arch.omit_fp) {
1746                                         ins->inst_offset = offset;
1747                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1748                                         // Arguments are yet supported by the stack map creation code
1749                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1750                                 } else {
1751                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1752                                         ins->inst_offset = - offset;
1753                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1754                                 }
1755                         }
1756                 }
1757         }
1758
1759         cfg->stack_offset = offset;
1760 }
1761
1762 void
1763 mono_arch_create_vars (MonoCompile *cfg)
1764 {
1765         MonoMethodSignature *sig;
1766         CallInfo *cinfo;
1767         MonoType *sig_ret;
1768
1769         sig = mono_method_signature (cfg->method);
1770
1771         if (!cfg->arch.cinfo)
1772                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1773         cinfo = (CallInfo *)cfg->arch.cinfo;
1774
1775         if (cinfo->ret.storage == ArgValuetypeInReg)
1776                 cfg->ret_var_is_local = TRUE;
1777
1778         sig_ret = mini_get_underlying_type (sig->ret);
1779         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1780                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1781                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1782                         printf ("vret_addr = ");
1783                         mono_print_ins (cfg->vret_addr);
1784                 }
1785         }
1786
1787         if (cfg->gen_sdb_seq_points) {
1788                 MonoInst *ins;
1789
1790                 if (cfg->compile_aot) {
1791                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1792                         ins->flags |= MONO_INST_VOLATILE;
1793                         cfg->arch.seq_point_info_var = ins;
1794                 }
1795                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1796                 ins->flags |= MONO_INST_VOLATILE;
1797                 cfg->arch.ss_tramp_var = ins;
1798
1799                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1800                 ins->flags |= MONO_INST_VOLATILE;
1801                 cfg->arch.bp_tramp_var = ins;
1802         }
1803
1804         if (cfg->method->save_lmf)
1805                 cfg->create_lmf_var = TRUE;
1806
1807         if (cfg->method->save_lmf) {
1808                 cfg->lmf_ir = TRUE;
1809         }
1810 }
1811
1812 static void
1813 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1814 {
1815         MonoInst *ins;
1816
1817         switch (storage) {
1818         case ArgInIReg:
1819                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1820                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1821                 ins->sreg1 = tree->dreg;
1822                 MONO_ADD_INS (cfg->cbb, ins);
1823                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1824                 break;
1825         case ArgInFloatSSEReg:
1826                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1827                 ins->dreg = mono_alloc_freg (cfg);
1828                 ins->sreg1 = tree->dreg;
1829                 MONO_ADD_INS (cfg->cbb, ins);
1830
1831                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1832                 break;
1833         case ArgInDoubleSSEReg:
1834                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1835                 ins->dreg = mono_alloc_freg (cfg);
1836                 ins->sreg1 = tree->dreg;
1837                 MONO_ADD_INS (cfg->cbb, ins);
1838
1839                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1840
1841                 break;
1842         default:
1843                 g_assert_not_reached ();
1844         }
1845 }
1846
1847 static int
1848 arg_storage_to_load_membase (ArgStorage storage)
1849 {
1850         switch (storage) {
1851         case ArgInIReg:
1852 #if defined(__mono_ilp32__)
1853                 return OP_LOADI8_MEMBASE;
1854 #else
1855                 return OP_LOAD_MEMBASE;
1856 #endif
1857         case ArgInDoubleSSEReg:
1858                 return OP_LOADR8_MEMBASE;
1859         case ArgInFloatSSEReg:
1860                 return OP_LOADR4_MEMBASE;
1861         default:
1862                 g_assert_not_reached ();
1863         }
1864
1865         return -1;
1866 }
1867
1868 static void
1869 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1870 {
1871         MonoMethodSignature *tmp_sig;
1872         int sig_reg;
1873
1874         if (call->tail_call)
1875                 NOT_IMPLEMENTED;
1876
1877         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1878
1879         /*
1880          * mono_ArgIterator_Setup assumes the signature cookie is
1881          * passed first and all the arguments which were before it are
1882          * passed on the stack after the signature. So compensate by
1883          * passing a different signature.
1884          */
1885         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1886         tmp_sig->param_count -= call->signature->sentinelpos;
1887         tmp_sig->sentinelpos = 0;
1888         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1889
1890         sig_reg = mono_alloc_ireg (cfg);
1891         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1892
1893         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1894 }
1895
1896 #ifdef ENABLE_LLVM
1897 static inline LLVMArgStorage
1898 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1899 {
1900         switch (storage) {
1901         case ArgInIReg:
1902                 return LLVMArgInIReg;
1903         case ArgNone:
1904                 return LLVMArgNone;
1905         case ArgGSharedVtInReg:
1906         case ArgGSharedVtOnStack:
1907                 return LLVMArgGSharedVt;
1908         default:
1909                 g_assert_not_reached ();
1910                 return LLVMArgNone;
1911         }
1912 }
1913
1914 LLVMCallInfo*
1915 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1916 {
1917         int i, n;
1918         CallInfo *cinfo;
1919         ArgInfo *ainfo;
1920         int j;
1921         LLVMCallInfo *linfo;
1922         MonoType *t, *sig_ret;
1923
1924         n = sig->param_count + sig->hasthis;
1925         sig_ret = mini_get_underlying_type (sig->ret);
1926
1927         cinfo = get_call_info (cfg->mempool, sig);
1928
1929         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1930
1931         /*
1932          * LLVM always uses the native ABI while we use our own ABI, the
1933          * only difference is the handling of vtypes:
1934          * - we only pass/receive them in registers in some cases, and only
1935          *   in 1 or 2 integer registers.
1936          */
1937         switch (cinfo->ret.storage) {
1938         case ArgNone:
1939                 linfo->ret.storage = LLVMArgNone;
1940                 break;
1941         case ArgInIReg:
1942         case ArgInFloatSSEReg:
1943         case ArgInDoubleSSEReg:
1944                 linfo->ret.storage = LLVMArgNormal;
1945                 break;
1946         case ArgValuetypeInReg: {
1947                 ainfo = &cinfo->ret;
1948
1949                 if (sig->pinvoke &&
1950                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1951                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1952                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1953                         cfg->disable_llvm = TRUE;
1954                         return linfo;
1955                 }
1956
1957                 linfo->ret.storage = LLVMArgVtypeInReg;
1958                 for (j = 0; j < 2; ++j)
1959                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1960                 break;
1961         }
1962         case ArgValuetypeAddrInIReg:
1963         case ArgGsharedvtVariableInReg:
1964                 /* Vtype returned using a hidden argument */
1965                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1966                 linfo->vret_arg_index = cinfo->vret_arg_index;
1967                 break;
1968         default:
1969                 g_assert_not_reached ();
1970                 break;
1971         }
1972
1973         for (i = 0; i < n; ++i) {
1974                 ainfo = cinfo->args + i;
1975
1976                 if (i >= sig->hasthis)
1977                         t = sig->params [i - sig->hasthis];
1978                 else
1979                         t = &mono_defaults.int_class->byval_arg;
1980                 t = mini_type_get_underlying_type (t);
1981
1982                 linfo->args [i].storage = LLVMArgNone;
1983
1984                 switch (ainfo->storage) {
1985                 case ArgInIReg:
1986                         linfo->args [i].storage = LLVMArgNormal;
1987                         break;
1988                 case ArgInDoubleSSEReg:
1989                 case ArgInFloatSSEReg:
1990                         linfo->args [i].storage = LLVMArgNormal;
1991                         break;
1992                 case ArgOnStack:
1993                         if (MONO_TYPE_ISSTRUCT (t))
1994                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1995                         else
1996                                 linfo->args [i].storage = LLVMArgNormal;
1997                         break;
1998                 case ArgValuetypeInReg:
1999                         if (sig->pinvoke &&
2000                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2001                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2002                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2003                                 cfg->disable_llvm = TRUE;
2004                                 return linfo;
2005                         }
2006
2007                         linfo->args [i].storage = LLVMArgVtypeInReg;
2008                         for (j = 0; j < 2; ++j)
2009                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2010                         break;
2011                 case ArgGSharedVtInReg:
2012                 case ArgGSharedVtOnStack:
2013                         linfo->args [i].storage = LLVMArgGSharedVt;
2014                         break;
2015                 default:
2016                         cfg->exception_message = g_strdup ("ainfo->storage");
2017                         cfg->disable_llvm = TRUE;
2018                         break;
2019                 }
2020         }
2021
2022         return linfo;
2023 }
2024 #endif
2025
2026 void
2027 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2028 {
2029         MonoInst *arg, *in;
2030         MonoMethodSignature *sig;
2031         MonoType *sig_ret;
2032         int i, n;
2033         CallInfo *cinfo;
2034         ArgInfo *ainfo;
2035
2036         sig = call->signature;
2037         n = sig->param_count + sig->hasthis;
2038
2039         cinfo = get_call_info (cfg->mempool, sig);
2040
2041         sig_ret = sig->ret;
2042
2043         if (COMPILE_LLVM (cfg)) {
2044                 /* We shouldn't be called in the llvm case */
2045                 cfg->disable_llvm = TRUE;
2046                 return;
2047         }
2048
2049         /*
2050          * Emit all arguments which are passed on the stack to prevent register
2051          * allocation problems.
2052          */
2053         for (i = 0; i < n; ++i) {
2054                 MonoType *t;
2055                 ainfo = cinfo->args + i;
2056
2057                 in = call->args [i];
2058
2059                 if (sig->hasthis && i == 0)
2060                         t = &mono_defaults.object_class->byval_arg;
2061                 else
2062                         t = sig->params [i - sig->hasthis];
2063
2064                 t = mini_get_underlying_type (t);
2065                 //XXX what about ArgGSharedVtOnStack here?
2066                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2067                         if (!t->byref) {
2068                                 if (t->type == MONO_TYPE_R4)
2069                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2070                                 else if (t->type == MONO_TYPE_R8)
2071                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2072                                 else
2073                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2074                         } else {
2075                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2076                         }
2077                         if (cfg->compute_gc_maps) {
2078                                 MonoInst *def;
2079
2080                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2081                         }
2082                 }
2083         }
2084
2085         /*
2086          * Emit all parameters passed in registers in non-reverse order for better readability
2087          * and to help the optimization in emit_prolog ().
2088          */
2089         for (i = 0; i < n; ++i) {
2090                 ainfo = cinfo->args + i;
2091
2092                 in = call->args [i];
2093
2094                 if (ainfo->storage == ArgInIReg)
2095                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2096         }
2097
2098         for (i = n - 1; i >= 0; --i) {
2099                 MonoType *t;
2100
2101                 ainfo = cinfo->args + i;
2102
2103                 in = call->args [i];
2104
2105                 if (sig->hasthis && i == 0)
2106                         t = &mono_defaults.object_class->byval_arg;
2107                 else
2108                         t = sig->params [i - sig->hasthis];
2109                 t = mini_get_underlying_type (t);
2110
2111                 switch (ainfo->storage) {
2112                 case ArgInIReg:
2113                         /* Already done */
2114                         break;
2115                 case ArgInFloatSSEReg:
2116                 case ArgInDoubleSSEReg:
2117                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2118                         break;
2119                 case ArgOnStack:
2120                 case ArgValuetypeInReg:
2121                 case ArgValuetypeAddrInIReg:
2122                 case ArgValuetypeAddrOnStack:
2123                 case ArgGSharedVtInReg:
2124                 case ArgGSharedVtOnStack: {
2125                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2126                                 /* Already emitted above */
2127                                 break;
2128                         //FIXME what about ArgGSharedVtOnStack ?
2129                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2130                                 MonoInst *call_inst = (MonoInst*)call;
2131                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2132                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2133                                 break;
2134                         }
2135
2136                         guint32 align;
2137                         guint32 size;
2138
2139                         if (sig->pinvoke)
2140                                 size = mono_type_native_stack_size (t, &align);
2141                         else {
2142                                 /*
2143                                  * Other backends use mono_type_stack_size (), but that
2144                                  * aligns the size to 8, which is larger than the size of
2145                                  * the source, leading to reads of invalid memory if the
2146                                  * source is at the end of address space.
2147                                  */
2148                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2149                         }
2150
2151                         if (size >= 10000) {
2152                                 /* Avoid asserts in emit_memcpy () */
2153                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2154                                 /* Continue normally */
2155                         }
2156
2157                         if (size > 0 || ainfo->pass_empty_struct) {
2158                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2159                                 arg->sreg1 = in->dreg;
2160                                 arg->klass = mono_class_from_mono_type (t);
2161                                 arg->backend.size = size;
2162                                 arg->inst_p0 = call;
2163                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2164                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2165
2166                                 MONO_ADD_INS (cfg->cbb, arg);
2167                         }
2168                         break;
2169                 }
2170                 default:
2171                         g_assert_not_reached ();
2172                 }
2173
2174                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2175                         /* Emit the signature cookie just before the implicit arguments */
2176                         emit_sig_cookie (cfg, call, cinfo);
2177         }
2178
2179         /* Handle the case where there are no implicit arguments */
2180         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2181                 emit_sig_cookie (cfg, call, cinfo);
2182
2183         switch (cinfo->ret.storage) {
2184         case ArgValuetypeInReg:
2185                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2186                         /*
2187                          * Tell the JIT to use a more efficient calling convention: call using
2188                          * OP_CALL, compute the result location after the call, and save the
2189                          * result there.
2190                          */
2191                         call->vret_in_reg = TRUE;
2192                         /*
2193                          * Nullify the instruction computing the vret addr to enable
2194                          * future optimizations.
2195                          */
2196                         if (call->vret_var)
2197                                 NULLIFY_INS (call->vret_var);
2198                 } else {
2199                         if (call->tail_call)
2200                                 NOT_IMPLEMENTED;
2201                         /*
2202                          * The valuetype is in RAX:RDX after the call, need to be copied to
2203                          * the stack. Push the address here, so the call instruction can
2204                          * access it.
2205                          */
2206                         if (!cfg->arch.vret_addr_loc) {
2207                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2208                                 /* Prevent it from being register allocated or optimized away */
2209                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2210                         }
2211
2212                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2213                 }
2214                 break;
2215         case ArgValuetypeAddrInIReg:
2216         case ArgGsharedvtVariableInReg: {
2217                 MonoInst *vtarg;
2218                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2219                 vtarg->sreg1 = call->vret_var->dreg;
2220                 vtarg->dreg = mono_alloc_preg (cfg);
2221                 MONO_ADD_INS (cfg->cbb, vtarg);
2222
2223                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2224                 break;
2225         }
2226         default:
2227                 break;
2228         }
2229
2230         if (cfg->method->save_lmf) {
2231                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2232                 MONO_ADD_INS (cfg->cbb, arg);
2233         }
2234
2235         call->stack_usage = cinfo->stack_usage;
2236 }
2237
2238 void
2239 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2240 {
2241         MonoInst *arg;
2242         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2243         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2244         int size = ins->backend.size;
2245
2246         switch (ainfo->storage) {
2247         case ArgValuetypeInReg: {
2248                 MonoInst *load;
2249                 int part;
2250
2251                 for (part = 0; part < 2; ++part) {
2252                         if (ainfo->pair_storage [part] == ArgNone)
2253                                 continue;
2254
2255                         if (ainfo->pass_empty_struct) {
2256                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2257                                 NEW_ICONST (cfg, load, 0);
2258                         }
2259                         else {
2260                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2261                                 load->inst_basereg = src->dreg;
2262                                 load->inst_offset = part * sizeof(mgreg_t);
2263
2264                                 switch (ainfo->pair_storage [part]) {
2265                                 case ArgInIReg:
2266                                         load->dreg = mono_alloc_ireg (cfg);
2267                                         break;
2268                                 case ArgInDoubleSSEReg:
2269                                 case ArgInFloatSSEReg:
2270                                         load->dreg = mono_alloc_freg (cfg);
2271                                         break;
2272                                 default:
2273                                         g_assert_not_reached ();
2274                                 }
2275                         }
2276
2277                         MONO_ADD_INS (cfg->cbb, load);
2278
2279                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2280                 }
2281                 break;
2282         }
2283         case ArgValuetypeAddrInIReg:
2284         case ArgValuetypeAddrOnStack: {
2285                 MonoInst *vtaddr, *load;
2286
2287                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2288
2289                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2290
2291                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2292                 cfg->has_indirection = TRUE;
2293                 load->inst_p0 = vtaddr;
2294                 vtaddr->flags |= MONO_INST_INDIRECT;
2295                 load->type = STACK_MP;
2296                 load->klass = vtaddr->klass;
2297                 load->dreg = mono_alloc_ireg (cfg);
2298                 MONO_ADD_INS (cfg->cbb, load);
2299                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, SIZEOF_VOID_P);
2300
2301                 if (ainfo->pair_storage [0] == ArgInIReg) {
2302                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2303                         arg->dreg = mono_alloc_ireg (cfg);
2304                         arg->sreg1 = load->dreg;
2305                         arg->inst_imm = 0;
2306                         MONO_ADD_INS (cfg->cbb, arg);
2307                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2308                 } else {
2309                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2310                 }
2311                 break;
2312         }
2313         case ArgGSharedVtInReg:
2314                 /* Pass by addr */
2315                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2316                 break;
2317         case ArgGSharedVtOnStack:
2318                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2319                 break;
2320         default:
2321                 if (size == 8) {
2322                         int dreg = mono_alloc_ireg (cfg);
2323
2324                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2325                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2326                 } else if (size <= 40) {
2327                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2328                 } else {
2329                         // FIXME: Code growth
2330                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2331                 }
2332
2333                 if (cfg->compute_gc_maps) {
2334                         MonoInst *def;
2335                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2336                 }
2337         }
2338 }
2339
2340 void
2341 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2342 {
2343         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2344
2345         if (ret->type == MONO_TYPE_R4) {
2346                 if (COMPILE_LLVM (cfg))
2347                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2348                 else
2349                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2350                 return;
2351         } else if (ret->type == MONO_TYPE_R8) {
2352                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2353                 return;
2354         }
2355
2356         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2357 }
2358
2359 #endif /* DISABLE_JIT */
2360
2361 #define EMIT_COND_BRANCH(ins,cond,sign) \
2362         if (ins->inst_true_bb->native_offset) { \
2363                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2364         } else { \
2365                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2366                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2367             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2368                         x86_branch8 (code, cond, 0, sign); \
2369                 else \
2370                         x86_branch32 (code, cond, 0, sign); \
2371 }
2372
2373 typedef struct {
2374         MonoMethodSignature *sig;
2375         CallInfo *cinfo;
2376 } ArchDynCallInfo;
2377
2378 static gboolean
2379 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2380 {
2381         int i;
2382
2383         switch (cinfo->ret.storage) {
2384         case ArgNone:
2385         case ArgInIReg:
2386         case ArgInFloatSSEReg:
2387         case ArgInDoubleSSEReg:
2388         case ArgValuetypeAddrInIReg:
2389         case ArgValuetypeInReg:
2390                 break;
2391         default:
2392                 return FALSE;
2393         }
2394
2395         for (i = 0; i < cinfo->nargs; ++i) {
2396                 ArgInfo *ainfo = &cinfo->args [i];
2397                 switch (ainfo->storage) {
2398                 case ArgInIReg:
2399                 case ArgInFloatSSEReg:
2400                 case ArgInDoubleSSEReg:
2401                 case ArgValuetypeInReg:
2402                         break;
2403                 case ArgOnStack:
2404                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2405                                 return FALSE;
2406                         break;
2407                 default:
2408                         return FALSE;
2409                 }
2410         }
2411
2412         return TRUE;
2413 }
2414
2415 /*
2416  * mono_arch_dyn_call_prepare:
2417  *
2418  *   Return a pointer to an arch-specific structure which contains information
2419  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2420  * supported for SIG.
2421  * This function is equivalent to ffi_prep_cif in libffi.
2422  */
2423 MonoDynCallInfo*
2424 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2425 {
2426         ArchDynCallInfo *info;
2427         CallInfo *cinfo;
2428
2429         cinfo = get_call_info (NULL, sig);
2430
2431         if (!dyn_call_supported (sig, cinfo)) {
2432                 g_free (cinfo);
2433                 return NULL;
2434         }
2435
2436         info = g_new0 (ArchDynCallInfo, 1);
2437         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2438         info->sig = sig;
2439         info->cinfo = cinfo;
2440
2441         return (MonoDynCallInfo*)info;
2442 }
2443
2444 /*
2445  * mono_arch_dyn_call_free:
2446  *
2447  *   Free a MonoDynCallInfo structure.
2448  */
2449 void
2450 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2451 {
2452         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2453
2454         g_free (ainfo->cinfo);
2455         g_free (ainfo);
2456 }
2457
2458 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2459 #define GREG_TO_PTR(greg) (gpointer)(greg)
2460
2461 /*
2462  * mono_arch_get_start_dyn_call:
2463  *
2464  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2465  * store the result into BUF.
2466  * ARGS should be an array of pointers pointing to the arguments.
2467  * RET should point to a memory buffer large enought to hold the result of the
2468  * call.
2469  * This function should be as fast as possible, any work which does not depend
2470  * on the actual values of the arguments should be done in
2471  * mono_arch_dyn_call_prepare ().
2472  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2473  * libffi.
2474  */
2475 void
2476 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2477 {
2478         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2479         DynCallArgs *p = (DynCallArgs*)buf;
2480         int arg_index, greg, freg, i, pindex;
2481         MonoMethodSignature *sig = dinfo->sig;
2482         int buffer_offset = 0;
2483         static int param_reg_to_index [16];
2484         static gboolean param_reg_to_index_inited;
2485
2486         if (!param_reg_to_index_inited) {
2487                 for (i = 0; i < PARAM_REGS; ++i)
2488                         param_reg_to_index [param_regs [i]] = i;
2489                 mono_memory_barrier ();
2490                 param_reg_to_index_inited = 1;
2491         }
2492
2493         g_assert (buf_len >= sizeof (DynCallArgs));
2494
2495         p->res = 0;
2496         p->ret = ret;
2497
2498         arg_index = 0;
2499         greg = 0;
2500         freg = 0;
2501         pindex = 0;
2502
2503         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2504                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2505                 if (!sig->hasthis)
2506                         pindex = 1;
2507         }
2508
2509         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2510                 p->regs [greg ++] = PTR_TO_GREG(ret);
2511
2512         for (; pindex < sig->param_count; pindex++) {
2513                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2514                 gpointer *arg = args [arg_index ++];
2515                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2516                 int slot;
2517
2518                 if (ainfo->storage == ArgOnStack) {
2519                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2520                 } else {
2521                         slot = param_reg_to_index [ainfo->reg];
2522                 }
2523
2524                 if (t->byref) {
2525                         p->regs [slot] = PTR_TO_GREG(*(arg));
2526                         greg ++;
2527                         continue;
2528                 }
2529
2530                 switch (t->type) {
2531                 case MONO_TYPE_OBJECT:
2532                 case MONO_TYPE_PTR:
2533                 case MONO_TYPE_I:
2534                 case MONO_TYPE_U:
2535 #if !defined(__mono_ilp32__)
2536                 case MONO_TYPE_I8:
2537                 case MONO_TYPE_U8:
2538 #endif
2539                         p->regs [slot] = PTR_TO_GREG(*(arg));
2540                         break;
2541 #if defined(__mono_ilp32__)
2542                 case MONO_TYPE_I8:
2543                 case MONO_TYPE_U8:
2544                         p->regs [slot] = *(guint64*)(arg);
2545                         break;
2546 #endif
2547                 case MONO_TYPE_U1:
2548                         p->regs [slot] = *(guint8*)(arg);
2549                         break;
2550                 case MONO_TYPE_I1:
2551                         p->regs [slot] = *(gint8*)(arg);
2552                         break;
2553                 case MONO_TYPE_I2:
2554                         p->regs [slot] = *(gint16*)(arg);
2555                         break;
2556                 case MONO_TYPE_U2:
2557                         p->regs [slot] = *(guint16*)(arg);
2558                         break;
2559                 case MONO_TYPE_I4:
2560                         p->regs [slot] = *(gint32*)(arg);
2561                         break;
2562                 case MONO_TYPE_U4:
2563                         p->regs [slot] = *(guint32*)(arg);
2564                         break;
2565                 case MONO_TYPE_R4: {
2566                         double d;
2567
2568                         *(float*)&d = *(float*)(arg);
2569                         p->has_fp = 1;
2570                         p->fregs [freg ++] = d;
2571                         break;
2572                 }
2573                 case MONO_TYPE_R8:
2574                         p->has_fp = 1;
2575                         p->fregs [freg ++] = *(double*)(arg);
2576                         break;
2577                 case MONO_TYPE_GENERICINST:
2578                     if (MONO_TYPE_IS_REFERENCE (t)) {
2579                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2580                                 break;
2581                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2582                                         MonoClass *klass = mono_class_from_mono_type (t);
2583                                         guint8 *nullable_buf;
2584                                         int size;
2585
2586                                         size = mono_class_value_size (klass, NULL);
2587                                         nullable_buf = p->buffer + buffer_offset;
2588                                         buffer_offset += size;
2589                                         g_assert (buffer_offset <= 256);
2590
2591                                         /* The argument pointed to by arg is either a boxed vtype or null */
2592                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2593
2594                                         arg = (gpointer*)nullable_buf;
2595                                         /* Fall though */
2596
2597                         } else {
2598                                 /* Fall through */
2599                         }
2600                 case MONO_TYPE_VALUETYPE: {
2601                         switch (ainfo->storage) {
2602                         case ArgValuetypeInReg:
2603                                 for (i = 0; i < 2; ++i) {
2604                                         switch (ainfo->pair_storage [i]) {
2605                                         case ArgNone:
2606                                                 break;
2607                                         case ArgInIReg:
2608                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2609                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2610                                                 break;
2611                                         case ArgInDoubleSSEReg:
2612                                                 p->has_fp = 1;
2613                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2614                                                 break;
2615                                         default:
2616                                                 g_assert_not_reached ();
2617                                                 break;
2618                                         }
2619                                 }
2620                                 break;
2621                         case ArgOnStack:
2622                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2623                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2624                                 break;
2625                         default:
2626                                 g_assert_not_reached ();
2627                                 break;
2628                         }
2629                         break;
2630                 }
2631                 default:
2632                         g_assert_not_reached ();
2633                 }
2634         }
2635 }
2636
2637 /*
2638  * mono_arch_finish_dyn_call:
2639  *
2640  *   Store the result of a dyn call into the return value buffer passed to
2641  * start_dyn_call ().
2642  * This function should be as fast as possible, any work which does not depend
2643  * on the actual values of the arguments should be done in
2644  * mono_arch_dyn_call_prepare ().
2645  */
2646 void
2647 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2648 {
2649         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2650         MonoMethodSignature *sig = dinfo->sig;
2651         DynCallArgs *dargs = (DynCallArgs*)buf;
2652         guint8 *ret = dargs->ret;
2653         mgreg_t res = dargs->res;
2654         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2655         int i;
2656
2657         switch (sig_ret->type) {
2658         case MONO_TYPE_VOID:
2659                 *(gpointer*)ret = NULL;
2660                 break;
2661         case MONO_TYPE_OBJECT:
2662         case MONO_TYPE_I:
2663         case MONO_TYPE_U:
2664         case MONO_TYPE_PTR:
2665                 *(gpointer*)ret = GREG_TO_PTR(res);
2666                 break;
2667         case MONO_TYPE_I1:
2668                 *(gint8*)ret = res;
2669                 break;
2670         case MONO_TYPE_U1:
2671                 *(guint8*)ret = res;
2672                 break;
2673         case MONO_TYPE_I2:
2674                 *(gint16*)ret = res;
2675                 break;
2676         case MONO_TYPE_U2:
2677                 *(guint16*)ret = res;
2678                 break;
2679         case MONO_TYPE_I4:
2680                 *(gint32*)ret = res;
2681                 break;
2682         case MONO_TYPE_U4:
2683                 *(guint32*)ret = res;
2684                 break;
2685         case MONO_TYPE_I8:
2686                 *(gint64*)ret = res;
2687                 break;
2688         case MONO_TYPE_U8:
2689                 *(guint64*)ret = res;
2690                 break;
2691         case MONO_TYPE_R4:
2692                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2693                 break;
2694         case MONO_TYPE_R8:
2695                 *(double*)ret = dargs->fregs [0];
2696                 break;
2697         case MONO_TYPE_GENERICINST:
2698                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2699                         *(gpointer*)ret = GREG_TO_PTR(res);
2700                         break;
2701                 } else {
2702                         /* Fall through */
2703                 }
2704         case MONO_TYPE_VALUETYPE:
2705                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2706                         /* Nothing to do */
2707                 } else {
2708                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2709
2710                         g_assert (ainfo->storage == ArgValuetypeInReg);
2711
2712                         for (i = 0; i < 2; ++i) {
2713                                 switch (ainfo->pair_storage [0]) {
2714                                 case ArgInIReg:
2715                                         ((mgreg_t*)ret)[i] = res;
2716                                         break;
2717                                 case ArgInDoubleSSEReg:
2718                                         ((double*)ret)[i] = dargs->fregs [i];
2719                                         break;
2720                                 case ArgNone:
2721                                         break;
2722                                 default:
2723                                         g_assert_not_reached ();
2724                                         break;
2725                                 }
2726                         }
2727                 }
2728                 break;
2729         default:
2730                 g_assert_not_reached ();
2731         }
2732 }
2733
2734 /* emit an exception if condition is fail */
2735 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2736         do {                                                        \
2737                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2738                 if (tins == NULL) {                                                                             \
2739                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2740                                         MONO_PATCH_INFO_EXC, exc_name);  \
2741                         x86_branch32 (code, cond, 0, signed);               \
2742                 } else {        \
2743                         EMIT_COND_BRANCH (tins, cond, signed);  \
2744                 }                       \
2745         } while (0);
2746
2747 #define EMIT_FPCOMPARE(code) do { \
2748         amd64_fcompp (code); \
2749         amd64_fnstsw (code); \
2750 } while (0);
2751
2752 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2753     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2754         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2755         amd64_ ##op (code); \
2756         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2757         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2758 } while (0);
2759
2760 static guint8*
2761 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2762 {
2763         gboolean no_patch = FALSE;
2764
2765         /*
2766          * FIXME: Add support for thunks
2767          */
2768         {
2769                 gboolean near_call = FALSE;
2770
2771                 /*
2772                  * Indirect calls are expensive so try to make a near call if possible.
2773                  * The caller memory is allocated by the code manager so it is
2774                  * guaranteed to be at a 32 bit offset.
2775                  */
2776
2777                 if (patch_type != MONO_PATCH_INFO_ABS) {
2778                         /* The target is in memory allocated using the code manager */
2779                         near_call = TRUE;
2780
2781                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2782                                 if (((MonoMethod*)data)->klass->image->aot_module)
2783                                         /* The callee might be an AOT method */
2784                                         near_call = FALSE;
2785                                 if (((MonoMethod*)data)->dynamic)
2786                                         /* The target is in malloc-ed memory */
2787                                         near_call = FALSE;
2788                         }
2789
2790                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2791                                 /*
2792                                  * The call might go directly to a native function without
2793                                  * the wrapper.
2794                                  */
2795                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2796                                 if (mi) {
2797                                         gconstpointer target = mono_icall_get_wrapper (mi);
2798                                         if ((((guint64)target) >> 32) != 0)
2799                                                 near_call = FALSE;
2800                                 }
2801                         }
2802                 }
2803                 else {
2804                         MonoJumpInfo *jinfo = NULL;
2805
2806                         if (cfg->abs_patches)
2807                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2808                         if (jinfo) {
2809                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2810                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2811                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2812                                                 near_call = TRUE;
2813                                         no_patch = TRUE;
2814                                 } else {
2815                                         /*
2816                                          * This is not really an optimization, but required because the
2817                                          * generic class init trampolines use R11 to pass the vtable.
2818                                          */
2819                                         near_call = TRUE;
2820                                 }
2821                         } else {
2822                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2823                                 if (info) {
2824                                         if (info->func == info->wrapper) {
2825                                                 /* No wrapper */
2826                                                 if ((((guint64)info->func) >> 32) == 0)
2827                                                         near_call = TRUE;
2828                                         }
2829                                         else {
2830                                                 /* See the comment in mono_codegen () */
2831                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2832                                                         near_call = TRUE;
2833                                         }
2834                                 }
2835                                 else if ((((guint64)data) >> 32) == 0) {
2836                                         near_call = TRUE;
2837                                         no_patch = TRUE;
2838                                 }
2839                         }
2840                 }
2841
2842                 if (cfg->method->dynamic)
2843                         /* These methods are allocated using malloc */
2844                         near_call = FALSE;
2845
2846 #ifdef MONO_ARCH_NOMAP32BIT
2847                 near_call = FALSE;
2848 #endif
2849                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2850                 if (optimize_for_xen)
2851                         near_call = FALSE;
2852
2853                 if (cfg->compile_aot) {
2854                         near_call = TRUE;
2855                         no_patch = TRUE;
2856                 }
2857
2858                 if (near_call) {
2859                         /*
2860                          * Align the call displacement to an address divisible by 4 so it does
2861                          * not span cache lines. This is required for code patching to work on SMP
2862                          * systems.
2863                          */
2864                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2865                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2866                                 amd64_padding (code, pad_size);
2867                         }
2868                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2869                         amd64_call_code (code, 0);
2870                 }
2871                 else {
2872                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2873                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2874                         amd64_call_reg (code, GP_SCRATCH_REG);
2875                 }
2876         }
2877
2878         return code;
2879 }
2880
2881 static inline guint8*
2882 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2883 {
2884 #ifdef TARGET_WIN32
2885         if (win64_adjust_stack)
2886                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2887 #endif
2888         code = emit_call_body (cfg, code, patch_type, data);
2889 #ifdef TARGET_WIN32
2890         if (win64_adjust_stack)
2891                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2892 #endif
2893
2894         return code;
2895 }
2896
2897 static inline int
2898 store_membase_imm_to_store_membase_reg (int opcode)
2899 {
2900         switch (opcode) {
2901         case OP_STORE_MEMBASE_IMM:
2902                 return OP_STORE_MEMBASE_REG;
2903         case OP_STOREI4_MEMBASE_IMM:
2904                 return OP_STOREI4_MEMBASE_REG;
2905         case OP_STOREI8_MEMBASE_IMM:
2906                 return OP_STOREI8_MEMBASE_REG;
2907         }
2908
2909         return -1;
2910 }
2911
2912 #ifndef DISABLE_JIT
2913
2914 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2915
2916 /*
2917  * mono_arch_peephole_pass_1:
2918  *
2919  *   Perform peephole opts which should/can be performed before local regalloc
2920  */
2921 void
2922 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2923 {
2924         MonoInst *ins, *n;
2925
2926         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2927                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2928
2929                 switch (ins->opcode) {
2930                 case OP_ADD_IMM:
2931                 case OP_IADD_IMM:
2932                 case OP_LADD_IMM:
2933                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2934                                 /*
2935                                  * X86_LEA is like ADD, but doesn't have the
2936                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2937                                  * its operand to 64 bit.
2938                                  */
2939                                 ins->opcode = OP_X86_LEA_MEMBASE;
2940                                 ins->inst_basereg = ins->sreg1;
2941                         }
2942                         break;
2943                 case OP_LXOR:
2944                 case OP_IXOR:
2945                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2946                                 MonoInst *ins2;
2947
2948                                 /*
2949                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2950                                  * the latter has length 2-3 instead of 6 (reverse constant
2951                                  * propagation). These instruction sequences are very common
2952                                  * in the initlocals bblock.
2953                                  */
2954                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2955                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2956                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2957                                                 ins2->sreg1 = ins->dreg;
2958                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2959                                                 /* Continue */
2960                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2961                                                 NULLIFY_INS (ins2);
2962                                                 /* Continue */
2963                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2964                                                 /* Continue */
2965                                         } else {
2966                                                 break;
2967                                         }
2968                                 }
2969                         }
2970                         break;
2971                 case OP_COMPARE_IMM:
2972                 case OP_LCOMPARE_IMM:
2973                         /* OP_COMPARE_IMM (reg, 0)
2974                          * -->
2975                          * OP_AMD64_TEST_NULL (reg)
2976                          */
2977                         if (!ins->inst_imm)
2978                                 ins->opcode = OP_AMD64_TEST_NULL;
2979                         break;
2980                 case OP_ICOMPARE_IMM:
2981                         if (!ins->inst_imm)
2982                                 ins->opcode = OP_X86_TEST_NULL;
2983                         break;
2984                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2985                         /*
2986                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2987                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2988                          * -->
2989                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2990                          * OP_COMPARE_IMM reg, imm
2991                          *
2992                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2993                          */
2994                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2995                             ins->inst_basereg == last_ins->inst_destbasereg &&
2996                             ins->inst_offset == last_ins->inst_offset) {
2997                                         ins->opcode = OP_ICOMPARE_IMM;
2998                                         ins->sreg1 = last_ins->sreg1;
2999
3000                                         /* check if we can remove cmp reg,0 with test null */
3001                                         if (!ins->inst_imm)
3002                                                 ins->opcode = OP_X86_TEST_NULL;
3003                                 }
3004
3005                         break;
3006                 }
3007
3008                 mono_peephole_ins (bb, ins);
3009         }
3010 }
3011
3012 void
3013 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3014 {
3015         MonoInst *ins, *n;
3016
3017         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3018                 switch (ins->opcode) {
3019                 case OP_ICONST:
3020                 case OP_I8CONST: {
3021                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3022                         /* reg = 0 -> XOR (reg, reg) */
3023                         /* XOR sets cflags on x86, so we cant do it always */
3024                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3025                                 ins->opcode = OP_LXOR;
3026                                 ins->sreg1 = ins->dreg;
3027                                 ins->sreg2 = ins->dreg;
3028                                 /* Fall through */
3029                         } else {
3030                                 break;
3031                         }
3032                 }
3033                 case OP_LXOR:
3034                         /*
3035                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3036                          * 0 result into 64 bits.
3037                          */
3038                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3039                                 ins->opcode = OP_IXOR;
3040                         }
3041                         /* Fall through */
3042                 case OP_IXOR:
3043                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3044                                 MonoInst *ins2;
3045
3046                                 /*
3047                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3048                                  * the latter has length 2-3 instead of 6 (reverse constant
3049                                  * propagation). These instruction sequences are very common
3050                                  * in the initlocals bblock.
3051                                  */
3052                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3053                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3054                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3055                                                 ins2->sreg1 = ins->dreg;
3056                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3057                                                 /* Continue */
3058                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3059                                                 NULLIFY_INS (ins2);
3060                                                 /* Continue */
3061                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3062                                                 /* Continue */
3063                                         } else {
3064                                                 break;
3065                                         }
3066                                 }
3067                         }
3068                         break;
3069                 case OP_IADD_IMM:
3070                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3071                                 ins->opcode = OP_X86_INC_REG;
3072                         break;
3073                 case OP_ISUB_IMM:
3074                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3075                                 ins->opcode = OP_X86_DEC_REG;
3076                         break;
3077                 }
3078
3079                 mono_peephole_ins (bb, ins);
3080         }
3081 }
3082
3083 #define NEW_INS(cfg,ins,dest,op) do {   \
3084                 MONO_INST_NEW ((cfg), (dest), (op)); \
3085         (dest)->cil_code = (ins)->cil_code; \
3086         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3087         } while (0)
3088
3089 /*
3090  * mono_arch_lowering_pass:
3091  *
3092  *  Converts complex opcodes into simpler ones so that each IR instruction
3093  * corresponds to one machine instruction.
3094  */
3095 void
3096 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3097 {
3098         MonoInst *ins, *n, *temp;
3099
3100         /*
3101          * FIXME: Need to add more instructions, but the current machine
3102          * description can't model some parts of the composite instructions like
3103          * cdq.
3104          */
3105         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3106                 switch (ins->opcode) {
3107                 case OP_DIV_IMM:
3108                 case OP_REM_IMM:
3109                 case OP_IDIV_IMM:
3110                 case OP_IDIV_UN_IMM:
3111                 case OP_IREM_UN_IMM:
3112                 case OP_LREM_IMM:
3113                 case OP_IREM_IMM:
3114                         mono_decompose_op_imm (cfg, bb, ins);
3115                         break;
3116                 case OP_COMPARE_IMM:
3117                 case OP_LCOMPARE_IMM:
3118                         if (!amd64_use_imm32 (ins->inst_imm)) {
3119                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3120                                 temp->inst_c0 = ins->inst_imm;
3121                                 temp->dreg = mono_alloc_ireg (cfg);
3122                                 ins->opcode = OP_COMPARE;
3123                                 ins->sreg2 = temp->dreg;
3124                         }
3125                         break;
3126 #ifndef __mono_ilp32__
3127                 case OP_LOAD_MEMBASE:
3128 #endif
3129                 case OP_LOADI8_MEMBASE:
3130                 /*  Don't generate memindex opcodes (to simplify */
3131                 /*  read sandboxing) */
3132                         if (!amd64_use_imm32 (ins->inst_offset)) {
3133                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3134                                 temp->inst_c0 = ins->inst_offset;
3135                                 temp->dreg = mono_alloc_ireg (cfg);
3136                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3137                                 ins->inst_indexreg = temp->dreg;
3138                         }
3139                         break;
3140 #ifndef __mono_ilp32__
3141                 case OP_STORE_MEMBASE_IMM:
3142 #endif
3143                 case OP_STOREI8_MEMBASE_IMM:
3144                         if (!amd64_use_imm32 (ins->inst_imm)) {
3145                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3146                                 temp->inst_c0 = ins->inst_imm;
3147                                 temp->dreg = mono_alloc_ireg (cfg);
3148                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3149                                 ins->sreg1 = temp->dreg;
3150                         }
3151                         break;
3152 #ifdef MONO_ARCH_SIMD_INTRINSICS
3153                 case OP_EXPAND_I1: {
3154                                 int temp_reg1 = mono_alloc_ireg (cfg);
3155                                 int temp_reg2 = mono_alloc_ireg (cfg);
3156                                 int original_reg = ins->sreg1;
3157
3158                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3159                                 temp->sreg1 = original_reg;
3160                                 temp->dreg = temp_reg1;
3161
3162                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3163                                 temp->sreg1 = temp_reg1;
3164                                 temp->dreg = temp_reg2;
3165                                 temp->inst_imm = 8;
3166
3167                                 NEW_INS (cfg, ins, temp, OP_LOR);
3168                                 temp->sreg1 = temp->dreg = temp_reg2;
3169                                 temp->sreg2 = temp_reg1;
3170
3171                                 ins->opcode = OP_EXPAND_I2;
3172                                 ins->sreg1 = temp_reg2;
3173                         }
3174                         break;
3175 #endif
3176                 default:
3177                         break;
3178                 }
3179         }
3180
3181         bb->max_vreg = cfg->next_vreg;
3182 }
3183
3184 static const int
3185 branch_cc_table [] = {
3186         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3187         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3188         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3189 };
3190
3191 /* Maps CMP_... constants to X86_CC_... constants */
3192 static const int
3193 cc_table [] = {
3194         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3195         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3196 };
3197
3198 static const int
3199 cc_signed_table [] = {
3200         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3201         FALSE, FALSE, FALSE, FALSE
3202 };
3203
3204 /*#include "cprop.c"*/
3205
3206 static unsigned char*
3207 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3208 {
3209         if (size == 8)
3210                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3211         else
3212                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3213
3214         if (size == 1)
3215                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3216         else if (size == 2)
3217                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3218         return code;
3219 }
3220
3221 static unsigned char*
3222 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3223 {
3224         int sreg = tree->sreg1;
3225         int need_touch = FALSE;
3226
3227 #if defined(TARGET_WIN32)
3228         need_touch = TRUE;
3229 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3230         if (!(tree->flags & MONO_INST_INIT))
3231                 need_touch = TRUE;
3232 #endif
3233
3234         if (need_touch) {
3235                 guint8* br[5];
3236
3237                 /*
3238                  * Under Windows:
3239                  * If requested stack size is larger than one page,
3240                  * perform stack-touch operation
3241                  */
3242                 /*
3243                  * Generate stack probe code.
3244                  * Under Windows, it is necessary to allocate one page at a time,
3245                  * "touching" stack after each successful sub-allocation. This is
3246                  * because of the way stack growth is implemented - there is a
3247                  * guard page before the lowest stack page that is currently commited.
3248                  * Stack normally grows sequentially so OS traps access to the
3249                  * guard page and commits more pages when needed.
3250                  */
3251                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3252                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3253
3254                 br[2] = code; /* loop */
3255                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3256                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3257                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3258                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3259                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3260                 amd64_patch (br[3], br[2]);
3261                 amd64_test_reg_reg (code, sreg, sreg);
3262                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3263                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3264
3265                 br[1] = code; x86_jump8 (code, 0);
3266
3267                 amd64_patch (br[0], code);
3268                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3269                 amd64_patch (br[1], code);
3270                 amd64_patch (br[4], code);
3271         }
3272         else
3273                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3274
3275         if (tree->flags & MONO_INST_INIT) {
3276                 int offset = 0;
3277                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3278                         amd64_push_reg (code, AMD64_RAX);
3279                         offset += 8;
3280                 }
3281                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3282                         amd64_push_reg (code, AMD64_RCX);
3283                         offset += 8;
3284                 }
3285                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3286                         amd64_push_reg (code, AMD64_RDI);
3287                         offset += 8;
3288                 }
3289
3290                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3291                 if (sreg != AMD64_RCX)
3292                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3293                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3294
3295                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3296                 if (cfg->param_area)
3297                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3298                 amd64_cld (code);
3299                 amd64_prefix (code, X86_REP_PREFIX);
3300                 amd64_stosl (code);
3301
3302                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3303                         amd64_pop_reg (code, AMD64_RDI);
3304                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3305                         amd64_pop_reg (code, AMD64_RCX);
3306                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3307                         amd64_pop_reg (code, AMD64_RAX);
3308         }
3309         return code;
3310 }
3311
3312 static guint8*
3313 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3314 {
3315         CallInfo *cinfo;
3316         guint32 quad;
3317
3318         /* Move return value to the target register */
3319         /* FIXME: do this in the local reg allocator */
3320         switch (ins->opcode) {
3321         case OP_CALL:
3322         case OP_CALL_REG:
3323         case OP_CALL_MEMBASE:
3324         case OP_LCALL:
3325         case OP_LCALL_REG:
3326         case OP_LCALL_MEMBASE:
3327                 g_assert (ins->dreg == AMD64_RAX);
3328                 break;
3329         case OP_FCALL:
3330         case OP_FCALL_REG:
3331         case OP_FCALL_MEMBASE: {
3332                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3333                 if (rtype->type == MONO_TYPE_R4) {
3334                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3335                 }
3336                 else {
3337                         if (ins->dreg != AMD64_XMM0)
3338                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3339                 }
3340                 break;
3341         }
3342         case OP_RCALL:
3343         case OP_RCALL_REG:
3344         case OP_RCALL_MEMBASE:
3345                 if (ins->dreg != AMD64_XMM0)
3346                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3347                 break;
3348         case OP_VCALL:
3349         case OP_VCALL_REG:
3350         case OP_VCALL_MEMBASE:
3351         case OP_VCALL2:
3352         case OP_VCALL2_REG:
3353         case OP_VCALL2_MEMBASE:
3354                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3355                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3356                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3357
3358                         /* Load the destination address */
3359                         g_assert (loc->opcode == OP_REGOFFSET);
3360                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3361
3362                         for (quad = 0; quad < 2; quad ++) {
3363                                 switch (cinfo->ret.pair_storage [quad]) {
3364                                 case ArgInIReg:
3365                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3366                                         break;
3367                                 case ArgInFloatSSEReg:
3368                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3369                                         break;
3370                                 case ArgInDoubleSSEReg:
3371                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3372                                         break;
3373                                 case ArgNone:
3374                                         break;
3375                                 default:
3376                                         NOT_IMPLEMENTED;
3377                                 }
3378                         }
3379                 }
3380                 break;
3381         }
3382
3383         return code;
3384 }
3385
3386 #endif /* DISABLE_JIT */
3387
3388 #ifdef TARGET_MACH
3389 static int tls_gs_offset;
3390 #endif
3391
3392 gboolean
3393 mono_arch_have_fast_tls (void)
3394 {
3395 #ifdef TARGET_MACH
3396         static gboolean have_fast_tls = FALSE;
3397         static gboolean inited = FALSE;
3398         guint8 *ins;
3399
3400         if (mini_get_debug_options ()->use_fallback_tls)
3401                 return FALSE;
3402
3403         if (inited)
3404                 return have_fast_tls;
3405
3406         ins = (guint8*)pthread_getspecific;
3407
3408         /*
3409          * We're looking for these two instructions:
3410          *
3411          * mov    %gs:[offset](,%rdi,8),%rax
3412          * retq
3413          */
3414         have_fast_tls = ins [0] == 0x65 &&
3415                        ins [1] == 0x48 &&
3416                        ins [2] == 0x8b &&
3417                        ins [3] == 0x04 &&
3418                        ins [4] == 0xfd &&
3419                        ins [6] == 0x00 &&
3420                        ins [7] == 0x00 &&
3421                        ins [8] == 0x00 &&
3422                        ins [9] == 0xc3;
3423
3424         tls_gs_offset = ins[5];
3425
3426         /*
3427          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3428          * For that version we're looking for these instructions:
3429          *
3430          * pushq  %rbp
3431          * movq   %rsp, %rbp
3432          * mov    %gs:[offset](,%rdi,8),%rax
3433          * popq   %rbp
3434          * retq
3435          */
3436         if (!have_fast_tls) {
3437                 have_fast_tls = ins [0] == 0x55 &&
3438                                ins [1] == 0x48 &&
3439                                ins [2] == 0x89 &&
3440                                ins [3] == 0xe5 &&
3441                                ins [4] == 0x65 &&
3442                                ins [5] == 0x48 &&
3443                                ins [6] == 0x8b &&
3444                                ins [7] == 0x04 &&
3445                                ins [8] == 0xfd &&
3446                                ins [10] == 0x00 &&
3447                                ins [11] == 0x00 &&
3448                                ins [12] == 0x00 &&
3449                                ins [13] == 0x5d &&
3450                                ins [14] == 0xc3;
3451
3452                 tls_gs_offset = ins[9];
3453         }
3454         inited = TRUE;
3455
3456         return have_fast_tls;
3457 #elif defined(TARGET_ANDROID)
3458         return FALSE;
3459 #else
3460         if (mini_get_debug_options ()->use_fallback_tls)
3461                 return FALSE;
3462         return TRUE;
3463 #endif
3464 }
3465
3466 int
3467 mono_amd64_get_tls_gs_offset (void)
3468 {
3469 #ifdef TARGET_OSX
3470         return tls_gs_offset;
3471 #else
3472         g_assert_not_reached ();
3473         return -1;
3474 #endif
3475 }
3476
3477 /*
3478  * \param code buffer to store code to
3479  * \param dreg hard register where to place the result
3480  * \param tls_offset offset info
3481  * \return a pointer to the end of the stored code
3482  *
3483  * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3484  * the dreg register the item in the thread local storage identified
3485  * by tls_offset.
3486  */
3487 static guint8*
3488 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3489 {
3490 #ifdef TARGET_WIN32
3491         if (tls_offset < 64) {
3492                 x86_prefix (code, X86_GS_PREFIX);
3493                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3494         } else {
3495                 guint8 *buf [16];
3496
3497                 g_assert (tls_offset < 0x440);
3498                 /* Load TEB->TlsExpansionSlots */
3499                 x86_prefix (code, X86_GS_PREFIX);
3500                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3501                 amd64_test_reg_reg (code, dreg, dreg);
3502                 buf [0] = code;
3503                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3504                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3505                 amd64_patch (buf [0], code);
3506         }
3507 #elif defined(TARGET_MACH)
3508         x86_prefix (code, X86_GS_PREFIX);
3509         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3510 #else
3511         if (optimize_for_xen) {
3512                 x86_prefix (code, X86_FS_PREFIX);
3513                 amd64_mov_reg_mem (code, dreg, 0, 8);
3514                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3515         } else {
3516                 x86_prefix (code, X86_FS_PREFIX);
3517                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3518         }
3519 #endif
3520         return code;
3521 }
3522
3523 static guint8*
3524 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3525 {
3526 #ifdef TARGET_WIN32
3527         g_assert_not_reached ();
3528 #elif defined(TARGET_MACH)
3529         x86_prefix (code, X86_GS_PREFIX);
3530         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3531 #else
3532         g_assert (!optimize_for_xen);
3533         x86_prefix (code, X86_FS_PREFIX);
3534         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3535 #endif
3536         return code;
3537 }
3538
3539 /*
3540  * emit_setup_lmf:
3541  *
3542  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3543  */
3544 static guint8*
3545 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3546 {
3547         /*
3548          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3549          */
3550         /*
3551          * sp is saved right before calls but we need to save it here too so
3552          * async stack walks would work.
3553          */
3554         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3555         /* Save rbp */
3556         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3557         if (cfg->arch.omit_fp && cfa_offset != -1)
3558                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3559
3560         /* These can't contain refs */
3561         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3562         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3563         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3564         /* These are handled automatically by the stack marking code */
3565         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3566
3567         return code;
3568 }
3569
3570 #ifdef TARGET_WIN32
3571
3572 #define TEB_LAST_ERROR_OFFSET 0x068
3573
3574 static guint8*
3575 emit_get_last_error (guint8* code, int dreg)
3576 {
3577         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3578         x86_prefix (code, X86_GS_PREFIX);
3579         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3580
3581         return code;
3582 }
3583
3584 #else
3585
3586 static guint8*
3587 emit_get_last_error (guint8* code, int dreg)
3588 {
3589         g_assert_not_reached ();
3590 }
3591
3592 #endif
3593
3594 /* benchmark and set based on cpu */
3595 #define LOOP_ALIGNMENT 8
3596 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3597
3598 #ifndef DISABLE_JIT
3599 void
3600 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3601 {
3602         MonoInst *ins;
3603         MonoCallInst *call;
3604         guint offset;
3605         guint8 *code = cfg->native_code + cfg->code_len;
3606         int max_len;
3607
3608         /* Fix max_offset estimate for each successor bb */
3609         if (cfg->opt & MONO_OPT_BRANCH) {
3610                 int current_offset = cfg->code_len;
3611                 MonoBasicBlock *current_bb;
3612                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3613                         current_bb->max_offset = current_offset;
3614                         current_offset += current_bb->max_length;
3615                 }
3616         }
3617
3618         if (cfg->opt & MONO_OPT_LOOP) {
3619                 int pad, align = LOOP_ALIGNMENT;
3620                 /* set alignment depending on cpu */
3621                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3622                         pad = align - pad;
3623                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3624                         amd64_padding (code, pad);
3625                         cfg->code_len += pad;
3626                         bb->native_offset = cfg->code_len;
3627                 }
3628         }
3629
3630         if (cfg->verbose_level > 2)
3631                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3632
3633         offset = code - cfg->native_code;
3634
3635         mono_debug_open_block (cfg, bb, offset);
3636
3637     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3638                 x86_breakpoint (code);
3639
3640         MONO_BB_FOR_EACH_INS (bb, ins) {
3641                 offset = code - cfg->native_code;
3642
3643                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3644
3645 #define EXTRA_CODE_SPACE (16)
3646
3647                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3648                         cfg->code_size *= 2;
3649                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3650                         code = cfg->native_code + offset;
3651                         cfg->stat_code_reallocs++;
3652                 }
3653
3654                 if (cfg->debug_info)
3655                         mono_debug_record_line_number (cfg, ins, offset);
3656
3657                 switch (ins->opcode) {
3658                 case OP_BIGMUL:
3659                         amd64_mul_reg (code, ins->sreg2, TRUE);
3660                         break;
3661                 case OP_BIGMUL_UN:
3662                         amd64_mul_reg (code, ins->sreg2, FALSE);
3663                         break;
3664                 case OP_X86_SETEQ_MEMBASE:
3665                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3666                         break;
3667                 case OP_STOREI1_MEMBASE_IMM:
3668                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3669                         break;
3670                 case OP_STOREI2_MEMBASE_IMM:
3671                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3672                         break;
3673                 case OP_STOREI4_MEMBASE_IMM:
3674                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3675                         break;
3676                 case OP_STOREI1_MEMBASE_REG:
3677                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3678                         break;
3679                 case OP_STOREI2_MEMBASE_REG:
3680                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3681                         break;
3682                 /* In AMD64 NaCl, pointers are 4 bytes, */
3683                 /*  so STORE_* != STOREI8_*. Likewise below. */
3684                 case OP_STORE_MEMBASE_REG:
3685                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3686                         break;
3687                 case OP_STOREI8_MEMBASE_REG:
3688                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3689                         break;
3690                 case OP_STOREI4_MEMBASE_REG:
3691                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3692                         break;
3693                 case OP_STORE_MEMBASE_IMM:
3694                         /* In NaCl, this could be a PCONST type, which could */
3695                         /* mean a pointer type was copied directly into the  */
3696                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3697                         /* the value would be 0x00000000FFFFFFFF which is    */
3698                         /* not proper for an imm32 unless you cast it.       */
3699                         g_assert (amd64_is_imm32 (ins->inst_imm));
3700                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3701                         break;
3702                 case OP_STOREI8_MEMBASE_IMM:
3703                         g_assert (amd64_is_imm32 (ins->inst_imm));
3704                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3705                         break;
3706                 case OP_LOAD_MEM:
3707 #ifdef __mono_ilp32__
3708                         /* In ILP32, pointers are 4 bytes, so separate these */
3709                         /* cases, use literal 8 below where we really want 8 */
3710                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3711                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3712                         break;
3713 #endif
3714                 case OP_LOADI8_MEM:
3715                         // FIXME: Decompose this earlier
3716                         if (amd64_use_imm32 (ins->inst_imm))
3717                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3718                         else {
3719                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3720                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3721                         }
3722                         break;
3723                 case OP_LOADI4_MEM:
3724                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3725                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3726                         break;
3727                 case OP_LOADU4_MEM:
3728                         // FIXME: Decompose this earlier
3729                         if (amd64_use_imm32 (ins->inst_imm))
3730                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3731                         else {
3732                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3733                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3734                         }
3735                         break;
3736                 case OP_LOADU1_MEM:
3737                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3738                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3739                         break;
3740                 case OP_LOADU2_MEM:
3741                         /* For NaCl, pointers are 4 bytes, so separate these */
3742                         /* cases, use literal 8 below where we really want 8 */
3743                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3744                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3745                         break;
3746                 case OP_LOAD_MEMBASE:
3747                         g_assert (amd64_is_imm32 (ins->inst_offset));
3748                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3749                         break;
3750                 case OP_LOADI8_MEMBASE:
3751                         /* Use literal 8 instead of sizeof pointer or */
3752                         /* register, we really want 8 for this opcode */
3753                         g_assert (amd64_is_imm32 (ins->inst_offset));
3754                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3755                         break;
3756                 case OP_LOADI4_MEMBASE:
3757                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3758                         break;
3759                 case OP_LOADU4_MEMBASE:
3760                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3761                         break;
3762                 case OP_LOADU1_MEMBASE:
3763                         /* The cpu zero extends the result into 64 bits */
3764                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3765                         break;
3766                 case OP_LOADI1_MEMBASE:
3767                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3768                         break;
3769                 case OP_LOADU2_MEMBASE:
3770                         /* The cpu zero extends the result into 64 bits */
3771                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3772                         break;
3773                 case OP_LOADI2_MEMBASE:
3774                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3775                         break;
3776                 case OP_AMD64_LOADI8_MEMINDEX:
3777                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3778                         break;
3779                 case OP_LCONV_TO_I1:
3780                 case OP_ICONV_TO_I1:
3781                 case OP_SEXT_I1:
3782                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3783                         break;
3784                 case OP_LCONV_TO_I2:
3785                 case OP_ICONV_TO_I2:
3786                 case OP_SEXT_I2:
3787                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3788                         break;
3789                 case OP_LCONV_TO_U1:
3790                 case OP_ICONV_TO_U1:
3791                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3792                         break;
3793                 case OP_LCONV_TO_U2:
3794                 case OP_ICONV_TO_U2:
3795                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3796                         break;
3797                 case OP_ZEXT_I4:
3798                         /* Clean out the upper word */
3799                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3800                         break;
3801                 case OP_SEXT_I4:
3802                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3803                         break;
3804                 case OP_COMPARE:
3805                 case OP_LCOMPARE:
3806                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3807                         break;
3808                 case OP_COMPARE_IMM:
3809 #if defined(__mono_ilp32__)
3810                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3811                         g_assert (amd64_is_imm32 (ins->inst_imm));
3812                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3813                         break;
3814 #endif
3815                 case OP_LCOMPARE_IMM:
3816                         g_assert (amd64_is_imm32 (ins->inst_imm));
3817                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3818                         break;
3819                 case OP_X86_COMPARE_REG_MEMBASE:
3820                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3821                         break;
3822                 case OP_X86_TEST_NULL:
3823                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3824                         break;
3825                 case OP_AMD64_TEST_NULL:
3826                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3827                         break;
3828
3829                 case OP_X86_ADD_REG_MEMBASE:
3830                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3831                         break;
3832                 case OP_X86_SUB_REG_MEMBASE:
3833                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3834                         break;
3835                 case OP_X86_AND_REG_MEMBASE:
3836                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3837                         break;
3838                 case OP_X86_OR_REG_MEMBASE:
3839                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3840                         break;
3841                 case OP_X86_XOR_REG_MEMBASE:
3842                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3843                         break;
3844
3845                 case OP_X86_ADD_MEMBASE_IMM:
3846                         /* FIXME: Make a 64 version too */
3847                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3848                         break;
3849                 case OP_X86_SUB_MEMBASE_IMM:
3850                         g_assert (amd64_is_imm32 (ins->inst_imm));
3851                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3852                         break;
3853                 case OP_X86_AND_MEMBASE_IMM:
3854                         g_assert (amd64_is_imm32 (ins->inst_imm));
3855                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3856                         break;
3857                 case OP_X86_OR_MEMBASE_IMM:
3858                         g_assert (amd64_is_imm32 (ins->inst_imm));
3859                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3860                         break;
3861                 case OP_X86_XOR_MEMBASE_IMM:
3862                         g_assert (amd64_is_imm32 (ins->inst_imm));
3863                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3864                         break;
3865                 case OP_X86_ADD_MEMBASE_REG:
3866                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3867                         break;
3868                 case OP_X86_SUB_MEMBASE_REG:
3869                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3870                         break;
3871                 case OP_X86_AND_MEMBASE_REG:
3872                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3873                         break;
3874                 case OP_X86_OR_MEMBASE_REG:
3875                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3876                         break;
3877                 case OP_X86_XOR_MEMBASE_REG:
3878                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3879                         break;
3880                 case OP_X86_INC_MEMBASE:
3881                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3882                         break;
3883                 case OP_X86_INC_REG:
3884                         amd64_inc_reg_size (code, ins->dreg, 4);
3885                         break;
3886                 case OP_X86_DEC_MEMBASE:
3887                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3888                         break;
3889                 case OP_X86_DEC_REG:
3890                         amd64_dec_reg_size (code, ins->dreg, 4);
3891                         break;
3892                 case OP_X86_MUL_REG_MEMBASE:
3893                 case OP_X86_MUL_MEMBASE_REG:
3894                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3895                         break;
3896                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3897                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3898                         break;
3899                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3900                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3901                         break;
3902                 case OP_AMD64_COMPARE_MEMBASE_REG:
3903                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3904                         break;
3905                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3906                         g_assert (amd64_is_imm32 (ins->inst_imm));
3907                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3908                         break;
3909                 case OP_X86_COMPARE_MEMBASE8_IMM:
3910                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3911                         break;
3912                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3913                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3914                         break;
3915                 case OP_AMD64_COMPARE_REG_MEMBASE:
3916                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3917                         break;
3918
3919                 case OP_AMD64_ADD_REG_MEMBASE:
3920                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3921                         break;
3922                 case OP_AMD64_SUB_REG_MEMBASE:
3923                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3924                         break;
3925                 case OP_AMD64_AND_REG_MEMBASE:
3926                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3927                         break;
3928                 case OP_AMD64_OR_REG_MEMBASE:
3929                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3930                         break;
3931                 case OP_AMD64_XOR_REG_MEMBASE:
3932                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3933                         break;
3934
3935                 case OP_AMD64_ADD_MEMBASE_REG:
3936                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3937                         break;
3938                 case OP_AMD64_SUB_MEMBASE_REG:
3939                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3940                         break;
3941                 case OP_AMD64_AND_MEMBASE_REG:
3942                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3943                         break;
3944                 case OP_AMD64_OR_MEMBASE_REG:
3945                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3946                         break;
3947                 case OP_AMD64_XOR_MEMBASE_REG:
3948                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3949                         break;
3950
3951                 case OP_AMD64_ADD_MEMBASE_IMM:
3952                         g_assert (amd64_is_imm32 (ins->inst_imm));
3953                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3954                         break;
3955                 case OP_AMD64_SUB_MEMBASE_IMM:
3956                         g_assert (amd64_is_imm32 (ins->inst_imm));
3957                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3958                         break;
3959                 case OP_AMD64_AND_MEMBASE_IMM:
3960                         g_assert (amd64_is_imm32 (ins->inst_imm));
3961                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3962                         break;
3963                 case OP_AMD64_OR_MEMBASE_IMM:
3964                         g_assert (amd64_is_imm32 (ins->inst_imm));
3965                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3966                         break;
3967                 case OP_AMD64_XOR_MEMBASE_IMM:
3968                         g_assert (amd64_is_imm32 (ins->inst_imm));
3969                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3970                         break;
3971
3972                 case OP_BREAK:
3973                         amd64_breakpoint (code);
3974                         break;
3975                 case OP_RELAXED_NOP:
3976                         x86_prefix (code, X86_REP_PREFIX);
3977                         x86_nop (code);
3978                         break;
3979                 case OP_HARD_NOP:
3980                         x86_nop (code);
3981                         break;
3982                 case OP_NOP:
3983                 case OP_DUMMY_USE:
3984                 case OP_DUMMY_STORE:
3985                 case OP_DUMMY_ICONST:
3986                 case OP_DUMMY_R8CONST:
3987                 case OP_NOT_REACHED:
3988                 case OP_NOT_NULL:
3989                         break;
3990                 case OP_IL_SEQ_POINT:
3991                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3992                         break;
3993                 case OP_SEQ_POINT: {
3994                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3995                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
3996                                 guint8 *label;
3997
3998                                 /* Load ss_tramp_var */
3999                                 /* This is equal to &ss_trampoline */
4000                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4001                                 /* Load the trampoline address */
4002                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4003                                 /* Call it if it is non-null */
4004                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4005                                 label = code;
4006                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4007                                 amd64_call_reg (code, AMD64_R11);
4008                                 amd64_patch (label, code);
4009                         }
4010
4011                         /*
4012                          * This is the address which is saved in seq points,
4013                          */
4014                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4015
4016                         if (cfg->compile_aot) {
4017                                 guint32 offset = code - cfg->native_code;
4018                                 guint32 val;
4019                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4020                                 guint8 *label;
4021
4022                                 /* Load info var */
4023                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4024                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4025                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4026                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4027                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4028                                 label = code;
4029                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4030                                 /* Call the trampoline */
4031                                 amd64_call_reg (code, AMD64_R11);
4032                                 amd64_patch (label, code);
4033                         } else {
4034                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4035                                 guint8 *label;
4036
4037                                 /*
4038                                  * Emit a test+branch against a constant, the constant will be overwritten
4039                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4040                                  */
4041                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4042                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4043                                 label = code;
4044                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4045
4046                                 g_assert (var);
4047                                 g_assert (var->opcode == OP_REGOFFSET);
4048                                 /* Load bp_tramp_var */
4049                                 /* This is equal to &bp_trampoline */
4050                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4051                                 /* Call the trampoline */
4052                                 amd64_call_membase (code, AMD64_R11, 0);
4053                                 amd64_patch (label, code);
4054                         }
4055                         /*
4056                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4057                          * to another IL offset.
4058                          */
4059                         x86_nop (code);
4060                         break;
4061                 }
4062                 case OP_ADDCC:
4063                 case OP_LADDCC:
4064                 case OP_LADD:
4065                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4066                         break;
4067                 case OP_ADC:
4068                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4069                         break;
4070                 case OP_ADD_IMM:
4071                 case OP_LADD_IMM:
4072                         g_assert (amd64_is_imm32 (ins->inst_imm));
4073                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4074                         break;
4075                 case OP_ADC_IMM:
4076                         g_assert (amd64_is_imm32 (ins->inst_imm));
4077                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4078                         break;
4079                 case OP_SUBCC:
4080                 case OP_LSUBCC:
4081                 case OP_LSUB:
4082                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4083                         break;
4084                 case OP_SBB:
4085                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4086                         break;
4087                 case OP_SUB_IMM:
4088                 case OP_LSUB_IMM:
4089                         g_assert (amd64_is_imm32 (ins->inst_imm));
4090                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4091                         break;
4092                 case OP_SBB_IMM:
4093                         g_assert (amd64_is_imm32 (ins->inst_imm));
4094                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4095                         break;
4096                 case OP_LAND:
4097                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4098                         break;
4099                 case OP_AND_IMM:
4100                 case OP_LAND_IMM:
4101                         g_assert (amd64_is_imm32 (ins->inst_imm));
4102                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4103                         break;
4104                 case OP_LMUL:
4105                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4106                         break;
4107                 case OP_MUL_IMM:
4108                 case OP_LMUL_IMM:
4109                 case OP_IMUL_IMM: {
4110                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4111
4112                         switch (ins->inst_imm) {
4113                         case 2:
4114                                 /* MOV r1, r2 */
4115                                 /* ADD r1, r1 */
4116                                 if (ins->dreg != ins->sreg1)
4117                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4118                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4119                                 break;
4120                         case 3:
4121                                 /* LEA r1, [r2 + r2*2] */
4122                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4123                                 break;
4124                         case 5:
4125                                 /* LEA r1, [r2 + r2*4] */
4126                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4127                                 break;
4128                         case 6:
4129                                 /* LEA r1, [r2 + r2*2] */
4130                                 /* ADD r1, r1          */
4131                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4132                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4133                                 break;
4134                         case 9:
4135                                 /* LEA r1, [r2 + r2*8] */
4136                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4137                                 break;
4138                         case 10:
4139                                 /* LEA r1, [r2 + r2*4] */
4140                                 /* ADD r1, r1          */
4141                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4142                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4143                                 break;
4144                         case 12:
4145                                 /* LEA r1, [r2 + r2*2] */
4146                                 /* SHL r1, 2           */
4147                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4148                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4149                                 break;
4150                         case 25:
4151                                 /* LEA r1, [r2 + r2*4] */
4152                                 /* LEA r1, [r1 + r1*4] */
4153                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4154                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4155                                 break;
4156                         case 100:
4157                                 /* LEA r1, [r2 + r2*4] */
4158                                 /* SHL r1, 2           */
4159                                 /* LEA r1, [r1 + r1*4] */
4160                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4161                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4162                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4163                                 break;
4164                         default:
4165                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4166                                 break;
4167                         }
4168                         break;
4169                 }
4170                 case OP_LDIV:
4171                 case OP_LREM:
4172                         /* Regalloc magic makes the div/rem cases the same */
4173                         if (ins->sreg2 == AMD64_RDX) {
4174                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4175                                 amd64_cdq (code);
4176                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4177                         } else {
4178                                 amd64_cdq (code);
4179                                 amd64_div_reg (code, ins->sreg2, TRUE);
4180                         }
4181                         break;
4182                 case OP_LDIV_UN:
4183                 case OP_LREM_UN:
4184                         if (ins->sreg2 == AMD64_RDX) {
4185                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4186                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4187                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4188                         } else {
4189                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4190                                 amd64_div_reg (code, ins->sreg2, FALSE);
4191                         }
4192                         break;
4193                 case OP_IDIV:
4194                 case OP_IREM:
4195                         if (ins->sreg2 == AMD64_RDX) {
4196                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4197                                 amd64_cdq_size (code, 4);
4198                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4199                         } else {
4200                                 amd64_cdq_size (code, 4);
4201                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4202                         }
4203                         break;
4204                 case OP_IDIV_UN:
4205                 case OP_IREM_UN:
4206                         if (ins->sreg2 == AMD64_RDX) {
4207                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4208                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4209                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4210                         } else {
4211                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4212                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4213                         }
4214                         break;
4215                 case OP_LMUL_OVF:
4216                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4217                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4218                         break;
4219                 case OP_LOR:
4220                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4221                         break;
4222                 case OP_OR_IMM:
4223                 case OP_LOR_IMM:
4224                         g_assert (amd64_is_imm32 (ins->inst_imm));
4225                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4226                         break;
4227                 case OP_LXOR:
4228                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4229                         break;
4230                 case OP_XOR_IMM:
4231                 case OP_LXOR_IMM:
4232                         g_assert (amd64_is_imm32 (ins->inst_imm));
4233                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4234                         break;
4235                 case OP_LSHL:
4236                         g_assert (ins->sreg2 == AMD64_RCX);
4237                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4238                         break;
4239                 case OP_LSHR:
4240                         g_assert (ins->sreg2 == AMD64_RCX);
4241                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4242                         break;
4243                 case OP_SHR_IMM:
4244                 case OP_LSHR_IMM:
4245                         g_assert (amd64_is_imm32 (ins->inst_imm));
4246                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4247                         break;
4248                 case OP_SHR_UN_IMM:
4249                         g_assert (amd64_is_imm32 (ins->inst_imm));
4250                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4251                         break;
4252                 case OP_LSHR_UN_IMM:
4253                         g_assert (amd64_is_imm32 (ins->inst_imm));
4254                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4255                         break;
4256                 case OP_LSHR_UN:
4257                         g_assert (ins->sreg2 == AMD64_RCX);
4258                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4259                         break;
4260                 case OP_SHL_IMM:
4261                 case OP_LSHL_IMM:
4262                         g_assert (amd64_is_imm32 (ins->inst_imm));
4263                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4264                         break;
4265
4266                 case OP_IADDCC:
4267                 case OP_IADD:
4268                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4269                         break;
4270                 case OP_IADC:
4271                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4272                         break;
4273                 case OP_IADD_IMM:
4274                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4275                         break;
4276                 case OP_IADC_IMM:
4277                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4278                         break;
4279                 case OP_ISUBCC:
4280                 case OP_ISUB:
4281                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4282                         break;
4283                 case OP_ISBB:
4284                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4285                         break;
4286                 case OP_ISUB_IMM:
4287                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4288                         break;
4289                 case OP_ISBB_IMM:
4290                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4291                         break;
4292                 case OP_IAND:
4293                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4294                         break;
4295                 case OP_IAND_IMM:
4296                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4297                         break;
4298                 case OP_IOR:
4299                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4300                         break;
4301                 case OP_IOR_IMM:
4302                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4303                         break;
4304                 case OP_IXOR:
4305                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4306                         break;
4307                 case OP_IXOR_IMM:
4308                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4309                         break;
4310                 case OP_INEG:
4311                         amd64_neg_reg_size (code, ins->sreg1, 4);
4312                         break;
4313                 case OP_INOT:
4314                         amd64_not_reg_size (code, ins->sreg1, 4);
4315                         break;
4316                 case OP_ISHL:
4317                         g_assert (ins->sreg2 == AMD64_RCX);
4318                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4319                         break;
4320                 case OP_ISHR:
4321                         g_assert (ins->sreg2 == AMD64_RCX);
4322                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4323                         break;
4324                 case OP_ISHR_IMM:
4325                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4326                         break;
4327                 case OP_ISHR_UN_IMM:
4328                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4329                         break;
4330                 case OP_ISHR_UN:
4331                         g_assert (ins->sreg2 == AMD64_RCX);
4332                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4333                         break;
4334                 case OP_ISHL_IMM:
4335                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4336                         break;
4337                 case OP_IMUL:
4338                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4339                         break;
4340                 case OP_IMUL_OVF:
4341                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4342                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4343                         break;
4344                 case OP_IMUL_OVF_UN:
4345                 case OP_LMUL_OVF_UN: {
4346                         /* the mul operation and the exception check should most likely be split */
4347                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4348                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4349                         /*g_assert (ins->sreg2 == X86_EAX);
4350                         g_assert (ins->dreg == X86_EAX);*/
4351                         if (ins->sreg2 == X86_EAX) {
4352                                 non_eax_reg = ins->sreg1;
4353                         } else if (ins->sreg1 == X86_EAX) {
4354                                 non_eax_reg = ins->sreg2;
4355                         } else {
4356                                 /* no need to save since we're going to store to it anyway */
4357                                 if (ins->dreg != X86_EAX) {
4358                                         saved_eax = TRUE;
4359                                         amd64_push_reg (code, X86_EAX);
4360                                 }
4361                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4362                                 non_eax_reg = ins->sreg2;
4363                         }
4364                         if (ins->dreg == X86_EDX) {
4365                                 if (!saved_eax) {
4366                                         saved_eax = TRUE;
4367                                         amd64_push_reg (code, X86_EAX);
4368                                 }
4369                         } else {
4370                                 saved_edx = TRUE;
4371                                 amd64_push_reg (code, X86_EDX);
4372                         }
4373                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4374                         /* save before the check since pop and mov don't change the flags */
4375                         if (ins->dreg != X86_EAX)
4376                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4377                         if (saved_edx)
4378                                 amd64_pop_reg (code, X86_EDX);
4379                         if (saved_eax)
4380                                 amd64_pop_reg (code, X86_EAX);
4381                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4382                         break;
4383                 }
4384                 case OP_ICOMPARE:
4385                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4386                         break;
4387                 case OP_ICOMPARE_IMM:
4388                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4389                         break;
4390                 case OP_IBEQ:
4391                 case OP_IBLT:
4392                 case OP_IBGT:
4393                 case OP_IBGE:
4394                 case OP_IBLE:
4395                 case OP_LBEQ:
4396                 case OP_LBLT:
4397                 case OP_LBGT:
4398                 case OP_LBGE:
4399                 case OP_LBLE:
4400                 case OP_IBNE_UN:
4401                 case OP_IBLT_UN:
4402                 case OP_IBGT_UN:
4403                 case OP_IBGE_UN:
4404                 case OP_IBLE_UN:
4405                 case OP_LBNE_UN:
4406                 case OP_LBLT_UN:
4407                 case OP_LBGT_UN:
4408                 case OP_LBGE_UN:
4409                 case OP_LBLE_UN:
4410                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4411                         break;
4412
4413                 case OP_CMOV_IEQ:
4414                 case OP_CMOV_IGE:
4415                 case OP_CMOV_IGT:
4416                 case OP_CMOV_ILE:
4417                 case OP_CMOV_ILT:
4418                 case OP_CMOV_INE_UN:
4419                 case OP_CMOV_IGE_UN:
4420                 case OP_CMOV_IGT_UN:
4421                 case OP_CMOV_ILE_UN:
4422                 case OP_CMOV_ILT_UN:
4423                 case OP_CMOV_LEQ:
4424                 case OP_CMOV_LGE:
4425                 case OP_CMOV_LGT:
4426                 case OP_CMOV_LLE:
4427                 case OP_CMOV_LLT:
4428                 case OP_CMOV_LNE_UN:
4429                 case OP_CMOV_LGE_UN:
4430                 case OP_CMOV_LGT_UN:
4431                 case OP_CMOV_LLE_UN:
4432                 case OP_CMOV_LLT_UN:
4433                         g_assert (ins->dreg == ins->sreg1);
4434                         /* This needs to operate on 64 bit values */
4435                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4436                         break;
4437
4438                 case OP_LNOT:
4439                         amd64_not_reg (code, ins->sreg1);
4440                         break;
4441                 case OP_LNEG:
4442                         amd64_neg_reg (code, ins->sreg1);
4443                         break;
4444
4445                 case OP_ICONST:
4446                 case OP_I8CONST:
4447                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4448                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4449                         else
4450                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4451                         break;
4452                 case OP_AOTCONST:
4453                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4454                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4455                         break;
4456                 case OP_JUMP_TABLE:
4457                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4458                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4459                         break;
4460                 case OP_MOVE:
4461                         if (ins->dreg != ins->sreg1)
4462                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4463                         break;
4464                 case OP_AMD64_SET_XMMREG_R4: {
4465                         if (cfg->r4fp) {
4466                                 if (ins->dreg != ins->sreg1)
4467                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4468                         } else {
4469                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4470                         }
4471                         break;
4472                 }
4473                 case OP_AMD64_SET_XMMREG_R8: {
4474                         if (ins->dreg != ins->sreg1)
4475                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4476                         break;
4477                 }
4478                 case OP_TAILCALL: {
4479                         MonoCallInst *call = (MonoCallInst*)ins;
4480                         int i, save_area_offset;
4481
4482                         g_assert (!cfg->method->save_lmf);
4483
4484                         /* Restore callee saved registers */
4485                         save_area_offset = cfg->arch.reg_save_area_offset;
4486                         for (i = 0; i < AMD64_NREG; ++i)
4487                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4488                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4489                                         save_area_offset += 8;
4490                                 }
4491
4492                         if (cfg->arch.omit_fp) {
4493                                 if (cfg->arch.stack_alloc_size)
4494                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4495                                 // FIXME:
4496                                 if (call->stack_usage)
4497                                         NOT_IMPLEMENTED;
4498                         } else {
4499                                 /* Copy arguments on the stack to our argument area */
4500                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4501                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4502                                         amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4503                                 }
4504
4505 #ifdef TARGET_WIN32
4506                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4507                                 amd64_pop_reg (code, AMD64_RBP);
4508                                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4509 #else
4510                                 amd64_leave (code);
4511 #endif
4512                         }
4513
4514                         offset = code - cfg->native_code;
4515                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4516                         if (cfg->compile_aot)
4517                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4518                         else
4519                                 amd64_set_reg_template (code, AMD64_R11);
4520                         amd64_jump_reg (code, AMD64_R11);
4521                         ins->flags |= MONO_INST_GC_CALLSITE;
4522                         ins->backend.pc_offset = code - cfg->native_code;
4523                         break;
4524                 }
4525                 case OP_CHECK_THIS:
4526                         /* ensure ins->sreg1 is not NULL */
4527                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4528                         break;
4529                 case OP_ARGLIST: {
4530                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4531                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4532                         break;
4533                 }
4534                 case OP_CALL:
4535                 case OP_FCALL:
4536                 case OP_RCALL:
4537                 case OP_LCALL:
4538                 case OP_VCALL:
4539                 case OP_VCALL2:
4540                 case OP_VOIDCALL:
4541                         call = (MonoCallInst*)ins;
4542                         /*
4543                          * The AMD64 ABI forces callers to know about varargs.
4544                          */
4545                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4546                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4547                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4548                                 /*
4549                                  * Since the unmanaged calling convention doesn't contain a
4550                                  * 'vararg' entry, we have to treat every pinvoke call as a
4551                                  * potential vararg call.
4552                                  */
4553                                 guint32 nregs, i;
4554                                 nregs = 0;
4555                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4556                                         if (call->used_fregs & (1 << i))
4557                                                 nregs ++;
4558                                 if (!nregs)
4559                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4560                                 else
4561                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4562                         }
4563
4564                         if (ins->flags & MONO_INST_HAS_METHOD)
4565                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4566                         else
4567                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4568                         ins->flags |= MONO_INST_GC_CALLSITE;
4569                         ins->backend.pc_offset = code - cfg->native_code;
4570                         code = emit_move_return_value (cfg, ins, code);
4571                         break;
4572                 case OP_FCALL_REG:
4573                 case OP_RCALL_REG:
4574                 case OP_LCALL_REG:
4575                 case OP_VCALL_REG:
4576                 case OP_VCALL2_REG:
4577                 case OP_VOIDCALL_REG:
4578                 case OP_CALL_REG:
4579                         call = (MonoCallInst*)ins;
4580
4581                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4582                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4583                                 ins->sreg1 = AMD64_R11;
4584                         }
4585
4586                         /*
4587                          * The AMD64 ABI forces callers to know about varargs.
4588                          */
4589                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4590                                 if (ins->sreg1 == AMD64_RAX) {
4591                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4592                                         ins->sreg1 = AMD64_R11;
4593                                 }
4594                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4595                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4596                                 /*
4597                                  * Since the unmanaged calling convention doesn't contain a
4598                                  * 'vararg' entry, we have to treat every pinvoke call as a
4599                                  * potential vararg call.
4600                                  */
4601                                 guint32 nregs, i;
4602                                 nregs = 0;
4603                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4604                                         if (call->used_fregs & (1 << i))
4605                                                 nregs ++;
4606                                 if (ins->sreg1 == AMD64_RAX) {
4607                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4608                                         ins->sreg1 = AMD64_R11;
4609                                 }
4610                                 if (!nregs)
4611                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4612                                 else
4613                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4614                         }
4615
4616                         amd64_call_reg (code, ins->sreg1);
4617                         ins->flags |= MONO_INST_GC_CALLSITE;
4618                         ins->backend.pc_offset = code - cfg->native_code;
4619                         code = emit_move_return_value (cfg, ins, code);
4620                         break;
4621                 case OP_FCALL_MEMBASE:
4622                 case OP_RCALL_MEMBASE:
4623                 case OP_LCALL_MEMBASE:
4624                 case OP_VCALL_MEMBASE:
4625                 case OP_VCALL2_MEMBASE:
4626                 case OP_VOIDCALL_MEMBASE:
4627                 case OP_CALL_MEMBASE:
4628                         call = (MonoCallInst*)ins;
4629
4630                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4631                         ins->flags |= MONO_INST_GC_CALLSITE;
4632                         ins->backend.pc_offset = code - cfg->native_code;
4633                         code = emit_move_return_value (cfg, ins, code);
4634                         break;
4635                 case OP_DYN_CALL: {
4636                         int i;
4637                         MonoInst *var = cfg->dyn_call_var;
4638                         guint8 *label;
4639
4640                         g_assert (var->opcode == OP_REGOFFSET);
4641
4642                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4643                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4644                         /* r10 = ftn */
4645                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4646
4647                         /* Save args buffer */
4648                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4649
4650                         /* Set fp arg regs */
4651                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4652                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4653                         label = code;
4654                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4655                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4656                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4657                         amd64_patch (label, code);
4658
4659                         /* Set stack args */
4660                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4661                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4662                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4663                         }
4664
4665                         /* Set argument registers */
4666                         for (i = 0; i < PARAM_REGS; ++i)
4667                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4668
4669                         /* Make the call */
4670                         amd64_call_reg (code, AMD64_R10);
4671
4672                         ins->flags |= MONO_INST_GC_CALLSITE;
4673                         ins->backend.pc_offset = code - cfg->native_code;
4674
4675                         /* Save result */
4676                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4677                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4678                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4679                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4680                         break;
4681                 }
4682                 case OP_AMD64_SAVE_SP_TO_LMF: {
4683                         MonoInst *lmf_var = cfg->lmf_var;
4684                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4685                         break;
4686                 }
4687                 case OP_X86_PUSH:
4688                         g_assert_not_reached ();
4689                         amd64_push_reg (code, ins->sreg1);
4690                         break;
4691                 case OP_X86_PUSH_IMM:
4692                         g_assert_not_reached ();
4693                         g_assert (amd64_is_imm32 (ins->inst_imm));
4694                         amd64_push_imm (code, ins->inst_imm);
4695                         break;
4696                 case OP_X86_PUSH_MEMBASE:
4697                         g_assert_not_reached ();
4698                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4699                         break;
4700                 case OP_X86_PUSH_OBJ: {
4701                         int size = ALIGN_TO (ins->inst_imm, 8);
4702
4703                         g_assert_not_reached ();
4704
4705                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4706                         amd64_push_reg (code, AMD64_RDI);
4707                         amd64_push_reg (code, AMD64_RSI);
4708                         amd64_push_reg (code, AMD64_RCX);
4709                         if (ins->inst_offset)
4710                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4711                         else
4712                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4713                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4714                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4715                         amd64_cld (code);
4716                         amd64_prefix (code, X86_REP_PREFIX);
4717                         amd64_movsd (code);
4718                         amd64_pop_reg (code, AMD64_RCX);
4719                         amd64_pop_reg (code, AMD64_RSI);
4720                         amd64_pop_reg (code, AMD64_RDI);
4721                         break;
4722                 }
4723                 case OP_GENERIC_CLASS_INIT: {
4724                         guint8 *jump;
4725
4726                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4727
4728                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4729                         jump = code;
4730                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4731
4732                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4733                         ins->flags |= MONO_INST_GC_CALLSITE;
4734                         ins->backend.pc_offset = code - cfg->native_code;
4735
4736                         x86_patch (jump, code);
4737                         break;
4738                 }
4739
4740                 case OP_X86_LEA:
4741                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4742                         break;
4743                 case OP_X86_LEA_MEMBASE:
4744                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4745                         break;
4746                 case OP_X86_XCHG:
4747                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4748                         break;
4749                 case OP_LOCALLOC:
4750                         /* keep alignment */
4751                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4752                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4753                         code = mono_emit_stack_alloc (cfg, code, ins);
4754                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4755                         if (cfg->param_area)
4756                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4757                         break;
4758                 case OP_LOCALLOC_IMM: {
4759                         guint32 size = ins->inst_imm;
4760                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4761
4762                         if (ins->flags & MONO_INST_INIT) {
4763                                 if (size < 64) {
4764                                         int i;
4765
4766                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4767                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4768
4769                                         for (i = 0; i < size; i += 8)
4770                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4771                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4772                                 } else {
4773                                         amd64_mov_reg_imm (code, ins->dreg, size);
4774                                         ins->sreg1 = ins->dreg;
4775
4776                                         code = mono_emit_stack_alloc (cfg, code, ins);
4777                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4778                                 }
4779                         } else {
4780                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4781                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4782                         }
4783                         if (cfg->param_area)
4784                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4785                         break;
4786                 }
4787                 case OP_THROW: {
4788                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4789                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4790                                              (gpointer)"mono_arch_throw_exception", FALSE);
4791                         ins->flags |= MONO_INST_GC_CALLSITE;
4792                         ins->backend.pc_offset = code - cfg->native_code;
4793                         break;
4794                 }
4795                 case OP_RETHROW: {
4796                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4797                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4798                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4799                         ins->flags |= MONO_INST_GC_CALLSITE;
4800                         ins->backend.pc_offset = code - cfg->native_code;
4801                         break;
4802                 }
4803                 case OP_CALL_HANDLER:
4804                         /* Align stack */
4805                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4806                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4807                         amd64_call_imm (code, 0);
4808                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4809                         /* Restore stack alignment */
4810                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4811                         break;
4812                 case OP_START_HANDLER: {
4813                         /* Even though we're saving RSP, use sizeof */
4814                         /* gpointer because spvar is of type IntPtr */
4815                         /* see: mono_create_spvar_for_region */
4816                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4817                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4818
4819                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4820                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FILTER)) &&
4821                                 cfg->param_area) {
4822                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4823                         }
4824                         break;
4825                 }
4826                 case OP_ENDFINALLY: {
4827                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4828                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4829                         amd64_ret (code);
4830                         break;
4831                 }
4832                 case OP_ENDFILTER: {
4833                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4834                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4835                         /* The local allocator will put the result into RAX */
4836                         amd64_ret (code);
4837                         break;
4838                 }
4839                 case OP_GET_EX_OBJ:
4840                         if (ins->dreg != AMD64_RAX)
4841                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4842                         break;
4843                 case OP_LABEL:
4844                         ins->inst_c0 = code - cfg->native_code;
4845                         break;
4846                 case OP_BR:
4847                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4848                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4849                         //break;
4850                                 if (ins->inst_target_bb->native_offset) {
4851                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4852                                 } else {
4853                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4854                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4855                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4856                                                 x86_jump8 (code, 0);
4857                                         else
4858                                                 x86_jump32 (code, 0);
4859                         }
4860                         break;
4861                 case OP_BR_REG:
4862                         amd64_jump_reg (code, ins->sreg1);
4863                         break;
4864                 case OP_ICNEQ:
4865                 case OP_ICGE:
4866                 case OP_ICLE:
4867                 case OP_ICGE_UN:
4868                 case OP_ICLE_UN:
4869
4870                 case OP_CEQ:
4871                 case OP_LCEQ:
4872                 case OP_ICEQ:
4873                 case OP_CLT:
4874                 case OP_LCLT:
4875                 case OP_ICLT:
4876                 case OP_CGT:
4877                 case OP_ICGT:
4878                 case OP_LCGT:
4879                 case OP_CLT_UN:
4880                 case OP_LCLT_UN:
4881                 case OP_ICLT_UN:
4882                 case OP_CGT_UN:
4883                 case OP_LCGT_UN:
4884                 case OP_ICGT_UN:
4885                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4886                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4887                         break;
4888                 case OP_COND_EXC_EQ:
4889                 case OP_COND_EXC_NE_UN:
4890                 case OP_COND_EXC_LT:
4891                 case OP_COND_EXC_LT_UN:
4892                 case OP_COND_EXC_GT:
4893                 case OP_COND_EXC_GT_UN:
4894                 case OP_COND_EXC_GE:
4895                 case OP_COND_EXC_GE_UN:
4896                 case OP_COND_EXC_LE:
4897                 case OP_COND_EXC_LE_UN:
4898                 case OP_COND_EXC_IEQ:
4899                 case OP_COND_EXC_INE_UN:
4900                 case OP_COND_EXC_ILT:
4901                 case OP_COND_EXC_ILT_UN:
4902                 case OP_COND_EXC_IGT:
4903                 case OP_COND_EXC_IGT_UN:
4904                 case OP_COND_EXC_IGE:
4905                 case OP_COND_EXC_IGE_UN:
4906                 case OP_COND_EXC_ILE:
4907                 case OP_COND_EXC_ILE_UN:
4908                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4909                         break;
4910                 case OP_COND_EXC_OV:
4911                 case OP_COND_EXC_NO:
4912                 case OP_COND_EXC_C:
4913                 case OP_COND_EXC_NC:
4914                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4915                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4916                         break;
4917                 case OP_COND_EXC_IOV:
4918                 case OP_COND_EXC_INO:
4919                 case OP_COND_EXC_IC:
4920                 case OP_COND_EXC_INC:
4921                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4922                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4923                         break;
4924
4925                 /* floating point opcodes */
4926                 case OP_R8CONST: {
4927                         double d = *(double *)ins->inst_p0;
4928
4929                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4930                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4931                         }
4932                         else {
4933                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4934                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4935                         }
4936                         break;
4937                 }
4938                 case OP_R4CONST: {
4939                         float f = *(float *)ins->inst_p0;
4940
4941                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4942                                 if (cfg->r4fp)
4943                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4944                                 else
4945                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4946                         }
4947                         else {
4948                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4949                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4950                                 if (!cfg->r4fp)
4951                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4952                         }
4953                         break;
4954                 }
4955                 case OP_STORER8_MEMBASE_REG:
4956                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4957                         break;
4958                 case OP_LOADR8_MEMBASE:
4959                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4960                         break;
4961                 case OP_STORER4_MEMBASE_REG:
4962                         if (cfg->r4fp) {
4963                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4964                         } else {
4965                                 /* This requires a double->single conversion */
4966                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4967                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4968                         }
4969                         break;
4970                 case OP_LOADR4_MEMBASE:
4971                         if (cfg->r4fp) {
4972                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4973                         } else {
4974                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4975                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4976                         }
4977                         break;
4978                 case OP_ICONV_TO_R4:
4979                         if (cfg->r4fp) {
4980                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4981                         } else {
4982                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4983                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4984                         }
4985                         break;
4986                 case OP_ICONV_TO_R8:
4987                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4988                         break;
4989                 case OP_LCONV_TO_R4:
4990                         if (cfg->r4fp) {
4991                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
4992                         } else {
4993                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
4994                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4995                         }
4996                         break;
4997                 case OP_LCONV_TO_R8:
4998                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4999                         break;
5000                 case OP_FCONV_TO_R4:
5001                         if (cfg->r4fp) {
5002                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5003                         } else {
5004                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5005                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5006                         }
5007                         break;
5008                 case OP_FCONV_TO_I1:
5009                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5010                         break;
5011                 case OP_FCONV_TO_U1:
5012                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5013                         break;
5014                 case OP_FCONV_TO_I2:
5015                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5016                         break;
5017                 case OP_FCONV_TO_U2:
5018                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5019                         break;
5020                 case OP_FCONV_TO_U4:
5021                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5022                         break;
5023                 case OP_FCONV_TO_I4:
5024                 case OP_FCONV_TO_I:
5025                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5026                         break;
5027                 case OP_FCONV_TO_I8:
5028                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5029                         break;
5030
5031                 case OP_RCONV_TO_I1:
5032                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5033                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5034                         break;
5035                 case OP_RCONV_TO_U1:
5036                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5037                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5038                         break;
5039                 case OP_RCONV_TO_I2:
5040                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5041                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5042                         break;
5043                 case OP_RCONV_TO_U2:
5044                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5045                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5046                         break;
5047                 case OP_RCONV_TO_I4:
5048                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5049                         break;
5050                 case OP_RCONV_TO_U4:
5051                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5052                         break;
5053                 case OP_RCONV_TO_I8:
5054                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5055                         break;
5056                 case OP_RCONV_TO_R8:
5057                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5058                         break;
5059                 case OP_RCONV_TO_R4:
5060                         if (ins->dreg != ins->sreg1)
5061                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5062                         break;
5063
5064                 case OP_LCONV_TO_R_UN: {
5065                         guint8 *br [2];
5066
5067                         /* Based on gcc code */
5068                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5069                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5070
5071                         /* Positive case */
5072                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5073                         br [1] = code; x86_jump8 (code, 0);
5074                         amd64_patch (br [0], code);
5075
5076                         /* Negative case */
5077                         /* Save to the red zone */
5078                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5079                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5080                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5081                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5082                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5083                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5084                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5085                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5086                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5087                         /* Restore */
5088                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5089                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5090                         amd64_patch (br [1], code);
5091                         break;
5092                 }
5093                 case OP_LCONV_TO_OVF_U4:
5094                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5095                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5096                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5097                         break;
5098                 case OP_LCONV_TO_OVF_I4_UN:
5099                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5100                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5101                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5102                         break;
5103                 case OP_FMOVE:
5104                         if (ins->dreg != ins->sreg1)
5105                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5106                         break;
5107                 case OP_RMOVE:
5108                         if (ins->dreg != ins->sreg1)
5109                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5110                         break;
5111                 case OP_MOVE_F_TO_I4:
5112                         if (cfg->r4fp) {
5113                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5114                         } else {
5115                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5116                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5117                         }
5118                         break;
5119                 case OP_MOVE_I4_TO_F:
5120                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5121                         if (!cfg->r4fp)
5122                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5123                         break;
5124                 case OP_MOVE_F_TO_I8:
5125                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5126                         break;
5127                 case OP_MOVE_I8_TO_F:
5128                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5129                         break;
5130                 case OP_FADD:
5131                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5132                         break;
5133                 case OP_FSUB:
5134                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5135                         break;
5136                 case OP_FMUL:
5137                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5138                         break;
5139                 case OP_FDIV:
5140                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5141                         break;
5142                 case OP_FNEG: {
5143                         static double r8_0 = -0.0;
5144
5145                         g_assert (ins->sreg1 == ins->dreg);
5146
5147                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5148                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5149                         break;
5150                 }
5151                 case OP_SIN:
5152                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5153                         break;
5154                 case OP_COS:
5155                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5156                         break;
5157                 case OP_ABS: {
5158                         static guint64 d = 0x7fffffffffffffffUL;
5159
5160                         g_assert (ins->sreg1 == ins->dreg);
5161
5162                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5163                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5164                         break;
5165                 }
5166                 case OP_SQRT:
5167                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5168                         break;
5169
5170                 case OP_RADD:
5171                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5172                         break;
5173                 case OP_RSUB:
5174                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5175                         break;
5176                 case OP_RMUL:
5177                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5178                         break;
5179                 case OP_RDIV:
5180                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5181                         break;
5182                 case OP_RNEG: {
5183                         static float r4_0 = -0.0;
5184
5185                         g_assert (ins->sreg1 == ins->dreg);
5186
5187                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5188                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5189                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5190                         break;
5191                 }
5192
5193                 case OP_IMIN:
5194                         g_assert (cfg->opt & MONO_OPT_CMOV);
5195                         g_assert (ins->dreg == ins->sreg1);
5196                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5197                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5198                         break;
5199                 case OP_IMIN_UN:
5200                         g_assert (cfg->opt & MONO_OPT_CMOV);
5201                         g_assert (ins->dreg == ins->sreg1);
5202                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5203                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5204                         break;
5205                 case OP_IMAX:
5206                         g_assert (cfg->opt & MONO_OPT_CMOV);
5207                         g_assert (ins->dreg == ins->sreg1);
5208                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5209                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5210                         break;
5211                 case OP_IMAX_UN:
5212                         g_assert (cfg->opt & MONO_OPT_CMOV);
5213                         g_assert (ins->dreg == ins->sreg1);
5214                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5215                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5216                         break;
5217                 case OP_LMIN:
5218                         g_assert (cfg->opt & MONO_OPT_CMOV);
5219                         g_assert (ins->dreg == ins->sreg1);
5220                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5221                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5222                         break;
5223                 case OP_LMIN_UN:
5224                         g_assert (cfg->opt & MONO_OPT_CMOV);
5225                         g_assert (ins->dreg == ins->sreg1);
5226                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5227                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5228                         break;
5229                 case OP_LMAX:
5230                         g_assert (cfg->opt & MONO_OPT_CMOV);
5231                         g_assert (ins->dreg == ins->sreg1);
5232                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5233                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5234                         break;
5235                 case OP_LMAX_UN:
5236                         g_assert (cfg->opt & MONO_OPT_CMOV);
5237                         g_assert (ins->dreg == ins->sreg1);
5238                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5239                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5240                         break;
5241                 case OP_X86_FPOP:
5242                         break;
5243                 case OP_FCOMPARE:
5244                         /*
5245                          * The two arguments are swapped because the fbranch instructions
5246                          * depend on this for the non-sse case to work.
5247                          */
5248                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5249                         break;
5250                 case OP_RCOMPARE:
5251                         /*
5252                          * FIXME: Get rid of this.
5253                          * The two arguments are swapped because the fbranch instructions
5254                          * depend on this for the non-sse case to work.
5255                          */
5256                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5257                         break;
5258                 case OP_FCNEQ:
5259                 case OP_FCEQ: {
5260                         /* zeroing the register at the start results in
5261                          * shorter and faster code (we can also remove the widening op)
5262                          */
5263                         guchar *unordered_check;
5264
5265                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5266                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5267                         unordered_check = code;
5268                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5269
5270                         if (ins->opcode == OP_FCEQ) {
5271                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5272                                 amd64_patch (unordered_check, code);
5273                         } else {
5274                                 guchar *jump_to_end;
5275                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5276                                 jump_to_end = code;
5277                                 x86_jump8 (code, 0);
5278                                 amd64_patch (unordered_check, code);
5279                                 amd64_inc_reg (code, ins->dreg);
5280                                 amd64_patch (jump_to_end, code);
5281                         }
5282                         break;
5283                 }
5284                 case OP_FCLT:
5285                 case OP_FCLT_UN: {
5286                         /* zeroing the register at the start results in
5287                          * shorter and faster code (we can also remove the widening op)
5288                          */
5289                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5290                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5291                         if (ins->opcode == OP_FCLT_UN) {
5292                                 guchar *unordered_check = code;
5293                                 guchar *jump_to_end;
5294                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5295                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5296                                 jump_to_end = code;
5297                                 x86_jump8 (code, 0);
5298                                 amd64_patch (unordered_check, code);
5299                                 amd64_inc_reg (code, ins->dreg);
5300                                 amd64_patch (jump_to_end, code);
5301                         } else {
5302                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5303                         }
5304                         break;
5305                 }
5306                 case OP_FCLE: {
5307                         guchar *unordered_check;
5308                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5309                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5310                         unordered_check = code;
5311                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5312                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5313                         amd64_patch (unordered_check, code);
5314                         break;
5315                 }
5316                 case OP_FCGT:
5317                 case OP_FCGT_UN: {
5318                         /* zeroing the register at the start results in
5319                          * shorter and faster code (we can also remove the widening op)
5320                          */
5321                         guchar *unordered_check;
5322
5323                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5324                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5325                         if (ins->opcode == OP_FCGT) {
5326                                 unordered_check = code;
5327                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5328                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5329                                 amd64_patch (unordered_check, code);
5330                         } else {
5331                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5332                         }
5333                         break;
5334                 }
5335                 case OP_FCGE: {
5336                         guchar *unordered_check;
5337                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5338                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5339                         unordered_check = code;
5340                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5341                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5342                         amd64_patch (unordered_check, code);
5343                         break;
5344                 }
5345
5346                 case OP_RCEQ:
5347                 case OP_RCGT:
5348                 case OP_RCLT:
5349                 case OP_RCLT_UN:
5350                 case OP_RCGT_UN: {
5351                         int x86_cond;
5352                         gboolean unordered = FALSE;
5353
5354                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5355                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5356
5357                         switch (ins->opcode) {
5358                         case OP_RCEQ:
5359                                 x86_cond = X86_CC_EQ;
5360                                 break;
5361                         case OP_RCGT:
5362                                 x86_cond = X86_CC_LT;
5363                                 break;
5364                         case OP_RCLT:
5365                                 x86_cond = X86_CC_GT;
5366                                 break;
5367                         case OP_RCLT_UN:
5368                                 x86_cond = X86_CC_GT;
5369                                 unordered = TRUE;
5370                                 break;
5371                         case OP_RCGT_UN:
5372                                 x86_cond = X86_CC_LT;
5373                                 unordered = TRUE;
5374                                 break;
5375                         default:
5376                                 g_assert_not_reached ();
5377                                 break;
5378                         }
5379
5380                         if (unordered) {
5381                                 guchar *unordered_check;
5382                                 guchar *jump_to_end;
5383
5384                                 unordered_check = code;
5385                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5386                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5387                                 jump_to_end = code;
5388                                 x86_jump8 (code, 0);
5389                                 amd64_patch (unordered_check, code);
5390                                 amd64_inc_reg (code, ins->dreg);
5391                                 amd64_patch (jump_to_end, code);
5392                         } else {
5393                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5394                         }
5395                         break;
5396                 }
5397                 case OP_FCLT_MEMBASE:
5398                 case OP_FCGT_MEMBASE:
5399                 case OP_FCLT_UN_MEMBASE:
5400                 case OP_FCGT_UN_MEMBASE:
5401                 case OP_FCEQ_MEMBASE: {
5402                         guchar *unordered_check, *jump_to_end;
5403                         int x86_cond;
5404
5405                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5406                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5407
5408                         switch (ins->opcode) {
5409                         case OP_FCEQ_MEMBASE:
5410                                 x86_cond = X86_CC_EQ;
5411                                 break;
5412                         case OP_FCLT_MEMBASE:
5413                         case OP_FCLT_UN_MEMBASE:
5414                                 x86_cond = X86_CC_LT;
5415                                 break;
5416                         case OP_FCGT_MEMBASE:
5417                         case OP_FCGT_UN_MEMBASE:
5418                                 x86_cond = X86_CC_GT;
5419                                 break;
5420                         default:
5421                                 g_assert_not_reached ();
5422                         }
5423
5424                         unordered_check = code;
5425                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5426                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5427
5428                         switch (ins->opcode) {
5429                         case OP_FCEQ_MEMBASE:
5430                         case OP_FCLT_MEMBASE:
5431                         case OP_FCGT_MEMBASE:
5432                                 amd64_patch (unordered_check, code);
5433                                 break;
5434                         case OP_FCLT_UN_MEMBASE:
5435                         case OP_FCGT_UN_MEMBASE:
5436                                 jump_to_end = code;
5437                                 x86_jump8 (code, 0);
5438                                 amd64_patch (unordered_check, code);
5439                                 amd64_inc_reg (code, ins->dreg);
5440                                 amd64_patch (jump_to_end, code);
5441                                 break;
5442                         default:
5443                                 break;
5444                         }
5445                         break;
5446                 }
5447                 case OP_FBEQ: {
5448                         guchar *jump = code;
5449                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5450                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5451                         amd64_patch (jump, code);
5452                         break;
5453                 }
5454                 case OP_FBNE_UN:
5455                         /* Branch if C013 != 100 */
5456                         /* branch if !ZF or (PF|CF) */
5457                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5458                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5459                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5460                         break;
5461                 case OP_FBLT:
5462                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5463                         break;
5464                 case OP_FBLT_UN:
5465                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5466                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5467                         break;
5468                 case OP_FBGT:
5469                 case OP_FBGT_UN:
5470                         if (ins->opcode == OP_FBGT) {
5471                                 guchar *br1;
5472
5473                                 /* skip branch if C1=1 */
5474                                 br1 = code;
5475                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5476                                 /* branch if (C0 | C3) = 1 */
5477                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5478                                 amd64_patch (br1, code);
5479                                 break;
5480                         } else {
5481                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5482                         }
5483                         break;
5484                 case OP_FBGE: {
5485                         /* Branch if C013 == 100 or 001 */
5486                         guchar *br1;
5487
5488                         /* skip branch if C1=1 */
5489                         br1 = code;
5490                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5491                         /* branch if (C0 | C3) = 1 */
5492                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5493                         amd64_patch (br1, code);
5494                         break;
5495                 }
5496                 case OP_FBGE_UN:
5497                         /* Branch if C013 == 000 */
5498                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5499                         break;
5500                 case OP_FBLE: {
5501                         /* Branch if C013=000 or 100 */
5502                         guchar *br1;
5503
5504                         /* skip branch if C1=1 */
5505                         br1 = code;
5506                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5507                         /* branch if C0=0 */
5508                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5509                         amd64_patch (br1, code);
5510                         break;
5511                 }
5512                 case OP_FBLE_UN:
5513                         /* Branch if C013 != 001 */
5514                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5515                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5516                         break;
5517                 case OP_CKFINITE:
5518                         /* Transfer value to the fp stack */
5519                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5520                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5521                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5522
5523                         amd64_push_reg (code, AMD64_RAX);
5524                         amd64_fxam (code);
5525                         amd64_fnstsw (code);
5526                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5527                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5528                         amd64_pop_reg (code, AMD64_RAX);
5529                         amd64_fstp (code, 0);
5530                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5531                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5532                         break;
5533                 case OP_TLS_GET: {
5534                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5535                         break;
5536                 }
5537                 case OP_TLS_SET: {
5538                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5539                         break;
5540                 }
5541                 case OP_MEMORY_BARRIER: {
5542                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5543                                 x86_mfence (code);
5544                         break;
5545                 }
5546                 case OP_ATOMIC_ADD_I4:
5547                 case OP_ATOMIC_ADD_I8: {
5548                         int dreg = ins->dreg;
5549                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5550
5551                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5552                                 dreg = AMD64_R11;
5553
5554                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5555                         amd64_prefix (code, X86_LOCK_PREFIX);
5556                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5557                         /* dreg contains the old value, add with sreg2 value */
5558                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5559
5560                         if (ins->dreg != dreg)
5561                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5562
5563                         break;
5564                 }
5565                 case OP_ATOMIC_EXCHANGE_I4:
5566                 case OP_ATOMIC_EXCHANGE_I8: {
5567                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5568
5569                         /* LOCK prefix is implied. */
5570                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5571                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5572                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5573                         break;
5574                 }
5575                 case OP_ATOMIC_CAS_I4:
5576                 case OP_ATOMIC_CAS_I8: {
5577                         guint32 size;
5578
5579                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5580                                 size = 8;
5581                         else
5582                                 size = 4;
5583
5584                         /*
5585                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5586                          * an explanation of how this works.
5587                          */
5588                         g_assert (ins->sreg3 == AMD64_RAX);
5589                         g_assert (ins->sreg1 != AMD64_RAX);
5590                         g_assert (ins->sreg1 != ins->sreg2);
5591
5592                         amd64_prefix (code, X86_LOCK_PREFIX);
5593                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5594
5595                         if (ins->dreg != AMD64_RAX)
5596                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5597                         break;
5598                 }
5599                 case OP_ATOMIC_LOAD_I1: {
5600                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5601                         break;
5602                 }
5603                 case OP_ATOMIC_LOAD_U1: {
5604                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5605                         break;
5606                 }
5607                 case OP_ATOMIC_LOAD_I2: {
5608                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5609                         break;
5610                 }
5611                 case OP_ATOMIC_LOAD_U2: {
5612                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5613                         break;
5614                 }
5615                 case OP_ATOMIC_LOAD_I4: {
5616                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5617                         break;
5618                 }
5619                 case OP_ATOMIC_LOAD_U4:
5620                 case OP_ATOMIC_LOAD_I8:
5621                 case OP_ATOMIC_LOAD_U8: {
5622                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5623                         break;
5624                 }
5625                 case OP_ATOMIC_LOAD_R4: {
5626                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5627                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5628                         break;
5629                 }
5630                 case OP_ATOMIC_LOAD_R8: {
5631                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5632                         break;
5633                 }
5634                 case OP_ATOMIC_STORE_I1:
5635                 case OP_ATOMIC_STORE_U1:
5636                 case OP_ATOMIC_STORE_I2:
5637                 case OP_ATOMIC_STORE_U2:
5638                 case OP_ATOMIC_STORE_I4:
5639                 case OP_ATOMIC_STORE_U4:
5640                 case OP_ATOMIC_STORE_I8:
5641                 case OP_ATOMIC_STORE_U8: {
5642                         int size;
5643
5644                         switch (ins->opcode) {
5645                         case OP_ATOMIC_STORE_I1:
5646                         case OP_ATOMIC_STORE_U1:
5647                                 size = 1;
5648                                 break;
5649                         case OP_ATOMIC_STORE_I2:
5650                         case OP_ATOMIC_STORE_U2:
5651                                 size = 2;
5652                                 break;
5653                         case OP_ATOMIC_STORE_I4:
5654                         case OP_ATOMIC_STORE_U4:
5655                                 size = 4;
5656                                 break;
5657                         case OP_ATOMIC_STORE_I8:
5658                         case OP_ATOMIC_STORE_U8:
5659                                 size = 8;
5660                                 break;
5661                         }
5662
5663                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5664
5665                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5666                                 x86_mfence (code);
5667                         break;
5668                 }
5669                 case OP_ATOMIC_STORE_R4: {
5670                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5671                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5672
5673                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5674                                 x86_mfence (code);
5675                         break;
5676                 }
5677                 case OP_ATOMIC_STORE_R8: {
5678                         x86_nop (code);
5679                         x86_nop (code);
5680                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5681                         x86_nop (code);
5682                         x86_nop (code);
5683
5684                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5685                                 x86_mfence (code);
5686                         break;
5687                 }
5688                 case OP_CARD_TABLE_WBARRIER: {
5689                         int ptr = ins->sreg1;
5690                         int value = ins->sreg2;
5691                         guchar *br = 0;
5692                         int nursery_shift, card_table_shift;
5693                         gpointer card_table_mask;
5694                         size_t nursery_size;
5695
5696                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5697                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5698                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5699
5700                         /*If either point to the stack we can simply avoid the WB. This happens due to
5701                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5702                          */
5703                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5704                                 continue;
5705
5706                         /*
5707                          * We need one register we can clobber, we choose EDX and make sreg1
5708                          * fixed EAX to work around limitations in the local register allocator.
5709                          * sreg2 might get allocated to EDX, but that is not a problem since
5710                          * we use it before clobbering EDX.
5711                          */
5712                         g_assert (ins->sreg1 == AMD64_RAX);
5713
5714                         /*
5715                          * This is the code we produce:
5716                          *
5717                          *   edx = value
5718                          *   edx >>= nursery_shift
5719                          *   cmp edx, (nursery_start >> nursery_shift)
5720                          *   jne done
5721                          *   edx = ptr
5722                          *   edx >>= card_table_shift
5723                          *   edx += cardtable
5724                          *   [edx] = 1
5725                          * done:
5726                          */
5727
5728                         if (mono_gc_card_table_nursery_check ()) {
5729                                 if (value != AMD64_RDX)
5730                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5731                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5732                                 if (shifted_nursery_start >> 31) {
5733                                         /*
5734                                          * The value we need to compare against is 64 bits, so we need
5735                                          * another spare register.  We use RBX, which we save and
5736                                          * restore.
5737                                          */
5738                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5739                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5740                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5741                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5742                                 } else {
5743                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5744                                 }
5745                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5746                         }
5747                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5748                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5749                         if (card_table_mask)
5750                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5751
5752                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5753                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5754
5755                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5756
5757                         if (mono_gc_card_table_nursery_check ())
5758                                 x86_patch (br, code);
5759                         break;
5760                 }
5761 #ifdef MONO_ARCH_SIMD_INTRINSICS
5762                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5763                 case OP_ADDPS:
5764                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5765                         break;
5766                 case OP_DIVPS:
5767                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5768                         break;
5769                 case OP_MULPS:
5770                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5771                         break;
5772                 case OP_SUBPS:
5773                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5774                         break;
5775                 case OP_MAXPS:
5776                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5777                         break;
5778                 case OP_MINPS:
5779                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5780                         break;
5781                 case OP_COMPPS:
5782                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5783                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5784                         break;
5785                 case OP_ANDPS:
5786                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5787                         break;
5788                 case OP_ANDNPS:
5789                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5790                         break;
5791                 case OP_ORPS:
5792                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5793                         break;
5794                 case OP_XORPS:
5795                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5796                         break;
5797                 case OP_SQRTPS:
5798                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5799                         break;
5800                 case OP_RSQRTPS:
5801                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5802                         break;
5803                 case OP_RCPPS:
5804                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5805                         break;
5806                 case OP_ADDSUBPS:
5807                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5808                         break;
5809                 case OP_HADDPS:
5810                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5811                         break;
5812                 case OP_HSUBPS:
5813                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5814                         break;
5815                 case OP_DUPPS_HIGH:
5816                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5817                         break;
5818                 case OP_DUPPS_LOW:
5819                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5820                         break;
5821
5822                 case OP_PSHUFLEW_HIGH:
5823                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5824                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5825                         break;
5826                 case OP_PSHUFLEW_LOW:
5827                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5828                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5829                         break;
5830                 case OP_PSHUFLED:
5831                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5832                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5833                         break;
5834                 case OP_SHUFPS:
5835                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5836                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5837                         break;
5838                 case OP_SHUFPD:
5839                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5840                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5841                         break;
5842
5843                 case OP_ADDPD:
5844                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5845                         break;
5846                 case OP_DIVPD:
5847                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5848                         break;
5849                 case OP_MULPD:
5850                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5851                         break;
5852                 case OP_SUBPD:
5853                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5854                         break;
5855                 case OP_MAXPD:
5856                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5857                         break;
5858                 case OP_MINPD:
5859                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5860                         break;
5861                 case OP_COMPPD:
5862                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5863                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5864                         break;
5865                 case OP_ANDPD:
5866                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868                 case OP_ANDNPD:
5869                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5870                         break;
5871                 case OP_ORPD:
5872                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5873                         break;
5874                 case OP_XORPD:
5875                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5876                         break;
5877                 case OP_SQRTPD:
5878                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5879                         break;
5880                 case OP_ADDSUBPD:
5881                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5882                         break;
5883                 case OP_HADDPD:
5884                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5885                         break;
5886                 case OP_HSUBPD:
5887                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5888                         break;
5889                 case OP_DUPPD:
5890                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5891                         break;
5892
5893                 case OP_EXTRACT_MASK:
5894                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5895                         break;
5896
5897                 case OP_PAND:
5898                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5899                         break;
5900                 case OP_POR:
5901                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5902                         break;
5903                 case OP_PXOR:
5904                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906
5907                 case OP_PADDB:
5908                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_PADDW:
5911                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_PADDD:
5914                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5915                         break;
5916                 case OP_PADDQ:
5917                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919
5920                 case OP_PSUBB:
5921                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_PSUBW:
5924                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_PSUBD:
5927                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_PSUBQ:
5930                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932
5933                 case OP_PMAXB_UN:
5934                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_PMAXW_UN:
5937                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_PMAXD_UN:
5940                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942
5943                 case OP_PMAXB:
5944                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_PMAXW:
5947                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_PMAXD:
5950                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952
5953                 case OP_PAVGB_UN:
5954                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5955                         break;
5956                 case OP_PAVGW_UN:
5957                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959
5960                 case OP_PMINB_UN:
5961                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_PMINW_UN:
5964                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5965                         break;
5966                 case OP_PMIND_UN:
5967                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5968                         break;
5969
5970                 case OP_PMINB:
5971                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5972                         break;
5973                 case OP_PMINW:
5974                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5975                         break;
5976                 case OP_PMIND:
5977                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5978                         break;
5979
5980                 case OP_PCMPEQB:
5981                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5982                         break;
5983                 case OP_PCMPEQW:
5984                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5985                         break;
5986                 case OP_PCMPEQD:
5987                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5988                         break;
5989                 case OP_PCMPEQQ:
5990                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992
5993                 case OP_PCMPGTB:
5994                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5995                         break;
5996                 case OP_PCMPGTW:
5997                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_PCMPGTD:
6000                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_PCMPGTQ:
6003                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005
6006                 case OP_PSUM_ABS_DIFF:
6007                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009
6010                 case OP_UNPACK_LOWB:
6011                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6012                         break;
6013                 case OP_UNPACK_LOWW:
6014                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6015                         break;
6016                 case OP_UNPACK_LOWD:
6017                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6018                         break;
6019                 case OP_UNPACK_LOWQ:
6020                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_UNPACK_LOWPS:
6023                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_UNPACK_LOWPD:
6026                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028
6029                 case OP_UNPACK_HIGHB:
6030                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_UNPACK_HIGHW:
6033                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_UNPACK_HIGHD:
6036                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_UNPACK_HIGHQ:
6039                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041                 case OP_UNPACK_HIGHPS:
6042                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_UNPACK_HIGHPD:
6045                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047
6048                 case OP_PACKW:
6049                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_PACKD:
6052                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_PACKW_UN:
6055                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_PACKD_UN:
6058                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060
6061                 case OP_PADDB_SAT_UN:
6062                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064                 case OP_PSUBB_SAT_UN:
6065                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PADDW_SAT_UN:
6068                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PSUBW_SAT_UN:
6071                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073
6074                 case OP_PADDB_SAT:
6075                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077                 case OP_PSUBB_SAT:
6078                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_PADDW_SAT:
6081                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_PSUBW_SAT:
6084                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086
6087                 case OP_PMULW:
6088                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_PMULD:
6091                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_PMULQ:
6094                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096                 case OP_PMULW_HIGH_UN:
6097                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PMULW_HIGH:
6100                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102
6103                 case OP_PSHRW:
6104                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6105                         break;
6106                 case OP_PSHRW_REG:
6107                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6108                         break;
6109
6110                 case OP_PSARW:
6111                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6112                         break;
6113                 case OP_PSARW_REG:
6114                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6115                         break;
6116
6117                 case OP_PSHLW:
6118                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6119                         break;
6120                 case OP_PSHLW_REG:
6121                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6122                         break;
6123
6124                 case OP_PSHRD:
6125                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6126                         break;
6127                 case OP_PSHRD_REG:
6128                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6129                         break;
6130
6131                 case OP_PSARD:
6132                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6133                         break;
6134                 case OP_PSARD_REG:
6135                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6136                         break;
6137
6138                 case OP_PSHLD:
6139                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6140                         break;
6141                 case OP_PSHLD_REG:
6142                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6143                         break;
6144
6145                 case OP_PSHRQ:
6146                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6147                         break;
6148                 case OP_PSHRQ_REG:
6149                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6150                         break;
6151
6152                 /*TODO: This is appart of the sse spec but not added
6153                 case OP_PSARQ:
6154                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6155                         break;
6156                 case OP_PSARQ_REG:
6157                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6158                         break;
6159                 */
6160
6161                 case OP_PSHLQ:
6162                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6163                         break;
6164                 case OP_PSHLQ_REG:
6165                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6166                         break;
6167                 case OP_CVTDQ2PD:
6168                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6169                         break;
6170                 case OP_CVTDQ2PS:
6171                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6172                         break;
6173                 case OP_CVTPD2DQ:
6174                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6175                         break;
6176                 case OP_CVTPD2PS:
6177                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6178                         break;
6179                 case OP_CVTPS2DQ:
6180                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6181                         break;
6182                 case OP_CVTPS2PD:
6183                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6184                         break;
6185                 case OP_CVTTPD2DQ:
6186                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6187                         break;
6188                 case OP_CVTTPS2DQ:
6189                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6190                         break;
6191
6192                 case OP_ICONV_TO_X:
6193                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6194                         break;
6195                 case OP_EXTRACT_I4:
6196                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6197                         break;
6198                 case OP_EXTRACT_I8:
6199                         if (ins->inst_c0) {
6200                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6201                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6202                         } else {
6203                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6204                         }
6205                         break;
6206                 case OP_EXTRACT_I1:
6207                 case OP_EXTRACT_U1:
6208                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6209                         if (ins->inst_c0)
6210                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6211                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6212                         break;
6213                 case OP_EXTRACT_I2:
6214                 case OP_EXTRACT_U2:
6215                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6216                         if (ins->inst_c0)
6217                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6218                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6219                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6220                         break;
6221                 case OP_EXTRACT_R8:
6222                         if (ins->inst_c0)
6223                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6224                         else
6225                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6226                         break;
6227                 case OP_INSERT_I2:
6228                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6229                         break;
6230                 case OP_EXTRACTX_U2:
6231                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6232                         break;
6233                 case OP_INSERTX_U1_SLOW:
6234                         /*sreg1 is the extracted ireg (scratch)
6235                         /sreg2 is the to be inserted ireg (scratch)
6236                         /dreg is the xreg to receive the value*/
6237
6238                         /*clear the bits from the extracted word*/
6239                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6240                         /*shift the value to insert if needed*/
6241                         if (ins->inst_c0 & 1)
6242                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6243                         /*join them together*/
6244                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6245                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6246                         break;
6247                 case OP_INSERTX_I4_SLOW:
6248                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6249                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6250                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6251                         break;
6252                 case OP_INSERTX_I8_SLOW:
6253                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6254                         if (ins->inst_c0)
6255                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6256                         else
6257                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6258                         break;
6259
6260                 case OP_INSERTX_R4_SLOW:
6261                         switch (ins->inst_c0) {
6262                         case 0:
6263                                 if (cfg->r4fp)
6264                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6265                                 else
6266                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6267                                 break;
6268                         case 1:
6269                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6270                                 if (cfg->r4fp)
6271                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6272                                 else
6273                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6274                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6275                                 break;
6276                         case 2:
6277                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6278                                 if (cfg->r4fp)
6279                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6280                                 else
6281                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6282                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6283                                 break;
6284                         case 3:
6285                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6286                                 if (cfg->r4fp)
6287                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6288                                 else
6289                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6290                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6291                                 break;
6292                         }
6293                         break;
6294                 case OP_INSERTX_R8_SLOW:
6295                         if (ins->inst_c0)
6296                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6297                         else
6298                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6299                         break;
6300                 case OP_STOREX_MEMBASE_REG:
6301                 case OP_STOREX_MEMBASE:
6302                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6303                         break;
6304                 case OP_LOADX_MEMBASE:
6305                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6306                         break;
6307                 case OP_LOADX_ALIGNED_MEMBASE:
6308                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6309                         break;
6310                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6311                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6312                         break;
6313                 case OP_STOREX_NTA_MEMBASE_REG:
6314                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6315                         break;
6316                 case OP_PREFETCH_MEMBASE:
6317                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6318                         break;
6319
6320                 case OP_XMOVE:
6321                         /*FIXME the peephole pass should have killed this*/
6322                         if (ins->dreg != ins->sreg1)
6323                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6324                         break;
6325                 case OP_XZERO:
6326                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6327                         break;
6328                 case OP_XONES:
6329                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6330                         break;
6331                 case OP_ICONV_TO_R4_RAW:
6332                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6333                         if (!cfg->r4fp)
6334                           amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6335                         break;
6336
6337                 case OP_FCONV_TO_R8_X:
6338                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6339                         break;
6340
6341                 case OP_XCONV_R8_TO_I4:
6342                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6343                         switch (ins->backend.source_opcode) {
6344                         case OP_FCONV_TO_I1:
6345                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6346                                 break;
6347                         case OP_FCONV_TO_U1:
6348                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6349                                 break;
6350                         case OP_FCONV_TO_I2:
6351                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6352                                 break;
6353                         case OP_FCONV_TO_U2:
6354                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6355                                 break;
6356                         }
6357                         break;
6358
6359                 case OP_EXPAND_I2:
6360                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6361                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6362                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6363                         break;
6364                 case OP_EXPAND_I4:
6365                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6366                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6367                         break;
6368                 case OP_EXPAND_I8:
6369                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6370                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6371                         break;
6372                 case OP_EXPAND_R4:
6373                         if (cfg->r4fp) {
6374                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6375                         } else {
6376                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6377                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6378                         }
6379                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6380                         break;
6381                 case OP_EXPAND_R8:
6382                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6383                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6384                         break;
6385 #endif
6386                 case OP_LIVERANGE_START: {
6387                         if (cfg->verbose_level > 1)
6388                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6389                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6390                         break;
6391                 }
6392                 case OP_LIVERANGE_END: {
6393                         if (cfg->verbose_level > 1)
6394                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6395                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6396                         break;
6397                 }
6398                 case OP_GC_SAFE_POINT: {
6399                         guint8 *br [1];
6400
6401                         g_assert (mono_threads_is_coop_enabled ());
6402
6403                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6404                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6405                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6406                         amd64_patch (br[0], code);
6407                         break;
6408                 }
6409
6410                 case OP_GC_LIVENESS_DEF:
6411                 case OP_GC_LIVENESS_USE:
6412                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6413                         ins->backend.pc_offset = code - cfg->native_code;
6414                         break;
6415                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6416                         ins->backend.pc_offset = code - cfg->native_code;
6417                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6418                         break;
6419                 case OP_GET_LAST_ERROR:
6420                         emit_get_last_error(code, ins->dreg);
6421                         break;
6422                 default:
6423                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6424                         g_assert_not_reached ();
6425                 }
6426
6427                 if ((code - cfg->native_code - offset) > max_len) {
6428                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6429                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6430                         g_assert_not_reached ();
6431                 }
6432         }
6433
6434         cfg->code_len = code - cfg->native_code;
6435 }
6436
6437 #endif /* DISABLE_JIT */
6438
6439 void
6440 mono_arch_register_lowlevel_calls (void)
6441 {
6442         /* The signature doesn't matter */
6443         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6444
6445 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6446 #if _MSC_VER
6447         extern void __chkstk (void);
6448         mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6449 #else
6450         extern void ___chkstk_ms (void);
6451         mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6452 #endif
6453 #endif
6454 }
6455
6456 void
6457 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6458 {
6459         unsigned char *ip = ji->ip.i + code;
6460
6461         /*
6462          * Debug code to help track down problems where the target of a near call is
6463          * is not valid.
6464          */
6465         if (amd64_is_near_call (ip)) {
6466                 gint64 disp = (guint8*)target - (guint8*)ip;
6467
6468                 if (!amd64_is_imm32 (disp)) {
6469                         printf ("TYPE: %d\n", ji->type);
6470                         switch (ji->type) {
6471                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6472                                 printf ("V: %s\n", ji->data.name);
6473                                 break;
6474                         case MONO_PATCH_INFO_METHOD_JUMP:
6475                         case MONO_PATCH_INFO_METHOD:
6476                                 printf ("V: %s\n", ji->data.method->name);
6477                                 break;
6478                         default:
6479                                 break;
6480                         }
6481                 }
6482         }
6483
6484         amd64_patch (ip, (gpointer)target);
6485 }
6486
6487 #ifndef DISABLE_JIT
6488
6489 static int
6490 get_max_epilog_size (MonoCompile *cfg)
6491 {
6492         int max_epilog_size = 16;
6493
6494         if (cfg->method->save_lmf)
6495                 max_epilog_size += 256;
6496
6497         if (mono_jit_trace_calls != NULL)
6498                 max_epilog_size += 50;
6499
6500         max_epilog_size += (AMD64_NREG * 2);
6501
6502         return max_epilog_size;
6503 }
6504
6505 /*
6506  * This macro is used for testing whenever the unwinder works correctly at every point
6507  * where an async exception can happen.
6508  */
6509 /* This will generate a SIGSEGV at the given point in the code */
6510 #define async_exc_point(code) do { \
6511     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6512          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6513              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6514          cfg->arch.async_point_count ++; \
6515     } \
6516 } while (0)
6517
6518 #ifdef TARGET_WIN32
6519 static guint8 *
6520 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6521 {
6522         int cfa_offset = *cfa_offset_input;
6523
6524         /* Allocate windows stack frame using stack probing method */
6525         if (alloc_size) {
6526
6527                 if (alloc_size >= 0x1000) {
6528                         amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6529                         code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6530                 }
6531
6532                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6533                 if (cfg->arch.omit_fp) {
6534                         cfa_offset += alloc_size;
6535                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6536                         async_exc_point (code);
6537                 }
6538
6539                 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6540                 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6541                 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6542                 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6543                 // that will retrieve the expected results.
6544                 if (cfg->arch.omit_fp)
6545                         mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6546         }
6547
6548         *cfa_offset_input = cfa_offset;
6549         return code;
6550 }
6551 #endif /* TARGET_WIN32 */
6552
6553 guint8 *
6554 mono_arch_emit_prolog (MonoCompile *cfg)
6555 {
6556         MonoMethod *method = cfg->method;
6557         MonoBasicBlock *bb;
6558         MonoMethodSignature *sig;
6559         MonoInst *ins;
6560         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6561         guint8 *code;
6562         CallInfo *cinfo;
6563         MonoInst *lmf_var = cfg->lmf_var;
6564         gboolean args_clobbered = FALSE;
6565         gboolean trace = FALSE;
6566
6567         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6568
6569         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6570
6571         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6572                 trace = TRUE;
6573
6574         /* Amount of stack space allocated by register saving code */
6575         pos = 0;
6576
6577         /* Offset between RSP and the CFA */
6578         cfa_offset = 0;
6579
6580         /*
6581          * The prolog consists of the following parts:
6582          * FP present:
6583          * - push rbp
6584          * - mov rbp, rsp
6585          * - save callee saved regs using moves
6586          * - allocate frame
6587          * - save rgctx if needed
6588          * - save lmf if needed
6589          * FP not present:
6590          * - allocate frame
6591          * - save rgctx if needed
6592          * - save lmf if needed
6593          * - save callee saved regs using moves
6594          */
6595
6596         // CFA = sp + 8
6597         cfa_offset = 8;
6598         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6599         // IP saved at CFA - 8
6600         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6601         async_exc_point (code);
6602         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6603
6604         if (!cfg->arch.omit_fp) {
6605                 amd64_push_reg (code, AMD64_RBP);
6606                 cfa_offset += 8;
6607                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6608                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6609                 async_exc_point (code);
6610                 /* These are handled automatically by the stack marking code */
6611                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6612
6613                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6614                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6615                 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6616                 async_exc_point (code);
6617         }
6618
6619         /* The param area is always at offset 0 from sp */
6620         /* This needs to be allocated here, since it has to come after the spill area */
6621         if (cfg->param_area) {
6622                 if (cfg->arch.omit_fp)
6623                         // FIXME:
6624                         g_assert_not_reached ();
6625                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6626         }
6627
6628         if (cfg->arch.omit_fp) {
6629                 /*
6630                  * On enter, the stack is misaligned by the pushing of the return
6631                  * address. It is either made aligned by the pushing of %rbp, or by
6632                  * this.
6633                  */
6634                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6635                 if ((alloc_size % 16) == 0) {
6636                         alloc_size += 8;
6637                         /* Mark the padding slot as NOREF */
6638                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6639                 }
6640         } else {
6641                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6642                 if (cfg->stack_offset != alloc_size) {
6643                         /* Mark the padding slot as NOREF */
6644                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6645                 }
6646                 cfg->arch.sp_fp_offset = alloc_size;
6647                 alloc_size -= pos;
6648         }
6649
6650         cfg->arch.stack_alloc_size = alloc_size;
6651
6652         /* Allocate stack frame */
6653 #ifdef TARGET_WIN32
6654         code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6655 #else
6656         if (alloc_size) {
6657                 /* See mono_emit_stack_alloc */
6658 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6659                 guint32 remaining_size = alloc_size;
6660
6661                 /* Use a loop for large sizes */
6662                 if (remaining_size > 10 * 0x1000) {
6663                         amd64_mov_reg_imm (code, X86_EAX, remaining_size / 0x1000);
6664                         guint8 *label = code;
6665                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6666                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6667                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RAX, 1);
6668                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6669                         guint8 *label2 = code;
6670                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
6671                         amd64_patch (label2, label);
6672                         if (cfg->arch.omit_fp) {
6673                                 cfa_offset += (remaining_size / 0x1000) * 0x1000;
6674                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6675                         }
6676
6677                         remaining_size = remaining_size % 0x1000;
6678                 }
6679
6680                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6681                 guint32 offset = code - cfg->native_code;
6682                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6683                         while (required_code_size >= (cfg->code_size - offset))
6684                                 cfg->code_size *= 2;
6685                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6686                         code = cfg->native_code + offset;
6687                         cfg->stat_code_reallocs++;
6688                 }
6689
6690                 while (remaining_size >= 0x1000) {
6691                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6692                         if (cfg->arch.omit_fp) {
6693                                 cfa_offset += 0x1000;
6694                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6695                         }
6696                         async_exc_point (code);
6697
6698                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6699                         remaining_size -= 0x1000;
6700                 }
6701                 if (remaining_size) {
6702                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6703                         if (cfg->arch.omit_fp) {
6704                                 cfa_offset += remaining_size;
6705                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6706                                 async_exc_point (code);
6707                         }
6708                 }
6709 #else
6710                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6711                 if (cfg->arch.omit_fp) {
6712                         cfa_offset += alloc_size;
6713                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6714                         async_exc_point (code);
6715                 }
6716 #endif
6717         }
6718 #endif
6719
6720         /* Stack alignment check */
6721 #if 0
6722         {
6723                 guint8 *buf;
6724
6725                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6726                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6727                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6728                 buf = code;
6729                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6730                 amd64_breakpoint (code);
6731                 amd64_patch (buf, code);
6732         }
6733 #endif
6734
6735         if (mini_get_debug_options ()->init_stacks) {
6736                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6737
6738                 /* Save registers to the red zone */
6739                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6740                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6741
6742                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6743                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6744                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6745
6746                 amd64_cld (code);
6747                 amd64_prefix (code, X86_REP_PREFIX);
6748                 amd64_stosl (code);
6749
6750                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6751                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6752         }
6753
6754         /* Save LMF */
6755         if (method->save_lmf)
6756                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6757
6758         /* Save callee saved registers */
6759         if (cfg->arch.omit_fp) {
6760                 save_area_offset = cfg->arch.reg_save_area_offset;
6761                 /* Save caller saved registers after sp is adjusted */
6762                 /* The registers are saved at the bottom of the frame */
6763                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6764         } else {
6765                 /* The registers are saved just below the saved rbp */
6766                 save_area_offset = cfg->arch.reg_save_area_offset;
6767         }
6768
6769         for (i = 0; i < AMD64_NREG; ++i) {
6770                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6771                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6772
6773                         if (cfg->arch.omit_fp) {
6774                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6775                                 /* These are handled automatically by the stack marking code */
6776                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6777                         } else {
6778                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6779                                 // FIXME: GC
6780                         }
6781
6782                         save_area_offset += 8;
6783                         async_exc_point (code);
6784                 }
6785         }
6786
6787         /* store runtime generic context */
6788         if (cfg->rgctx_var) {
6789                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6790                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6791
6792                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6793
6794                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6795                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6796         }
6797
6798         /* compute max_length in order to use short forward jumps */
6799         max_epilog_size = get_max_epilog_size (cfg);
6800         if (cfg->opt & MONO_OPT_BRANCH) {
6801                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6802                         MonoInst *ins;
6803                         int max_length = 0;
6804
6805                         /* max alignment for loops */
6806                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6807                                 max_length += LOOP_ALIGNMENT;
6808
6809                         MONO_BB_FOR_EACH_INS (bb, ins) {
6810                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6811                         }
6812
6813                         /* Take prolog and epilog instrumentation into account */
6814                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6815                                 max_length += max_epilog_size;
6816
6817                         bb->max_length = max_length;
6818                 }
6819         }
6820
6821         sig = mono_method_signature (method);
6822         pos = 0;
6823
6824         cinfo = (CallInfo *)cfg->arch.cinfo;
6825
6826         if (sig->ret->type != MONO_TYPE_VOID) {
6827                 /* Save volatile arguments to the stack */
6828                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6829                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6830         }
6831
6832         /* Keep this in sync with emit_load_volatile_arguments */
6833         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6834                 ArgInfo *ainfo = cinfo->args + i;
6835
6836                 ins = cfg->args [i];
6837
6838                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6839                         /* Unused arguments */
6840                         continue;
6841
6842                 /* Save volatile arguments to the stack */
6843                 if (ins->opcode != OP_REGVAR) {
6844                         switch (ainfo->storage) {
6845                         case ArgInIReg: {
6846                                 guint32 size = 8;
6847
6848                                 /* FIXME: I1 etc */
6849                                 /*
6850                                 if (stack_offset & 0x1)
6851                                         size = 1;
6852                                 else if (stack_offset & 0x2)
6853                                         size = 2;
6854                                 else if (stack_offset & 0x4)
6855                                         size = 4;
6856                                 else
6857                                         size = 8;
6858                                 */
6859                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6860
6861                                 /*
6862                                  * Save the original location of 'this',
6863                                  * get_generic_info_from_stack_frame () needs this to properly look up
6864                                  * the argument value during the handling of async exceptions.
6865                                  */
6866                                 if (ins == cfg->args [0]) {
6867                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6868                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6869                                 }
6870                                 break;
6871                         }
6872                         case ArgInFloatSSEReg:
6873                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6874                                 break;
6875                         case ArgInDoubleSSEReg:
6876                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6877                                 break;
6878                         case ArgValuetypeInReg:
6879                                 for (quad = 0; quad < 2; quad ++) {
6880                                         switch (ainfo->pair_storage [quad]) {
6881                                         case ArgInIReg:
6882                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6883                                                 break;
6884                                         case ArgInFloatSSEReg:
6885                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6886                                                 break;
6887                                         case ArgInDoubleSSEReg:
6888                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6889                                                 break;
6890                                         case ArgNone:
6891                                                 break;
6892                                         default:
6893                                                 g_assert_not_reached ();
6894                                         }
6895                                 }
6896                                 break;
6897                         case ArgValuetypeAddrInIReg:
6898                                 if (ainfo->pair_storage [0] == ArgInIReg)
6899                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6900                                 break;
6901                         case ArgValuetypeAddrOnStack:
6902                                 break;
6903                         case ArgGSharedVtInReg:
6904                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6905                                 break;
6906                         default:
6907                                 break;
6908                         }
6909                 } else {
6910                         /* Argument allocated to (non-volatile) register */
6911                         switch (ainfo->storage) {
6912                         case ArgInIReg:
6913                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6914                                 break;
6915                         case ArgOnStack:
6916                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6917                                 break;
6918                         default:
6919                                 g_assert_not_reached ();
6920                         }
6921
6922                         if (ins == cfg->args [0]) {
6923                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6924                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6925                         }
6926                 }
6927         }
6928
6929         if (cfg->method->save_lmf)
6930                 args_clobbered = TRUE;
6931
6932         if (trace) {
6933                 args_clobbered = TRUE;
6934                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6935         }
6936
6937         /*
6938          * Optimize the common case of the first bblock making a call with the same
6939          * arguments as the method. This works because the arguments are still in their
6940          * original argument registers.
6941          * FIXME: Generalize this
6942          */
6943         if (!args_clobbered) {
6944                 MonoBasicBlock *first_bb = cfg->bb_entry;
6945                 MonoInst *next;
6946                 int filter = FILTER_IL_SEQ_POINT;
6947
6948                 next = mono_bb_first_inst (first_bb, filter);
6949                 if (!next && first_bb->next_bb) {
6950                         first_bb = first_bb->next_bb;
6951                         next = mono_bb_first_inst (first_bb, filter);
6952                 }
6953
6954                 if (first_bb->in_count > 1)
6955                         next = NULL;
6956
6957                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6958                         ArgInfo *ainfo = cinfo->args + i;
6959                         gboolean match = FALSE;
6960
6961                         ins = cfg->args [i];
6962                         if (ins->opcode != OP_REGVAR) {
6963                                 switch (ainfo->storage) {
6964                                 case ArgInIReg: {
6965                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6966                                                 if (next->dreg == ainfo->reg) {
6967                                                         NULLIFY_INS (next);
6968                                                         match = TRUE;
6969                                                 } else {
6970                                                         next->opcode = OP_MOVE;
6971                                                         next->sreg1 = ainfo->reg;
6972                                                         /* Only continue if the instruction doesn't change argument regs */
6973                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6974                                                                 match = TRUE;
6975                                                 }
6976                                         }
6977                                         break;
6978                                 }
6979                                 default:
6980                                         break;
6981                                 }
6982                         } else {
6983                                 /* Argument allocated to (non-volatile) register */
6984                                 switch (ainfo->storage) {
6985                                 case ArgInIReg:
6986                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6987                                                 NULLIFY_INS (next);
6988                                                 match = TRUE;
6989                                         }
6990                                         break;
6991                                 default:
6992                                         break;
6993                                 }
6994                         }
6995
6996                         if (match) {
6997                                 next = mono_inst_next (next, filter);
6998                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6999                                 if (!next)
7000                                         break;
7001                         }
7002                 }
7003         }
7004
7005         if (cfg->gen_sdb_seq_points) {
7006                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7007
7008                 /* Initialize seq_point_info_var */
7009                 if (cfg->compile_aot) {
7010                         /* Initialize the variable from a GOT slot */
7011                         /* Same as OP_AOTCONST */
7012                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7013                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7014                         g_assert (info_var->opcode == OP_REGOFFSET);
7015                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7016                 }
7017
7018                 if (cfg->compile_aot) {
7019                         /* Initialize ss_tramp_var */
7020                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7021                         g_assert (ins->opcode == OP_REGOFFSET);
7022
7023                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7024                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7025                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7026                 } else {
7027                         /* Initialize ss_tramp_var */
7028                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7029                         g_assert (ins->opcode == OP_REGOFFSET);
7030
7031                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7032                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7033
7034                         /* Initialize bp_tramp_var */
7035                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7036                         g_assert (ins->opcode == OP_REGOFFSET);
7037
7038                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7039                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7040                 }
7041         }
7042
7043         cfg->code_len = code - cfg->native_code;
7044
7045         g_assert (cfg->code_len < cfg->code_size);
7046
7047         return code;
7048 }
7049
7050 void
7051 mono_arch_emit_epilog (MonoCompile *cfg)
7052 {
7053         MonoMethod *method = cfg->method;
7054         int quad, i;
7055         guint8 *code;
7056         int max_epilog_size;
7057         CallInfo *cinfo;
7058         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7059         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7060
7061         max_epilog_size = get_max_epilog_size (cfg);
7062
7063         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7064                 cfg->code_size *= 2;
7065                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7066                 cfg->stat_code_reallocs++;
7067         }
7068         code = cfg->native_code + cfg->code_len;
7069
7070         cfg->has_unwind_info_for_epilog = TRUE;
7071
7072         /* Mark the start of the epilog */
7073         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7074
7075         /* Save the uwind state which is needed by the out-of-line code */
7076         mono_emit_unwind_op_remember_state (cfg, code);
7077
7078         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7079                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7080
7081         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7082
7083         if (method->save_lmf) {
7084                 /* check if we need to restore protection of the stack after a stack overflow */
7085                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7086                         guint8 *patch;
7087                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7088                         /* we load the value in a separate instruction: this mechanism may be
7089                          * used later as a safer way to do thread interruption
7090                          */
7091                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7092                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7093                         patch = code;
7094                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7095                         /* note that the call trampoline will preserve eax/edx */
7096                         x86_call_reg (code, X86_ECX);
7097                         x86_patch (patch, code);
7098                 } else {
7099                         /* FIXME: maybe save the jit tls in the prolog */
7100                 }
7101                 if (cfg->used_int_regs & (1 << AMD64_RBP))
7102                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7103                 if (cfg->arch.omit_fp)
7104                         /*
7105                          * emit_setup_lmf () marks RBP as saved, we have to mark it as same value here before clearing up the stack
7106                          * since its stack slot will become invalid.
7107                          */
7108                         mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7109         }
7110
7111         /* Restore callee saved regs */
7112         for (i = 0; i < AMD64_NREG; ++i) {
7113                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7114                         /* Restore only used_int_regs, not arch.saved_iregs */
7115 #if defined(MONO_SUPPORT_TASKLETS)
7116                         int restore_reg = 1;
7117 #else
7118                         int restore_reg = (cfg->used_int_regs & (1 << i));
7119 #endif
7120                         if (restore_reg) {
7121                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7122                                 mono_emit_unwind_op_same_value (cfg, code, i);
7123                                 async_exc_point (code);
7124                         }
7125                         save_area_offset += 8;
7126                 }
7127         }
7128
7129         /* Load returned vtypes into registers if needed */
7130         cinfo = (CallInfo *)cfg->arch.cinfo;
7131         if (cinfo->ret.storage == ArgValuetypeInReg) {
7132                 ArgInfo *ainfo = &cinfo->ret;
7133                 MonoInst *inst = cfg->ret;
7134
7135                 for (quad = 0; quad < 2; quad ++) {
7136                         switch (ainfo->pair_storage [quad]) {
7137                         case ArgInIReg:
7138                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7139                                 break;
7140                         case ArgInFloatSSEReg:
7141                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7142                                 break;
7143                         case ArgInDoubleSSEReg:
7144                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7145                                 break;
7146                         case ArgNone:
7147                                 break;
7148                         default:
7149                                 g_assert_not_reached ();
7150                         }
7151                 }
7152         }
7153
7154         if (cfg->arch.omit_fp) {
7155                 if (cfg->arch.stack_alloc_size) {
7156                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7157                 }
7158         } else {
7159 #ifdef TARGET_WIN32
7160                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7161                 amd64_pop_reg (code, AMD64_RBP);
7162                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7163 #else
7164                 amd64_leave (code);
7165                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7166 #endif
7167         }
7168         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7169         async_exc_point (code);
7170         amd64_ret (code);
7171
7172         /* Restore the unwind state to be the same as before the epilog */
7173         mono_emit_unwind_op_restore_state (cfg, code);
7174
7175         cfg->code_len = code - cfg->native_code;
7176
7177         g_assert (cfg->code_len < cfg->code_size);
7178 }
7179
7180 void
7181 mono_arch_emit_exceptions (MonoCompile *cfg)
7182 {
7183         MonoJumpInfo *patch_info;
7184         int nthrows, i;
7185         guint8 *code;
7186         MonoClass *exc_classes [16];
7187         guint8 *exc_throw_start [16], *exc_throw_end [16];
7188         guint32 code_size = 0;
7189
7190         /* Compute needed space */
7191         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7192                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7193                         code_size += 40;
7194                 if (patch_info->type == MONO_PATCH_INFO_R8)
7195                         code_size += 8 + 15; /* sizeof (double) + alignment */
7196                 if (patch_info->type == MONO_PATCH_INFO_R4)
7197                         code_size += 4 + 15; /* sizeof (float) + alignment */
7198                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7199                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7200         }
7201
7202         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7203                 cfg->code_size *= 2;
7204                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7205                 cfg->stat_code_reallocs++;
7206         }
7207
7208         code = cfg->native_code + cfg->code_len;
7209
7210         /* add code to raise exceptions */
7211         nthrows = 0;
7212         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7213                 switch (patch_info->type) {
7214                 case MONO_PATCH_INFO_EXC: {
7215                         MonoClass *exc_class;
7216                         guint8 *buf, *buf2;
7217                         guint32 throw_ip;
7218
7219                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7220
7221                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7222                         throw_ip = patch_info->ip.i;
7223
7224                         //x86_breakpoint (code);
7225                         /* Find a throw sequence for the same exception class */
7226                         for (i = 0; i < nthrows; ++i)
7227                                 if (exc_classes [i] == exc_class)
7228                                         break;
7229                         if (i < nthrows) {
7230                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7231                                 x86_jump_code (code, exc_throw_start [i]);
7232                                 patch_info->type = MONO_PATCH_INFO_NONE;
7233                         }
7234                         else {
7235                                 buf = code;
7236                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7237                                 buf2 = code;
7238
7239                                 if (nthrows < 16) {
7240                                         exc_classes [nthrows] = exc_class;
7241                                         exc_throw_start [nthrows] = code;
7242                                 }
7243                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7244
7245                                 patch_info->type = MONO_PATCH_INFO_NONE;
7246
7247                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7248
7249                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7250                                 while (buf < buf2)
7251                                         x86_nop (buf);
7252
7253                                 if (nthrows < 16) {
7254                                         exc_throw_end [nthrows] = code;
7255                                         nthrows ++;
7256                                 }
7257                         }
7258                         break;
7259                 }
7260                 default:
7261                         /* do nothing */
7262                         break;
7263                 }
7264                 g_assert(code < cfg->native_code + cfg->code_size);
7265         }
7266
7267         /* Handle relocations with RIP relative addressing */
7268         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7269                 gboolean remove = FALSE;
7270                 guint8 *orig_code = code;
7271
7272                 switch (patch_info->type) {
7273                 case MONO_PATCH_INFO_R8:
7274                 case MONO_PATCH_INFO_R4: {
7275                         guint8 *pos, *patch_pos;
7276                         guint32 target_pos;
7277
7278                         /* The SSE opcodes require a 16 byte alignment */
7279                         code = (guint8*)ALIGN_TO (code, 16);
7280
7281                         pos = cfg->native_code + patch_info->ip.i;
7282                         if (IS_REX (pos [1])) {
7283                                 patch_pos = pos + 5;
7284                                 target_pos = code - pos - 9;
7285                         }
7286                         else {
7287                                 patch_pos = pos + 4;
7288                                 target_pos = code - pos - 8;
7289                         }
7290
7291                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7292                                 *(double*)code = *(double*)patch_info->data.target;
7293                                 code += sizeof (double);
7294                         } else {
7295                                 *(float*)code = *(float*)patch_info->data.target;
7296                                 code += sizeof (float);
7297                         }
7298
7299                         *(guint32*)(patch_pos) = target_pos;
7300
7301                         remove = TRUE;
7302                         break;
7303                 }
7304                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7305                         guint8 *pos;
7306
7307                         if (cfg->compile_aot)
7308                                 continue;
7309
7310                         /*loading is faster against aligned addresses.*/
7311                         code = (guint8*)ALIGN_TO (code, 8);
7312                         memset (orig_code, 0, code - orig_code);
7313
7314                         pos = cfg->native_code + patch_info->ip.i;
7315
7316                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7317                         if (IS_REX (pos [1]))
7318                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7319                         else
7320                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7321
7322                         *(gpointer*)code = (gpointer)patch_info->data.target;
7323                         code += sizeof (gpointer);
7324
7325                         remove = TRUE;
7326                         break;
7327                 }
7328                 default:
7329                         break;
7330                 }
7331
7332                 if (remove) {
7333                         if (patch_info == cfg->patch_info)
7334                                 cfg->patch_info = patch_info->next;
7335                         else {
7336                                 MonoJumpInfo *tmp;
7337
7338                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7339                                         ;
7340                                 tmp->next = patch_info->next;
7341                         }
7342                 }
7343                 g_assert (code < cfg->native_code + cfg->code_size);
7344         }
7345
7346         cfg->code_len = code - cfg->native_code;
7347
7348         g_assert (cfg->code_len < cfg->code_size);
7349
7350 }
7351
7352 #endif /* DISABLE_JIT */
7353
7354 void*
7355 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7356 {
7357         guchar *code = (guchar *)p;
7358         MonoMethodSignature *sig;
7359         MonoInst *inst;
7360         int i, n, stack_area = 0;
7361
7362         /* Keep this in sync with mono_arch_get_argument_info */
7363
7364         if (enable_arguments) {
7365                 /* Allocate a new area on the stack and save arguments there */
7366                 sig = mono_method_signature (cfg->method);
7367
7368                 n = sig->param_count + sig->hasthis;
7369
7370                 stack_area = ALIGN_TO (n * 8, 16);
7371
7372                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7373
7374                 for (i = 0; i < n; ++i) {
7375                         inst = cfg->args [i];
7376
7377                         if (inst->opcode == OP_REGVAR)
7378                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7379                         else {
7380                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7381                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7382                         }
7383                 }
7384         }
7385
7386         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7387         amd64_set_reg_template (code, AMD64_ARG_REG1);
7388         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7389         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7390
7391         if (enable_arguments)
7392                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7393
7394         return code;
7395 }
7396
7397 enum {
7398         SAVE_NONE,
7399         SAVE_STRUCT,
7400         SAVE_EAX,
7401         SAVE_EAX_EDX,
7402         SAVE_XMM
7403 };
7404
7405 void*
7406 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7407 {
7408         guchar *code = (guchar *)p;
7409         int save_mode = SAVE_NONE;
7410         MonoMethod *method = cfg->method;
7411         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7412         int i;
7413
7414         switch (ret_type->type) {
7415         case MONO_TYPE_VOID:
7416                 /* special case string .ctor icall */
7417                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7418                         save_mode = SAVE_EAX;
7419                 else
7420                         save_mode = SAVE_NONE;
7421                 break;
7422         case MONO_TYPE_I8:
7423         case MONO_TYPE_U8:
7424                 save_mode = SAVE_EAX;
7425                 break;
7426         case MONO_TYPE_R4:
7427         case MONO_TYPE_R8:
7428                 save_mode = SAVE_XMM;
7429                 break;
7430         case MONO_TYPE_GENERICINST:
7431                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7432                         save_mode = SAVE_EAX;
7433                         break;
7434                 }
7435                 /* Fall through */
7436         case MONO_TYPE_VALUETYPE:
7437                 save_mode = SAVE_STRUCT;
7438                 break;
7439         default:
7440                 save_mode = SAVE_EAX;
7441                 break;
7442         }
7443
7444         /* Save the result and copy it into the proper argument register */
7445         switch (save_mode) {
7446         case SAVE_EAX:
7447                 amd64_push_reg (code, AMD64_RAX);
7448                 /* Align stack */
7449                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7450                 if (enable_arguments)
7451                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7452                 break;
7453         case SAVE_STRUCT:
7454                 /* FIXME: */
7455                 if (enable_arguments)
7456                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7457                 break;
7458         case SAVE_XMM:
7459                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7460                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7461                 /* Align stack */
7462                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7463                 /*
7464                  * The result is already in the proper argument register so no copying
7465                  * needed.
7466                  */
7467                 break;
7468         case SAVE_NONE:
7469                 break;
7470         default:
7471                 g_assert_not_reached ();
7472         }
7473
7474         /* Set %al since this is a varargs call */
7475         if (save_mode == SAVE_XMM)
7476                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7477         else
7478                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7479
7480         if (preserve_argument_registers) {
7481                 for (i = 0; i < PARAM_REGS; ++i)
7482                         amd64_push_reg (code, param_regs [i]);
7483         }
7484
7485         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7486         amd64_set_reg_template (code, AMD64_ARG_REG1);
7487         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7488
7489         if (preserve_argument_registers) {
7490                 for (i = PARAM_REGS - 1; i >= 0; --i)
7491                         amd64_pop_reg (code, param_regs [i]);
7492         }
7493
7494         /* Restore result */
7495         switch (save_mode) {
7496         case SAVE_EAX:
7497                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7498                 amd64_pop_reg (code, AMD64_RAX);
7499                 break;
7500         case SAVE_STRUCT:
7501                 /* FIXME: */
7502                 break;
7503         case SAVE_XMM:
7504                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7505                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7506                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7507                 break;
7508         case SAVE_NONE:
7509                 break;
7510         default:
7511                 g_assert_not_reached ();
7512         }
7513
7514         return code;
7515 }
7516
7517 void
7518 mono_arch_flush_icache (guint8 *code, gint size)
7519 {
7520         /* Not needed */
7521 }
7522
7523 void
7524 mono_arch_flush_register_windows (void)
7525 {
7526 }
7527
7528 gboolean
7529 mono_arch_is_inst_imm (gint64 imm)
7530 {
7531         return amd64_use_imm32 (imm);
7532 }
7533
7534 /*
7535  * Determine whenever the trap whose info is in SIGINFO is caused by
7536  * integer overflow.
7537  */
7538 gboolean
7539 mono_arch_is_int_overflow (void *sigctx, void *info)
7540 {
7541         MonoContext ctx;
7542         guint8* rip;
7543         int reg;
7544         gint64 value;
7545
7546         mono_sigctx_to_monoctx (sigctx, &ctx);
7547
7548         rip = (guint8*)ctx.gregs [AMD64_RIP];
7549
7550         if (IS_REX (rip [0])) {
7551                 reg = amd64_rex_b (rip [0]);
7552                 rip ++;
7553         }
7554         else
7555                 reg = 0;
7556
7557         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7558                 /* idiv REG */
7559                 reg += x86_modrm_rm (rip [1]);
7560
7561                 value = ctx.gregs [reg];
7562
7563                 if (value == -1)
7564                         return TRUE;
7565         }
7566
7567         return FALSE;
7568 }
7569
7570 guint32
7571 mono_arch_get_patch_offset (guint8 *code)
7572 {
7573         return 3;
7574 }
7575
7576 /**
7577  * \return TRUE if no sw breakpoint was present.
7578  *
7579  * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7580  * breakpoints in the original code, they are removed in the copy.
7581  */
7582 gboolean
7583 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7584 {
7585         /*
7586          * If method_start is non-NULL we need to perform bound checks, since we access memory
7587          * at code - offset we could go before the start of the method and end up in a different
7588          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7589          * instead.
7590          */
7591         if (!method_start || code - offset >= method_start) {
7592                 memcpy (buf, code - offset, size);
7593         } else {
7594                 int diff = code - method_start;
7595                 memset (buf, 0, size);
7596                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7597         }
7598         return TRUE;
7599 }
7600
7601 int
7602 mono_arch_get_this_arg_reg (guint8 *code)
7603 {
7604         return AMD64_ARG_REG1;
7605 }
7606
7607 gpointer
7608 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7609 {
7610         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7611 }
7612
7613 #define MAX_ARCH_DELEGATE_PARAMS 10
7614
7615 static gpointer
7616 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7617 {
7618         guint8 *code, *start;
7619         GSList *unwind_ops = NULL;
7620         int i;
7621
7622         unwind_ops = mono_arch_get_cie_program ();
7623
7624         if (has_target) {
7625                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7626
7627                 /* Replace the this argument with the target */
7628                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7629                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7630                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7631
7632                 g_assert ((code - start) < 64);
7633                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7634         } else {
7635                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7636
7637                 if (param_count == 0) {
7638                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7639                 } else {
7640                         /* We have to shift the arguments left */
7641                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7642                         for (i = 0; i < param_count; ++i) {
7643 #ifdef TARGET_WIN32
7644                                 if (i < 3)
7645                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7646                                 else
7647                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7648 #else
7649                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7650 #endif
7651                         }
7652
7653                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7654                 }
7655                 g_assert ((code - start) < 64);
7656                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7657         }
7658
7659         mono_arch_flush_icache (start, code - start);
7660
7661         if (has_target) {
7662                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7663         } else {
7664                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7665                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7666                 g_free (name);
7667         }
7668
7669         if (mono_jit_map_is_enabled ()) {
7670                 char *buff;
7671                 if (has_target)
7672                         buff = (char*)"delegate_invoke_has_target";
7673                 else
7674                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7675                 mono_emit_jit_tramp (start, code - start, buff);
7676                 if (!has_target)
7677                         g_free (buff);
7678         }
7679         MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7680
7681         return start;
7682 }
7683
7684 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7685
7686 static gpointer
7687 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7688 {
7689         guint8 *code, *start;
7690         int size = 20;
7691         char *tramp_name;
7692         GSList *unwind_ops;
7693
7694         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7695                 return NULL;
7696
7697         start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7698
7699         unwind_ops = mono_arch_get_cie_program ();
7700
7701         /* Replace the this argument with the target */
7702         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7703         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7704
7705         if (load_imt_reg) {
7706                 /* Load the IMT reg */
7707                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7708         }
7709
7710         /* Load the vtable */
7711         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7712         amd64_jump_membase (code, AMD64_RAX, offset);
7713         MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7714
7715         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7716         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7717         g_free (tramp_name);
7718
7719         return start;
7720 }
7721
7722 /*
7723  * mono_arch_get_delegate_invoke_impls:
7724  *
7725  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7726  * trampolines.
7727  */
7728 GSList*
7729 mono_arch_get_delegate_invoke_impls (void)
7730 {
7731         GSList *res = NULL;
7732         MonoTrampInfo *info;
7733         int i;
7734
7735         get_delegate_invoke_impl (&info, TRUE, 0);
7736         res = g_slist_prepend (res, info);
7737
7738         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7739                 get_delegate_invoke_impl (&info, FALSE, i);
7740                 res = g_slist_prepend (res, info);
7741         }
7742
7743         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7744                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7745                 res = g_slist_prepend (res, info);
7746         }
7747
7748         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7749                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7750                 res = g_slist_prepend (res, info);
7751                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7752                 res = g_slist_prepend (res, info);
7753         }
7754
7755         return res;
7756 }
7757
7758 gpointer
7759 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7760 {
7761         guint8 *code, *start;
7762         int i;
7763
7764         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7765                 return NULL;
7766
7767         /* FIXME: Support more cases */
7768         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7769                 return NULL;
7770
7771         if (has_target) {
7772                 static guint8* cached = NULL;
7773
7774                 if (cached)
7775                         return cached;
7776
7777                 if (mono_aot_only) {
7778                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7779                 } else {
7780                         MonoTrampInfo *info;
7781                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7782                         mono_tramp_info_register (info, NULL);
7783                 }
7784
7785                 mono_memory_barrier ();
7786
7787                 cached = start;
7788         } else {
7789                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7790                 for (i = 0; i < sig->param_count; ++i)
7791                         if (!mono_is_regsize_var (sig->params [i]))
7792                                 return NULL;
7793                 if (sig->param_count > 4)
7794                         return NULL;
7795
7796                 code = cache [sig->param_count];
7797                 if (code)
7798                         return code;
7799
7800                 if (mono_aot_only) {
7801                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7802                         start = (guint8 *)mono_aot_get_trampoline (name);
7803                         g_free (name);
7804                 } else {
7805                         MonoTrampInfo *info;
7806                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7807                         mono_tramp_info_register (info, NULL);
7808                 }
7809
7810                 mono_memory_barrier ();
7811
7812                 cache [sig->param_count] = start;
7813         }
7814
7815         return start;
7816 }
7817
7818 gpointer
7819 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7820 {
7821         MonoTrampInfo *info;
7822         gpointer code;
7823
7824         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7825         if (code)
7826                 mono_tramp_info_register (info, NULL);
7827         return code;
7828 }
7829
7830 void
7831 mono_arch_finish_init (void)
7832 {
7833 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7834         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7835 #endif
7836 }
7837
7838 void
7839 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7840 {
7841 }
7842
7843 #define CMP_SIZE (6 + 1)
7844 #define CMP_REG_REG_SIZE (4 + 1)
7845 #define BR_SMALL_SIZE 2
7846 #define BR_LARGE_SIZE 6
7847 #define MOV_REG_IMM_SIZE 10
7848 #define MOV_REG_IMM_32BIT_SIZE 6
7849 #define JUMP_REG_SIZE (2 + 1)
7850
7851 static int
7852 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7853 {
7854         int i, distance = 0;
7855         for (i = start; i < target; ++i)
7856                 distance += imt_entries [i]->chunk_size;
7857         return distance;
7858 }
7859
7860 /*
7861  * LOCKING: called with the domain lock held
7862  */
7863 gpointer
7864 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7865         gpointer fail_tramp)
7866 {
7867         int i;
7868         int size = 0;
7869         guint8 *code, *start;
7870         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7871         GSList *unwind_ops;
7872
7873         for (i = 0; i < count; ++i) {
7874                 MonoIMTCheckItem *item = imt_entries [i];
7875                 if (item->is_equals) {
7876                         if (item->check_target_idx) {
7877                                 if (!item->compare_done) {
7878                                         if (amd64_use_imm32 ((gint64)item->key))
7879                                                 item->chunk_size += CMP_SIZE;
7880                                         else
7881                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7882                                 }
7883                                 if (item->has_target_code) {
7884                                         item->chunk_size += MOV_REG_IMM_SIZE;
7885                                 } else {
7886                                         if (vtable_is_32bit)
7887                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7888                                         else
7889                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7890                                 }
7891                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7892                         } else {
7893                                 if (fail_tramp) {
7894                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7895                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7896                                 } else {
7897                                         if (vtable_is_32bit)
7898                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7899                                         else
7900                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7901                                         item->chunk_size += JUMP_REG_SIZE;
7902                                         /* with assert below:
7903                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7904                                          */
7905                                 }
7906                         }
7907                 } else {
7908                         if (amd64_use_imm32 ((gint64)item->key))
7909                                 item->chunk_size += CMP_SIZE;
7910                         else
7911                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7912                         item->chunk_size += BR_LARGE_SIZE;
7913                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7914                 }
7915                 size += item->chunk_size;
7916         }
7917         if (fail_tramp)
7918                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7919         else
7920                 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7921         start = code;
7922
7923         unwind_ops = mono_arch_get_cie_program ();
7924
7925         for (i = 0; i < count; ++i) {
7926                 MonoIMTCheckItem *item = imt_entries [i];
7927                 item->code_target = code;
7928                 if (item->is_equals) {
7929                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7930
7931                         if (item->check_target_idx || fail_case) {
7932                                 if (!item->compare_done || fail_case) {
7933                                         if (amd64_use_imm32 ((gint64)item->key))
7934                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7935                                         else {
7936                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7937                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7938                                         }
7939                                 }
7940                                 item->jmp_code = code;
7941                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7942                                 if (item->has_target_code) {
7943                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7944                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7945                                 } else {
7946                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7947                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7948                                 }
7949
7950                                 if (fail_case) {
7951                                         amd64_patch (item->jmp_code, code);
7952                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7953                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7954                                         item->jmp_code = NULL;
7955                                 }
7956                         } else {
7957                                 /* enable the commented code to assert on wrong method */
7958 #if 0
7959                                 if (amd64_is_imm32 (item->key))
7960                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7961                                 else {
7962                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7963                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7964                                 }
7965                                 item->jmp_code = code;
7966                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7967                                 /* See the comment below about R10 */
7968                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7969                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7970                                 amd64_patch (item->jmp_code, code);
7971                                 amd64_breakpoint (code);
7972                                 item->jmp_code = NULL;
7973 #else
7974                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7975                                    needs to be preserved.  R10 needs
7976                                    to be preserved for calls which
7977                                    require a runtime generic context,
7978                                    but interface calls don't. */
7979                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7980                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7981 #endif
7982                         }
7983                 } else {
7984                         if (amd64_use_imm32 ((gint64)item->key))
7985                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7986                         else {
7987                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7988                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7989                         }
7990                         item->jmp_code = code;
7991                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7992                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7993                         else
7994                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7995                 }
7996                 g_assert (code - item->code_target <= item->chunk_size);
7997         }
7998         /* patch the branches to get to the target items */
7999         for (i = 0; i < count; ++i) {
8000                 MonoIMTCheckItem *item = imt_entries [i];
8001                 if (item->jmp_code) {
8002                         if (item->check_target_idx) {
8003                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8004                         }
8005                 }
8006         }
8007
8008         if (!fail_tramp)
8009                 mono_stats.imt_trampolines_size += code - start;
8010         g_assert (code - start <= size);
8011         g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8012
8013         MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
8014
8015         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8016
8017         return start;
8018 }
8019
8020 MonoMethod*
8021 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8022 {
8023         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8024 }
8025
8026 MonoVTable*
8027 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8028 {
8029         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8030 }
8031
8032 GSList*
8033 mono_arch_get_cie_program (void)
8034 {
8035         GSList *l = NULL;
8036
8037         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8038         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8039
8040         return l;
8041 }
8042
8043 #ifndef DISABLE_JIT
8044
8045 MonoInst*
8046 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8047 {
8048         MonoInst *ins = NULL;
8049         int opcode = 0;
8050
8051         if (cmethod->klass == mono_defaults.math_class) {
8052                 if (strcmp (cmethod->name, "Sin") == 0) {
8053                         opcode = OP_SIN;
8054                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8055                         opcode = OP_COS;
8056                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8057                         opcode = OP_SQRT;
8058                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8059                         opcode = OP_ABS;
8060                 }
8061
8062                 if (opcode && fsig->param_count == 1) {
8063                         MONO_INST_NEW (cfg, ins, opcode);
8064                         ins->type = STACK_R8;
8065                         ins->dreg = mono_alloc_freg (cfg);
8066                         ins->sreg1 = args [0]->dreg;
8067                         MONO_ADD_INS (cfg->cbb, ins);
8068                 }
8069
8070                 opcode = 0;
8071                 if (cfg->opt & MONO_OPT_CMOV) {
8072                         if (strcmp (cmethod->name, "Min") == 0) {
8073                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8074                                         opcode = OP_IMIN;
8075                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8076                                         opcode = OP_IMIN_UN;
8077                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8078                                         opcode = OP_LMIN;
8079                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8080                                         opcode = OP_LMIN_UN;
8081                         } else if (strcmp (cmethod->name, "Max") == 0) {
8082                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8083                                         opcode = OP_IMAX;
8084                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8085                                         opcode = OP_IMAX_UN;
8086                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8087                                         opcode = OP_LMAX;
8088                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8089                                         opcode = OP_LMAX_UN;
8090                         }
8091                 }
8092
8093                 if (opcode && fsig->param_count == 2) {
8094                         MONO_INST_NEW (cfg, ins, opcode);
8095                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8096                         ins->dreg = mono_alloc_ireg (cfg);
8097                         ins->sreg1 = args [0]->dreg;
8098                         ins->sreg2 = args [1]->dreg;
8099                         MONO_ADD_INS (cfg->cbb, ins);
8100                 }
8101
8102 #if 0
8103                 /* OP_FREM is not IEEE compatible */
8104                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8105                         MONO_INST_NEW (cfg, ins, OP_FREM);
8106                         ins->inst_i0 = args [0];
8107                         ins->inst_i1 = args [1];
8108                 }
8109 #endif
8110         }
8111
8112         return ins;
8113 }
8114 #endif
8115
8116 gboolean
8117 mono_arch_print_tree (MonoInst *tree, int arity)
8118 {
8119         return 0;
8120 }
8121
8122 mgreg_t
8123 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8124 {
8125         return ctx->gregs [reg];
8126 }
8127
8128 void
8129 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8130 {
8131         ctx->gregs [reg] = val;
8132 }
8133
8134 /*
8135  * mono_arch_emit_load_aotconst:
8136  *
8137  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8138  * TARGET from the mscorlib GOT in full-aot code.
8139  * On AMD64, the result is placed into R11.
8140  */
8141 guint8*
8142 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8143 {
8144         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8145         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8146
8147         return code;
8148 }
8149
8150 /*
8151  * mono_arch_get_trampolines:
8152  *
8153  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8154  * for AOT.
8155  */
8156 GSList *
8157 mono_arch_get_trampolines (gboolean aot)
8158 {
8159         return mono_amd64_get_exception_trampolines (aot);
8160 }
8161
8162 /* Soft Debug support */
8163 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8164
8165 /*
8166  * mono_arch_set_breakpoint:
8167  *
8168  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8169  * The location should contain code emitted by OP_SEQ_POINT.
8170  */
8171 void
8172 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8173 {
8174         guint8 *code = ip;
8175
8176         if (ji->from_aot) {
8177                 guint32 native_offset = ip - (guint8*)ji->code_start;
8178                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8179
8180                 g_assert (info->bp_addrs [native_offset] == 0);
8181                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8182         } else {
8183                 /* ip points to a mov r11, 0 */
8184                 g_assert (code [0] == 0x41);
8185                 g_assert (code [1] == 0xbb);
8186                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8187         }
8188 }
8189
8190 /*
8191  * mono_arch_clear_breakpoint:
8192  *
8193  *   Clear the breakpoint at IP.
8194  */
8195 void
8196 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8197 {
8198         guint8 *code = ip;
8199
8200         if (ji->from_aot) {
8201                 guint32 native_offset = ip - (guint8*)ji->code_start;
8202                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8203
8204                 info->bp_addrs [native_offset] = NULL;
8205         } else {
8206                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8207         }
8208 }
8209
8210 gboolean
8211 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8212 {
8213         /* We use soft breakpoints on amd64 */
8214         return FALSE;
8215 }
8216
8217 /*
8218  * mono_arch_skip_breakpoint:
8219  *
8220  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8221  * we resume, the instruction is not executed again.
8222  */
8223 void
8224 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8225 {
8226         g_assert_not_reached ();
8227 }
8228
8229 /*
8230  * mono_arch_start_single_stepping:
8231  *
8232  *   Start single stepping.
8233  */
8234 void
8235 mono_arch_start_single_stepping (void)
8236 {
8237         ss_trampoline = mini_get_single_step_trampoline ();
8238 }
8239
8240 /*
8241  * mono_arch_stop_single_stepping:
8242  *
8243  *   Stop single stepping.
8244  */
8245 void
8246 mono_arch_stop_single_stepping (void)
8247 {
8248         ss_trampoline = NULL;
8249 }
8250
8251 /*
8252  * mono_arch_is_single_step_event:
8253  *
8254  *   Return whenever the machine state in SIGCTX corresponds to a single
8255  * step event.
8256  */
8257 gboolean
8258 mono_arch_is_single_step_event (void *info, void *sigctx)
8259 {
8260         /* We use soft breakpoints on amd64 */
8261         return FALSE;
8262 }
8263
8264 /*
8265  * mono_arch_skip_single_step:
8266  *
8267  *   Modify CTX so the ip is placed after the single step trigger instruction,
8268  * we resume, the instruction is not executed again.
8269  */
8270 void
8271 mono_arch_skip_single_step (MonoContext *ctx)
8272 {
8273         g_assert_not_reached ();
8274 }
8275
8276 /*
8277  * mono_arch_create_seq_point_info:
8278  *
8279  *   Return a pointer to a data structure which is used by the sequence
8280  * point implementation in AOTed code.
8281  */
8282 gpointer
8283 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8284 {
8285         SeqPointInfo *info;
8286         MonoJitInfo *ji;
8287
8288         // FIXME: Add a free function
8289
8290         mono_domain_lock (domain);
8291         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8292                                                                 code);
8293         mono_domain_unlock (domain);
8294
8295         if (!info) {
8296                 ji = mono_jit_info_table_find (domain, (char*)code);
8297                 g_assert (ji);
8298
8299                 // FIXME: Optimize the size
8300                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8301
8302                 info->ss_tramp_addr = &ss_trampoline;
8303
8304                 mono_domain_lock (domain);
8305                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8306                                                          code, info);
8307                 mono_domain_unlock (domain);
8308         }
8309
8310         return info;
8311 }
8312
8313 void
8314 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8315 {
8316         ext->lmf.previous_lmf = prev_lmf;
8317         /* Mark that this is a MonoLMFExt */
8318         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8319         ext->lmf.rsp = (gssize)ext;
8320 }
8321
8322 #endif
8323
8324 gboolean
8325 mono_arch_opcode_supported (int opcode)
8326 {
8327         switch (opcode) {
8328         case OP_ATOMIC_ADD_I4:
8329         case OP_ATOMIC_ADD_I8:
8330         case OP_ATOMIC_EXCHANGE_I4:
8331         case OP_ATOMIC_EXCHANGE_I8:
8332         case OP_ATOMIC_CAS_I4:
8333         case OP_ATOMIC_CAS_I8:
8334         case OP_ATOMIC_LOAD_I1:
8335         case OP_ATOMIC_LOAD_I2:
8336         case OP_ATOMIC_LOAD_I4:
8337         case OP_ATOMIC_LOAD_I8:
8338         case OP_ATOMIC_LOAD_U1:
8339         case OP_ATOMIC_LOAD_U2:
8340         case OP_ATOMIC_LOAD_U4:
8341         case OP_ATOMIC_LOAD_U8:
8342         case OP_ATOMIC_LOAD_R4:
8343         case OP_ATOMIC_LOAD_R8:
8344         case OP_ATOMIC_STORE_I1:
8345         case OP_ATOMIC_STORE_I2:
8346         case OP_ATOMIC_STORE_I4:
8347         case OP_ATOMIC_STORE_I8:
8348         case OP_ATOMIC_STORE_U1:
8349         case OP_ATOMIC_STORE_U2:
8350         case OP_ATOMIC_STORE_U4:
8351         case OP_ATOMIC_STORE_U8:
8352         case OP_ATOMIC_STORE_R4:
8353         case OP_ATOMIC_STORE_R8:
8354                 return TRUE;
8355         default:
8356                 return FALSE;
8357         }
8358 }
8359
8360 CallInfo*
8361 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8362 {
8363         return get_call_info (mp, sig);
8364 }