mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         int nregs;
 506 } ArgInfo;
 507
 508 typedef struct {
 509         int nargs;
 510         guint32 stack_usage;
 511         guint32 reg_usage;
 512         guint32 freg_usage;
 513         gboolean need_stack_align;
 514         gboolean vtype_retaddr;
 515         /* The index of the vret arg in the argument list */
 516         int vret_arg_index;
 517         ArgInfo ret;
 518         ArgInfo sig_cookie;
 519         ArgInfo args [1];
 520 } CallInfo;
 521
 522 #define DEBUG(a) if (cfg->verbose_level > 1) a
 523
 524 #ifdef HOST_WIN32
 525 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 526
 527 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 528 #else
 529 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 530
 531  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 532 #endif
 533
 534 static void inline
 535 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 536 {
 537     ainfo->offset = *stack_size;
 538
 539     if (*gr >= PARAM_REGS) {
 540                 ainfo->storage = ArgOnStack;
 541                 /* Since the same stack slot size is used for all arg */
 542                 /*  types, it needs to be big enough to hold them all */
 543                 (*stack_size) += sizeof(mgreg_t);
 544     }
 545     else {
 546                 ainfo->storage = ArgInIReg;
 547                 ainfo->reg = param_regs [*gr];
 548                 (*gr) ++;
 549     }
 550 }
 551
 552 #ifdef HOST_WIN32
 553 #define FLOAT_PARAM_REGS 4
 554 #else
 555 #define FLOAT_PARAM_REGS 8
 556 #endif
 557
 558 static void inline
 559 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 560 {
 561     ainfo->offset = *stack_size;
 562
 563     if (*gr >= FLOAT_PARAM_REGS) {
 564                 ainfo->storage = ArgOnStack;
 565                 /* Since the same stack slot size is used for both float */
 566                 /*  types, it needs to be big enough to hold them both */
 567                 (*stack_size) += sizeof(mgreg_t);
 568     }
 569     else {
 570                 /* A double register */
 571                 if (is_double)
 572                         ainfo->storage = ArgInDoubleSSEReg;
 573                 else
 574                         ainfo->storage = ArgInFloatSSEReg;
 575                 ainfo->reg = *gr;
 576                 (*gr) += 1;
 577     }
 578 }
 579
 580 typedef enum ArgumentClass {
 581         ARG_CLASS_NO_CLASS,
 582         ARG_CLASS_MEMORY,
 583         ARG_CLASS_INTEGER,
 584         ARG_CLASS_SSE
 585 } ArgumentClass;
 586
 587 static ArgumentClass
 588 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 589 {
 590         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 591         MonoType *ptype;
 592
 593         ptype = mini_type_get_underlying_type (gsctx, type);
 594         switch (ptype->type) {
 595         case MONO_TYPE_BOOLEAN:
 596         case MONO_TYPE_CHAR:
 597         case MONO_TYPE_I1:
 598         case MONO_TYPE_U1:
 599         case MONO_TYPE_I2:
 600         case MONO_TYPE_U2:
 601         case MONO_TYPE_I4:
 602         case MONO_TYPE_U4:
 603         case MONO_TYPE_I:
 604         case MONO_TYPE_U:
 605         case MONO_TYPE_STRING:
 606         case MONO_TYPE_OBJECT:
 607         case MONO_TYPE_CLASS:
 608         case MONO_TYPE_SZARRAY:
 609         case MONO_TYPE_PTR:
 610         case MONO_TYPE_FNPTR:
 611         case MONO_TYPE_ARRAY:
 612         case MONO_TYPE_I8:
 613         case MONO_TYPE_U8:
 614                 class2 = ARG_CLASS_INTEGER;
 615                 break;
 616         case MONO_TYPE_R4:
 617         case MONO_TYPE_R8:
 618 #ifdef HOST_WIN32
 619                 class2 = ARG_CLASS_INTEGER;
 620 #else
 621                 class2 = ARG_CLASS_SSE;
 622 #endif
 623                 break;
 624
 625         case MONO_TYPE_TYPEDBYREF:
 626                 g_assert_not_reached ();
 627
 628         case MONO_TYPE_GENERICINST:
 629                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 630                         class2 = ARG_CLASS_INTEGER;
 631                         break;
 632                 }
 633                 /* fall through */
 634         case MONO_TYPE_VALUETYPE: {
 635                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 636                 int i;
 637
 638                 for (i = 0; i < info->num_fields; ++i) {
 639                         class2 = class1;
 640                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 641                 }
 642                 break;
 643         }
 644         default:
 645                 g_assert_not_reached ();
 646         }
 647
 648         /* Merge */
 649         if (class1 == class2)
 650                 ;
 651         else if (class1 == ARG_CLASS_NO_CLASS)
 652                 class1 = class2;
 653         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 654                 class1 = ARG_CLASS_MEMORY;
 655         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 656                 class1 = ARG_CLASS_INTEGER;
 657         else
 658                 class1 = ARG_CLASS_SSE;
 659
 660         return class1;
 661 }
 662 #ifdef __native_client_codegen__
 663
 664 /* Default alignment for Native Client is 32-byte. */
 665 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 666
 667 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 668 /* Check that alignment doesn't cross an alignment boundary.             */
 669 guint8*
 670 mono_arch_nacl_pad(guint8 *code, int pad)
 671 {
 672         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 673
 674         if (pad == 0) return code;
 675         /* assertion: alignment cannot cross a block boundary */
 676         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 677                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 678         while (pad >= kMaxPadding) {
 679                 amd64_padding (code, kMaxPadding);
 680                 pad -= kMaxPadding;
 681         }
 682         if (pad != 0) amd64_padding (code, pad);
 683         return code;
 684 }
 685 #endif
 686
 687 static void
 688 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 689                            gboolean is_return,
 690                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 691 {
 692         guint32 size, quad, nquads, i;
 693         /* Keep track of the size used in each quad so we can */
 694         /* use the right size when copying args/return vars.  */
 695         guint32 quadsize [2] = {8, 8};
 696         ArgumentClass args [2];
 697         MonoMarshalType *info = NULL;
 698         MonoClass *klass;
 699         MonoGenericSharingContext tmp_gsctx;
 700         gboolean pass_on_stack = FALSE;
 701
 702         /*
 703          * The gsctx currently contains no data, it is only used for checking whenever
 704          * open types are allowed, some callers like mono_arch_get_argument_info ()
 705          * don't pass it to us, so work around that.
 706          */
 707         if (!gsctx)
 708                 gsctx = &tmp_gsctx;
 709
 710         klass = mono_class_from_mono_type (type);
 711         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 712 #ifndef HOST_WIN32
 713         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 714                 /* We pass and return vtypes of size 8 in a register */
 715         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 716                 pass_on_stack = TRUE;
 717         }
 718 #else
 719         if (!sig->pinvoke) {
 720                 pass_on_stack = TRUE;
 721         }
 722 #endif
 723
 724         /* If this struct can't be split up naturally into 8-byte */
 725         /* chunks (registers), pass it on the stack.              */
 726         if (sig->pinvoke && !pass_on_stack) {
 727                 guint32 align;
 728                 guint32 field_size;
 729
 730                 info = mono_marshal_load_type_info (klass);
 731                 g_assert(info);
 732                 for (i = 0; i < info->num_fields; ++i) {
 733                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 734                                                            info->fields [i].mspec,
 735                                                            &align, TRUE, klass->unicode);
 736                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 737                                 pass_on_stack = TRUE;
 738                                 break;
 739                         }
 740                 }
 741         }
 742
 743         if (pass_on_stack) {
 744                 /* Allways pass in memory */
 745                 ainfo->offset = *stack_size;
 746                 *stack_size += ALIGN_TO (size, 8);
 747                 ainfo->storage = ArgOnStack;
 748
 749                 return;
 750         }
 751
 752         /* FIXME: Handle structs smaller than 8 bytes */
 753         //if ((size % 8) != 0)
 754         //      NOT_IMPLEMENTED;
 755
 756         if (size > 8)
 757                 nquads = 2;
 758         else
 759                 nquads = 1;
 760
 761         if (!sig->pinvoke) {
 762                 /* Always pass in 1 or 2 integer registers */
 763                 args [0] = ARG_CLASS_INTEGER;
 764                 args [1] = ARG_CLASS_INTEGER;
 765                 /* Only the simplest cases are supported */
 766                 if (is_return && nquads != 1) {
 767                         args [0] = ARG_CLASS_MEMORY;
 768                         args [1] = ARG_CLASS_MEMORY;
 769                 }
 770         } else {
 771                 /*
 772                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 773                  * The X87 and SSEUP stuff is left out since there are no such types in
 774                  * the CLR.
 775                  */
 776                 info = mono_marshal_load_type_info (klass);
 777                 g_assert (info);
 778
 779 #ifndef HOST_WIN32
 780                 if (info->native_size > 16) {
 781                         ainfo->offset = *stack_size;
 782                         *stack_size += ALIGN_TO (info->native_size, 8);
 783                         ainfo->storage = ArgOnStack;
 784
 785                         return;
 786                 }
 787 #else
 788                 switch (info->native_size) {
 789                 case 1: case 2: case 4: case 8:
 790                         break;
 791                 default:
 792                         if (is_return) {
 793                                 ainfo->storage = ArgOnStack;
 794                                 ainfo->offset = *stack_size;
 795                                 *stack_size += ALIGN_TO (info->native_size, 8);
 796                         }
 797                         else {
 798                                 ainfo->storage = ArgValuetypeAddrInIReg;
 799
 800                                 if (*gr < PARAM_REGS) {
 801                                         ainfo->pair_storage [0] = ArgInIReg;
 802                                         ainfo->pair_regs [0] = param_regs [*gr];
 803                                         (*gr) ++;
 804                                 }
 805                                 else {
 806                                         ainfo->pair_storage [0] = ArgOnStack;
 807                                         ainfo->offset = *stack_size;
 808                                         *stack_size += 8;
 809                                 }
 810                         }
 811
 812                         return;
 813                 }
 814 #endif
 815
 816                 args [0] = ARG_CLASS_NO_CLASS;
 817                 args [1] = ARG_CLASS_NO_CLASS;
 818                 for (quad = 0; quad < nquads; ++quad) {
 819                         int size;
 820                         guint32 align;
 821                         ArgumentClass class1;
 822
 823                         if (info->num_fields == 0)
 824                                 class1 = ARG_CLASS_MEMORY;
 825                         else
 826                                 class1 = ARG_CLASS_NO_CLASS;
 827                         for (i = 0; i < info->num_fields; ++i) {
 828                                 size = mono_marshal_type_size (info->fields [i].field->type,
 829                                                                                            info->fields [i].mspec,
 830                                                                                            &align, TRUE, klass->unicode);
 831                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 832                                         /* Unaligned field */
 833                                         NOT_IMPLEMENTED;
 834                                 }
 835
 836                                 /* Skip fields in other quad */
 837                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 838                                         continue;
 839                                 if ((quad == 1) && (info->fields [i].offset < 8))
 840                                         continue;
 841
 842                                 /* How far into this quad this data extends.*/
 843                                 /* (8 is size of quad) */
 844                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 845
 846                                 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
 847                         }
 848                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 849                         args [quad] = class1;
 850                 }
 851         }
 852
 853         /* Post merger cleanup */
 854         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 855                 args [0] = args [1] = ARG_CLASS_MEMORY;
 856
 857         /* Allocate registers */
 858         {
 859                 int orig_gr = *gr;
 860                 int orig_fr = *fr;
 861
 862                 ainfo->storage = ArgValuetypeInReg;
 863                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 864                 ainfo->nregs = nquads;
 865                 for (quad = 0; quad < nquads; ++quad) {
 866                         switch (args [quad]) {
 867                         case ARG_CLASS_INTEGER:
 868                                 if (*gr >= PARAM_REGS)
 869                                         args [quad] = ARG_CLASS_MEMORY;
 870                                 else {
 871                                         ainfo->pair_storage [quad] = ArgInIReg;
 872                                         if (is_return)
 873                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 874                                         else
 875                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 876                                         (*gr) ++;
 877                                 }
 878                                 break;
 879                         case ARG_CLASS_SSE:
 880                                 if (*fr >= FLOAT_PARAM_REGS)
 881                                         args [quad] = ARG_CLASS_MEMORY;
 882                                 else {
 883                                         if (quadsize[quad] <= 4)
 884                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 885                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 886                                         ainfo->pair_regs [quad] = *fr;
 887                                         (*fr) ++;
 888                                 }
 889                                 break;
 890                         case ARG_CLASS_MEMORY:
 891                                 break;
 892                         default:
 893                                 g_assert_not_reached ();
 894                         }
 895                 }
 896
 897                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 898                         /* Revert possible register assignments */
 899                         *gr = orig_gr;
 900                         *fr = orig_fr;
 901
 902                         ainfo->offset = *stack_size;
 903                         if (sig->pinvoke)
 904                                 *stack_size += ALIGN_TO (info->native_size, 8);
 905                         else
 906                                 *stack_size += nquads * sizeof(mgreg_t);
 907                         ainfo->storage = ArgOnStack;
 908                 }
 909         }
 910 }
 911
 912 /*
 913  * get_call_info:
 914  *
 915  *  Obtain information about a call according to the calling convention.
 916  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 917  * Draft Version 0.23" document for more information.
 918  */
 919 static CallInfo*
 920 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 921 {
 922         guint32 i, gr, fr, pstart;
 923         MonoType *ret_type;
 924         int n = sig->hasthis + sig->param_count;
 925         guint32 stack_size = 0;
 926         CallInfo *cinfo;
 927         gboolean is_pinvoke = sig->pinvoke;
 928
 929         if (mp)
 930                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 931         else
 932                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 933
 934         cinfo->nargs = n;
 935
 936         gr = 0;
 937         fr = 0;
 938
 939 #ifdef HOST_WIN32
 940         /* Reserve space where the callee can save the argument registers */
 941         stack_size = 4 * sizeof (mgreg_t);
 942 #endif
 943
 944         /* return value */
 945         {
 946                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 947                 switch (ret_type->type) {
 948                 case MONO_TYPE_BOOLEAN:
 949                 case MONO_TYPE_I1:
 950                 case MONO_TYPE_U1:
 951                 case MONO_TYPE_I2:
 952                 case MONO_TYPE_U2:
 953                 case MONO_TYPE_CHAR:
 954                 case MONO_TYPE_I4:
 955                 case MONO_TYPE_U4:
 956                 case MONO_TYPE_I:
 957                 case MONO_TYPE_U:
 958                 case MONO_TYPE_PTR:
 959                 case MONO_TYPE_FNPTR:
 960                 case MONO_TYPE_CLASS:
 961                 case MONO_TYPE_OBJECT:
 962                 case MONO_TYPE_SZARRAY:
 963                 case MONO_TYPE_ARRAY:
 964                 case MONO_TYPE_STRING:
 965                         cinfo->ret.storage = ArgInIReg;
 966                         cinfo->ret.reg = AMD64_RAX;
 967                         break;
 968                 case MONO_TYPE_U8:
 969                 case MONO_TYPE_I8:
 970                         cinfo->ret.storage = ArgInIReg;
 971                         cinfo->ret.reg = AMD64_RAX;
 972                         break;
 973                 case MONO_TYPE_R4:
 974                         cinfo->ret.storage = ArgInFloatSSEReg;
 975                         cinfo->ret.reg = AMD64_XMM0;
 976                         break;
 977                 case MONO_TYPE_R8:
 978                         cinfo->ret.storage = ArgInDoubleSSEReg;
 979                         cinfo->ret.reg = AMD64_XMM0;
 980                         break;
 981                 case MONO_TYPE_GENERICINST:
 982                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 983                                 cinfo->ret.storage = ArgInIReg;
 984                                 cinfo->ret.reg = AMD64_RAX;
 985                                 break;
 986                         }
 987                         /* fall through */
 988 #if defined( __native_client_codegen__ )
 989                 case MONO_TYPE_TYPEDBYREF:
 990 #endif
 991                 case MONO_TYPE_VALUETYPE: {
 992                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 993
 994                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 995                         if (cinfo->ret.storage == ArgOnStack) {
 996                                 cinfo->vtype_retaddr = TRUE;
 997                                 /* The caller passes the address where the value is stored */
 998                         }
 999                         break;
1000                 }
1001 #if !defined( __native_client_codegen__ )
1002                 case MONO_TYPE_TYPEDBYREF:
1003                         /* Same as a valuetype with size 24 */
1004                         cinfo->vtype_retaddr = TRUE;
1005                         break;
1006 #endif
1007                 case MONO_TYPE_VOID:
1008                         break;
1009                 default:
1010                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1011                 }
1012         }
1013
1014         pstart = 0;
1015         /*
1016          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1017          * the first argument, allowing 'this' to be always passed in the first arg reg.
1018          * Also do this if the first argument is a reference type, since virtual calls
1019          * are sometimes made using calli without sig->hasthis set, like in the delegate
1020          * invoke wrappers.
1021          */
1022         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1023                 if (sig->hasthis) {
1024                         add_general (&gr, &stack_size, cinfo->args + 0);
1025                 } else {
1026                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1027                         pstart = 1;
1028                 }
1029                 add_general (&gr, &stack_size, &cinfo->ret);
1030                 cinfo->vret_arg_index = 1;
1031         } else {
1032                 /* this */
1033                 if (sig->hasthis)
1034                         add_general (&gr, &stack_size, cinfo->args + 0);
1035
1036                 if (cinfo->vtype_retaddr)
1037                         add_general (&gr, &stack_size, &cinfo->ret);
1038         }
1039
1040         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1041                 gr = PARAM_REGS;
1042                 fr = FLOAT_PARAM_REGS;
1043
1044                 /* Emit the signature cookie just before the implicit arguments */
1045                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1046         }
1047
1048         for (i = pstart; i < sig->param_count; ++i) {
1049                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1050                 MonoType *ptype;
1051
1052 #ifdef HOST_WIN32
1053                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1054                 if (gr > fr)
1055                         fr = gr;
1056                 else if (fr > gr)
1057                         gr = fr;
1058 #endif
1059
1060                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1061                         /* We allways pass the sig cookie on the stack for simplicity */
1062                         /*
1063                          * Prevent implicit arguments + the sig cookie from being passed
1064                          * in registers.
1065                          */
1066                         gr = PARAM_REGS;
1067                         fr = FLOAT_PARAM_REGS;
1068
1069                         /* Emit the signature cookie just before the implicit arguments */
1070                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1071                 }
1072
1073                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1074                 switch (ptype->type) {
1075                 case MONO_TYPE_BOOLEAN:
1076                 case MONO_TYPE_I1:
1077                 case MONO_TYPE_U1:
1078                         add_general (&gr, &stack_size, ainfo);
1079                         break;
1080                 case MONO_TYPE_I2:
1081                 case MONO_TYPE_U2:
1082                 case MONO_TYPE_CHAR:
1083                         add_general (&gr, &stack_size, ainfo);
1084                         break;
1085                 case MONO_TYPE_I4:
1086                 case MONO_TYPE_U4:
1087                         add_general (&gr, &stack_size, ainfo);
1088                         break;
1089                 case MONO_TYPE_I:
1090                 case MONO_TYPE_U:
1091                 case MONO_TYPE_PTR:
1092                 case MONO_TYPE_FNPTR:
1093                 case MONO_TYPE_CLASS:
1094                 case MONO_TYPE_OBJECT:
1095                 case MONO_TYPE_STRING:
1096                 case MONO_TYPE_SZARRAY:
1097                 case MONO_TYPE_ARRAY:
1098                         add_general (&gr, &stack_size, ainfo);
1099                         break;
1100                 case MONO_TYPE_GENERICINST:
1101                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1102                                 add_general (&gr, &stack_size, ainfo);
1103                                 break;
1104                         }
1105                         /* fall through */
1106                 case MONO_TYPE_VALUETYPE:
1107                 case MONO_TYPE_TYPEDBYREF:
1108                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1109                         break;
1110                 case MONO_TYPE_U8:
1111
1112                 case MONO_TYPE_I8:
1113                         add_general (&gr, &stack_size, ainfo);
1114                         break;
1115                 case MONO_TYPE_R4:
1116                         add_float (&fr, &stack_size, ainfo, FALSE);
1117                         break;
1118                 case MONO_TYPE_R8:
1119                         add_float (&fr, &stack_size, ainfo, TRUE);
1120                         break;
1121                 default:
1122                         g_assert_not_reached ();
1123                 }
1124         }
1125
1126         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1127                 gr = PARAM_REGS;
1128                 fr = FLOAT_PARAM_REGS;
1129
1130                 /* Emit the signature cookie just before the implicit arguments */
1131                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1132         }
1133
1134         cinfo->stack_usage = stack_size;
1135         cinfo->reg_usage = gr;
1136         cinfo->freg_usage = fr;
1137         return cinfo;
1138 }
1139
1140 /*
1141  * mono_arch_get_argument_info:
1142  * @csig:  a method signature
1143  * @param_count: the number of parameters to consider
1144  * @arg_info: an array to store the result infos
1145  *
1146  * Gathers information on parameters such as size, alignment and
1147  * padding. arg_info should be large enought to hold param_count + 1 entries.
1148  *
1149  * Returns the size of the argument area on the stack.
1150  */
1151 int
1152 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1153 {
1154         int k;
1155         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1156         guint32 args_size = cinfo->stack_usage;
1157
1158         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1159         if (csig->hasthis) {
1160                 arg_info [0].offset = 0;
1161         }
1162
1163         for (k = 0; k < param_count; k++) {
1164                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1165                 /* FIXME: */
1166                 arg_info [k + 1].size = 0;
1167         }
1168
1169         g_free (cinfo);
1170
1171         return args_size;
1172 }
1173
1174 gboolean
1175 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1176 {
1177         CallInfo *c1, *c2;
1178         gboolean res;
1179         MonoType *callee_ret;
1180
1181         c1 = get_call_info (NULL, NULL, caller_sig);
1182         c2 = get_call_info (NULL, NULL, callee_sig);
1183         res = c1->stack_usage >= c2->stack_usage;
1184         callee_ret = mini_replace_type (callee_sig->ret);
1185         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1186                 /* An address on the callee's stack is passed as the first argument */
1187                 res = FALSE;
1188
1189         g_free (c1);
1190         g_free (c2);
1191
1192         return res;
1193 }
1194
1195 /*
1196  * Initialize the cpu to execute managed code.
1197  */
1198 void
1199 mono_arch_cpu_init (void)
1200 {
1201 #ifndef _MSC_VER
1202         guint16 fpcw;
1203
1204         /* spec compliance requires running with double precision */
1205         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1206         fpcw &= ~X86_FPCW_PRECC_MASK;
1207         fpcw |= X86_FPCW_PREC_DOUBLE;
1208         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1209         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1210 #else
1211         /* TODO: This is crashing on Win64 right now.
1212         * _control87 (_PC_53, MCW_PC);
1213         */
1214 #endif
1215 }
1216
1217 /*
1218  * Initialize architecture specific code.
1219  */
1220 void
1221 mono_arch_init (void)
1222 {
1223         int flags;
1224
1225         mono_mutex_init_recursive (&mini_arch_mutex);
1226 #if defined(__native_client_codegen__)
1227         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1228         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1229         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1230         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1231 #endif
1232
1233 #ifdef MONO_ARCH_NOMAP32BIT
1234         flags = MONO_MMAP_READ;
1235         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1236         breakpoint_size = 13;
1237         breakpoint_fault_size = 3;
1238 #else
1239         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1240         /* amd64_mov_reg_mem () */
1241         breakpoint_size = 8;
1242         breakpoint_fault_size = 8;
1243 #endif
1244
1245         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1246         single_step_fault_size = 4;
1247
1248         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1249         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1250         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1251
1252         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1253         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1254         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1255 }
1256
1257 /*
1258  * Cleanup architecture specific code.
1259  */
1260 void
1261 mono_arch_cleanup (void)
1262 {
1263         mono_mutex_destroy (&mini_arch_mutex);
1264 #if defined(__native_client_codegen__)
1265         mono_native_tls_free (nacl_instruction_depth);
1266         mono_native_tls_free (nacl_rex_tag);
1267         mono_native_tls_free (nacl_legacy_prefix_tag);
1268 #endif
1269 }
1270
1271 /*
1272  * This function returns the optimizations supported on this cpu.
1273  */
1274 guint32
1275 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1276 {
1277         guint32 opts = 0;
1278
1279         *exclude_mask = 0;
1280
1281         if (mono_hwcap_x86_has_cmov) {
1282                 opts |= MONO_OPT_CMOV;
1283
1284                 if (mono_hwcap_x86_has_fcmov)
1285                         opts |= MONO_OPT_FCMOV;
1286                 else
1287                         *exclude_mask |= MONO_OPT_FCMOV;
1288         } else {
1289                 *exclude_mask |= MONO_OPT_CMOV;
1290         }
1291
1292         return opts;
1293 }
1294
1295 /*
1296  * This function test for all SSE functions supported.
1297  *
1298  * Returns a bitmask corresponding to all supported versions.
1299  *
1300  */
1301 guint32
1302 mono_arch_cpu_enumerate_simd_versions (void)
1303 {
1304         guint32 sse_opts = 0;
1305
1306         if (mono_hwcap_x86_has_sse1)
1307                 sse_opts |= SIMD_VERSION_SSE1;
1308
1309         if (mono_hwcap_x86_has_sse2)
1310                 sse_opts |= SIMD_VERSION_SSE2;
1311
1312         if (mono_hwcap_x86_has_sse3)
1313                 sse_opts |= SIMD_VERSION_SSE3;
1314
1315         if (mono_hwcap_x86_has_ssse3)
1316                 sse_opts |= SIMD_VERSION_SSSE3;
1317
1318         if (mono_hwcap_x86_has_sse41)
1319                 sse_opts |= SIMD_VERSION_SSE41;
1320
1321         if (mono_hwcap_x86_has_sse42)
1322                 sse_opts |= SIMD_VERSION_SSE42;
1323
1324         if (mono_hwcap_x86_has_sse4a)
1325                 sse_opts |= SIMD_VERSION_SSE4a;
1326
1327         return sse_opts;
1328 }
1329
1330 #ifndef DISABLE_JIT
1331
1332 GList *
1333 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1334 {
1335         GList *vars = NULL;
1336         int i;
1337
1338         for (i = 0; i < cfg->num_varinfo; i++) {
1339                 MonoInst *ins = cfg->varinfo [i];
1340                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1341
1342                 /* unused vars */
1343                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1344                         continue;
1345
1346                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1347                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1348                         continue;
1349
1350                 if (mono_is_regsize_var (ins->inst_vtype)) {
1351                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1352                         g_assert (i == vmv->idx);
1353                         vars = g_list_prepend (vars, vmv);
1354                 }
1355         }
1356
1357         vars = mono_varlist_sort (cfg, vars, 0);
1358
1359         return vars;
1360 }
1361
1362 /**
1363  * mono_arch_compute_omit_fp:
1364  *
1365  *   Determine whenever the frame pointer can be eliminated.
1366  */
1367 static void
1368 mono_arch_compute_omit_fp (MonoCompile *cfg)
1369 {
1370         MonoMethodSignature *sig;
1371         MonoMethodHeader *header;
1372         int i, locals_size;
1373         CallInfo *cinfo;
1374
1375         if (cfg->arch.omit_fp_computed)
1376                 return;
1377
1378         header = cfg->header;
1379
1380         sig = mono_method_signature (cfg->method);
1381
1382         if (!cfg->arch.cinfo)
1383                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1384         cinfo = cfg->arch.cinfo;
1385
1386         /*
1387          * FIXME: Remove some of the restrictions.
1388          */
1389         cfg->arch.omit_fp = TRUE;
1390         cfg->arch.omit_fp_computed = TRUE;
1391
1392 #ifdef __native_client_codegen__
1393         /* NaCl modules may not change the value of RBP, so it cannot be */
1394         /* used as a normal register, but it can be used as a frame pointer*/
1395         cfg->disable_omit_fp = TRUE;
1396         cfg->arch.omit_fp = FALSE;
1397 #endif
1398
1399         if (cfg->disable_omit_fp)
1400                 cfg->arch.omit_fp = FALSE;
1401
1402         if (!debug_omit_fp ())
1403                 cfg->arch.omit_fp = FALSE;
1404         /*
1405         if (cfg->method->save_lmf)
1406                 cfg->arch.omit_fp = FALSE;
1407         */
1408         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1409                 cfg->arch.omit_fp = FALSE;
1410         if (header->num_clauses)
1411                 cfg->arch.omit_fp = FALSE;
1412         if (cfg->param_area)
1413                 cfg->arch.omit_fp = FALSE;
1414         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1415                 cfg->arch.omit_fp = FALSE;
1416         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1417                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1418                 cfg->arch.omit_fp = FALSE;
1419         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1420                 ArgInfo *ainfo = &cinfo->args [i];
1421
1422                 if (ainfo->storage == ArgOnStack) {
1423                         /*
1424                          * The stack offset can only be determined when the frame
1425                          * size is known.
1426                          */
1427                         cfg->arch.omit_fp = FALSE;
1428                 }
1429         }
1430
1431         locals_size = 0;
1432         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1433                 MonoInst *ins = cfg->varinfo [i];
1434                 int ialign;
1435
1436                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1437         }
1438 }
1439
1440 GList *
1441 mono_arch_get_global_int_regs (MonoCompile *cfg)
1442 {
1443         GList *regs = NULL;
1444
1445         mono_arch_compute_omit_fp (cfg);
1446
1447         if (cfg->globalra) {
1448                 if (cfg->arch.omit_fp)
1449                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1450
1451                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1452                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1453                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1454                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1455 #ifndef __native_client_codegen__
1456                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1457 #endif
1458
1459                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1460                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1461                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1462                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1463                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1464                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1465                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1466                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1467         } else {
1468                 if (cfg->arch.omit_fp)
1469                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1470
1471                 /* We use the callee saved registers for global allocation */
1472                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1473                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1474                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1475                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1476 #ifndef __native_client_codegen__
1477                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1478 #endif
1479 #ifdef HOST_WIN32
1480                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1481                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1482 #endif
1483         }
1484
1485         return regs;
1486 }
1487
1488 GList*
1489 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1490 {
1491         GList *regs = NULL;
1492         int i;
1493
1494         /* All XMM registers */
1495         for (i = 0; i < 16; ++i)
1496                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1497
1498         return regs;
1499 }
1500
1501 GList*
1502 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1503 {
1504         static GList *r = NULL;
1505
1506         if (r == NULL) {
1507                 GList *regs = NULL;
1508
1509                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1510                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1511                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1512                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1513                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1514 #ifndef __native_client_codegen__
1515                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1516 #endif
1517
1518                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1519                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1524                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1526
1527                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1528         }
1529
1530         return r;
1531 }
1532
1533 GList*
1534 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1535 {
1536         int i;
1537         static GList *r = NULL;
1538
1539         if (r == NULL) {
1540                 GList *regs = NULL;
1541
1542                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1543                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1544
1545                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1546         }
1547
1548         return r;
1549 }
1550
1551 /*
1552  * mono_arch_regalloc_cost:
1553  *
1554  *  Return the cost, in number of memory references, of the action of
1555  * allocating the variable VMV into a register during global register
1556  * allocation.
1557  */
1558 guint32
1559 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1560 {
1561         MonoInst *ins = cfg->varinfo [vmv->idx];
1562
1563         if (cfg->method->save_lmf)
1564                 /* The register is already saved */
1565                 /* substract 1 for the invisible store in the prolog */
1566                 return (ins->opcode == OP_ARG) ? 0 : 1;
1567         else
1568                 /* push+pop */
1569                 return (ins->opcode == OP_ARG) ? 1 : 2;
1570 }
1571
1572 /*
1573  * mono_arch_fill_argument_info:
1574  *
1575  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1576  * of the method.
1577  */
1578 void
1579 mono_arch_fill_argument_info (MonoCompile *cfg)
1580 {
1581         MonoType *sig_ret;
1582         MonoMethodSignature *sig;
1583         MonoMethodHeader *header;
1584         MonoInst *ins;
1585         int i;
1586         CallInfo *cinfo;
1587
1588         header = cfg->header;
1589
1590         sig = mono_method_signature (cfg->method);
1591
1592         cinfo = cfg->arch.cinfo;
1593         sig_ret = mini_replace_type (sig->ret);
1594
1595         /*
1596          * Contrary to mono_arch_allocate_vars (), the information should describe
1597          * where the arguments are at the beginning of the method, not where they can be
1598          * accessed during the execution of the method. The later makes no sense for the
1599          * global register allocator, since a variable can be in more than one location.
1600          */
1601         if (sig_ret->type != MONO_TYPE_VOID) {
1602                 switch (cinfo->ret.storage) {
1603                 case ArgInIReg:
1604                 case ArgInFloatSSEReg:
1605                 case ArgInDoubleSSEReg:
1606                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1607                                 cfg->vret_addr->opcode = OP_REGVAR;
1608                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1609                         }
1610                         else {
1611                                 cfg->ret->opcode = OP_REGVAR;
1612                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1613                         }
1614                         break;
1615                 case ArgValuetypeInReg:
1616                         cfg->ret->opcode = OP_REGOFFSET;
1617                         cfg->ret->inst_basereg = -1;
1618                         cfg->ret->inst_offset = -1;
1619                         break;
1620                 default:
1621                         g_assert_not_reached ();
1622                 }
1623         }
1624
1625         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1626                 ArgInfo *ainfo = &cinfo->args [i];
1627                 MonoType *arg_type;
1628
1629                 ins = cfg->args [i];
1630
1631                 if (sig->hasthis && (i == 0))
1632                         arg_type = &mono_defaults.object_class->byval_arg;
1633                 else
1634                         arg_type = sig->params [i - sig->hasthis];
1635
1636                 switch (ainfo->storage) {
1637                 case ArgInIReg:
1638                 case ArgInFloatSSEReg:
1639                 case ArgInDoubleSSEReg:
1640                         ins->opcode = OP_REGVAR;
1641                         ins->inst_c0 = ainfo->reg;
1642                         break;
1643                 case ArgOnStack:
1644                         ins->opcode = OP_REGOFFSET;
1645                         ins->inst_basereg = -1;
1646                         ins->inst_offset = -1;
1647                         break;
1648                 case ArgValuetypeInReg:
1649                         /* Dummy */
1650                         ins->opcode = OP_NOP;
1651                         break;
1652                 default:
1653                         g_assert_not_reached ();
1654                 }
1655         }
1656 }
1657
1658 void
1659 mono_arch_allocate_vars (MonoCompile *cfg)
1660 {
1661         MonoType *sig_ret;
1662         MonoMethodSignature *sig;
1663         MonoMethodHeader *header;
1664         MonoInst *ins;
1665         int i, offset;
1666         guint32 locals_stack_size, locals_stack_align;
1667         gint32 *offsets;
1668         CallInfo *cinfo;
1669
1670         header = cfg->header;
1671
1672         sig = mono_method_signature (cfg->method);
1673
1674         cinfo = cfg->arch.cinfo;
1675         sig_ret = mini_replace_type (sig->ret);
1676
1677         mono_arch_compute_omit_fp (cfg);
1678
1679         /*
1680          * We use the ABI calling conventions for managed code as well.
1681          * Exception: valuetypes are only sometimes passed or returned in registers.
1682          */
1683
1684         /*
1685          * The stack looks like this:
1686          * <incoming arguments passed on the stack>
1687          * <return value>
1688          * <lmf/caller saved registers>
1689          * <locals>
1690          * <spill area>
1691          * <localloc area>  -> grows dynamically
1692          * <params area>
1693          */
1694
1695         if (cfg->arch.omit_fp) {
1696                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1697                 cfg->frame_reg = AMD64_RSP;
1698                 offset = 0;
1699         } else {
1700                 /* Locals are allocated backwards from %fp */
1701                 cfg->frame_reg = AMD64_RBP;
1702                 offset = 0;
1703         }
1704
1705         cfg->arch.saved_iregs = cfg->used_int_regs;
1706         if (cfg->method->save_lmf)
1707                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1708                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1709
1710         if (cfg->arch.omit_fp)
1711                 cfg->arch.reg_save_area_offset = offset;
1712         /* Reserve space for callee saved registers */
1713         for (i = 0; i < AMD64_NREG; ++i)
1714                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1715                         offset += sizeof(mgreg_t);
1716                 }
1717         if (!cfg->arch.omit_fp)
1718                 cfg->arch.reg_save_area_offset = -offset;
1719
1720         if (sig_ret->type != MONO_TYPE_VOID) {
1721                 switch (cinfo->ret.storage) {
1722                 case ArgInIReg:
1723                 case ArgInFloatSSEReg:
1724                 case ArgInDoubleSSEReg:
1725                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1726                                 if (cfg->globalra) {
1727                                         cfg->vret_addr->opcode = OP_REGVAR;
1728                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1729                                 } else {
1730                                         /* The register is volatile */
1731                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1732                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1733                                         if (cfg->arch.omit_fp) {
1734                                                 cfg->vret_addr->inst_offset = offset;
1735                                                 offset += 8;
1736                                         } else {
1737                                                 offset += 8;
1738                                                 cfg->vret_addr->inst_offset = -offset;
1739                                         }
1740                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1741                                                 printf ("vret_addr =");
1742                                                 mono_print_ins (cfg->vret_addr);
1743                                         }
1744                                 }
1745                         }
1746                         else {
1747                                 cfg->ret->opcode = OP_REGVAR;
1748                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1749                         }
1750                         break;
1751                 case ArgValuetypeInReg:
1752                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1753                         cfg->ret->opcode = OP_REGOFFSET;
1754                         cfg->ret->inst_basereg = cfg->frame_reg;
1755                         if (cfg->arch.omit_fp) {
1756                                 cfg->ret->inst_offset = offset;
1757                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1758                         } else {
1759                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1760                                 cfg->ret->inst_offset = - offset;
1761                         }
1762                         break;
1763                 default:
1764                         g_assert_not_reached ();
1765                 }
1766                 if (!cfg->globalra)
1767                         cfg->ret->dreg = cfg->ret->inst_c0;
1768         }
1769
1770         /* Allocate locals */
1771         if (!cfg->globalra) {
1772                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1773                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1774                         char *mname = mono_method_full_name (cfg->method, TRUE);
1775                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1776                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1777                         g_free (mname);
1778                         return;
1779                 }
1780
1781                 if (locals_stack_align) {
1782                         offset += (locals_stack_align - 1);
1783                         offset &= ~(locals_stack_align - 1);
1784                 }
1785                 if (cfg->arch.omit_fp) {
1786                         cfg->locals_min_stack_offset = offset;
1787                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1788                 } else {
1789                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1790                         cfg->locals_max_stack_offset = - offset;
1791                 }
1792
1793                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1794                         if (offsets [i] != -1) {
1795                                 MonoInst *ins = cfg->varinfo [i];
1796                                 ins->opcode = OP_REGOFFSET;
1797                                 ins->inst_basereg = cfg->frame_reg;
1798                                 if (cfg->arch.omit_fp)
1799                                         ins->inst_offset = (offset + offsets [i]);
1800                                 else
1801                                         ins->inst_offset = - (offset + offsets [i]);
1802                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1803                         }
1804                 }
1805                 offset += locals_stack_size;
1806         }
1807
1808         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1809                 g_assert (!cfg->arch.omit_fp);
1810                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1811                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1812         }
1813
1814         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1815                 ins = cfg->args [i];
1816                 if (ins->opcode != OP_REGVAR) {
1817                         ArgInfo *ainfo = &cinfo->args [i];
1818                         gboolean inreg = TRUE;
1819                         MonoType *arg_type;
1820
1821                         if (sig->hasthis && (i == 0))
1822                                 arg_type = &mono_defaults.object_class->byval_arg;
1823                         else
1824                                 arg_type = sig->params [i - sig->hasthis];
1825
1826                         if (cfg->globalra) {
1827                                 /* The new allocator needs info about the original locations of the arguments */
1828                                 switch (ainfo->storage) {
1829                                 case ArgInIReg:
1830                                 case ArgInFloatSSEReg:
1831                                 case ArgInDoubleSSEReg:
1832                                         ins->opcode = OP_REGVAR;
1833                                         ins->inst_c0 = ainfo->reg;
1834                                         break;
1835                                 case ArgOnStack:
1836                                         g_assert (!cfg->arch.omit_fp);
1837                                         ins->opcode = OP_REGOFFSET;
1838                                         ins->inst_basereg = cfg->frame_reg;
1839                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1840                                         break;
1841                                 case ArgValuetypeInReg:
1842                                         ins->opcode = OP_REGOFFSET;
1843                                         ins->inst_basereg = cfg->frame_reg;
1844                                         /* These arguments are saved to the stack in the prolog */
1845                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1846                                         if (cfg->arch.omit_fp) {
1847                                                 ins->inst_offset = offset;
1848                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1849                                         } else {
1850                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1851                                                 ins->inst_offset = - offset;
1852                                         }
1853                                         break;
1854                                 default:
1855                                         g_assert_not_reached ();
1856                                 }
1857
1858                                 continue;
1859                         }
1860
1861                         /* FIXME: Allocate volatile arguments to registers */
1862                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1863                                 inreg = FALSE;
1864
1865                         /*
1866                          * Under AMD64, all registers used to pass arguments to functions
1867                          * are volatile across calls.
1868                          * FIXME: Optimize this.
1869                          */
1870                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1871                                 inreg = FALSE;
1872
1873                         ins->opcode = OP_REGOFFSET;
1874
1875                         switch (ainfo->storage) {
1876                         case ArgInIReg:
1877                         case ArgInFloatSSEReg:
1878                         case ArgInDoubleSSEReg:
1879                                 if (inreg) {
1880                                         ins->opcode = OP_REGVAR;
1881                                         ins->dreg = ainfo->reg;
1882                                 }
1883                                 break;
1884                         case ArgOnStack:
1885                                 g_assert (!cfg->arch.omit_fp);
1886                                 ins->opcode = OP_REGOFFSET;
1887                                 ins->inst_basereg = cfg->frame_reg;
1888                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1889                                 break;
1890                         case ArgValuetypeInReg:
1891                                 break;
1892                         case ArgValuetypeAddrInIReg: {
1893                                 MonoInst *indir;
1894                                 g_assert (!cfg->arch.omit_fp);
1895
1896                                 MONO_INST_NEW (cfg, indir, 0);
1897                                 indir->opcode = OP_REGOFFSET;
1898                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1899                                         indir->inst_basereg = cfg->frame_reg;
1900                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1901                                         offset += (sizeof (gpointer));
1902                                         indir->inst_offset = - offset;
1903                                 }
1904                                 else {
1905                                         indir->inst_basereg = cfg->frame_reg;
1906                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1907                                 }
1908
1909                                 ins->opcode = OP_VTARG_ADDR;
1910                                 ins->inst_left = indir;
1911
1912                                 break;
1913                         }
1914                         default:
1915                                 NOT_IMPLEMENTED;
1916                         }
1917
1918                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1919                                 ins->opcode = OP_REGOFFSET;
1920                                 ins->inst_basereg = cfg->frame_reg;
1921                                 /* These arguments are saved to the stack in the prolog */
1922                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1923                                 if (cfg->arch.omit_fp) {
1924                                         ins->inst_offset = offset;
1925                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1926                                         // Arguments are yet supported by the stack map creation code
1927                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1928                                 } else {
1929                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1930                                         ins->inst_offset = - offset;
1931                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1932                                 }
1933                         }
1934                 }
1935         }
1936
1937         cfg->stack_offset = offset;
1938 }
1939
1940 void
1941 mono_arch_create_vars (MonoCompile *cfg)
1942 {
1943         MonoMethodSignature *sig;
1944         CallInfo *cinfo;
1945         MonoType *sig_ret;
1946
1947         sig = mono_method_signature (cfg->method);
1948
1949         if (!cfg->arch.cinfo)
1950                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1951         cinfo = cfg->arch.cinfo;
1952
1953         if (cinfo->ret.storage == ArgValuetypeInReg)
1954                 cfg->ret_var_is_local = TRUE;
1955
1956         sig_ret = mini_replace_type (sig->ret);
1957         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1958                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1959                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1960                         printf ("vret_addr = ");
1961                         mono_print_ins (cfg->vret_addr);
1962                 }
1963         }
1964
1965         if (cfg->gen_seq_points) {
1966                 MonoInst *ins;
1967
1968                 if (cfg->compile_aot) {
1969                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1970                         ins->flags |= MONO_INST_VOLATILE;
1971                         cfg->arch.seq_point_info_var = ins;
1972                 }
1973
1974             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1975                 ins->flags |= MONO_INST_VOLATILE;
1976                 cfg->arch.ss_trigger_page_var = ins;
1977         }
1978
1979         if (cfg->method->save_lmf)
1980                 cfg->create_lmf_var = TRUE;
1981
1982         if (cfg->method->save_lmf) {
1983                 cfg->lmf_ir = TRUE;
1984 #if !defined(HOST_WIN32)
1985                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1986                         cfg->lmf_ir_mono_lmf = TRUE;
1987 #endif
1988         }
1989 }
1990
1991 static void
1992 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1993 {
1994         MonoInst *ins;
1995
1996         switch (storage) {
1997         case ArgInIReg:
1998                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1999                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2000                 ins->sreg1 = tree->dreg;
2001                 MONO_ADD_INS (cfg->cbb, ins);
2002                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2003                 break;
2004         case ArgInFloatSSEReg:
2005                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2006                 ins->dreg = mono_alloc_freg (cfg);
2007                 ins->sreg1 = tree->dreg;
2008                 MONO_ADD_INS (cfg->cbb, ins);
2009
2010                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2011                 break;
2012         case ArgInDoubleSSEReg:
2013                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2014                 ins->dreg = mono_alloc_freg (cfg);
2015                 ins->sreg1 = tree->dreg;
2016                 MONO_ADD_INS (cfg->cbb, ins);
2017
2018                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2019
2020                 break;
2021         default:
2022                 g_assert_not_reached ();
2023         }
2024 }
2025
2026 static int
2027 arg_storage_to_load_membase (ArgStorage storage)
2028 {
2029         switch (storage) {
2030         case ArgInIReg:
2031 #if defined(__mono_ilp32__)
2032                 return OP_LOADI8_MEMBASE;
2033 #else
2034                 return OP_LOAD_MEMBASE;
2035 #endif
2036         case ArgInDoubleSSEReg:
2037                 return OP_LOADR8_MEMBASE;
2038         case ArgInFloatSSEReg:
2039                 return OP_LOADR4_MEMBASE;
2040         default:
2041                 g_assert_not_reached ();
2042         }
2043
2044         return -1;
2045 }
2046
2047 static void
2048 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2049 {
2050         MonoMethodSignature *tmp_sig;
2051         int sig_reg;
2052
2053         if (call->tail_call)
2054                 NOT_IMPLEMENTED;
2055
2056         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2057
2058         /*
2059          * mono_ArgIterator_Setup assumes the signature cookie is
2060          * passed first and all the arguments which were before it are
2061          * passed on the stack after the signature. So compensate by
2062          * passing a different signature.
2063          */
2064         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2065         tmp_sig->param_count -= call->signature->sentinelpos;
2066         tmp_sig->sentinelpos = 0;
2067         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2068
2069         sig_reg = mono_alloc_ireg (cfg);
2070         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2071
2072         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2073 }
2074
2075 static inline LLVMArgStorage
2076 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2077 {
2078         switch (storage) {
2079         case ArgInIReg:
2080                 return LLVMArgInIReg;
2081         case ArgNone:
2082                 return LLVMArgNone;
2083         default:
2084                 g_assert_not_reached ();
2085                 return LLVMArgNone;
2086         }
2087 }
2088
2089 #ifdef ENABLE_LLVM
2090 LLVMCallInfo*
2091 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2092 {
2093         int i, n;
2094         CallInfo *cinfo;
2095         ArgInfo *ainfo;
2096         int j;
2097         LLVMCallInfo *linfo;
2098         MonoType *t, *sig_ret;
2099
2100         n = sig->param_count + sig->hasthis;
2101         sig_ret = mini_replace_type (sig->ret);
2102
2103         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2104
2105         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2106
2107         /*
2108          * LLVM always uses the native ABI while we use our own ABI, the
2109          * only difference is the handling of vtypes:
2110          * - we only pass/receive them in registers in some cases, and only
2111          *   in 1 or 2 integer registers.
2112          */
2113         if (cinfo->ret.storage == ArgValuetypeInReg) {
2114                 if (sig->pinvoke) {
2115                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2116                         cfg->disable_llvm = TRUE;
2117                         return linfo;
2118                 }
2119
2120                 linfo->ret.storage = LLVMArgVtypeInReg;
2121                 for (j = 0; j < 2; ++j)
2122                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2123         }
2124
2125         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2126                 /* Vtype returned using a hidden argument */
2127                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2128                 linfo->vret_arg_index = cinfo->vret_arg_index;
2129         }
2130
2131         for (i = 0; i < n; ++i) {
2132                 ainfo = cinfo->args + i;
2133
2134                 if (i >= sig->hasthis)
2135                         t = sig->params [i - sig->hasthis];
2136                 else
2137                         t = &mono_defaults.int_class->byval_arg;
2138
2139                 linfo->args [i].storage = LLVMArgNone;
2140
2141                 switch (ainfo->storage) {
2142                 case ArgInIReg:
2143                         linfo->args [i].storage = LLVMArgInIReg;
2144                         break;
2145                 case ArgInDoubleSSEReg:
2146                 case ArgInFloatSSEReg:
2147                         linfo->args [i].storage = LLVMArgInFPReg;
2148                         break;
2149                 case ArgOnStack:
2150                         if (MONO_TYPE_ISSTRUCT (t)) {
2151                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2152                         } else {
2153                                 linfo->args [i].storage = LLVMArgInIReg;
2154                                 if (!t->byref) {
2155                                         if (t->type == MONO_TYPE_R4)
2156                                                 linfo->args [i].storage = LLVMArgInFPReg;
2157                                         else if (t->type == MONO_TYPE_R8)
2158                                                 linfo->args [i].storage = LLVMArgInFPReg;
2159                                 }
2160                         }
2161                         break;
2162                 case ArgValuetypeInReg:
2163                         if (sig->pinvoke) {
2164                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2165                                 cfg->disable_llvm = TRUE;
2166                                 return linfo;
2167                         }
2168
2169                         linfo->args [i].storage = LLVMArgVtypeInReg;
2170                         for (j = 0; j < 2; ++j)
2171                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2172                         break;
2173                 default:
2174                         cfg->exception_message = g_strdup ("ainfo->storage");
2175                         cfg->disable_llvm = TRUE;
2176                         break;
2177                 }
2178         }
2179
2180         return linfo;
2181 }
2182 #endif
2183
2184 void
2185 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2186 {
2187         MonoInst *arg, *in;
2188         MonoMethodSignature *sig;
2189         MonoType *sig_ret;
2190         int i, n, stack_size;
2191         CallInfo *cinfo;
2192         ArgInfo *ainfo;
2193
2194         stack_size = 0;
2195
2196         sig = call->signature;
2197         n = sig->param_count + sig->hasthis;
2198
2199         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2200
2201         sig_ret = sig->ret;
2202
2203         if (COMPILE_LLVM (cfg)) {
2204                 /* We shouldn't be called in the llvm case */
2205                 cfg->disable_llvm = TRUE;
2206                 return;
2207         }
2208
2209         /*
2210          * Emit all arguments which are passed on the stack to prevent register
2211          * allocation problems.
2212          */
2213         for (i = 0; i < n; ++i) {
2214                 MonoType *t;
2215                 ainfo = cinfo->args + i;
2216
2217                 in = call->args [i];
2218
2219                 if (sig->hasthis && i == 0)
2220                         t = &mono_defaults.object_class->byval_arg;
2221                 else
2222                         t = sig->params [i - sig->hasthis];
2223
2224                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2225                         if (!t->byref) {
2226                                 if (t->type == MONO_TYPE_R4)
2227                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2228                                 else if (t->type == MONO_TYPE_R8)
2229                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2230                                 else
2231                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2232                         } else {
2233                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2234                         }
2235                         if (cfg->compute_gc_maps) {
2236                                 MonoInst *def;
2237
2238                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2239                         }
2240                 }
2241         }
2242
2243         /*
2244          * Emit all parameters passed in registers in non-reverse order for better readability
2245          * and to help the optimization in emit_prolog ().
2246          */
2247         for (i = 0; i < n; ++i) {
2248                 ainfo = cinfo->args + i;
2249
2250                 in = call->args [i];
2251
2252                 if (ainfo->storage == ArgInIReg)
2253                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2254         }
2255
2256         for (i = n - 1; i >= 0; --i) {
2257                 ainfo = cinfo->args + i;
2258
2259                 in = call->args [i];
2260
2261                 switch (ainfo->storage) {
2262                 case ArgInIReg:
2263                         /* Already done */
2264                         break;
2265                 case ArgInFloatSSEReg:
2266                 case ArgInDoubleSSEReg:
2267                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2268                         break;
2269                 case ArgOnStack:
2270                 case ArgValuetypeInReg:
2271                 case ArgValuetypeAddrInIReg:
2272                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2273                                 MonoInst *call_inst = (MonoInst*)call;
2274                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2275                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2276                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2277                                 guint32 align;
2278                                 guint32 size;
2279
2280                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2281                                         size = sizeof (MonoTypedRef);
2282                                         align = sizeof (gpointer);
2283                                 }
2284                                 else {
2285                                         if (sig->pinvoke)
2286                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2287                                         else {
2288                                                 /*
2289                                                  * Other backends use mono_type_stack_size (), but that
2290                                                  * aligns the size to 8, which is larger than the size of
2291                                                  * the source, leading to reads of invalid memory if the
2292                                                  * source is at the end of address space.
2293                                                  */
2294                                                 size = mono_class_value_size (in->klass, &align);
2295                                         }
2296                                 }
2297                                 g_assert (in->klass);
2298
2299                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2300                                         /* Avoid asserts in emit_memcpy () */
2301                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2302                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2303                                         /* Continue normally */
2304                                 }
2305
2306                                 if (size > 0) {
2307                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2308                                         arg->sreg1 = in->dreg;
2309                                         arg->klass = in->klass;
2310                                         arg->backend.size = size;
2311                                         arg->inst_p0 = call;
2312                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2313                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2314
2315                                         MONO_ADD_INS (cfg->cbb, arg);
2316                                 }
2317                         }
2318                         break;
2319                 default:
2320                         g_assert_not_reached ();
2321                 }
2322
2323                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2324                         /* Emit the signature cookie just before the implicit arguments */
2325                         emit_sig_cookie (cfg, call, cinfo);
2326         }
2327
2328         /* Handle the case where there are no implicit arguments */
2329         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2330                 emit_sig_cookie (cfg, call, cinfo);
2331
2332         sig_ret = mini_replace_type (sig->ret);
2333         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2334                 MonoInst *vtarg;
2335
2336                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2337                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2338                                 /*
2339                                  * Tell the JIT to use a more efficient calling convention: call using
2340                                  * OP_CALL, compute the result location after the call, and save the
2341                                  * result there.
2342                                  */
2343                                 call->vret_in_reg = TRUE;
2344                                 /*
2345                                  * Nullify the instruction computing the vret addr to enable
2346                                  * future optimizations.
2347                                  */
2348                                 if (call->vret_var)
2349                                         NULLIFY_INS (call->vret_var);
2350                         } else {
2351                                 if (call->tail_call)
2352                                         NOT_IMPLEMENTED;
2353                                 /*
2354                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2355                                  * the stack. Push the address here, so the call instruction can
2356                                  * access it.
2357                                  */
2358                                 if (!cfg->arch.vret_addr_loc) {
2359                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2360                                         /* Prevent it from being register allocated or optimized away */
2361                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2362                                 }
2363
2364                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2365                         }
2366                 }
2367                 else {
2368                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2369                         vtarg->sreg1 = call->vret_var->dreg;
2370                         vtarg->dreg = mono_alloc_preg (cfg);
2371                         MONO_ADD_INS (cfg->cbb, vtarg);
2372
2373                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2374                 }
2375         }
2376
2377         if (cfg->method->save_lmf) {
2378                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2379                 MONO_ADD_INS (cfg->cbb, arg);
2380         }
2381
2382         call->stack_usage = cinfo->stack_usage;
2383 }
2384
2385 void
2386 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2387 {
2388         MonoInst *arg;
2389         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2390         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2391         int size = ins->backend.size;
2392
2393         if (ainfo->storage == ArgValuetypeInReg) {
2394                 MonoInst *load;
2395                 int part;
2396
2397                 for (part = 0; part < 2; ++part) {
2398                         if (ainfo->pair_storage [part] == ArgNone)
2399                                 continue;
2400
2401                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2402                         load->inst_basereg = src->dreg;
2403                         load->inst_offset = part * sizeof(mgreg_t);
2404
2405                         switch (ainfo->pair_storage [part]) {
2406                         case ArgInIReg:
2407                                 load->dreg = mono_alloc_ireg (cfg);
2408                                 break;
2409                         case ArgInDoubleSSEReg:
2410                         case ArgInFloatSSEReg:
2411                                 load->dreg = mono_alloc_freg (cfg);
2412                                 break;
2413                         default:
2414                                 g_assert_not_reached ();
2415                         }
2416                         MONO_ADD_INS (cfg->cbb, load);
2417
2418                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2419                 }
2420         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2421                 MonoInst *vtaddr, *load;
2422                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2423
2424                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2425                 cfg->has_indirection = TRUE;
2426                 load->inst_p0 = vtaddr;
2427                 vtaddr->flags |= MONO_INST_INDIRECT;
2428                 load->type = STACK_MP;
2429                 load->klass = vtaddr->klass;
2430                 load->dreg = mono_alloc_ireg (cfg);
2431                 MONO_ADD_INS (cfg->cbb, load);
2432                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2433
2434                 if (ainfo->pair_storage [0] == ArgInIReg) {
2435                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2436                         arg->dreg = mono_alloc_ireg (cfg);
2437                         arg->sreg1 = load->dreg;
2438                         arg->inst_imm = 0;
2439                         MONO_ADD_INS (cfg->cbb, arg);
2440                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2441                 } else {
2442                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2443                 }
2444         } else {
2445                 if (size == 8) {
2446                         int dreg = mono_alloc_ireg (cfg);
2447
2448                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2449                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2450                 } else if (size <= 40) {
2451                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2452                 } else {
2453                         // FIXME: Code growth
2454                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2455                 }
2456
2457                 if (cfg->compute_gc_maps) {
2458                         MonoInst *def;
2459                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2460                 }
2461         }
2462 }
2463
2464 void
2465 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2466 {
2467         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2468
2469         if (ret->type == MONO_TYPE_R4) {
2470                 if (COMPILE_LLVM (cfg))
2471                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2472                 else
2473                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2474                 return;
2475         } else if (ret->type == MONO_TYPE_R8) {
2476                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2477                 return;
2478         }
2479
2480         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2481 }
2482
2483 #endif /* DISABLE_JIT */
2484
2485 #define EMIT_COND_BRANCH(ins,cond,sign) \
2486         if (ins->inst_true_bb->native_offset) { \
2487                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2488         } else { \
2489                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2490                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2491             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2492                         x86_branch8 (code, cond, 0, sign); \
2493                 else \
2494                         x86_branch32 (code, cond, 0, sign); \
2495 }
2496
2497 typedef struct {
2498         MonoMethodSignature *sig;
2499         CallInfo *cinfo;
2500 } ArchDynCallInfo;
2501
2502 static gboolean
2503 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2504 {
2505         int i;
2506
2507 #ifdef HOST_WIN32
2508         return FALSE;
2509 #endif
2510
2511         switch (cinfo->ret.storage) {
2512         case ArgNone:
2513         case ArgInIReg:
2514                 break;
2515         case ArgValuetypeInReg: {
2516                 ArgInfo *ainfo = &cinfo->ret;
2517
2518                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2519                         return FALSE;
2520                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2521                         return FALSE;
2522                 break;
2523         }
2524         default:
2525                 return FALSE;
2526         }
2527
2528         for (i = 0; i < cinfo->nargs; ++i) {
2529                 ArgInfo *ainfo = &cinfo->args [i];
2530                 switch (ainfo->storage) {
2531                 case ArgInIReg:
2532                         break;
2533                 case ArgValuetypeInReg:
2534                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2535                                 return FALSE;
2536                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2537                                 return FALSE;
2538                         break;
2539                 default:
2540                         return FALSE;
2541                 }
2542         }
2543
2544         return TRUE;
2545 }
2546
2547 /*
2548  * mono_arch_dyn_call_prepare:
2549  *
2550  *   Return a pointer to an arch-specific structure which contains information
2551  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2552  * supported for SIG.
2553  * This function is equivalent to ffi_prep_cif in libffi.
2554  */
2555 MonoDynCallInfo*
2556 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2557 {
2558         ArchDynCallInfo *info;
2559         CallInfo *cinfo;
2560
2561         cinfo = get_call_info (NULL, NULL, sig);
2562
2563         if (!dyn_call_supported (sig, cinfo)) {
2564                 g_free (cinfo);
2565                 return NULL;
2566         }
2567
2568         info = g_new0 (ArchDynCallInfo, 1);
2569         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2570         info->sig = sig;
2571         info->cinfo = cinfo;
2572
2573         return (MonoDynCallInfo*)info;
2574 }
2575
2576 /*
2577  * mono_arch_dyn_call_free:
2578  *
2579  *   Free a MonoDynCallInfo structure.
2580  */
2581 void
2582 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2583 {
2584         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2585
2586         g_free (ainfo->cinfo);
2587         g_free (ainfo);
2588 }
2589
2590 #if !defined(__native_client__)
2591 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2592 #define GREG_TO_PTR(greg) (gpointer)(greg)
2593 #else
2594 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2595 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2596 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2597 #endif
2598
2599 /*
2600  * mono_arch_get_start_dyn_call:
2601  *
2602  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2603  * store the result into BUF.
2604  * ARGS should be an array of pointers pointing to the arguments.
2605  * RET should point to a memory buffer large enought to hold the result of the
2606  * call.
2607  * This function should be as fast as possible, any work which does not depend
2608  * on the actual values of the arguments should be done in
2609  * mono_arch_dyn_call_prepare ().
2610  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2611  * libffi.
2612  */
2613 void
2614 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2615 {
2616         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2617         DynCallArgs *p = (DynCallArgs*)buf;
2618         int arg_index, greg, i, pindex;
2619         MonoMethodSignature *sig = dinfo->sig;
2620
2621         g_assert (buf_len >= sizeof (DynCallArgs));
2622
2623         p->res = 0;
2624         p->ret = ret;
2625
2626         arg_index = 0;
2627         greg = 0;
2628         pindex = 0;
2629
2630         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2631                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2632                 if (!sig->hasthis)
2633                         pindex = 1;
2634         }
2635
2636         if (dinfo->cinfo->vtype_retaddr)
2637                 p->regs [greg ++] = PTR_TO_GREG(ret);
2638
2639         for (i = pindex; i < sig->param_count; i++) {
2640                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2641                 gpointer *arg = args [arg_index ++];
2642
2643                 if (t->byref) {
2644                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2645                         continue;
2646                 }
2647
2648                 switch (t->type) {
2649                 case MONO_TYPE_STRING:
2650                 case MONO_TYPE_CLASS:
2651                 case MONO_TYPE_ARRAY:
2652                 case MONO_TYPE_SZARRAY:
2653                 case MONO_TYPE_OBJECT:
2654                 case MONO_TYPE_PTR:
2655                 case MONO_TYPE_I:
2656                 case MONO_TYPE_U:
2657 #if !defined(__mono_ilp32__)
2658                 case MONO_TYPE_I8:
2659                 case MONO_TYPE_U8:
2660 #endif
2661                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2662                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2663                         break;
2664 #if defined(__mono_ilp32__)
2665                 case MONO_TYPE_I8:
2666                 case MONO_TYPE_U8:
2667                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2668                         p->regs [greg ++] = *(guint64*)(arg);
2669                         break;
2670 #endif
2671                 case MONO_TYPE_BOOLEAN:
2672                 case MONO_TYPE_U1:
2673                         p->regs [greg ++] = *(guint8*)(arg);
2674                         break;
2675                 case MONO_TYPE_I1:
2676                         p->regs [greg ++] = *(gint8*)(arg);
2677                         break;
2678                 case MONO_TYPE_I2:
2679                         p->regs [greg ++] = *(gint16*)(arg);
2680                         break;
2681                 case MONO_TYPE_U2:
2682                 case MONO_TYPE_CHAR:
2683                         p->regs [greg ++] = *(guint16*)(arg);
2684                         break;
2685                 case MONO_TYPE_I4:
2686                         p->regs [greg ++] = *(gint32*)(arg);
2687                         break;
2688                 case MONO_TYPE_U4:
2689                         p->regs [greg ++] = *(guint32*)(arg);
2690                         break;
2691                 case MONO_TYPE_GENERICINST:
2692                     if (MONO_TYPE_IS_REFERENCE (t)) {
2693                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2694                                 break;
2695                         } else {
2696                                 /* Fall through */
2697                         }
2698                 case MONO_TYPE_VALUETYPE: {
2699                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2700
2701                         g_assert (ainfo->storage == ArgValuetypeInReg);
2702                         if (ainfo->pair_storage [0] != ArgNone) {
2703                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2704                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2705                         }
2706                         if (ainfo->pair_storage [1] != ArgNone) {
2707                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2708                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2709                         }
2710                         break;
2711                 }
2712                 default:
2713                         g_assert_not_reached ();
2714                 }
2715         }
2716
2717         g_assert (greg <= PARAM_REGS);
2718 }
2719
2720 /*
2721  * mono_arch_finish_dyn_call:
2722  *
2723  *   Store the result of a dyn call into the return value buffer passed to
2724  * start_dyn_call ().
2725  * This function should be as fast as possible, any work which does not depend
2726  * on the actual values of the arguments should be done in
2727  * mono_arch_dyn_call_prepare ().
2728  */
2729 void
2730 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2731 {
2732         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2733         MonoMethodSignature *sig = dinfo->sig;
2734         guint8 *ret = ((DynCallArgs*)buf)->ret;
2735         mgreg_t res = ((DynCallArgs*)buf)->res;
2736         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2737
2738         switch (sig_ret->type) {
2739         case MONO_TYPE_VOID:
2740                 *(gpointer*)ret = NULL;
2741                 break;
2742         case MONO_TYPE_STRING:
2743         case MONO_TYPE_CLASS:
2744         case MONO_TYPE_ARRAY:
2745         case MONO_TYPE_SZARRAY:
2746         case MONO_TYPE_OBJECT:
2747         case MONO_TYPE_I:
2748         case MONO_TYPE_U:
2749         case MONO_TYPE_PTR:
2750                 *(gpointer*)ret = GREG_TO_PTR(res);
2751                 break;
2752         case MONO_TYPE_I1:
2753                 *(gint8*)ret = res;
2754                 break;
2755         case MONO_TYPE_U1:
2756         case MONO_TYPE_BOOLEAN:
2757                 *(guint8*)ret = res;
2758                 break;
2759         case MONO_TYPE_I2:
2760                 *(gint16*)ret = res;
2761                 break;
2762         case MONO_TYPE_U2:
2763         case MONO_TYPE_CHAR:
2764                 *(guint16*)ret = res;
2765                 break;
2766         case MONO_TYPE_I4:
2767                 *(gint32*)ret = res;
2768                 break;
2769         case MONO_TYPE_U4:
2770                 *(guint32*)ret = res;
2771                 break;
2772         case MONO_TYPE_I8:
2773                 *(gint64*)ret = res;
2774                 break;
2775         case MONO_TYPE_U8:
2776                 *(guint64*)ret = res;
2777                 break;
2778         case MONO_TYPE_GENERICINST:
2779                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2780                         *(gpointer*)ret = GREG_TO_PTR(res);
2781                         break;
2782                 } else {
2783                         /* Fall through */
2784                 }
2785         case MONO_TYPE_VALUETYPE:
2786                 if (dinfo->cinfo->vtype_retaddr) {
2787                         /* Nothing to do */
2788                 } else {
2789                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2790
2791                         g_assert (ainfo->storage == ArgValuetypeInReg);
2792
2793                         if (ainfo->pair_storage [0] != ArgNone) {
2794                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2795                                 ((mgreg_t*)ret)[0] = res;
2796                         }
2797
2798                         g_assert (ainfo->pair_storage [1] == ArgNone);
2799                 }
2800                 break;
2801         default:
2802                 g_assert_not_reached ();
2803         }
2804 }
2805
2806 /* emit an exception if condition is fail */
2807 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2808         do {                                                        \
2809                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2810                 if (tins == NULL) {                                                                             \
2811                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2812                                         MONO_PATCH_INFO_EXC, exc_name);  \
2813                         x86_branch32 (code, cond, 0, signed);               \
2814                 } else {        \
2815                         EMIT_COND_BRANCH (tins, cond, signed);  \
2816                 }                       \
2817         } while (0);
2818
2819 #define EMIT_FPCOMPARE(code) do { \
2820         amd64_fcompp (code); \
2821         amd64_fnstsw (code); \
2822 } while (0);
2823
2824 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2825     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2826         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2827         amd64_ ##op (code); \
2828         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2829         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2830 } while (0);
2831
2832 static guint8*
2833 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2834 {
2835         gboolean no_patch = FALSE;
2836
2837         /*
2838          * FIXME: Add support for thunks
2839          */
2840         {
2841                 gboolean near_call = FALSE;
2842
2843                 /*
2844                  * Indirect calls are expensive so try to make a near call if possible.
2845                  * The caller memory is allocated by the code manager so it is
2846                  * guaranteed to be at a 32 bit offset.
2847                  */
2848
2849                 if (patch_type != MONO_PATCH_INFO_ABS) {
2850                         /* The target is in memory allocated using the code manager */
2851                         near_call = TRUE;
2852
2853                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2854                                 if (((MonoMethod*)data)->klass->image->aot_module)
2855                                         /* The callee might be an AOT method */
2856                                         near_call = FALSE;
2857                                 if (((MonoMethod*)data)->dynamic)
2858                                         /* The target is in malloc-ed memory */
2859                                         near_call = FALSE;
2860                         }
2861
2862                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2863                                 /*
2864                                  * The call might go directly to a native function without
2865                                  * the wrapper.
2866                                  */
2867                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2868                                 if (mi) {
2869                                         gconstpointer target = mono_icall_get_wrapper (mi);
2870                                         if ((((guint64)target) >> 32) != 0)
2871                                                 near_call = FALSE;
2872                                 }
2873                         }
2874                 }
2875                 else {
2876                         MonoJumpInfo *jinfo = NULL;
2877
2878                         if (cfg->abs_patches)
2879                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2880                         if (jinfo) {
2881                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2882                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2883                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2884                                                 near_call = TRUE;
2885                                         no_patch = TRUE;
2886                                 } else {
2887                                         /*
2888                                          * This is not really an optimization, but required because the
2889                                          * generic class init trampolines use R11 to pass the vtable.
2890                                          */
2891                                         near_call = TRUE;
2892                                 }
2893                         } else {
2894                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2895                                 if (info) {
2896                                         if (info->func == info->wrapper) {
2897                                                 /* No wrapper */
2898                                                 if ((((guint64)info->func) >> 32) == 0)
2899                                                         near_call = TRUE;
2900                                         }
2901                                         else {
2902                                                 /* See the comment in mono_codegen () */
2903                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2904                                                         near_call = TRUE;
2905                                         }
2906                                 }
2907                                 else if ((((guint64)data) >> 32) == 0) {
2908                                         near_call = TRUE;
2909                                         no_patch = TRUE;
2910                                 }
2911                         }
2912                 }
2913
2914                 if (cfg->method->dynamic)
2915                         /* These methods are allocated using malloc */
2916                         near_call = FALSE;
2917
2918 #ifdef MONO_ARCH_NOMAP32BIT
2919                 near_call = FALSE;
2920 #endif
2921 #if defined(__native_client__)
2922                 /* Always use near_call == TRUE for Native Client */
2923                 near_call = TRUE;
2924 #endif
2925                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2926                 if (optimize_for_xen)
2927                         near_call = FALSE;
2928
2929                 if (cfg->compile_aot) {
2930                         near_call = TRUE;
2931                         no_patch = TRUE;
2932                 }
2933
2934                 if (near_call) {
2935                         /*
2936                          * Align the call displacement to an address divisible by 4 so it does
2937                          * not span cache lines. This is required for code patching to work on SMP
2938                          * systems.
2939                          */
2940                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2941                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2942                                 amd64_padding (code, pad_size);
2943                         }
2944                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2945                         amd64_call_code (code, 0);
2946                 }
2947                 else {
2948                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2949                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2950                         amd64_call_reg (code, GP_SCRATCH_REG);
2951                 }
2952         }
2953
2954         return code;
2955 }
2956
2957 static inline guint8*
2958 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2959 {
2960 #ifdef HOST_WIN32
2961         if (win64_adjust_stack)
2962                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2963 #endif
2964         code = emit_call_body (cfg, code, patch_type, data);
2965 #ifdef HOST_WIN32
2966         if (win64_adjust_stack)
2967                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2968 #endif
2969
2970         return code;
2971 }
2972
2973 static inline int
2974 store_membase_imm_to_store_membase_reg (int opcode)
2975 {
2976         switch (opcode) {
2977         case OP_STORE_MEMBASE_IMM:
2978                 return OP_STORE_MEMBASE_REG;
2979         case OP_STOREI4_MEMBASE_IMM:
2980                 return OP_STOREI4_MEMBASE_REG;
2981         case OP_STOREI8_MEMBASE_IMM:
2982                 return OP_STOREI8_MEMBASE_REG;
2983         }
2984
2985         return -1;
2986 }
2987
2988 #ifndef DISABLE_JIT
2989
2990 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2991
2992 /*
2993  * mono_arch_peephole_pass_1:
2994  *
2995  *   Perform peephole opts which should/can be performed before local regalloc
2996  */
2997 void
2998 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2999 {
3000         MonoInst *ins, *n;
3001
3002         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3003                 MonoInst *last_ins = ins->prev;
3004
3005                 switch (ins->opcode) {
3006                 case OP_ADD_IMM:
3007                 case OP_IADD_IMM:
3008                 case OP_LADD_IMM:
3009                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3010                                 /*
3011                                  * X86_LEA is like ADD, but doesn't have the
3012                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3013                                  * its operand to 64 bit.
3014                                  */
3015                                 ins->opcode = OP_X86_LEA_MEMBASE;
3016                                 ins->inst_basereg = ins->sreg1;
3017                         }
3018                         break;
3019                 case OP_LXOR:
3020                 case OP_IXOR:
3021                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3022                                 MonoInst *ins2;
3023
3024                                 /*
3025                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3026                                  * the latter has length 2-3 instead of 6 (reverse constant
3027                                  * propagation). These instruction sequences are very common
3028                                  * in the initlocals bblock.
3029                                  */
3030                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3031                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3032                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3033                                                 ins2->sreg1 = ins->dreg;
3034                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3035                                                 /* Continue */
3036                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3037                                                 NULLIFY_INS (ins2);
3038                                                 /* Continue */
3039                                         } else {
3040                                                 break;
3041                                         }
3042                                 }
3043                         }
3044                         break;
3045                 case OP_COMPARE_IMM:
3046                 case OP_LCOMPARE_IMM:
3047                         /* OP_COMPARE_IMM (reg, 0)
3048                          * -->
3049                          * OP_AMD64_TEST_NULL (reg)
3050                          */
3051                         if (!ins->inst_imm)
3052                                 ins->opcode = OP_AMD64_TEST_NULL;
3053                         break;
3054                 case OP_ICOMPARE_IMM:
3055                         if (!ins->inst_imm)
3056                                 ins->opcode = OP_X86_TEST_NULL;
3057                         break;
3058                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3059                         /*
3060                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3061                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3062                          * -->
3063                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3064                          * OP_COMPARE_IMM reg, imm
3065                          *
3066                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3067                          */
3068                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3069                             ins->inst_basereg == last_ins->inst_destbasereg &&
3070                             ins->inst_offset == last_ins->inst_offset) {
3071                                         ins->opcode = OP_ICOMPARE_IMM;
3072                                         ins->sreg1 = last_ins->sreg1;
3073
3074                                         /* check if we can remove cmp reg,0 with test null */
3075                                         if (!ins->inst_imm)
3076                                                 ins->opcode = OP_X86_TEST_NULL;
3077                                 }
3078
3079                         break;
3080                 }
3081
3082                 mono_peephole_ins (bb, ins);
3083         }
3084 }
3085
3086 void
3087 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3088 {
3089         MonoInst *ins, *n;
3090
3091         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3092                 switch (ins->opcode) {
3093                 case OP_ICONST:
3094                 case OP_I8CONST: {
3095                         /* reg = 0 -> XOR (reg, reg) */
3096                         /* XOR sets cflags on x86, so we cant do it always */
3097                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3098                                 ins->opcode = OP_LXOR;
3099                                 ins->sreg1 = ins->dreg;
3100                                 ins->sreg2 = ins->dreg;
3101                                 /* Fall through */
3102                         } else {
3103                                 break;
3104                         }
3105                 }
3106                 case OP_LXOR:
3107                         /*
3108                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3109                          * 0 result into 64 bits.
3110                          */
3111                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3112                                 ins->opcode = OP_IXOR;
3113                         }
3114                         /* Fall through */
3115                 case OP_IXOR:
3116                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3117                                 MonoInst *ins2;
3118
3119                                 /*
3120                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3121                                  * the latter has length 2-3 instead of 6 (reverse constant
3122                                  * propagation). These instruction sequences are very common
3123                                  * in the initlocals bblock.
3124                                  */
3125                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3126                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3127                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3128                                                 ins2->sreg1 = ins->dreg;
3129                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3130                                                 /* Continue */
3131                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3132                                                 NULLIFY_INS (ins2);
3133                                                 /* Continue */
3134                                         } else {
3135                                                 break;
3136                                         }
3137                                 }
3138                         }
3139                         break;
3140                 case OP_IADD_IMM:
3141                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3142                                 ins->opcode = OP_X86_INC_REG;
3143                         break;
3144                 case OP_ISUB_IMM:
3145                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3146                                 ins->opcode = OP_X86_DEC_REG;
3147                         break;
3148                 }
3149
3150                 mono_peephole_ins (bb, ins);
3151         }
3152 }
3153
3154 #define NEW_INS(cfg,ins,dest,op) do {   \
3155                 MONO_INST_NEW ((cfg), (dest), (op)); \
3156         (dest)->cil_code = (ins)->cil_code; \
3157         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3158         } while (0)
3159
3160 /*
3161  * mono_arch_lowering_pass:
3162  *
3163  *  Converts complex opcodes into simpler ones so that each IR instruction
3164  * corresponds to one machine instruction.
3165  */
3166 void
3167 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3168 {
3169         MonoInst *ins, *n, *temp;
3170
3171         /*
3172          * FIXME: Need to add more instructions, but the current machine
3173          * description can't model some parts of the composite instructions like
3174          * cdq.
3175          */
3176         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3177                 switch (ins->opcode) {
3178                 case OP_DIV_IMM:
3179                 case OP_REM_IMM:
3180                 case OP_IDIV_IMM:
3181                 case OP_IDIV_UN_IMM:
3182                 case OP_IREM_UN_IMM:
3183                 case OP_LREM_IMM:
3184                 case OP_IREM_IMM:
3185                         mono_decompose_op_imm (cfg, bb, ins);
3186                         break;
3187                 case OP_COMPARE_IMM:
3188                 case OP_LCOMPARE_IMM:
3189                         if (!amd64_is_imm32 (ins->inst_imm)) {
3190                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3191                                 temp->inst_c0 = ins->inst_imm;
3192                                 temp->dreg = mono_alloc_ireg (cfg);
3193                                 ins->opcode = OP_COMPARE;
3194                                 ins->sreg2 = temp->dreg;
3195                         }
3196                         break;
3197 #ifndef __mono_ilp32__
3198                 case OP_LOAD_MEMBASE:
3199 #endif
3200                 case OP_LOADI8_MEMBASE:
3201 #ifndef __native_client_codegen__
3202                 /*  Don't generate memindex opcodes (to simplify */
3203                 /*  read sandboxing) */
3204                         if (!amd64_is_imm32 (ins->inst_offset)) {
3205                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3206                                 temp->inst_c0 = ins->inst_offset;
3207                                 temp->dreg = mono_alloc_ireg (cfg);
3208                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3209                                 ins->inst_indexreg = temp->dreg;
3210                         }
3211 #endif
3212                         break;
3213 #ifndef __mono_ilp32__
3214                 case OP_STORE_MEMBASE_IMM:
3215 #endif
3216                 case OP_STOREI8_MEMBASE_IMM:
3217                         if (!amd64_is_imm32 (ins->inst_imm)) {
3218                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3219                                 temp->inst_c0 = ins->inst_imm;
3220                                 temp->dreg = mono_alloc_ireg (cfg);
3221                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3222                                 ins->sreg1 = temp->dreg;
3223                         }
3224                         break;
3225 #ifdef MONO_ARCH_SIMD_INTRINSICS
3226                 case OP_EXPAND_I1: {
3227                                 int temp_reg1 = mono_alloc_ireg (cfg);
3228                                 int temp_reg2 = mono_alloc_ireg (cfg);
3229                                 int original_reg = ins->sreg1;
3230
3231                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3232                                 temp->sreg1 = original_reg;
3233                                 temp->dreg = temp_reg1;
3234
3235                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3236                                 temp->sreg1 = temp_reg1;
3237                                 temp->dreg = temp_reg2;
3238                                 temp->inst_imm = 8;
3239
3240                                 NEW_INS (cfg, ins, temp, OP_LOR);
3241                                 temp->sreg1 = temp->dreg = temp_reg2;
3242                                 temp->sreg2 = temp_reg1;
3243
3244                                 ins->opcode = OP_EXPAND_I2;
3245                                 ins->sreg1 = temp_reg2;
3246                         }
3247                         break;
3248 #endif
3249                 default:
3250                         break;
3251                 }
3252         }
3253
3254         bb->max_vreg = cfg->next_vreg;
3255 }
3256
3257 static const int
3258 branch_cc_table [] = {
3259         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3260         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3261         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3262 };
3263
3264 /* Maps CMP_... constants to X86_CC_... constants */
3265 static const int
3266 cc_table [] = {
3267         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3268         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3269 };
3270
3271 static const int
3272 cc_signed_table [] = {
3273         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3274         FALSE, FALSE, FALSE, FALSE
3275 };
3276
3277 /*#include "cprop.c"*/
3278
3279 static unsigned char*
3280 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3281 {
3282         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3283
3284         if (size == 1)
3285                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3286         else if (size == 2)
3287                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3288         return code;
3289 }
3290
3291 static unsigned char*
3292 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3293 {
3294         int sreg = tree->sreg1;
3295         int need_touch = FALSE;
3296
3297 #if defined(HOST_WIN32)
3298         need_touch = TRUE;
3299 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3300         if (!tree->flags & MONO_INST_INIT)
3301                 need_touch = TRUE;
3302 #endif
3303
3304         if (need_touch) {
3305                 guint8* br[5];
3306
3307                 /*
3308                  * Under Windows:
3309                  * If requested stack size is larger than one page,
3310                  * perform stack-touch operation
3311                  */
3312                 /*
3313                  * Generate stack probe code.
3314                  * Under Windows, it is necessary to allocate one page at a time,
3315                  * "touching" stack after each successful sub-allocation. This is
3316                  * because of the way stack growth is implemented - there is a
3317                  * guard page before the lowest stack page that is currently commited.
3318                  * Stack normally grows sequentially so OS traps access to the
3319                  * guard page and commits more pages when needed.
3320                  */
3321                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3322                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3323
3324                 br[2] = code; /* loop */
3325                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3326                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3327                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3328                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3329                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3330                 amd64_patch (br[3], br[2]);
3331                 amd64_test_reg_reg (code, sreg, sreg);
3332                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3333                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3334
3335                 br[1] = code; x86_jump8 (code, 0);
3336
3337                 amd64_patch (br[0], code);
3338                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3339                 amd64_patch (br[1], code);
3340                 amd64_patch (br[4], code);
3341         }
3342         else
3343                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3344
3345         if (tree->flags & MONO_INST_INIT) {
3346                 int offset = 0;
3347                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3348                         amd64_push_reg (code, AMD64_RAX);
3349                         offset += 8;
3350                 }
3351                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3352                         amd64_push_reg (code, AMD64_RCX);
3353                         offset += 8;
3354                 }
3355                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3356                         amd64_push_reg (code, AMD64_RDI);
3357                         offset += 8;
3358                 }
3359
3360                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3361                 if (sreg != AMD64_RCX)
3362                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3363                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3364
3365                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3366                 if (cfg->param_area)
3367                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3368                 amd64_cld (code);
3369 #if defined(__default_codegen__)
3370                 amd64_prefix (code, X86_REP_PREFIX);
3371                 amd64_stosl (code);
3372 #elif defined(__native_client_codegen__)
3373                 /* NaCl stos pseudo-instruction */
3374                 amd64_codegen_pre(code);
3375                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3376                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3377                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3378                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3379                 amd64_prefix (code, X86_REP_PREFIX);
3380                 amd64_stosl (code);
3381                 amd64_codegen_post(code);
3382 #endif /* __native_client_codegen__ */
3383
3384                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3385                         amd64_pop_reg (code, AMD64_RDI);
3386                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3387                         amd64_pop_reg (code, AMD64_RCX);
3388                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3389                         amd64_pop_reg (code, AMD64_RAX);
3390         }
3391         return code;
3392 }
3393
3394 static guint8*
3395 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3396 {
3397         CallInfo *cinfo;
3398         guint32 quad;
3399
3400         /* Move return value to the target register */
3401         /* FIXME: do this in the local reg allocator */
3402         switch (ins->opcode) {
3403         case OP_CALL:
3404         case OP_CALL_REG:
3405         case OP_CALL_MEMBASE:
3406         case OP_LCALL:
3407         case OP_LCALL_REG:
3408         case OP_LCALL_MEMBASE:
3409                 g_assert (ins->dreg == AMD64_RAX);
3410                 break;
3411         case OP_FCALL:
3412         case OP_FCALL_REG:
3413         case OP_FCALL_MEMBASE:
3414                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3415                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3416                 }
3417                 else {
3418                         if (ins->dreg != AMD64_XMM0)
3419                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3420                 }
3421                 break;
3422         case OP_VCALL:
3423         case OP_VCALL_REG:
3424         case OP_VCALL_MEMBASE:
3425         case OP_VCALL2:
3426         case OP_VCALL2_REG:
3427         case OP_VCALL2_MEMBASE:
3428                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3429                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3430                         MonoInst *loc = cfg->arch.vret_addr_loc;
3431
3432                         /* Load the destination address */
3433                         g_assert (loc->opcode == OP_REGOFFSET);
3434                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3435
3436                         for (quad = 0; quad < 2; quad ++) {
3437                                 switch (cinfo->ret.pair_storage [quad]) {
3438                                 case ArgInIReg:
3439                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3440                                         break;
3441                                 case ArgInFloatSSEReg:
3442                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3443                                         break;
3444                                 case ArgInDoubleSSEReg:
3445                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3446                                         break;
3447                                 case ArgNone:
3448                                         break;
3449                                 default:
3450                                         NOT_IMPLEMENTED;
3451                                 }
3452                         }
3453                 }
3454                 break;
3455         }
3456
3457         return code;
3458 }
3459
3460 #endif /* DISABLE_JIT */
3461
3462 #ifdef __APPLE__
3463 static int tls_gs_offset;
3464 #endif
3465
3466 gboolean
3467 mono_amd64_have_tls_get (void)
3468 {
3469 #ifdef __APPLE__
3470         static gboolean have_tls_get = FALSE;
3471         static gboolean inited = FALSE;
3472         guint8 *ins;
3473
3474         if (inited)
3475                 return have_tls_get;
3476
3477         ins = (guint8*)pthread_getspecific;
3478
3479         /*
3480          * We're looking for these two instructions:
3481          *
3482          * mov    %gs:[offset](,%rdi,8),%rax
3483          * retq
3484          */
3485         have_tls_get = ins [0] == 0x65 &&
3486                        ins [1] == 0x48 &&
3487                        ins [2] == 0x8b &&
3488                        ins [3] == 0x04 &&
3489                        ins [4] == 0xfd &&
3490                        ins [6] == 0x00 &&
3491                        ins [7] == 0x00 &&
3492                        ins [8] == 0x00 &&
3493                        ins [9] == 0xc3;
3494
3495         inited = TRUE;
3496
3497         tls_gs_offset = ins[5];
3498
3499         return have_tls_get;
3500 #else
3501         return TRUE;
3502 #endif
3503 }
3504
3505 int
3506 mono_amd64_get_tls_gs_offset (void)
3507 {
3508 #ifdef TARGET_OSX
3509         return tls_gs_offset;
3510 #else
3511         g_assert_not_reached ();
3512         return -1;
3513 #endif
3514 }
3515
3516 /*
3517  * mono_amd64_emit_tls_get:
3518  * @code: buffer to store code to
3519  * @dreg: hard register where to place the result
3520  * @tls_offset: offset info
3521  *
3522  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3523  * the dreg register the item in the thread local storage identified
3524  * by tls_offset.
3525  *
3526  * Returns: a pointer to the end of the stored code
3527  */
3528 guint8*
3529 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3530 {
3531 #ifdef HOST_WIN32
3532         if (tls_offset < 64) {
3533                 x86_prefix (code, X86_GS_PREFIX);
3534                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3535         } else {
3536                 guint8 *buf [16];
3537
3538                 g_assert (tls_offset < 0x440);
3539                 /* Load TEB->TlsExpansionSlots */
3540                 x86_prefix (code, X86_GS_PREFIX);
3541                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3542                 amd64_test_reg_reg (code, dreg, dreg);
3543                 buf [0] = code;
3544                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3545                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3546                 amd64_patch (buf [0], code);
3547         }
3548 #elif defined(__APPLE__)
3549         x86_prefix (code, X86_GS_PREFIX);
3550         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3551 #else
3552         if (optimize_for_xen) {
3553                 x86_prefix (code, X86_FS_PREFIX);
3554                 amd64_mov_reg_mem (code, dreg, 0, 8);
3555                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3556         } else {
3557                 x86_prefix (code, X86_FS_PREFIX);
3558                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3559         }
3560 #endif
3561         return code;
3562 }
3563
3564 static guint8*
3565 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3566 {
3567         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3568 #ifdef TARGET_OSX
3569         if (dreg != offset_reg)
3570                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3571         amd64_prefix (code, X86_GS_PREFIX);
3572         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3573 #elif defined(__linux__)
3574         int tmpreg = -1;
3575
3576         if (dreg == offset_reg) {
3577                 /* Use a temporary reg by saving it to the redzone */
3578                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3579                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3580                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3581                 offset_reg = tmpreg;
3582         }
3583         x86_prefix (code, X86_FS_PREFIX);
3584         amd64_mov_reg_mem (code, dreg, 0, 8);
3585         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3586         if (tmpreg != -1)
3587                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3588 #else
3589         g_assert_not_reached ();
3590 #endif
3591         return code;
3592 }
3593
3594 static guint8*
3595 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3596 {
3597 #ifdef HOST_WIN32
3598         g_assert_not_reached ();
3599 #elif defined(__APPLE__)
3600         x86_prefix (code, X86_GS_PREFIX);
3601         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3602 #else
3603         g_assert (!optimize_for_xen);
3604         x86_prefix (code, X86_FS_PREFIX);
3605         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3606 #endif
3607         return code;
3608 }
3609
3610 static guint8*
3611 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3612 {
3613         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3614 #ifdef HOST_WIN32
3615         g_assert_not_reached ();
3616 #elif defined(__APPLE__)
3617         x86_prefix (code, X86_GS_PREFIX);
3618         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3619 #else
3620         x86_prefix (code, X86_FS_PREFIX);
3621         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3622 #endif
3623         return code;
3624 }
3625
3626  /*
3627  * mono_arch_translate_tls_offset:
3628  *
3629  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3630  */
3631 int
3632 mono_arch_translate_tls_offset (int offset)
3633 {
3634 #ifdef __APPLE__
3635         return tls_gs_offset + (offset * 8);
3636 #else
3637         return offset;
3638 #endif
3639 }
3640
3641 /*
3642  * emit_setup_lmf:
3643  *
3644  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3645  */
3646 static guint8*
3647 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3648 {
3649         /*
3650          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3651          */
3652         /*
3653          * sp is saved right before calls but we need to save it here too so
3654          * async stack walks would work.
3655          */
3656         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3657         /* Save rbp */
3658         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3659         if (cfg->arch.omit_fp && cfa_offset != -1)
3660                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3661
3662         /* These can't contain refs */
3663         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3664         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3665         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3666         /* These are handled automatically by the stack marking code */
3667         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3668
3669         return code;
3670 }
3671
3672 #define REAL_PRINT_REG(text,reg) \
3673 mono_assert (reg >= 0); \
3674 amd64_push_reg (code, AMD64_RAX); \
3675 amd64_push_reg (code, AMD64_RDX); \
3676 amd64_push_reg (code, AMD64_RCX); \
3677 amd64_push_reg (code, reg); \
3678 amd64_push_imm (code, reg); \
3679 amd64_push_imm (code, text " %d %p\n"); \
3680 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3681 amd64_call_reg (code, AMD64_RAX); \
3682 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3683 amd64_pop_reg (code, AMD64_RCX); \
3684 amd64_pop_reg (code, AMD64_RDX); \
3685 amd64_pop_reg (code, AMD64_RAX);
3686
3687 /* benchmark and set based on cpu */
3688 #define LOOP_ALIGNMENT 8
3689 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3690
3691 #ifndef DISABLE_JIT
3692 void
3693 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3694 {
3695         MonoInst *ins;
3696         MonoCallInst *call;
3697         guint offset;
3698         guint8 *code = cfg->native_code + cfg->code_len;
3699         MonoInst *last_ins = NULL;
3700         guint last_offset = 0;
3701         int max_len;
3702
3703         /* Fix max_offset estimate for each successor bb */
3704         if (cfg->opt & MONO_OPT_BRANCH) {
3705                 int current_offset = cfg->code_len;
3706                 MonoBasicBlock *current_bb;
3707                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3708                         current_bb->max_offset = current_offset;
3709                         current_offset += current_bb->max_length;
3710                 }
3711         }
3712
3713         if (cfg->opt & MONO_OPT_LOOP) {
3714                 int pad, align = LOOP_ALIGNMENT;
3715                 /* set alignment depending on cpu */
3716                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3717                         pad = align - pad;
3718                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3719                         amd64_padding (code, pad);
3720                         cfg->code_len += pad;
3721                         bb->native_offset = cfg->code_len;
3722                 }
3723         }
3724
3725 #if defined(__native_client_codegen__)
3726         /* For Native Client, all indirect call/jump targets must be */
3727         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3728         /* indirectly as well.                                       */
3729         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3730                                       (bb->flags & BB_EXCEPTION_HANDLER);
3731
3732         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3733                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3734                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3735                 cfg->code_len += pad;
3736                 bb->native_offset = cfg->code_len;
3737         }
3738 #endif  /*__native_client_codegen__*/
3739
3740         if (cfg->verbose_level > 2)
3741                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3742
3743         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3744                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3745                 g_assert (!cfg->compile_aot);
3746
3747                 cov->data [bb->dfn].cil_code = bb->cil_code;
3748                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3749                 /* this is not thread save, but good enough */
3750                 amd64_inc_membase (code, AMD64_R11, 0);
3751         }
3752
3753         offset = code - cfg->native_code;
3754
3755         mono_debug_open_block (cfg, bb, offset);
3756
3757     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3758                 x86_breakpoint (code);
3759
3760         MONO_BB_FOR_EACH_INS (bb, ins) {
3761                 offset = code - cfg->native_code;
3762
3763                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3764
3765 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3766
3767                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3768                         cfg->code_size *= 2;
3769                         cfg->native_code = mono_realloc_native_code(cfg);
3770                         code = cfg->native_code + offset;
3771                         cfg->stat_code_reallocs++;
3772                 }
3773
3774                 if (cfg->debug_info)
3775                         mono_debug_record_line_number (cfg, ins, offset);
3776
3777                 switch (ins->opcode) {
3778                 case OP_BIGMUL:
3779                         amd64_mul_reg (code, ins->sreg2, TRUE);
3780                         break;
3781                 case OP_BIGMUL_UN:
3782                         amd64_mul_reg (code, ins->sreg2, FALSE);
3783                         break;
3784                 case OP_X86_SETEQ_MEMBASE:
3785                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3786                         break;
3787                 case OP_STOREI1_MEMBASE_IMM:
3788                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3789                         break;
3790                 case OP_STOREI2_MEMBASE_IMM:
3791                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3792                         break;
3793                 case OP_STOREI4_MEMBASE_IMM:
3794                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3795                         break;
3796                 case OP_STOREI1_MEMBASE_REG:
3797                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3798                         break;
3799                 case OP_STOREI2_MEMBASE_REG:
3800                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3801                         break;
3802                 /* In AMD64 NaCl, pointers are 4 bytes, */
3803                 /*  so STORE_* != STOREI8_*. Likewise below. */
3804                 case OP_STORE_MEMBASE_REG:
3805                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3806                         break;
3807                 case OP_STOREI8_MEMBASE_REG:
3808                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3809                         break;
3810                 case OP_STOREI4_MEMBASE_REG:
3811                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3812                         break;
3813                 case OP_STORE_MEMBASE_IMM:
3814 #ifndef __native_client_codegen__
3815                         /* In NaCl, this could be a PCONST type, which could */
3816                         /* mean a pointer type was copied directly into the  */
3817                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3818                         /* the value would be 0x00000000FFFFFFFF which is    */
3819                         /* not proper for an imm32 unless you cast it.       */
3820                         g_assert (amd64_is_imm32 (ins->inst_imm));
3821 #endif
3822                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3823                         break;
3824                 case OP_STOREI8_MEMBASE_IMM:
3825                         g_assert (amd64_is_imm32 (ins->inst_imm));
3826                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3827                         break;
3828                 case OP_LOAD_MEM:
3829 #ifdef __mono_ilp32__
3830                         /* In ILP32, pointers are 4 bytes, so separate these */
3831                         /* cases, use literal 8 below where we really want 8 */
3832                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3833                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3834                         break;
3835 #endif
3836                 case OP_LOADI8_MEM:
3837                         // FIXME: Decompose this earlier
3838                         if (amd64_is_imm32 (ins->inst_imm))
3839                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3840                         else {
3841                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3842                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3843                         }
3844                         break;
3845                 case OP_LOADI4_MEM:
3846                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3847                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3848                         break;
3849                 case OP_LOADU4_MEM:
3850                         // FIXME: Decompose this earlier
3851                         if (amd64_is_imm32 (ins->inst_imm))
3852                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3853                         else {
3854                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3855                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3856                         }
3857                         break;
3858                 case OP_LOADU1_MEM:
3859                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3860                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3861                         break;
3862                 case OP_LOADU2_MEM:
3863                         /* For NaCl, pointers are 4 bytes, so separate these */
3864                         /* cases, use literal 8 below where we really want 8 */
3865                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3866                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3867                         break;
3868                 case OP_LOAD_MEMBASE:
3869                         g_assert (amd64_is_imm32 (ins->inst_offset));
3870                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3871                         break;
3872                 case OP_LOADI8_MEMBASE:
3873                         /* Use literal 8 instead of sizeof pointer or */
3874                         /* register, we really want 8 for this opcode */
3875                         g_assert (amd64_is_imm32 (ins->inst_offset));
3876                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3877                         break;
3878                 case OP_LOADI4_MEMBASE:
3879                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3880                         break;
3881                 case OP_LOADU4_MEMBASE:
3882                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3883                         break;
3884                 case OP_LOADU1_MEMBASE:
3885                         /* The cpu zero extends the result into 64 bits */
3886                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3887                         break;
3888                 case OP_LOADI1_MEMBASE:
3889                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3890                         break;
3891                 case OP_LOADU2_MEMBASE:
3892                         /* The cpu zero extends the result into 64 bits */
3893                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3894                         break;
3895                 case OP_LOADI2_MEMBASE:
3896                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3897                         break;
3898                 case OP_AMD64_LOADI8_MEMINDEX:
3899                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3900                         break;
3901                 case OP_LCONV_TO_I1:
3902                 case OP_ICONV_TO_I1:
3903                 case OP_SEXT_I1:
3904                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3905                         break;
3906                 case OP_LCONV_TO_I2:
3907                 case OP_ICONV_TO_I2:
3908                 case OP_SEXT_I2:
3909                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3910                         break;
3911                 case OP_LCONV_TO_U1:
3912                 case OP_ICONV_TO_U1:
3913                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3914                         break;
3915                 case OP_LCONV_TO_U2:
3916                 case OP_ICONV_TO_U2:
3917                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3918                         break;
3919                 case OP_ZEXT_I4:
3920                         /* Clean out the upper word */
3921                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3922                         break;
3923                 case OP_SEXT_I4:
3924                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3925                         break;
3926                 case OP_COMPARE:
3927                 case OP_LCOMPARE:
3928                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3929                         break;
3930                 case OP_COMPARE_IMM:
3931 #if defined(__mono_ilp32__)
3932                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3933                         g_assert (amd64_is_imm32 (ins->inst_imm));
3934                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3935                         break;
3936 #endif
3937                 case OP_LCOMPARE_IMM:
3938                         g_assert (amd64_is_imm32 (ins->inst_imm));
3939                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3940                         break;
3941                 case OP_X86_COMPARE_REG_MEMBASE:
3942                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3943                         break;
3944                 case OP_X86_TEST_NULL:
3945                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3946                         break;
3947                 case OP_AMD64_TEST_NULL:
3948                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3949                         break;
3950
3951                 case OP_X86_ADD_REG_MEMBASE:
3952                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3953                         break;
3954                 case OP_X86_SUB_REG_MEMBASE:
3955                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3956                         break;
3957                 case OP_X86_AND_REG_MEMBASE:
3958                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3959                         break;
3960                 case OP_X86_OR_REG_MEMBASE:
3961                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3962                         break;
3963                 case OP_X86_XOR_REG_MEMBASE:
3964                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3965                         break;
3966
3967                 case OP_X86_ADD_MEMBASE_IMM:
3968                         /* FIXME: Make a 64 version too */
3969                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3970                         break;
3971                 case OP_X86_SUB_MEMBASE_IMM:
3972                         g_assert (amd64_is_imm32 (ins->inst_imm));
3973                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3974                         break;
3975                 case OP_X86_AND_MEMBASE_IMM:
3976                         g_assert (amd64_is_imm32 (ins->inst_imm));
3977                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3978                         break;
3979                 case OP_X86_OR_MEMBASE_IMM:
3980                         g_assert (amd64_is_imm32 (ins->inst_imm));
3981                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3982                         break;
3983                 case OP_X86_XOR_MEMBASE_IMM:
3984                         g_assert (amd64_is_imm32 (ins->inst_imm));
3985                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3986                         break;
3987                 case OP_X86_ADD_MEMBASE_REG:
3988                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3989                         break;
3990                 case OP_X86_SUB_MEMBASE_REG:
3991                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3992                         break;
3993                 case OP_X86_AND_MEMBASE_REG:
3994                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3995                         break;
3996                 case OP_X86_OR_MEMBASE_REG:
3997                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3998                         break;
3999                 case OP_X86_XOR_MEMBASE_REG:
4000                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4001                         break;
4002                 case OP_X86_INC_MEMBASE:
4003                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4004                         break;
4005                 case OP_X86_INC_REG:
4006                         amd64_inc_reg_size (code, ins->dreg, 4);
4007                         break;
4008                 case OP_X86_DEC_MEMBASE:
4009                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4010                         break;
4011                 case OP_X86_DEC_REG:
4012                         amd64_dec_reg_size (code, ins->dreg, 4);
4013                         break;
4014                 case OP_X86_MUL_REG_MEMBASE:
4015                 case OP_X86_MUL_MEMBASE_REG:
4016                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4017                         break;
4018                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4019                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4020                         break;
4021                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4022                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4023                         break;
4024                 case OP_AMD64_COMPARE_MEMBASE_REG:
4025                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4026                         break;
4027                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4028                         g_assert (amd64_is_imm32 (ins->inst_imm));
4029                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4030                         break;
4031                 case OP_X86_COMPARE_MEMBASE8_IMM:
4032                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4033                         break;
4034                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4035                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4036                         break;
4037                 case OP_AMD64_COMPARE_REG_MEMBASE:
4038                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4039                         break;
4040
4041                 case OP_AMD64_ADD_REG_MEMBASE:
4042                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4043                         break;
4044                 case OP_AMD64_SUB_REG_MEMBASE:
4045                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4046                         break;
4047                 case OP_AMD64_AND_REG_MEMBASE:
4048                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4049                         break;
4050                 case OP_AMD64_OR_REG_MEMBASE:
4051                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4052                         break;
4053                 case OP_AMD64_XOR_REG_MEMBASE:
4054                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4055                         break;
4056
4057                 case OP_AMD64_ADD_MEMBASE_REG:
4058                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4059                         break;
4060                 case OP_AMD64_SUB_MEMBASE_REG:
4061                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4062                         break;
4063                 case OP_AMD64_AND_MEMBASE_REG:
4064                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4065                         break;
4066                 case OP_AMD64_OR_MEMBASE_REG:
4067                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4068                         break;
4069                 case OP_AMD64_XOR_MEMBASE_REG:
4070                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4071                         break;
4072
4073                 case OP_AMD64_ADD_MEMBASE_IMM:
4074                         g_assert (amd64_is_imm32 (ins->inst_imm));
4075                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4076                         break;
4077                 case OP_AMD64_SUB_MEMBASE_IMM:
4078                         g_assert (amd64_is_imm32 (ins->inst_imm));
4079                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4080                         break;
4081                 case OP_AMD64_AND_MEMBASE_IMM:
4082                         g_assert (amd64_is_imm32 (ins->inst_imm));
4083                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4084                         break;
4085                 case OP_AMD64_OR_MEMBASE_IMM:
4086                         g_assert (amd64_is_imm32 (ins->inst_imm));
4087                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4088                         break;
4089                 case OP_AMD64_XOR_MEMBASE_IMM:
4090                         g_assert (amd64_is_imm32 (ins->inst_imm));
4091                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4092                         break;
4093
4094                 case OP_BREAK:
4095                         amd64_breakpoint (code);
4096                         break;
4097                 case OP_RELAXED_NOP:
4098                         x86_prefix (code, X86_REP_PREFIX);
4099                         x86_nop (code);
4100                         break;
4101                 case OP_HARD_NOP:
4102                         x86_nop (code);
4103                         break;
4104                 case OP_NOP:
4105                 case OP_DUMMY_USE:
4106                 case OP_DUMMY_STORE:
4107                 case OP_DUMMY_ICONST:
4108                 case OP_DUMMY_R8CONST:
4109                 case OP_NOT_REACHED:
4110                 case OP_NOT_NULL:
4111                         break;
4112                 case OP_IL_SEQ_POINT:
4113                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4114                         break;
4115                 case OP_SEQ_POINT: {
4116                         int i;
4117
4118                         /*
4119                          * Read from the single stepping trigger page. This will cause a
4120                          * SIGSEGV when single stepping is enabled.
4121                          * We do this _before_ the breakpoint, so single stepping after
4122                          * a breakpoint is hit will step to the next IL offset.
4123                          */
4124                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4125                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4126
4127                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4128                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4129                         }
4130
4131                         /*
4132                          * This is the address which is saved in seq points,
4133                          */
4134                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4135
4136                         if (cfg->compile_aot) {
4137                                 guint32 offset = code - cfg->native_code;
4138                                 guint32 val;
4139                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4140
4141                                 /* Load info var */
4142                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4143                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4144                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4145                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4146                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4147                         } else {
4148                                 /*
4149                                  * A placeholder for a possible breakpoint inserted by
4150                                  * mono_arch_set_breakpoint ().
4151                                  */
4152                                 for (i = 0; i < breakpoint_size; ++i)
4153                                         x86_nop (code);
4154                         }
4155                         /*
4156                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4157                          * to another IL offset.
4158                          */
4159                         x86_nop (code);
4160                         break;
4161                 }
4162                 case OP_ADDCC:
4163                 case OP_LADDCC:
4164                 case OP_LADD:
4165                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4166                         break;
4167                 case OP_ADC:
4168                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4169                         break;
4170                 case OP_ADD_IMM:
4171                 case OP_LADD_IMM:
4172                         g_assert (amd64_is_imm32 (ins->inst_imm));
4173                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4174                         break;
4175                 case OP_ADC_IMM:
4176                         g_assert (amd64_is_imm32 (ins->inst_imm));
4177                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4178                         break;
4179                 case OP_SUBCC:
4180                 case OP_LSUBCC:
4181                 case OP_LSUB:
4182                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4183                         break;
4184                 case OP_SBB:
4185                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4186                         break;
4187                 case OP_SUB_IMM:
4188                 case OP_LSUB_IMM:
4189                         g_assert (amd64_is_imm32 (ins->inst_imm));
4190                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4191                         break;
4192                 case OP_SBB_IMM:
4193                         g_assert (amd64_is_imm32 (ins->inst_imm));
4194                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4195                         break;
4196                 case OP_LAND:
4197                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4198                         break;
4199                 case OP_AND_IMM:
4200                 case OP_LAND_IMM:
4201                         g_assert (amd64_is_imm32 (ins->inst_imm));
4202                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4203                         break;
4204                 case OP_LMUL:
4205                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4206                         break;
4207                 case OP_MUL_IMM:
4208                 case OP_LMUL_IMM:
4209                 case OP_IMUL_IMM: {
4210                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4211
4212                         switch (ins->inst_imm) {
4213                         case 2:
4214                                 /* MOV r1, r2 */
4215                                 /* ADD r1, r1 */
4216                                 if (ins->dreg != ins->sreg1)
4217                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4218                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4219                                 break;
4220                         case 3:
4221                                 /* LEA r1, [r2 + r2*2] */
4222                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4223                                 break;
4224                         case 5:
4225                                 /* LEA r1, [r2 + r2*4] */
4226                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4227                                 break;
4228                         case 6:
4229                                 /* LEA r1, [r2 + r2*2] */
4230                                 /* ADD r1, r1          */
4231                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4232                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4233                                 break;
4234                         case 9:
4235                                 /* LEA r1, [r2 + r2*8] */
4236                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4237                                 break;
4238                         case 10:
4239                                 /* LEA r1, [r2 + r2*4] */
4240                                 /* ADD r1, r1          */
4241                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4242                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4243                                 break;
4244                         case 12:
4245                                 /* LEA r1, [r2 + r2*2] */
4246                                 /* SHL r1, 2           */
4247                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4248                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4249                                 break;
4250                         case 25:
4251                                 /* LEA r1, [r2 + r2*4] */
4252                                 /* LEA r1, [r1 + r1*4] */
4253                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4254                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4255                                 break;
4256                         case 100:
4257                                 /* LEA r1, [r2 + r2*4] */
4258                                 /* SHL r1, 2           */
4259                                 /* LEA r1, [r1 + r1*4] */
4260                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4261                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4262                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4263                                 break;
4264                         default:
4265                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4266                                 break;
4267                         }
4268                         break;
4269                 }
4270                 case OP_LDIV:
4271                 case OP_LREM:
4272 #if defined( __native_client_codegen__ )
4273                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4274                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4275 #endif
4276                         /* Regalloc magic makes the div/rem cases the same */
4277                         if (ins->sreg2 == AMD64_RDX) {
4278                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4279                                 amd64_cdq (code);
4280                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4281                         } else {
4282                                 amd64_cdq (code);
4283                                 amd64_div_reg (code, ins->sreg2, TRUE);
4284                         }
4285                         break;
4286                 case OP_LDIV_UN:
4287                 case OP_LREM_UN:
4288 #if defined( __native_client_codegen__ )
4289                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4290                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4291 #endif
4292                         if (ins->sreg2 == AMD64_RDX) {
4293                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4294                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4295                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4296                         } else {
4297                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4298                                 amd64_div_reg (code, ins->sreg2, FALSE);
4299                         }
4300                         break;
4301                 case OP_IDIV:
4302                 case OP_IREM:
4303 #if defined( __native_client_codegen__ )
4304                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4305                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4306 #endif
4307                         if (ins->sreg2 == AMD64_RDX) {
4308                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4309                                 amd64_cdq_size (code, 4);
4310                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4311                         } else {
4312                                 amd64_cdq_size (code, 4);
4313                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4314                         }
4315                         break;
4316                 case OP_IDIV_UN:
4317                 case OP_IREM_UN:
4318 #if defined( __native_client_codegen__ )
4319                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4320                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4321 #endif
4322                         if (ins->sreg2 == AMD64_RDX) {
4323                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4324                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4325                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4326                         } else {
4327                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4328                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4329                         }
4330                         break;
4331                 case OP_LMUL_OVF:
4332                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4333                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4334                         break;
4335                 case OP_LOR:
4336                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4337                         break;
4338                 case OP_OR_IMM:
4339                 case OP_LOR_IMM:
4340                         g_assert (amd64_is_imm32 (ins->inst_imm));
4341                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4342                         break;
4343                 case OP_LXOR:
4344                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4345                         break;
4346                 case OP_XOR_IMM:
4347                 case OP_LXOR_IMM:
4348                         g_assert (amd64_is_imm32 (ins->inst_imm));
4349                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4350                         break;
4351                 case OP_LSHL:
4352                         g_assert (ins->sreg2 == AMD64_RCX);
4353                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4354                         break;
4355                 case OP_LSHR:
4356                         g_assert (ins->sreg2 == AMD64_RCX);
4357                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4358                         break;
4359                 case OP_SHR_IMM:
4360                         g_assert (amd64_is_imm32 (ins->inst_imm));
4361                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4362                         break;
4363                 case OP_LSHR_IMM:
4364                         g_assert (amd64_is_imm32 (ins->inst_imm));
4365                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4366                         break;
4367                 case OP_SHR_UN_IMM:
4368                         g_assert (amd64_is_imm32 (ins->inst_imm));
4369                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4370                         break;
4371                 case OP_LSHR_UN_IMM:
4372                         g_assert (amd64_is_imm32 (ins->inst_imm));
4373                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4374                         break;
4375                 case OP_LSHR_UN:
4376                         g_assert (ins->sreg2 == AMD64_RCX);
4377                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4378                         break;
4379                 case OP_SHL_IMM:
4380                         g_assert (amd64_is_imm32 (ins->inst_imm));
4381                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4382                         break;
4383                 case OP_LSHL_IMM:
4384                         g_assert (amd64_is_imm32 (ins->inst_imm));
4385                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4386                         break;
4387
4388                 case OP_IADDCC:
4389                 case OP_IADD:
4390                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4391                         break;
4392                 case OP_IADC:
4393                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4394                         break;
4395                 case OP_IADD_IMM:
4396                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4397                         break;
4398                 case OP_IADC_IMM:
4399                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4400                         break;
4401                 case OP_ISUBCC:
4402                 case OP_ISUB:
4403                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4404                         break;
4405                 case OP_ISBB:
4406                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4407                         break;
4408                 case OP_ISUB_IMM:
4409                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4410                         break;
4411                 case OP_ISBB_IMM:
4412                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4413                         break;
4414                 case OP_IAND:
4415                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4416                         break;
4417                 case OP_IAND_IMM:
4418                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4419                         break;
4420                 case OP_IOR:
4421                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4422                         break;
4423                 case OP_IOR_IMM:
4424                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4425                         break;
4426                 case OP_IXOR:
4427                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4428                         break;
4429                 case OP_IXOR_IMM:
4430                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4431                         break;
4432                 case OP_INEG:
4433                         amd64_neg_reg_size (code, ins->sreg1, 4);
4434                         break;
4435                 case OP_INOT:
4436                         amd64_not_reg_size (code, ins->sreg1, 4);
4437                         break;
4438                 case OP_ISHL:
4439                         g_assert (ins->sreg2 == AMD64_RCX);
4440                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4441                         break;
4442                 case OP_ISHR:
4443                         g_assert (ins->sreg2 == AMD64_RCX);
4444                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4445                         break;
4446                 case OP_ISHR_IMM:
4447                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4448                         break;
4449                 case OP_ISHR_UN_IMM:
4450                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4451                         break;
4452                 case OP_ISHR_UN:
4453                         g_assert (ins->sreg2 == AMD64_RCX);
4454                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4455                         break;
4456                 case OP_ISHL_IMM:
4457                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4458                         break;
4459                 case OP_IMUL:
4460                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4461                         break;
4462                 case OP_IMUL_OVF:
4463                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4464                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4465                         break;
4466                 case OP_IMUL_OVF_UN:
4467                 case OP_LMUL_OVF_UN: {
4468                         /* the mul operation and the exception check should most likely be split */
4469                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4470                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4471                         /*g_assert (ins->sreg2 == X86_EAX);
4472                         g_assert (ins->dreg == X86_EAX);*/
4473                         if (ins->sreg2 == X86_EAX) {
4474                                 non_eax_reg = ins->sreg1;
4475                         } else if (ins->sreg1 == X86_EAX) {
4476                                 non_eax_reg = ins->sreg2;
4477                         } else {
4478                                 /* no need to save since we're going to store to it anyway */
4479                                 if (ins->dreg != X86_EAX) {
4480                                         saved_eax = TRUE;
4481                                         amd64_push_reg (code, X86_EAX);
4482                                 }
4483                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4484                                 non_eax_reg = ins->sreg2;
4485                         }
4486                         if (ins->dreg == X86_EDX) {
4487                                 if (!saved_eax) {
4488                                         saved_eax = TRUE;
4489                                         amd64_push_reg (code, X86_EAX);
4490                                 }
4491                         } else {
4492                                 saved_edx = TRUE;
4493                                 amd64_push_reg (code, X86_EDX);
4494                         }
4495                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4496                         /* save before the check since pop and mov don't change the flags */
4497                         if (ins->dreg != X86_EAX)
4498                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4499                         if (saved_edx)
4500                                 amd64_pop_reg (code, X86_EDX);
4501                         if (saved_eax)
4502                                 amd64_pop_reg (code, X86_EAX);
4503                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4504                         break;
4505                 }
4506                 case OP_ICOMPARE:
4507                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4508                         break;
4509                 case OP_ICOMPARE_IMM:
4510                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4511                         break;
4512                 case OP_IBEQ:
4513                 case OP_IBLT:
4514                 case OP_IBGT:
4515                 case OP_IBGE:
4516                 case OP_IBLE:
4517                 case OP_LBEQ:
4518                 case OP_LBLT:
4519                 case OP_LBGT:
4520                 case OP_LBGE:
4521                 case OP_LBLE:
4522                 case OP_IBNE_UN:
4523                 case OP_IBLT_UN:
4524                 case OP_IBGT_UN:
4525                 case OP_IBGE_UN:
4526                 case OP_IBLE_UN:
4527                 case OP_LBNE_UN:
4528                 case OP_LBLT_UN:
4529                 case OP_LBGT_UN:
4530                 case OP_LBGE_UN:
4531                 case OP_LBLE_UN:
4532                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4533                         break;
4534
4535                 case OP_CMOV_IEQ:
4536                 case OP_CMOV_IGE:
4537                 case OP_CMOV_IGT:
4538                 case OP_CMOV_ILE:
4539                 case OP_CMOV_ILT:
4540                 case OP_CMOV_INE_UN:
4541                 case OP_CMOV_IGE_UN:
4542                 case OP_CMOV_IGT_UN:
4543                 case OP_CMOV_ILE_UN:
4544                 case OP_CMOV_ILT_UN:
4545                 case OP_CMOV_LEQ:
4546                 case OP_CMOV_LGE:
4547                 case OP_CMOV_LGT:
4548                 case OP_CMOV_LLE:
4549                 case OP_CMOV_LLT:
4550                 case OP_CMOV_LNE_UN:
4551                 case OP_CMOV_LGE_UN:
4552                 case OP_CMOV_LGT_UN:
4553                 case OP_CMOV_LLE_UN:
4554                 case OP_CMOV_LLT_UN:
4555                         g_assert (ins->dreg == ins->sreg1);
4556                         /* This needs to operate on 64 bit values */
4557                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4558                         break;
4559
4560                 case OP_LNOT:
4561                         amd64_not_reg (code, ins->sreg1);
4562                         break;
4563                 case OP_LNEG:
4564                         amd64_neg_reg (code, ins->sreg1);
4565                         break;
4566
4567                 case OP_ICONST:
4568                 case OP_I8CONST:
4569                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4570                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4571                         else
4572                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4573                         break;
4574                 case OP_AOTCONST:
4575                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4576                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4577                         break;
4578                 case OP_JUMP_TABLE:
4579                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4580                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4581                         break;
4582                 case OP_MOVE:
4583                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4584                         break;
4585                 case OP_AMD64_SET_XMMREG_R4: {
4586                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4587                         break;
4588                 }
4589                 case OP_AMD64_SET_XMMREG_R8: {
4590                         if (ins->dreg != ins->sreg1)
4591                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4592                         break;
4593                 }
4594                 case OP_TAILCALL: {
4595                         MonoCallInst *call = (MonoCallInst*)ins;
4596                         int i, save_area_offset;
4597
4598                         g_assert (!cfg->method->save_lmf);
4599
4600                         /* Restore callee saved registers */
4601                         save_area_offset = cfg->arch.reg_save_area_offset;
4602                         for (i = 0; i < AMD64_NREG; ++i)
4603                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4604                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4605                                         save_area_offset += 8;
4606                                 }
4607
4608                         if (cfg->arch.omit_fp) {
4609                                 if (cfg->arch.stack_alloc_size)
4610                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4611                                 // FIXME:
4612                                 if (call->stack_usage)
4613                                         NOT_IMPLEMENTED;
4614                         } else {
4615                                 /* Copy arguments on the stack to our argument area */
4616                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4617                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4618                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4619                                 }
4620
4621                                 amd64_leave (code);
4622                         }
4623
4624                         offset = code - cfg->native_code;
4625                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4626                         if (cfg->compile_aot)
4627                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4628                         else
4629                                 amd64_set_reg_template (code, AMD64_R11);
4630                         amd64_jump_reg (code, AMD64_R11);
4631                         ins->flags |= MONO_INST_GC_CALLSITE;
4632                         ins->backend.pc_offset = code - cfg->native_code;
4633                         break;
4634                 }
4635                 case OP_CHECK_THIS:
4636                         /* ensure ins->sreg1 is not NULL */
4637                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4638                         break;
4639                 case OP_ARGLIST: {
4640                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4641                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4642                         break;
4643                 }
4644                 case OP_CALL:
4645                 case OP_FCALL:
4646                 case OP_LCALL:
4647                 case OP_VCALL:
4648                 case OP_VCALL2:
4649                 case OP_VOIDCALL:
4650                         call = (MonoCallInst*)ins;
4651                         /*
4652                          * The AMD64 ABI forces callers to know about varargs.
4653                          */
4654                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4655                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4656                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4657                                 /*
4658                                  * Since the unmanaged calling convention doesn't contain a
4659                                  * 'vararg' entry, we have to treat every pinvoke call as a
4660                                  * potential vararg call.
4661                                  */
4662                                 guint32 nregs, i;
4663                                 nregs = 0;
4664                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4665                                         if (call->used_fregs & (1 << i))
4666                                                 nregs ++;
4667                                 if (!nregs)
4668                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4669                                 else
4670                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4671                         }
4672
4673                         if (ins->flags & MONO_INST_HAS_METHOD)
4674                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4675                         else
4676                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4677                         ins->flags |= MONO_INST_GC_CALLSITE;
4678                         ins->backend.pc_offset = code - cfg->native_code;
4679                         code = emit_move_return_value (cfg, ins, code);
4680                         break;
4681                 case OP_FCALL_REG:
4682                 case OP_LCALL_REG:
4683                 case OP_VCALL_REG:
4684                 case OP_VCALL2_REG:
4685                 case OP_VOIDCALL_REG:
4686                 case OP_CALL_REG:
4687                         call = (MonoCallInst*)ins;
4688
4689                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4690                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4691                                 ins->sreg1 = AMD64_R11;
4692                         }
4693
4694                         /*
4695                          * The AMD64 ABI forces callers to know about varargs.
4696                          */
4697                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4698                                 if (ins->sreg1 == AMD64_RAX) {
4699                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4700                                         ins->sreg1 = AMD64_R11;
4701                                 }
4702                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4703                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4704                                 /*
4705                                  * Since the unmanaged calling convention doesn't contain a
4706                                  * 'vararg' entry, we have to treat every pinvoke call as a
4707                                  * potential vararg call.
4708                                  */
4709                                 guint32 nregs, i;
4710                                 nregs = 0;
4711                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4712                                         if (call->used_fregs & (1 << i))
4713                                                 nregs ++;
4714                                 if (ins->sreg1 == AMD64_RAX) {
4715                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4716                                         ins->sreg1 = AMD64_R11;
4717                                 }
4718                                 if (!nregs)
4719                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4720                                 else
4721                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4722                         }
4723
4724                         amd64_call_reg (code, ins->sreg1);
4725                         ins->flags |= MONO_INST_GC_CALLSITE;
4726                         ins->backend.pc_offset = code - cfg->native_code;
4727                         code = emit_move_return_value (cfg, ins, code);
4728                         break;
4729                 case OP_FCALL_MEMBASE:
4730                 case OP_LCALL_MEMBASE:
4731                 case OP_VCALL_MEMBASE:
4732                 case OP_VCALL2_MEMBASE:
4733                 case OP_VOIDCALL_MEMBASE:
4734                 case OP_CALL_MEMBASE:
4735                         call = (MonoCallInst*)ins;
4736
4737                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4738                         ins->flags |= MONO_INST_GC_CALLSITE;
4739                         ins->backend.pc_offset = code - cfg->native_code;
4740                         code = emit_move_return_value (cfg, ins, code);
4741                         break;
4742                 case OP_DYN_CALL: {
4743                         int i;
4744                         MonoInst *var = cfg->dyn_call_var;
4745
4746                         g_assert (var->opcode == OP_REGOFFSET);
4747
4748                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4749                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4750                         /* r10 = ftn */
4751                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4752
4753                         /* Save args buffer */
4754                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4755
4756                         /* Set argument registers */
4757                         for (i = 0; i < PARAM_REGS; ++i)
4758                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4759
4760                         /* Make the call */
4761                         amd64_call_reg (code, AMD64_R10);
4762
4763                         ins->flags |= MONO_INST_GC_CALLSITE;
4764                         ins->backend.pc_offset = code - cfg->native_code;
4765
4766                         /* Save result */
4767                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4768                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4769                         break;
4770                 }
4771                 case OP_AMD64_SAVE_SP_TO_LMF: {
4772                         MonoInst *lmf_var = cfg->lmf_var;
4773                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4774                         break;
4775                 }
4776                 case OP_X86_PUSH:
4777                         g_assert_not_reached ();
4778                         amd64_push_reg (code, ins->sreg1);
4779                         break;
4780                 case OP_X86_PUSH_IMM:
4781                         g_assert_not_reached ();
4782                         g_assert (amd64_is_imm32 (ins->inst_imm));
4783                         amd64_push_imm (code, ins->inst_imm);
4784                         break;
4785                 case OP_X86_PUSH_MEMBASE:
4786                         g_assert_not_reached ();
4787                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4788                         break;
4789                 case OP_X86_PUSH_OBJ: {
4790                         int size = ALIGN_TO (ins->inst_imm, 8);
4791
4792                         g_assert_not_reached ();
4793
4794                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4795                         amd64_push_reg (code, AMD64_RDI);
4796                         amd64_push_reg (code, AMD64_RSI);
4797                         amd64_push_reg (code, AMD64_RCX);
4798                         if (ins->inst_offset)
4799                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4800                         else
4801                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4802                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4803                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4804                         amd64_cld (code);
4805                         amd64_prefix (code, X86_REP_PREFIX);
4806                         amd64_movsd (code);
4807                         amd64_pop_reg (code, AMD64_RCX);
4808                         amd64_pop_reg (code, AMD64_RSI);
4809                         amd64_pop_reg (code, AMD64_RDI);
4810                         break;
4811                 }
4812                 case OP_X86_LEA:
4813                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4814                         break;
4815                 case OP_X86_LEA_MEMBASE:
4816                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4817                         break;
4818                 case OP_X86_XCHG:
4819                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4820                         break;
4821                 case OP_LOCALLOC:
4822                         /* keep alignment */
4823                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4824                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4825                         code = mono_emit_stack_alloc (cfg, code, ins);
4826                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4827                         if (cfg->param_area)
4828                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4829                         break;
4830                 case OP_LOCALLOC_IMM: {
4831                         guint32 size = ins->inst_imm;
4832                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4833
4834                         if (ins->flags & MONO_INST_INIT) {
4835                                 if (size < 64) {
4836                                         int i;
4837
4838                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4839                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4840
4841                                         for (i = 0; i < size; i += 8)
4842                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4843                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4844                                 } else {
4845                                         amd64_mov_reg_imm (code, ins->dreg, size);
4846                                         ins->sreg1 = ins->dreg;
4847
4848                                         code = mono_emit_stack_alloc (cfg, code, ins);
4849                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4850                                 }
4851                         } else {
4852                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4853                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4854                         }
4855                         if (cfg->param_area)
4856                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4857                         break;
4858                 }
4859                 case OP_THROW: {
4860                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4861                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4862                                              (gpointer)"mono_arch_throw_exception", FALSE);
4863                         ins->flags |= MONO_INST_GC_CALLSITE;
4864                         ins->backend.pc_offset = code - cfg->native_code;
4865                         break;
4866                 }
4867                 case OP_RETHROW: {
4868                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4869                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4870                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4871                         ins->flags |= MONO_INST_GC_CALLSITE;
4872                         ins->backend.pc_offset = code - cfg->native_code;
4873                         break;
4874                 }
4875                 case OP_CALL_HANDLER:
4876                         /* Align stack */
4877                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4878                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4879                         amd64_call_imm (code, 0);
4880                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4881                         /* Restore stack alignment */
4882                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4883                         break;
4884                 case OP_START_HANDLER: {
4885                         /* Even though we're saving RSP, use sizeof */
4886                         /* gpointer because spvar is of type IntPtr */
4887                         /* see: mono_create_spvar_for_region */
4888                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4889                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4890
4891                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4892                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4893                                 cfg->param_area) {
4894                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4895                         }
4896                         break;
4897                 }
4898                 case OP_ENDFINALLY: {
4899                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4900                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4901                         amd64_ret (code);
4902                         break;
4903                 }
4904                 case OP_ENDFILTER: {
4905                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4906                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4907                         /* The local allocator will put the result into RAX */
4908                         amd64_ret (code);
4909                         break;
4910                 }
4911
4912                 case OP_LABEL:
4913                         ins->inst_c0 = code - cfg->native_code;
4914                         break;
4915                 case OP_BR:
4916                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4917                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4918                         //break;
4919                                 if (ins->inst_target_bb->native_offset) {
4920                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4921                                 } else {
4922                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4923                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4924                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4925                                                 x86_jump8 (code, 0);
4926                                         else
4927                                                 x86_jump32 (code, 0);
4928                         }
4929                         break;
4930                 case OP_BR_REG:
4931                         amd64_jump_reg (code, ins->sreg1);
4932                         break;
4933                 case OP_ICNEQ:
4934                 case OP_ICGE:
4935                 case OP_ICLE:
4936                 case OP_ICGE_UN:
4937                 case OP_ICLE_UN:
4938
4939                 case OP_CEQ:
4940                 case OP_LCEQ:
4941                 case OP_ICEQ:
4942                 case OP_CLT:
4943                 case OP_LCLT:
4944                 case OP_ICLT:
4945                 case OP_CGT:
4946                 case OP_ICGT:
4947                 case OP_LCGT:
4948                 case OP_CLT_UN:
4949                 case OP_LCLT_UN:
4950                 case OP_ICLT_UN:
4951                 case OP_CGT_UN:
4952                 case OP_LCGT_UN:
4953                 case OP_ICGT_UN:
4954                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4955                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4956                         break;
4957                 case OP_COND_EXC_EQ:
4958                 case OP_COND_EXC_NE_UN:
4959                 case OP_COND_EXC_LT:
4960                 case OP_COND_EXC_LT_UN:
4961                 case OP_COND_EXC_GT:
4962                 case OP_COND_EXC_GT_UN:
4963                 case OP_COND_EXC_GE:
4964                 case OP_COND_EXC_GE_UN:
4965                 case OP_COND_EXC_LE:
4966                 case OP_COND_EXC_LE_UN:
4967                 case OP_COND_EXC_IEQ:
4968                 case OP_COND_EXC_INE_UN:
4969                 case OP_COND_EXC_ILT:
4970                 case OP_COND_EXC_ILT_UN:
4971                 case OP_COND_EXC_IGT:
4972                 case OP_COND_EXC_IGT_UN:
4973                 case OP_COND_EXC_IGE:
4974                 case OP_COND_EXC_IGE_UN:
4975                 case OP_COND_EXC_ILE:
4976                 case OP_COND_EXC_ILE_UN:
4977                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4978                         break;
4979                 case OP_COND_EXC_OV:
4980                 case OP_COND_EXC_NO:
4981                 case OP_COND_EXC_C:
4982                 case OP_COND_EXC_NC:
4983                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4984                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4985                         break;
4986                 case OP_COND_EXC_IOV:
4987                 case OP_COND_EXC_INO:
4988                 case OP_COND_EXC_IC:
4989                 case OP_COND_EXC_INC:
4990                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4991                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4992                         break;
4993
4994                 /* floating point opcodes */
4995                 case OP_R8CONST: {
4996                         double d = *(double *)ins->inst_p0;
4997
4998                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4999                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5000                         }
5001                         else {
5002                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5003                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5004                         }
5005                         break;
5006                 }
5007                 case OP_R4CONST: {
5008                         float f = *(float *)ins->inst_p0;
5009
5010                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5011                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5012                         }
5013                         else {
5014                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5015                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5016                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5017                         }
5018                         break;
5019                 }
5020                 case OP_STORER8_MEMBASE_REG:
5021                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5022                         break;
5023                 case OP_LOADR8_MEMBASE:
5024                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5025                         break;
5026                 case OP_STORER4_MEMBASE_REG:
5027                         /* This requires a double->single conversion */
5028                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5029                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5030                         break;
5031                 case OP_LOADR4_MEMBASE:
5032                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5033                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5034                         break;
5035                 case OP_ICONV_TO_R4:
5036                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5037                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5038                         break;
5039                 case OP_ICONV_TO_R8:
5040                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5041                         break;
5042                 case OP_LCONV_TO_R4:
5043                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5044                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5045                         break;
5046                 case OP_LCONV_TO_R8:
5047                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5048                         break;
5049                 case OP_FCONV_TO_R4:
5050                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5051                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5052                         break;
5053                 case OP_FCONV_TO_I1:
5054                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5055                         break;
5056                 case OP_FCONV_TO_U1:
5057                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5058                         break;
5059                 case OP_FCONV_TO_I2:
5060                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5061                         break;
5062                 case OP_FCONV_TO_U2:
5063                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5064                         break;
5065                 case OP_FCONV_TO_U4:
5066                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5067                         break;
5068                 case OP_FCONV_TO_I4:
5069                 case OP_FCONV_TO_I:
5070                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5071                         break;
5072                 case OP_FCONV_TO_I8:
5073                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5074                         break;
5075                 case OP_LCONV_TO_R_UN: {
5076                         guint8 *br [2];
5077
5078                         /* Based on gcc code */
5079                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5080                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5081
5082                         /* Positive case */
5083                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5084                         br [1] = code; x86_jump8 (code, 0);
5085                         amd64_patch (br [0], code);
5086
5087                         /* Negative case */
5088                         /* Save to the red zone */
5089                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5090                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5091                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5092                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5093                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5094                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5095                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5096                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5097                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5098                         /* Restore */
5099                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5100                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5101                         amd64_patch (br [1], code);
5102                         break;
5103                 }
5104                 case OP_LCONV_TO_OVF_U4:
5105                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5106                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5107                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5108                         break;
5109                 case OP_LCONV_TO_OVF_I4_UN:
5110                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5111                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5112                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5113                         break;
5114                 case OP_FMOVE:
5115                         if (ins->dreg != ins->sreg1)
5116                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5117                         break;
5118                 case OP_FADD:
5119                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5120                         break;
5121                 case OP_FSUB:
5122                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5123                         break;
5124                 case OP_FMUL:
5125                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5126                         break;
5127                 case OP_FDIV:
5128                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5129                         break;
5130                 case OP_FNEG: {
5131                         static double r8_0 = -0.0;
5132
5133                         g_assert (ins->sreg1 == ins->dreg);
5134
5135                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5136                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5137                         break;
5138                 }
5139                 case OP_SIN:
5140                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5141                         break;
5142                 case OP_COS:
5143                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5144                         break;
5145                 case OP_ABS: {
5146                         static guint64 d = 0x7fffffffffffffffUL;
5147
5148                         g_assert (ins->sreg1 == ins->dreg);
5149
5150                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5151                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5152                         break;
5153                 }
5154                 case OP_SQRT:
5155                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5156                         break;
5157                 case OP_IMIN:
5158                         g_assert (cfg->opt & MONO_OPT_CMOV);
5159                         g_assert (ins->dreg == ins->sreg1);
5160                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5161                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5162                         break;
5163                 case OP_IMIN_UN:
5164                         g_assert (cfg->opt & MONO_OPT_CMOV);
5165                         g_assert (ins->dreg == ins->sreg1);
5166                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5167                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5168                         break;
5169                 case OP_IMAX:
5170                         g_assert (cfg->opt & MONO_OPT_CMOV);
5171                         g_assert (ins->dreg == ins->sreg1);
5172                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5173                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5174                         break;
5175                 case OP_IMAX_UN:
5176                         g_assert (cfg->opt & MONO_OPT_CMOV);
5177                         g_assert (ins->dreg == ins->sreg1);
5178                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5179                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5180                         break;
5181                 case OP_LMIN:
5182                         g_assert (cfg->opt & MONO_OPT_CMOV);
5183                         g_assert (ins->dreg == ins->sreg1);
5184                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5185                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5186                         break;
5187                 case OP_LMIN_UN:
5188                         g_assert (cfg->opt & MONO_OPT_CMOV);
5189                         g_assert (ins->dreg == ins->sreg1);
5190                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5191                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5192                         break;
5193                 case OP_LMAX:
5194                         g_assert (cfg->opt & MONO_OPT_CMOV);
5195                         g_assert (ins->dreg == ins->sreg1);
5196                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5197                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5198                         break;
5199                 case OP_LMAX_UN:
5200                         g_assert (cfg->opt & MONO_OPT_CMOV);
5201                         g_assert (ins->dreg == ins->sreg1);
5202                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5203                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5204                         break;
5205                 case OP_X86_FPOP:
5206                         break;
5207                 case OP_FCOMPARE:
5208                         /*
5209                          * The two arguments are swapped because the fbranch instructions
5210                          * depend on this for the non-sse case to work.
5211                          */
5212                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5213                         break;
5214                 case OP_FCNEQ:
5215                 case OP_FCEQ: {
5216                         /* zeroing the register at the start results in
5217                          * shorter and faster code (we can also remove the widening op)
5218                          */
5219                         guchar *unordered_check;
5220                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5221                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5222                         unordered_check = code;
5223                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5224
5225                         if (ins->opcode == OP_FCEQ) {
5226                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5227                                 amd64_patch (unordered_check, code);
5228                         } else {
5229                                 guchar *jump_to_end;
5230                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5231                                 jump_to_end = code;
5232                                 x86_jump8 (code, 0);
5233                                 amd64_patch (unordered_check, code);
5234                                 amd64_inc_reg (code, ins->dreg);
5235                                 amd64_patch (jump_to_end, code);
5236                         }
5237                         break;
5238                 }
5239                 case OP_FCLT:
5240                 case OP_FCLT_UN:
5241                         /* zeroing the register at the start results in
5242                          * shorter and faster code (we can also remove the widening op)
5243                          */
5244                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5245                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5246                         if (ins->opcode == OP_FCLT_UN) {
5247                                 guchar *unordered_check = code;
5248                                 guchar *jump_to_end;
5249                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5250                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5251                                 jump_to_end = code;
5252                                 x86_jump8 (code, 0);
5253                                 amd64_patch (unordered_check, code);
5254                                 amd64_inc_reg (code, ins->dreg);
5255                                 amd64_patch (jump_to_end, code);
5256                         } else {
5257                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5258                         }
5259                         break;
5260                 case OP_FCLE: {
5261                         guchar *unordered_check;
5262                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5263                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5264                         unordered_check = code;
5265                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5266                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5267                         amd64_patch (unordered_check, code);
5268                         break;
5269                 }
5270                 case OP_FCGT:
5271                 case OP_FCGT_UN: {
5272                         /* zeroing the register at the start results in
5273                          * shorter and faster code (we can also remove the widening op)
5274                          */
5275                         guchar *unordered_check;
5276                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5277                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5278                         if (ins->opcode == OP_FCGT) {
5279                                 unordered_check = code;
5280                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5281                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5282                                 amd64_patch (unordered_check, code);
5283                         } else {
5284                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5285                         }
5286                         break;
5287                 }
5288                 case OP_FCGE: {
5289                         guchar *unordered_check;
5290                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5291                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5292                         unordered_check = code;
5293                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5294                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5295                         amd64_patch (unordered_check, code);
5296                         break;
5297                 }
5298
5299                 case OP_FCLT_MEMBASE:
5300                 case OP_FCGT_MEMBASE:
5301                 case OP_FCLT_UN_MEMBASE:
5302                 case OP_FCGT_UN_MEMBASE:
5303                 case OP_FCEQ_MEMBASE: {
5304                         guchar *unordered_check, *jump_to_end;
5305                         int x86_cond;
5306
5307                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5308                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5309
5310                         switch (ins->opcode) {
5311                         case OP_FCEQ_MEMBASE:
5312                                 x86_cond = X86_CC_EQ;
5313                                 break;
5314                         case OP_FCLT_MEMBASE:
5315                         case OP_FCLT_UN_MEMBASE:
5316                                 x86_cond = X86_CC_LT;
5317                                 break;
5318                         case OP_FCGT_MEMBASE:
5319                         case OP_FCGT_UN_MEMBASE:
5320                                 x86_cond = X86_CC_GT;
5321                                 break;
5322                         default:
5323                                 g_assert_not_reached ();
5324                         }
5325
5326                         unordered_check = code;
5327                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5328                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5329
5330                         switch (ins->opcode) {
5331                         case OP_FCEQ_MEMBASE:
5332                         case OP_FCLT_MEMBASE:
5333                         case OP_FCGT_MEMBASE:
5334                                 amd64_patch (unordered_check, code);
5335                                 break;
5336                         case OP_FCLT_UN_MEMBASE:
5337                         case OP_FCGT_UN_MEMBASE:
5338                                 jump_to_end = code;
5339                                 x86_jump8 (code, 0);
5340                                 amd64_patch (unordered_check, code);
5341                                 amd64_inc_reg (code, ins->dreg);
5342                                 amd64_patch (jump_to_end, code);
5343                                 break;
5344                         default:
5345                                 break;
5346                         }
5347                         break;
5348                 }
5349                 case OP_FBEQ: {
5350                         guchar *jump = code;
5351                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5352                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5353                         amd64_patch (jump, code);
5354                         break;
5355                 }
5356                 case OP_FBNE_UN:
5357                         /* Branch if C013 != 100 */
5358                         /* branch if !ZF or (PF|CF) */
5359                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5360                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5361                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5362                         break;
5363                 case OP_FBLT:
5364                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5365                         break;
5366                 case OP_FBLT_UN:
5367                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5368                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5369                         break;
5370                 case OP_FBGT:
5371                 case OP_FBGT_UN:
5372                         if (ins->opcode == OP_FBGT) {
5373                                 guchar *br1;
5374
5375                                 /* skip branch if C1=1 */
5376                                 br1 = code;
5377                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5378                                 /* branch if (C0 | C3) = 1 */
5379                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5380                                 amd64_patch (br1, code);
5381                                 break;
5382                         } else {
5383                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5384                         }
5385                         break;
5386                 case OP_FBGE: {
5387                         /* Branch if C013 == 100 or 001 */
5388                         guchar *br1;
5389
5390                         /* skip branch if C1=1 */
5391                         br1 = code;
5392                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5393                         /* branch if (C0 | C3) = 1 */
5394                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5395                         amd64_patch (br1, code);
5396                         break;
5397                 }
5398                 case OP_FBGE_UN:
5399                         /* Branch if C013 == 000 */
5400                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5401                         break;
5402                 case OP_FBLE: {
5403                         /* Branch if C013=000 or 100 */
5404                         guchar *br1;
5405
5406                         /* skip branch if C1=1 */
5407                         br1 = code;
5408                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5409                         /* branch if C0=0 */
5410                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5411                         amd64_patch (br1, code);
5412                         break;
5413                 }
5414                 case OP_FBLE_UN:
5415                         /* Branch if C013 != 001 */
5416                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5417                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5418                         break;
5419                 case OP_CKFINITE:
5420                         /* Transfer value to the fp stack */
5421                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5422                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5423                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5424
5425                         amd64_push_reg (code, AMD64_RAX);
5426                         amd64_fxam (code);
5427                         amd64_fnstsw (code);
5428                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5429                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5430                         amd64_pop_reg (code, AMD64_RAX);
5431                         amd64_fstp (code, 0);
5432                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5433                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5434                         break;
5435                 case OP_TLS_GET: {
5436                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5437                         break;
5438                 }
5439                 case OP_TLS_GET_REG:
5440                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5441                         break;
5442                 case OP_TLS_SET: {
5443                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5444                         break;
5445                 }
5446                 case OP_TLS_SET_REG: {
5447                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5448                         break;
5449                 }
5450                 case OP_MEMORY_BARRIER: {
5451                         switch (ins->backend.memory_barrier_kind) {
5452                         case StoreLoadBarrier:
5453                         case FullBarrier:
5454                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5455                                 x86_prefix (code, X86_LOCK_PREFIX);
5456                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5457                                 break;
5458                         }
5459                         break;
5460                 }
5461                 case OP_ATOMIC_ADD_I4:
5462                 case OP_ATOMIC_ADD_I8: {
5463                         int dreg = ins->dreg;
5464                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5465
5466                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5467                                 dreg = AMD64_R11;
5468
5469                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5470                         amd64_prefix (code, X86_LOCK_PREFIX);
5471                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5472                         /* dreg contains the old value, add with sreg2 value */
5473                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5474
5475                         if (ins->dreg != dreg)
5476                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5477
5478                         break;
5479                 }
5480                 case OP_ATOMIC_EXCHANGE_I4:
5481                 case OP_ATOMIC_EXCHANGE_I8: {
5482                         guchar *br[2];
5483                         int sreg2 = ins->sreg2;
5484                         int breg = ins->inst_basereg;
5485                         guint32 size;
5486                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5487
5488                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5489                                 size = 8;
5490                         else
5491                                 size = 4;
5492
5493                         /*
5494                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5495                          * an explanation of how this works.
5496                          */
5497
5498                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5499                          * hack to overcome limits in x86 reg allocator
5500                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5501                          */
5502                         g_assert (ins->dreg == AMD64_RAX);
5503
5504                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5505                                 /* Highly unlikely, but possible */
5506                                 need_push = TRUE;
5507
5508                         /* The pushes invalidate rsp */
5509                         if ((breg == AMD64_RAX) || need_push) {
5510                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5511                                 breg = AMD64_R11;
5512                         }
5513
5514                         /* We need the EAX reg for the comparand */
5515                         if (ins->sreg2 == AMD64_RAX) {
5516                                 if (breg != AMD64_R11) {
5517                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5518                                         sreg2 = AMD64_R11;
5519                                 } else {
5520                                         g_assert (need_push);
5521                                         amd64_push_reg (code, AMD64_RDX);
5522                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5523                                         sreg2 = AMD64_RDX;
5524                                         rdx_pushed = TRUE;
5525                                 }
5526                         }
5527
5528                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5529
5530                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5531                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5532                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5533                         amd64_patch (br [1], br [0]);
5534
5535                         if (rdx_pushed)
5536                                 amd64_pop_reg (code, AMD64_RDX);
5537
5538                         break;
5539                 }
5540                 case OP_ATOMIC_CAS_I4:
5541                 case OP_ATOMIC_CAS_I8: {
5542                         guint32 size;
5543
5544                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5545                                 size = 8;
5546                         else
5547                                 size = 4;
5548
5549                         /*
5550                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5551                          * an explanation of how this works.
5552                          */
5553                         g_assert (ins->sreg3 == AMD64_RAX);
5554                         g_assert (ins->sreg1 != AMD64_RAX);
5555                         g_assert (ins->sreg1 != ins->sreg2);
5556
5557                         amd64_prefix (code, X86_LOCK_PREFIX);
5558                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5559
5560                         if (ins->dreg != AMD64_RAX)
5561                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5562                         break;
5563                 }
5564                 case OP_CARD_TABLE_WBARRIER: {
5565                         int ptr = ins->sreg1;
5566                         int value = ins->sreg2;
5567                         guchar *br = 0;
5568                         int nursery_shift, card_table_shift;
5569                         gpointer card_table_mask;
5570                         size_t nursery_size;
5571
5572                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5573                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5574                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5575
5576                         /*If either point to the stack we can simply avoid the WB. This happens due to
5577                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5578                          */
5579                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5580                                 continue;
5581
5582                         /*
5583                          * We need one register we can clobber, we choose EDX and make sreg1
5584                          * fixed EAX to work around limitations in the local register allocator.
5585                          * sreg2 might get allocated to EDX, but that is not a problem since
5586                          * we use it before clobbering EDX.
5587                          */
5588                         g_assert (ins->sreg1 == AMD64_RAX);
5589
5590                         /*
5591                          * This is the code we produce:
5592                          *
5593                          *   edx = value
5594                          *   edx >>= nursery_shift
5595                          *   cmp edx, (nursery_start >> nursery_shift)
5596                          *   jne done
5597                          *   edx = ptr
5598                          *   edx >>= card_table_shift
5599                          *   edx += cardtable
5600                          *   [edx] = 1
5601                          * done:
5602                          */
5603
5604                         if (mono_gc_card_table_nursery_check ()) {
5605                                 if (value != AMD64_RDX)
5606                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5607                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5608                                 if (shifted_nursery_start >> 31) {
5609                                         /*
5610                                          * The value we need to compare against is 64 bits, so we need
5611                                          * another spare register.  We use RBX, which we save and
5612                                          * restore.
5613                                          */
5614                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5615                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5616                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5617                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5618                                 } else {
5619                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5620                                 }
5621                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5622                         }
5623                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5624                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5625                         if (card_table_mask)
5626                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5627
5628                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5629                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5630
5631                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5632
5633                         if (mono_gc_card_table_nursery_check ())
5634                                 x86_patch (br, code);
5635                         break;
5636                 }
5637 #ifdef MONO_ARCH_SIMD_INTRINSICS
5638                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5639                 case OP_ADDPS:
5640                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5641                         break;
5642                 case OP_DIVPS:
5643                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5644                         break;
5645                 case OP_MULPS:
5646                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5647                         break;
5648                 case OP_SUBPS:
5649                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5650                         break;
5651                 case OP_MAXPS:
5652                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5653                         break;
5654                 case OP_MINPS:
5655                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5656                         break;
5657                 case OP_COMPPS:
5658                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5659                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5660                         break;
5661                 case OP_ANDPS:
5662                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5663                         break;
5664                 case OP_ANDNPS:
5665                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5666                         break;
5667                 case OP_ORPS:
5668                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5669                         break;
5670                 case OP_XORPS:
5671                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5672                         break;
5673                 case OP_SQRTPS:
5674                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5675                         break;
5676                 case OP_RSQRTPS:
5677                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5678                         break;
5679                 case OP_RCPPS:
5680                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5681                         break;
5682                 case OP_ADDSUBPS:
5683                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5684                         break;
5685                 case OP_HADDPS:
5686                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5687                         break;
5688                 case OP_HSUBPS:
5689                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5690                         break;
5691                 case OP_DUPPS_HIGH:
5692                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5693                         break;
5694                 case OP_DUPPS_LOW:
5695                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5696                         break;
5697
5698                 case OP_PSHUFLEW_HIGH:
5699                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5700                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5701                         break;
5702                 case OP_PSHUFLEW_LOW:
5703                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5704                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5705                         break;
5706                 case OP_PSHUFLED:
5707                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5708                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5709                         break;
5710                 case OP_SHUFPS:
5711                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5712                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5713                         break;
5714                 case OP_SHUFPD:
5715                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5716                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5717                         break;
5718
5719                 case OP_ADDPD:
5720                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5721                         break;
5722                 case OP_DIVPD:
5723                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5724                         break;
5725                 case OP_MULPD:
5726                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5727                         break;
5728                 case OP_SUBPD:
5729                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5730                         break;
5731                 case OP_MAXPD:
5732                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5733                         break;
5734                 case OP_MINPD:
5735                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5736                         break;
5737                 case OP_COMPPD:
5738                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5739                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5740                         break;
5741                 case OP_ANDPD:
5742                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5743                         break;
5744                 case OP_ANDNPD:
5745                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5746                         break;
5747                 case OP_ORPD:
5748                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5749                         break;
5750                 case OP_XORPD:
5751                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5752                         break;
5753                 case OP_SQRTPD:
5754                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5755                         break;
5756                 case OP_ADDSUBPD:
5757                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5758                         break;
5759                 case OP_HADDPD:
5760                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5761                         break;
5762                 case OP_HSUBPD:
5763                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5764                         break;
5765                 case OP_DUPPD:
5766                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5767                         break;
5768
5769                 case OP_EXTRACT_MASK:
5770                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5771                         break;
5772
5773                 case OP_PAND:
5774                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5775                         break;
5776                 case OP_POR:
5777                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5778                         break;
5779                 case OP_PXOR:
5780                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5781                         break;
5782
5783                 case OP_PADDB:
5784                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5785                         break;
5786                 case OP_PADDW:
5787                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5788                         break;
5789                 case OP_PADDD:
5790                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5791                         break;
5792                 case OP_PADDQ:
5793                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5794                         break;
5795
5796                 case OP_PSUBB:
5797                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5798                         break;
5799                 case OP_PSUBW:
5800                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5801                         break;
5802                 case OP_PSUBD:
5803                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_PSUBQ:
5806                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5807                         break;
5808
5809                 case OP_PMAXB_UN:
5810                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5811                         break;
5812                 case OP_PMAXW_UN:
5813                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5814                         break;
5815                 case OP_PMAXD_UN:
5816                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5817                         break;
5818
5819                 case OP_PMAXB:
5820                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5821                         break;
5822                 case OP_PMAXW:
5823                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5824                         break;
5825                 case OP_PMAXD:
5826                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5827                         break;
5828
5829                 case OP_PAVGB_UN:
5830                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5831                         break;
5832                 case OP_PAVGW_UN:
5833                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5834                         break;
5835
5836                 case OP_PMINB_UN:
5837                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5838                         break;
5839                 case OP_PMINW_UN:
5840                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5841                         break;
5842                 case OP_PMIND_UN:
5843                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5844                         break;
5845
5846                 case OP_PMINB:
5847                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5848                         break;
5849                 case OP_PMINW:
5850                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5851                         break;
5852                 case OP_PMIND:
5853                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5854                         break;
5855
5856                 case OP_PCMPEQB:
5857                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5858                         break;
5859                 case OP_PCMPEQW:
5860                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5861                         break;
5862                 case OP_PCMPEQD:
5863                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5864                         break;
5865                 case OP_PCMPEQQ:
5866                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868
5869                 case OP_PCMPGTB:
5870                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5871                         break;
5872                 case OP_PCMPGTW:
5873                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5874                         break;
5875                 case OP_PCMPGTD:
5876                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5877                         break;
5878                 case OP_PCMPGTQ:
5879                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5880                         break;
5881
5882                 case OP_PSUM_ABS_DIFF:
5883                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5884                         break;
5885
5886                 case OP_UNPACK_LOWB:
5887                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5888                         break;
5889                 case OP_UNPACK_LOWW:
5890                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5891                         break;
5892                 case OP_UNPACK_LOWD:
5893                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5894                         break;
5895                 case OP_UNPACK_LOWQ:
5896                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_UNPACK_LOWPS:
5899                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_UNPACK_LOWPD:
5902                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904
5905                 case OP_UNPACK_HIGHB:
5906                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5907                         break;
5908                 case OP_UNPACK_HIGHW:
5909                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5910                         break;
5911                 case OP_UNPACK_HIGHD:
5912                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_UNPACK_HIGHQ:
5915                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_UNPACK_HIGHPS:
5918                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_UNPACK_HIGHPD:
5921                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923
5924                 case OP_PACKW:
5925                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5926                         break;
5927                 case OP_PACKD:
5928                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5929                         break;
5930                 case OP_PACKW_UN:
5931                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5932                         break;
5933                 case OP_PACKD_UN:
5934                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936
5937                 case OP_PADDB_SAT_UN:
5938                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940                 case OP_PSUBB_SAT_UN:
5941                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5942                         break;
5943                 case OP_PADDW_SAT_UN:
5944                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_PSUBW_SAT_UN:
5947                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949
5950                 case OP_PADDB_SAT:
5951                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5952                         break;
5953                 case OP_PSUBB_SAT:
5954                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5955                         break;
5956                 case OP_PADDW_SAT:
5957                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959                 case OP_PSUBW_SAT:
5960                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962
5963                 case OP_PMULW:
5964                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5965                         break;
5966                 case OP_PMULD:
5967                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5968                         break;
5969                 case OP_PMULQ:
5970                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_PMULW_HIGH_UN:
5973                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_PMULW_HIGH:
5976                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978
5979                 case OP_PSHRW:
5980                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5981                         break;
5982                 case OP_PSHRW_REG:
5983                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5984                         break;
5985
5986                 case OP_PSARW:
5987                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5988                         break;
5989                 case OP_PSARW_REG:
5990                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5991                         break;
5992
5993                 case OP_PSHLW:
5994                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5995                         break;
5996                 case OP_PSHLW_REG:
5997                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5998                         break;
5999
6000                 case OP_PSHRD:
6001                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6002                         break;
6003                 case OP_PSHRD_REG:
6004                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6005                         break;
6006
6007                 case OP_PSARD:
6008                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6009                         break;
6010                 case OP_PSARD_REG:
6011                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6012                         break;
6013
6014                 case OP_PSHLD:
6015                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6016                         break;
6017                 case OP_PSHLD_REG:
6018                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6019                         break;
6020
6021                 case OP_PSHRQ:
6022                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6023                         break;
6024                 case OP_PSHRQ_REG:
6025                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6026                         break;
6027
6028                 /*TODO: This is appart of the sse spec but not added
6029                 case OP_PSARQ:
6030                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6031                         break;
6032                 case OP_PSARQ_REG:
6033                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6034                         break;
6035                 */
6036
6037                 case OP_PSHLQ:
6038                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6039                         break;
6040                 case OP_PSHLQ_REG:
6041                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6042                         break;
6043                 case OP_CVTDQ2PD:
6044                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6045                         break;
6046                 case OP_CVTDQ2PS:
6047                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6048                         break;
6049                 case OP_CVTPD2DQ:
6050                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6051                         break;
6052                 case OP_CVTPD2PS:
6053                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6054                         break;
6055                 case OP_CVTPS2DQ:
6056                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6057                         break;
6058                 case OP_CVTPS2PD:
6059                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6060                         break;
6061                 case OP_CVTTPD2DQ:
6062                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6063                         break;
6064                 case OP_CVTTPS2DQ:
6065                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6066                         break;
6067
6068                 case OP_ICONV_TO_X:
6069                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6070                         break;
6071                 case OP_EXTRACT_I4:
6072                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6073                         break;
6074                 case OP_EXTRACT_I8:
6075                         if (ins->inst_c0) {
6076                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6077                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6078                         } else {
6079                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6080                         }
6081                         break;
6082                 case OP_EXTRACT_I1:
6083                 case OP_EXTRACT_U1:
6084                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6085                         if (ins->inst_c0)
6086                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6087                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6088                         break;
6089                 case OP_EXTRACT_I2:
6090                 case OP_EXTRACT_U2:
6091                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6092                         if (ins->inst_c0)
6093                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6094                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6095                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6096                         break;
6097                 case OP_EXTRACT_R8:
6098                         if (ins->inst_c0)
6099                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6100                         else
6101                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6102                         break;
6103                 case OP_INSERT_I2:
6104                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6105                         break;
6106                 case OP_EXTRACTX_U2:
6107                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6108                         break;
6109                 case OP_INSERTX_U1_SLOW:
6110                         /*sreg1 is the extracted ireg (scratch)
6111                         /sreg2 is the to be inserted ireg (scratch)
6112                         /dreg is the xreg to receive the value*/
6113
6114                         /*clear the bits from the extracted word*/
6115                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6116                         /*shift the value to insert if needed*/
6117                         if (ins->inst_c0 & 1)
6118                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6119                         /*join them together*/
6120                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6121                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6122                         break;
6123                 case OP_INSERTX_I4_SLOW:
6124                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6125                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6126                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6127                         break;
6128                 case OP_INSERTX_I8_SLOW:
6129                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6130                         if (ins->inst_c0)
6131                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6132                         else
6133                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6134                         break;
6135
6136                 case OP_INSERTX_R4_SLOW:
6137                         switch (ins->inst_c0) {
6138                         case 0:
6139                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6140                                 break;
6141                         case 1:
6142                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6143                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6144                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6145                                 break;
6146                         case 2:
6147                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6148                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6149                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6150                                 break;
6151                         case 3:
6152                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6153                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6154                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6155                                 break;
6156                         }
6157                         break;
6158                 case OP_INSERTX_R8_SLOW:
6159                         if (ins->inst_c0)
6160                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6161                         else
6162                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6163                         break;
6164                 case OP_STOREX_MEMBASE_REG:
6165                 case OP_STOREX_MEMBASE:
6166                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6167                         break;
6168                 case OP_LOADX_MEMBASE:
6169                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6170                         break;
6171                 case OP_LOADX_ALIGNED_MEMBASE:
6172                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6173                         break;
6174                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6175                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6176                         break;
6177                 case OP_STOREX_NTA_MEMBASE_REG:
6178                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6179                         break;
6180                 case OP_PREFETCH_MEMBASE:
6181                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6182                         break;
6183
6184                 case OP_XMOVE:
6185                         /*FIXME the peephole pass should have killed this*/
6186                         if (ins->dreg != ins->sreg1)
6187                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6188                         break;
6189                 case OP_XZERO:
6190                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6191                         break;
6192                 case OP_ICONV_TO_R8_RAW:
6193                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6194                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6195                         break;
6196
6197                 case OP_FCONV_TO_R8_X:
6198                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6199                         break;
6200
6201                 case OP_XCONV_R8_TO_I4:
6202                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6203                         switch (ins->backend.source_opcode) {
6204                         case OP_FCONV_TO_I1:
6205                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6206                                 break;
6207                         case OP_FCONV_TO_U1:
6208                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6209                                 break;
6210                         case OP_FCONV_TO_I2:
6211                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6212                                 break;
6213                         case OP_FCONV_TO_U2:
6214                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6215                                 break;
6216                         }
6217                         break;
6218
6219                 case OP_EXPAND_I2:
6220                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6221                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6222                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6223                         break;
6224                 case OP_EXPAND_I4:
6225                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6226                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6227                         break;
6228                 case OP_EXPAND_I8:
6229                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6230                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6231                         break;
6232                 case OP_EXPAND_R4:
6233                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6234                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6235                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6236                         break;
6237                 case OP_EXPAND_R8:
6238                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6239                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6240                         break;
6241 #endif
6242                 case OP_LIVERANGE_START: {
6243                         if (cfg->verbose_level > 1)
6244                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6245                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6246                         break;
6247                 }
6248                 case OP_LIVERANGE_END: {
6249                         if (cfg->verbose_level > 1)
6250                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6251                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6252                         break;
6253                 }
6254                 case OP_NACL_GC_SAFE_POINT: {
6255 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6256                         if (cfg->compile_aot)
6257                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6258                         else {
6259                                 guint8 *br [1];
6260
6261                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6262                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6263                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6264                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6265                                 amd64_patch (br[0], code);
6266                         }
6267 #endif
6268                         break;
6269                 }
6270                 case OP_GC_LIVENESS_DEF:
6271                 case OP_GC_LIVENESS_USE:
6272                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6273                         ins->backend.pc_offset = code - cfg->native_code;
6274                         break;
6275                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6276                         ins->backend.pc_offset = code - cfg->native_code;
6277                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6278                         break;
6279                 default:
6280                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6281                         g_assert_not_reached ();
6282                 }
6283
6284                 if ((code - cfg->native_code - offset) > max_len) {
6285 #if !defined(__native_client_codegen__)
6286                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6287                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6288                         g_assert_not_reached ();
6289 #endif
6290                 }
6291
6292                 last_ins = ins;
6293                 last_offset = offset;
6294         }
6295
6296         cfg->code_len = code - cfg->native_code;
6297 }
6298
6299 #endif /* DISABLE_JIT */
6300
6301 void
6302 mono_arch_register_lowlevel_calls (void)
6303 {
6304         /* The signature doesn't matter */
6305         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6306 }
6307
6308 void
6309 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6310 {
6311         MonoJumpInfo *patch_info;
6312         gboolean compile_aot = !run_cctors;
6313
6314         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6315                 unsigned char *ip = patch_info->ip.i + code;
6316                 unsigned char *target;
6317
6318                 if (compile_aot) {
6319                         switch (patch_info->type) {
6320                         case MONO_PATCH_INFO_BB:
6321                         case MONO_PATCH_INFO_LABEL:
6322                                 break;
6323                         default:
6324                                 /* No need to patch these */
6325                                 continue;
6326                         }
6327                 }
6328
6329                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6330
6331                 switch (patch_info->type) {
6332                 case MONO_PATCH_INFO_NONE:
6333                         continue;
6334                 case MONO_PATCH_INFO_METHOD_REL:
6335                 case MONO_PATCH_INFO_R8:
6336                 case MONO_PATCH_INFO_R4:
6337                         g_assert_not_reached ();
6338                         continue;
6339                 case MONO_PATCH_INFO_BB:
6340                         break;
6341                 default:
6342                         break;
6343                 }
6344
6345                 /*
6346                  * Debug code to help track down problems where the target of a near call is
6347                  * is not valid.
6348                  */
6349                 if (amd64_is_near_call (ip)) {
6350                         gint64 disp = (guint8*)target - (guint8*)ip;
6351
6352                         if (!amd64_is_imm32 (disp)) {
6353                                 printf ("TYPE: %d\n", patch_info->type);
6354                                 switch (patch_info->type) {
6355                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6356                                         printf ("V: %s\n", patch_info->data.name);
6357                                         break;
6358                                 case MONO_PATCH_INFO_METHOD_JUMP:
6359                                 case MONO_PATCH_INFO_METHOD:
6360                                         printf ("V: %s\n", patch_info->data.method->name);
6361                                         break;
6362                                 default:
6363                                         break;
6364                                 }
6365                         }
6366                 }
6367
6368                 amd64_patch (ip, (gpointer)target);
6369         }
6370 }
6371
6372 #ifndef DISABLE_JIT
6373
6374 static int
6375 get_max_epilog_size (MonoCompile *cfg)
6376 {
6377         int max_epilog_size = 16;
6378
6379         if (cfg->method->save_lmf)
6380                 max_epilog_size += 256;
6381
6382         if (mono_jit_trace_calls != NULL)
6383                 max_epilog_size += 50;
6384
6385         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6386                 max_epilog_size += 50;
6387
6388         max_epilog_size += (AMD64_NREG * 2);
6389
6390         return max_epilog_size;
6391 }
6392
6393 /*
6394  * This macro is used for testing whenever the unwinder works correctly at every point
6395  * where an async exception can happen.
6396  */
6397 /* This will generate a SIGSEGV at the given point in the code */
6398 #define async_exc_point(code) do { \
6399     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6400          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6401              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6402          cfg->arch.async_point_count ++; \
6403     } \
6404 } while (0)
6405
6406 guint8 *
6407 mono_arch_emit_prolog (MonoCompile *cfg)
6408 {
6409         MonoMethod *method = cfg->method;
6410         MonoBasicBlock *bb;
6411         MonoMethodSignature *sig;
6412         MonoInst *ins;
6413         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6414         guint8 *code;
6415         CallInfo *cinfo;
6416         MonoInst *lmf_var = cfg->lmf_var;
6417         gboolean args_clobbered = FALSE;
6418         gboolean trace = FALSE;
6419 #ifdef __native_client_codegen__
6420         guint alignment_check;
6421 #endif
6422
6423         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6424
6425 #if defined(__default_codegen__)
6426         code = cfg->native_code = g_malloc (cfg->code_size);
6427 #elif defined(__native_client_codegen__)
6428         /* native_code_alloc is not 32-byte aligned, native_code is. */
6429         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6430
6431         /* Align native_code to next nearest kNaclAlignment byte. */
6432         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6433         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6434
6435         code = cfg->native_code;
6436
6437         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6438         g_assert (alignment_check == 0);
6439 #endif
6440
6441         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6442                 trace = TRUE;
6443
6444         /* Amount of stack space allocated by register saving code */
6445         pos = 0;
6446
6447         /* Offset between RSP and the CFA */
6448         cfa_offset = 0;
6449
6450         /*
6451          * The prolog consists of the following parts:
6452          * FP present:
6453          * - push rbp, mov rbp, rsp
6454          * - save callee saved regs using pushes
6455          * - allocate frame
6456          * - save rgctx if needed
6457          * - save lmf if needed
6458          * FP not present:
6459          * - allocate frame
6460          * - save rgctx if needed
6461          * - save lmf if needed
6462          * - save callee saved regs using moves
6463          */
6464
6465         // CFA = sp + 8
6466         cfa_offset = 8;
6467         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6468         // IP saved at CFA - 8
6469         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6470         async_exc_point (code);
6471         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6472
6473         if (!cfg->arch.omit_fp) {
6474                 amd64_push_reg (code, AMD64_RBP);
6475                 cfa_offset += 8;
6476                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6477                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6478                 async_exc_point (code);
6479 #ifdef HOST_WIN32
6480                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6481 #endif
6482                 /* These are handled automatically by the stack marking code */
6483                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6484
6485                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6486                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6487                 async_exc_point (code);
6488 #ifdef HOST_WIN32
6489                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6490 #endif
6491         }
6492
6493         /* The param area is always at offset 0 from sp */
6494         /* This needs to be allocated here, since it has to come after the spill area */
6495         if (cfg->param_area) {
6496                 if (cfg->arch.omit_fp)
6497                         // FIXME:
6498                         g_assert_not_reached ();
6499                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6500         }
6501
6502         if (cfg->arch.omit_fp) {
6503                 /*
6504                  * On enter, the stack is misaligned by the pushing of the return
6505                  * address. It is either made aligned by the pushing of %rbp, or by
6506                  * this.
6507                  */
6508                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6509                 if ((alloc_size % 16) == 0) {
6510                         alloc_size += 8;
6511                         /* Mark the padding slot as NOREF */
6512                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6513                 }
6514         } else {
6515                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6516                 if (cfg->stack_offset != alloc_size) {
6517                         /* Mark the padding slot as NOREF */
6518                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6519                 }
6520                 cfg->arch.sp_fp_offset = alloc_size;
6521                 alloc_size -= pos;
6522         }
6523
6524         cfg->arch.stack_alloc_size = alloc_size;
6525
6526         /* Allocate stack frame */
6527         if (alloc_size) {
6528                 /* See mono_emit_stack_alloc */
6529 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6530                 guint32 remaining_size = alloc_size;
6531                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6532                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6533                 guint32 offset = code - cfg->native_code;
6534                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6535                         while (required_code_size >= (cfg->code_size - offset))
6536                                 cfg->code_size *= 2;
6537                         cfg->native_code = mono_realloc_native_code (cfg);
6538                         code = cfg->native_code + offset;
6539                         cfg->stat_code_reallocs++;
6540                 }
6541
6542                 while (remaining_size >= 0x1000) {
6543                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6544                         if (cfg->arch.omit_fp) {
6545                                 cfa_offset += 0x1000;
6546                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6547                         }
6548                         async_exc_point (code);
6549 #ifdef HOST_WIN32
6550                         if (cfg->arch.omit_fp)
6551                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6552 #endif
6553
6554                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6555                         remaining_size -= 0x1000;
6556                 }
6557                 if (remaining_size) {
6558                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6559                         if (cfg->arch.omit_fp) {
6560                                 cfa_offset += remaining_size;
6561                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6562                                 async_exc_point (code);
6563                         }
6564 #ifdef HOST_WIN32
6565                         if (cfg->arch.omit_fp)
6566                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6567 #endif
6568                 }
6569 #else
6570                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6571                 if (cfg->arch.omit_fp) {
6572                         cfa_offset += alloc_size;
6573                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6574                         async_exc_point (code);
6575                 }
6576 #endif
6577         }
6578
6579         /* Stack alignment check */
6580 #if 0
6581         {
6582                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6583                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6584                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6585                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6586                 amd64_breakpoint (code);
6587         }
6588 #endif
6589
6590         if (mini_get_debug_options ()->init_stacks) {
6591                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6592
6593                 /* Save registers to the red zone */
6594                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6595                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6596
6597                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6598                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6599                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6600
6601                 amd64_cld (code);
6602 #if defined(__default_codegen__)
6603                 amd64_prefix (code, X86_REP_PREFIX);
6604                 amd64_stosl (code);
6605 #elif defined(__native_client_codegen__)
6606                 /* NaCl stos pseudo-instruction */
6607                 amd64_codegen_pre (code);
6608                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6609                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6610                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6611                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6612                 amd64_prefix (code, X86_REP_PREFIX);
6613                 amd64_stosl (code);
6614                 amd64_codegen_post (code);
6615 #endif /* __native_client_codegen__ */
6616
6617                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6618                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6619         }
6620
6621         /* Save LMF */
6622         if (method->save_lmf)
6623                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6624
6625         /* Save callee saved registers */
6626         if (cfg->arch.omit_fp) {
6627                 save_area_offset = cfg->arch.reg_save_area_offset;
6628                 /* Save caller saved registers after sp is adjusted */
6629                 /* The registers are saved at the bottom of the frame */
6630                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6631         } else {
6632                 /* The registers are saved just below the saved rbp */
6633                 save_area_offset = cfg->arch.reg_save_area_offset;
6634         }
6635
6636         for (i = 0; i < AMD64_NREG; ++i) {
6637                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6638                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6639
6640                         if (cfg->arch.omit_fp) {
6641                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6642                                 /* These are handled automatically by the stack marking code */
6643                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6644                         } else {
6645                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6646                                 // FIXME: GC
6647                         }
6648
6649                         save_area_offset += 8;
6650                         async_exc_point (code);
6651                 }
6652         }
6653
6654         /* store runtime generic context */
6655         if (cfg->rgctx_var) {
6656                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6657                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6658
6659                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6660
6661                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6662                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6663         }
6664
6665         /* compute max_length in order to use short forward jumps */
6666         max_epilog_size = get_max_epilog_size (cfg);
6667         if (cfg->opt & MONO_OPT_BRANCH) {
6668                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6669                         MonoInst *ins;
6670                         int max_length = 0;
6671
6672                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6673                                 max_length += 6;
6674                         /* max alignment for loops */
6675                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6676                                 max_length += LOOP_ALIGNMENT;
6677 #ifdef __native_client_codegen__
6678                         /* max alignment for native client */
6679                         max_length += kNaClAlignment;
6680 #endif
6681
6682                         MONO_BB_FOR_EACH_INS (bb, ins) {
6683 #ifdef __native_client_codegen__
6684                                 {
6685                                         int space_in_block = kNaClAlignment -
6686                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6687                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6688                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6689                                                 max_length += space_in_block;
6690                                         }
6691                                 }
6692 #endif  /*__native_client_codegen__*/
6693                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6694                         }
6695
6696                         /* Take prolog and epilog instrumentation into account */
6697                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6698                                 max_length += max_epilog_size;
6699
6700                         bb->max_length = max_length;
6701                 }
6702         }
6703
6704         sig = mono_method_signature (method);
6705         pos = 0;
6706
6707         cinfo = cfg->arch.cinfo;
6708
6709         if (sig->ret->type != MONO_TYPE_VOID) {
6710                 /* Save volatile arguments to the stack */
6711                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6712                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6713         }
6714
6715         /* Keep this in sync with emit_load_volatile_arguments */
6716         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6717                 ArgInfo *ainfo = cinfo->args + i;
6718                 gint32 stack_offset;
6719                 MonoType *arg_type;
6720
6721                 ins = cfg->args [i];
6722
6723                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6724                         /* Unused arguments */
6725                         continue;
6726
6727                 if (sig->hasthis && (i == 0))
6728                         arg_type = &mono_defaults.object_class->byval_arg;
6729                 else
6730                         arg_type = sig->params [i - sig->hasthis];
6731
6732                 stack_offset = ainfo->offset + ARGS_OFFSET;
6733
6734                 if (cfg->globalra) {
6735                         /* All the other moves are done by the register allocator */
6736                         switch (ainfo->storage) {
6737                         case ArgInFloatSSEReg:
6738                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6739                                 break;
6740                         case ArgValuetypeInReg:
6741                                 for (quad = 0; quad < 2; quad ++) {
6742                                         switch (ainfo->pair_storage [quad]) {
6743                                         case ArgInIReg:
6744                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6745                                                 break;
6746                                         case ArgInFloatSSEReg:
6747                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6748                                                 break;
6749                                         case ArgInDoubleSSEReg:
6750                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6751                                                 break;
6752                                         case ArgNone:
6753                                                 break;
6754                                         default:
6755                                                 g_assert_not_reached ();
6756                                         }
6757                                 }
6758                                 break;
6759                         default:
6760                                 break;
6761                         }
6762
6763                         continue;
6764                 }
6765
6766                 /* Save volatile arguments to the stack */
6767                 if (ins->opcode != OP_REGVAR) {
6768                         switch (ainfo->storage) {
6769                         case ArgInIReg: {
6770                                 guint32 size = 8;
6771
6772                                 /* FIXME: I1 etc */
6773                                 /*
6774                                 if (stack_offset & 0x1)
6775                                         size = 1;
6776                                 else if (stack_offset & 0x2)
6777                                         size = 2;
6778                                 else if (stack_offset & 0x4)
6779                                         size = 4;
6780                                 else
6781                                         size = 8;
6782                                 */
6783                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6784
6785                                 /*
6786                                  * Save the original location of 'this',
6787                                  * get_generic_info_from_stack_frame () needs this to properly look up
6788                                  * the argument value during the handling of async exceptions.
6789                                  */
6790                                 if (ins == cfg->args [0]) {
6791                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6792                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6793                                 }
6794                                 break;
6795                         }
6796                         case ArgInFloatSSEReg:
6797                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6798                                 break;
6799                         case ArgInDoubleSSEReg:
6800                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6801                                 break;
6802                         case ArgValuetypeInReg:
6803                                 for (quad = 0; quad < 2; quad ++) {
6804                                         switch (ainfo->pair_storage [quad]) {
6805                                         case ArgInIReg:
6806                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6807                                                 break;
6808                                         case ArgInFloatSSEReg:
6809                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6810                                                 break;
6811                                         case ArgInDoubleSSEReg:
6812                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6813                                                 break;
6814                                         case ArgNone:
6815                                                 break;
6816                                         default:
6817                                                 g_assert_not_reached ();
6818                                         }
6819                                 }
6820                                 break;
6821                         case ArgValuetypeAddrInIReg:
6822                                 if (ainfo->pair_storage [0] == ArgInIReg)
6823                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6824                                 break;
6825                         default:
6826                                 break;
6827                         }
6828                 } else {
6829                         /* Argument allocated to (non-volatile) register */
6830                         switch (ainfo->storage) {
6831                         case ArgInIReg:
6832                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6833                                 break;
6834                         case ArgOnStack:
6835                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6836                                 break;
6837                         default:
6838                                 g_assert_not_reached ();
6839                         }
6840
6841                         if (ins == cfg->args [0]) {
6842                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6843                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6844                         }
6845                 }
6846         }
6847
6848         if (cfg->method->save_lmf)
6849                 args_clobbered = TRUE;
6850
6851         if (trace) {
6852                 args_clobbered = TRUE;
6853                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6854         }
6855
6856         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6857                 args_clobbered = TRUE;
6858
6859         /*
6860          * Optimize the common case of the first bblock making a call with the same
6861          * arguments as the method. This works because the arguments are still in their
6862          * original argument registers.
6863          * FIXME: Generalize this
6864          */
6865         if (!args_clobbered) {
6866                 MonoBasicBlock *first_bb = cfg->bb_entry;
6867                 MonoInst *next;
6868
6869                 next = mono_bb_first_ins (first_bb);
6870                 if (!next && first_bb->next_bb) {
6871                         first_bb = first_bb->next_bb;
6872                         next = mono_bb_first_ins (first_bb);
6873                 }
6874
6875                 if (first_bb->in_count > 1)
6876                         next = NULL;
6877
6878                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6879                         ArgInfo *ainfo = cinfo->args + i;
6880                         gboolean match = FALSE;
6881
6882                         ins = cfg->args [i];
6883                         if (ins->opcode != OP_REGVAR) {
6884                                 switch (ainfo->storage) {
6885                                 case ArgInIReg: {
6886                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6887                                                 if (next->dreg == ainfo->reg) {
6888                                                         NULLIFY_INS (next);
6889                                                         match = TRUE;
6890                                                 } else {
6891                                                         next->opcode = OP_MOVE;
6892                                                         next->sreg1 = ainfo->reg;
6893                                                         /* Only continue if the instruction doesn't change argument regs */
6894                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6895                                                                 match = TRUE;
6896                                                 }
6897                                         }
6898                                         break;
6899                                 }
6900                                 default:
6901                                         break;
6902                                 }
6903                         } else {
6904                                 /* Argument allocated to (non-volatile) register */
6905                                 switch (ainfo->storage) {
6906                                 case ArgInIReg:
6907                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6908                                                 NULLIFY_INS (next);
6909                                                 match = TRUE;
6910                                         }
6911                                         break;
6912                                 default:
6913                                         break;
6914                                 }
6915                         }
6916
6917                         if (match) {
6918                                 next = next->next;
6919                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6920                                 if (!next)
6921                                         break;
6922                         }
6923                 }
6924         }
6925
6926         if (cfg->gen_seq_points) {
6927                 MonoInst *info_var = cfg->arch.seq_point_info_var;
6928
6929                 /* Initialize seq_point_info_var */
6930                 if (cfg->compile_aot) {
6931                         /* Initialize the variable from a GOT slot */
6932                         /* Same as OP_AOTCONST */
6933                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6934                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
6935                         g_assert (info_var->opcode == OP_REGOFFSET);
6936                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
6937                 }
6938
6939                 /* Initialize ss_trigger_page_var */
6940                 ins = cfg->arch.ss_trigger_page_var;
6941
6942                 g_assert (ins->opcode == OP_REGOFFSET);
6943
6944                 if (cfg->compile_aot) {
6945                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
6946                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
6947                 } else {
6948                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6949                 }
6950                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
6951         }
6952
6953         cfg->code_len = code - cfg->native_code;
6954
6955         g_assert (cfg->code_len < cfg->code_size);
6956
6957         return code;
6958 }
6959
6960 void
6961 mono_arch_emit_epilog (MonoCompile *cfg)
6962 {
6963         MonoMethod *method = cfg->method;
6964         int quad, pos, i;
6965         guint8 *code;
6966         int max_epilog_size;
6967         CallInfo *cinfo;
6968         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
6969         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6970
6971         max_epilog_size = get_max_epilog_size (cfg);
6972
6973         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6974                 cfg->code_size *= 2;
6975                 cfg->native_code = mono_realloc_native_code (cfg);
6976                 cfg->stat_code_reallocs++;
6977         }
6978         code = cfg->native_code + cfg->code_len;
6979
6980         cfg->has_unwind_info_for_epilog = TRUE;
6981
6982         /* Mark the start of the epilog */
6983         mono_emit_unwind_op_mark_loc (cfg, code, 0);
6984
6985         /* Save the uwind state which is needed by the out-of-line code */
6986         mono_emit_unwind_op_remember_state (cfg, code);
6987
6988         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6989                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6990
6991         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
6992         pos = 0;
6993
6994         if (method->save_lmf) {
6995                 /* check if we need to restore protection of the stack after a stack overflow */
6996                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
6997                         guint8 *patch;
6998                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
6999                         /* we load the value in a separate instruction: this mechanism may be
7000                          * used later as a safer way to do thread interruption
7001                          */
7002                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7003                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7004                         patch = code;
7005                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7006                         /* note that the call trampoline will preserve eax/edx */
7007                         x86_call_reg (code, X86_ECX);
7008                         x86_patch (patch, code);
7009                 } else {
7010                         /* FIXME: maybe save the jit tls in the prolog */
7011                 }
7012                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7013                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7014                 }
7015         }
7016
7017         /* Restore callee saved regs */
7018         for (i = 0; i < AMD64_NREG; ++i) {
7019                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7020                         /* Restore only used_int_regs, not arch.saved_iregs */
7021                         if (cfg->used_int_regs & (1 << i)) {
7022                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7023                                 mono_emit_unwind_op_same_value (cfg, code, i);
7024                                 async_exc_point (code);
7025                         }
7026                         save_area_offset += 8;
7027                 }
7028         }
7029
7030         /* Load returned vtypes into registers if needed */
7031         cinfo = cfg->arch.cinfo;
7032         if (cinfo->ret.storage == ArgValuetypeInReg) {
7033                 ArgInfo *ainfo = &cinfo->ret;
7034                 MonoInst *inst = cfg->ret;
7035
7036                 for (quad = 0; quad < 2; quad ++) {
7037                         switch (ainfo->pair_storage [quad]) {
7038                         case ArgInIReg:
7039                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7040                                 break;
7041                         case ArgInFloatSSEReg:
7042                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7043                                 break;
7044                         case ArgInDoubleSSEReg:
7045                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7046                                 break;
7047                         case ArgNone:
7048                                 break;
7049                         default:
7050                                 g_assert_not_reached ();
7051                         }
7052                 }
7053         }
7054
7055         if (cfg->arch.omit_fp) {
7056                 if (cfg->arch.stack_alloc_size) {
7057                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7058                 }
7059         } else {
7060                 amd64_leave (code);
7061                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7062         }
7063         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7064         async_exc_point (code);
7065         amd64_ret (code);
7066
7067         /* Restore the unwind state to be the same as before the epilog */
7068         mono_emit_unwind_op_restore_state (cfg, code);
7069
7070         cfg->code_len = code - cfg->native_code;
7071
7072         g_assert (cfg->code_len < cfg->code_size);
7073 }
7074
7075 void
7076 mono_arch_emit_exceptions (MonoCompile *cfg)
7077 {
7078         MonoJumpInfo *patch_info;
7079         int nthrows, i;
7080         guint8 *code;
7081         MonoClass *exc_classes [16];
7082         guint8 *exc_throw_start [16], *exc_throw_end [16];
7083         guint32 code_size = 0;
7084
7085         /* Compute needed space */
7086         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7087                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7088                         code_size += 40;
7089                 if (patch_info->type == MONO_PATCH_INFO_R8)
7090                         code_size += 8 + 15; /* sizeof (double) + alignment */
7091                 if (patch_info->type == MONO_PATCH_INFO_R4)
7092                         code_size += 4 + 15; /* sizeof (float) + alignment */
7093                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7094                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7095         }
7096
7097 #ifdef __native_client_codegen__
7098         /* Give us extra room on Native Client.  This could be   */
7099         /* more carefully calculated, but bundle alignment makes */
7100         /* it much trickier, so *2 like other places is good.    */
7101         code_size *= 2;
7102 #endif
7103
7104         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7105                 cfg->code_size *= 2;
7106                 cfg->native_code = mono_realloc_native_code (cfg);
7107                 cfg->stat_code_reallocs++;
7108         }
7109
7110         code = cfg->native_code + cfg->code_len;
7111
7112         /* add code to raise exceptions */
7113         nthrows = 0;
7114         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7115                 switch (patch_info->type) {
7116                 case MONO_PATCH_INFO_EXC: {
7117                         MonoClass *exc_class;
7118                         guint8 *buf, *buf2;
7119                         guint32 throw_ip;
7120
7121                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7122
7123                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7124                         g_assert (exc_class);
7125                         throw_ip = patch_info->ip.i;
7126
7127                         //x86_breakpoint (code);
7128                         /* Find a throw sequence for the same exception class */
7129                         for (i = 0; i < nthrows; ++i)
7130                                 if (exc_classes [i] == exc_class)
7131                                         break;
7132                         if (i < nthrows) {
7133                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7134                                 x86_jump_code (code, exc_throw_start [i]);
7135                                 patch_info->type = MONO_PATCH_INFO_NONE;
7136                         }
7137                         else {
7138                                 buf = code;
7139                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7140                                 buf2 = code;
7141
7142                                 if (nthrows < 16) {
7143                                         exc_classes [nthrows] = exc_class;
7144                                         exc_throw_start [nthrows] = code;
7145                                 }
7146                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7147
7148                                 patch_info->type = MONO_PATCH_INFO_NONE;
7149
7150                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7151
7152                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7153                                 while (buf < buf2)
7154                                         x86_nop (buf);
7155
7156                                 if (nthrows < 16) {
7157                                         exc_throw_end [nthrows] = code;
7158                                         nthrows ++;
7159                                 }
7160                         }
7161                         break;
7162                 }
7163                 default:
7164                         /* do nothing */
7165                         break;
7166                 }
7167                 g_assert(code < cfg->native_code + cfg->code_size);
7168         }
7169
7170         /* Handle relocations with RIP relative addressing */
7171         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7172                 gboolean remove = FALSE;
7173                 guint8 *orig_code = code;
7174
7175                 switch (patch_info->type) {
7176                 case MONO_PATCH_INFO_R8:
7177                 case MONO_PATCH_INFO_R4: {
7178                         guint8 *pos, *patch_pos;
7179                         guint32 target_pos;
7180
7181                         /* The SSE opcodes require a 16 byte alignment */
7182 #if defined(__default_codegen__)
7183                         code = (guint8*)ALIGN_TO (code, 16);
7184 #elif defined(__native_client_codegen__)
7185                         {
7186                                 /* Pad this out with HLT instructions  */
7187                                 /* or we can get garbage bytes emitted */
7188                                 /* which will fail validation          */
7189                                 guint8 *aligned_code;
7190                                 /* extra align to make room for  */
7191                                 /* mov/push below                      */
7192                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7193                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7194                                 /* The technique of hiding data in an  */
7195                                 /* instruction has a problem here: we  */
7196                                 /* need the data aligned to a 16-byte  */
7197                                 /* boundary but the instruction cannot */
7198                                 /* cross the bundle boundary. so only  */
7199                                 /* odd multiples of 16 can be used     */
7200                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7201                                         aligned_code += 16;
7202                                 }
7203                                 while (code < aligned_code) {
7204                                         *(code++) = 0xf4; /* hlt */
7205                                 }
7206                         }
7207 #endif
7208
7209                         pos = cfg->native_code + patch_info->ip.i;
7210                         if (IS_REX (pos [1])) {
7211                                 patch_pos = pos + 5;
7212                                 target_pos = code - pos - 9;
7213                         }
7214                         else {
7215                                 patch_pos = pos + 4;
7216                                 target_pos = code - pos - 8;
7217                         }
7218
7219                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7220 #ifdef __native_client_codegen__
7221                                 /* Hide 64-bit data in a         */
7222                                 /* "mov imm64, r11" instruction. */
7223                                 /* write it before the start of  */
7224                                 /* the data*/
7225                                 *(code-2) = 0x49; /* prefix      */
7226                                 *(code-1) = 0xbb; /* mov X, %r11 */
7227 #endif
7228                                 *(double*)code = *(double*)patch_info->data.target;
7229                                 code += sizeof (double);
7230                         } else {
7231 #ifdef __native_client_codegen__
7232                                 /* Hide 32-bit data in a        */
7233                                 /* "push imm32" instruction.    */
7234                                 *(code-1) = 0x68; /* push */
7235 #endif
7236                                 *(float*)code = *(float*)patch_info->data.target;
7237                                 code += sizeof (float);
7238                         }
7239
7240                         *(guint32*)(patch_pos) = target_pos;
7241
7242                         remove = TRUE;
7243                         break;
7244                 }
7245                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7246                         guint8 *pos;
7247
7248                         if (cfg->compile_aot)
7249                                 continue;
7250
7251                         /*loading is faster against aligned addresses.*/
7252                         code = (guint8*)ALIGN_TO (code, 8);
7253                         memset (orig_code, 0, code - orig_code);
7254
7255                         pos = cfg->native_code + patch_info->ip.i;
7256
7257                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7258                         if (IS_REX (pos [1]))
7259                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7260                         else
7261                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7262
7263                         *(gpointer*)code = (gpointer)patch_info->data.target;
7264                         code += sizeof (gpointer);
7265
7266                         remove = TRUE;
7267                         break;
7268                 }
7269                 default:
7270                         break;
7271                 }
7272
7273                 if (remove) {
7274                         if (patch_info == cfg->patch_info)
7275                                 cfg->patch_info = patch_info->next;
7276                         else {
7277                                 MonoJumpInfo *tmp;
7278
7279                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7280                                         ;
7281                                 tmp->next = patch_info->next;
7282                         }
7283                 }
7284                 g_assert (code < cfg->native_code + cfg->code_size);
7285         }
7286
7287         cfg->code_len = code - cfg->native_code;
7288
7289         g_assert (cfg->code_len < cfg->code_size);
7290
7291 }
7292
7293 #endif /* DISABLE_JIT */
7294
7295 void*
7296 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7297 {
7298         guchar *code = p;
7299         CallInfo *cinfo = NULL;
7300         MonoMethodSignature *sig;
7301         MonoInst *inst;
7302         int i, n, stack_area = 0;
7303
7304         /* Keep this in sync with mono_arch_get_argument_info */
7305
7306         if (enable_arguments) {
7307                 /* Allocate a new area on the stack and save arguments there */
7308                 sig = mono_method_signature (cfg->method);
7309
7310                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7311
7312                 n = sig->param_count + sig->hasthis;
7313
7314                 stack_area = ALIGN_TO (n * 8, 16);
7315
7316                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7317
7318                 for (i = 0; i < n; ++i) {
7319                         inst = cfg->args [i];
7320
7321                         if (inst->opcode == OP_REGVAR)
7322                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7323                         else {
7324                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7325                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7326                         }
7327                 }
7328         }
7329
7330         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7331         amd64_set_reg_template (code, AMD64_ARG_REG1);
7332         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7333         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7334
7335         if (enable_arguments)
7336                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7337
7338         return code;
7339 }
7340
7341 enum {
7342         SAVE_NONE,
7343         SAVE_STRUCT,
7344         SAVE_EAX,
7345         SAVE_EAX_EDX,
7346         SAVE_XMM
7347 };
7348
7349 void*
7350 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7351 {
7352         guchar *code = p;
7353         int save_mode = SAVE_NONE;
7354         MonoMethod *method = cfg->method;
7355         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7356         int i;
7357
7358         switch (ret_type->type) {
7359         case MONO_TYPE_VOID:
7360                 /* special case string .ctor icall */
7361                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7362                         save_mode = SAVE_EAX;
7363                 else
7364                         save_mode = SAVE_NONE;
7365                 break;
7366         case MONO_TYPE_I8:
7367         case MONO_TYPE_U8:
7368                 save_mode = SAVE_EAX;
7369                 break;
7370         case MONO_TYPE_R4:
7371         case MONO_TYPE_R8:
7372                 save_mode = SAVE_XMM;
7373                 break;
7374         case MONO_TYPE_GENERICINST:
7375                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7376                         save_mode = SAVE_EAX;
7377                         break;
7378                 }
7379                 /* Fall through */
7380         case MONO_TYPE_VALUETYPE:
7381                 save_mode = SAVE_STRUCT;
7382                 break;
7383         default:
7384                 save_mode = SAVE_EAX;
7385                 break;
7386         }
7387
7388         /* Save the result and copy it into the proper argument register */
7389         switch (save_mode) {
7390         case SAVE_EAX:
7391                 amd64_push_reg (code, AMD64_RAX);
7392                 /* Align stack */
7393                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7394                 if (enable_arguments)
7395                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7396                 break;
7397         case SAVE_STRUCT:
7398                 /* FIXME: */
7399                 if (enable_arguments)
7400                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7401                 break;
7402         case SAVE_XMM:
7403                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7404                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7405                 /* Align stack */
7406                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7407                 /*
7408                  * The result is already in the proper argument register so no copying
7409                  * needed.
7410                  */
7411                 break;
7412         case SAVE_NONE:
7413                 break;
7414         default:
7415                 g_assert_not_reached ();
7416         }
7417
7418         /* Set %al since this is a varargs call */
7419         if (save_mode == SAVE_XMM)
7420                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7421         else
7422                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7423
7424         if (preserve_argument_registers) {
7425                 for (i = 0; i < PARAM_REGS; ++i)
7426                         amd64_push_reg (code, param_regs [i]);
7427         }
7428
7429         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7430         amd64_set_reg_template (code, AMD64_ARG_REG1);
7431         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7432
7433         if (preserve_argument_registers) {
7434                 for (i = PARAM_REGS - 1; i >= 0; --i)
7435                         amd64_pop_reg (code, param_regs [i]);
7436         }
7437
7438         /* Restore result */
7439         switch (save_mode) {
7440         case SAVE_EAX:
7441                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7442                 amd64_pop_reg (code, AMD64_RAX);
7443                 break;
7444         case SAVE_STRUCT:
7445                 /* FIXME: */
7446                 break;
7447         case SAVE_XMM:
7448                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7449                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7450                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7451                 break;
7452         case SAVE_NONE:
7453                 break;
7454         default:
7455                 g_assert_not_reached ();
7456         }
7457
7458         return code;
7459 }
7460
7461 void
7462 mono_arch_flush_icache (guint8 *code, gint size)
7463 {
7464         /* Not needed */
7465 }
7466
7467 void
7468 mono_arch_flush_register_windows (void)
7469 {
7470 }
7471
7472 gboolean
7473 mono_arch_is_inst_imm (gint64 imm)
7474 {
7475         return amd64_is_imm32 (imm);
7476 }
7477
7478 /*
7479  * Determine whenever the trap whose info is in SIGINFO is caused by
7480  * integer overflow.
7481  */
7482 gboolean
7483 mono_arch_is_int_overflow (void *sigctx, void *info)
7484 {
7485         MonoContext ctx;
7486         guint8* rip;
7487         int reg;
7488         gint64 value;
7489
7490         mono_sigctx_to_monoctx (sigctx, &ctx);
7491
7492         rip = (guint8*)ctx.rip;
7493
7494         if (IS_REX (rip [0])) {
7495                 reg = amd64_rex_b (rip [0]);
7496                 rip ++;
7497         }
7498         else
7499                 reg = 0;
7500
7501         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7502                 /* idiv REG */
7503                 reg += x86_modrm_rm (rip [1]);
7504
7505                 switch (reg) {
7506                 case AMD64_RAX:
7507                         value = ctx.rax;
7508                         break;
7509                 case AMD64_RBX:
7510                         value = ctx.rbx;
7511                         break;
7512                 case AMD64_RCX:
7513                         value = ctx.rcx;
7514                         break;
7515                 case AMD64_RDX:
7516                         value = ctx.rdx;
7517                         break;
7518                 case AMD64_RBP:
7519                         value = ctx.rbp;
7520                         break;
7521                 case AMD64_RSP:
7522                         value = ctx.rsp;
7523                         break;
7524                 case AMD64_RSI:
7525                         value = ctx.rsi;
7526                         break;
7527                 case AMD64_RDI:
7528                         value = ctx.rdi;
7529                         break;
7530                 case AMD64_R12:
7531                         value = ctx.r12;
7532                         break;
7533                 case AMD64_R13:
7534                         value = ctx.r13;
7535                         break;
7536                 case AMD64_R14:
7537                         value = ctx.r14;
7538                         break;
7539                 case AMD64_R15:
7540                         value = ctx.r15;
7541                         break;
7542                 default:
7543                         g_assert_not_reached ();
7544                         reg = -1;
7545                 }
7546
7547                 if (value == -1)
7548                         return TRUE;
7549         }
7550
7551         return FALSE;
7552 }
7553
7554 guint32
7555 mono_arch_get_patch_offset (guint8 *code)
7556 {
7557         return 3;
7558 }
7559
7560 /**
7561  * mono_breakpoint_clean_code:
7562  *
7563  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7564  * breakpoints in the original code, they are removed in the copy.
7565  *
7566  * Returns TRUE if no sw breakpoint was present.
7567  */
7568 gboolean
7569 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7570 {
7571         int i;
7572         gboolean can_write = TRUE;
7573         /*
7574          * If method_start is non-NULL we need to perform bound checks, since we access memory
7575          * at code - offset we could go before the start of the method and end up in a different
7576          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7577          * instead.
7578          */
7579         if (!method_start || code - offset >= method_start) {
7580                 memcpy (buf, code - offset, size);
7581         } else {
7582                 int diff = code - method_start;
7583                 memset (buf, 0, size);
7584                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7585         }
7586         code -= offset;
7587         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7588                 int idx = mono_breakpoint_info_index [i];
7589                 guint8 *ptr;
7590                 if (idx < 1)
7591                         continue;
7592                 ptr = mono_breakpoint_info [idx].address;
7593                 if (ptr >= code && ptr < code + size) {
7594                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7595                         can_write = FALSE;
7596                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7597                         buf [ptr - code] = saved_byte;
7598                 }
7599         }
7600         return can_write;
7601 }
7602
7603 #if defined(__native_client_codegen__)
7604 /* For membase calls, we want the base register. for Native Client,  */
7605 /* all indirect calls have the following sequence with the given sizes: */
7606 /* mov %eXX,%eXX                                [2-3]   */
7607 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7608 /* and $0xffffffffffffffe0,%r11d                [4]     */
7609 /* add %r15,%r11                                [3]     */
7610 /* callq *%r11                                  [3]     */
7611
7612
7613 /* Determine if code points to a NaCl call-through-register sequence, */
7614 /* (i.e., the last 3 instructions listed above) */
7615 int
7616 is_nacl_call_reg_sequence(guint8* code)
7617 {
7618         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7619                                "\x4d\x03\xdf"     /* add */
7620                                "\x41\xff\xd3";   /* call */
7621         return memcmp(code, sequence, 10) == 0;
7622 }
7623
7624 /* Determine if code points to the first opcode of the mov membase component */
7625 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7626 /* (there could be a REX prefix before the opcode but it is ignored) */
7627 static int
7628 is_nacl_indirect_call_membase_sequence(guint8* code)
7629 {
7630                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7631         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7632                /* and that src reg = dest reg */
7633                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7634                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7635                IS_REX(code[2]) &&
7636                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7637                /* and has dst of r11 and base of r15 */
7638                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7639                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7640 }
7641 #endif /* __native_client_codegen__ */
7642
7643 int
7644 mono_arch_get_this_arg_reg (guint8 *code)
7645 {
7646         return AMD64_ARG_REG1;
7647 }
7648
7649 gpointer
7650 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7651 {
7652         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7653 }
7654
7655 #define MAX_ARCH_DELEGATE_PARAMS 10
7656
7657 static gpointer
7658 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7659 {
7660         guint8 *code, *start;
7661         int i;
7662
7663         if (has_target) {
7664                 start = code = mono_global_codeman_reserve (64);
7665
7666                 /* Replace the this argument with the target */
7667                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7668                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7669                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7670
7671                 g_assert ((code - start) < 64);
7672         } else {
7673                 start = code = mono_global_codeman_reserve (64);
7674
7675                 if (param_count == 0) {
7676                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7677                 } else {
7678                         /* We have to shift the arguments left */
7679                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7680                         for (i = 0; i < param_count; ++i) {
7681 #ifdef HOST_WIN32
7682                                 if (i < 3)
7683                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7684                                 else
7685                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7686 #else
7687                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7688 #endif
7689                         }
7690
7691                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7692                 }
7693                 g_assert ((code - start) < 64);
7694         }
7695
7696         nacl_global_codeman_validate (&start, 64, &code);
7697
7698         if (code_len)
7699                 *code_len = code - start;
7700
7701         if (mono_jit_map_is_enabled ()) {
7702                 char *buff;
7703                 if (has_target)
7704                         buff = (char*)"delegate_invoke_has_target";
7705                 else
7706                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7707                 mono_emit_jit_tramp (start, code - start, buff);
7708                 if (!has_target)
7709                         g_free (buff);
7710         }
7711
7712         return start;
7713 }
7714
7715 /*
7716  * mono_arch_get_delegate_invoke_impls:
7717  *
7718  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7719  * trampolines.
7720  */
7721 GSList*
7722 mono_arch_get_delegate_invoke_impls (void)
7723 {
7724         GSList *res = NULL;
7725         guint8 *code;
7726         guint32 code_len;
7727         int i;
7728         char *tramp_name;
7729
7730         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7731         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7732
7733         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7734                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7735                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7736                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7737                 g_free (tramp_name);
7738         }
7739
7740         return res;
7741 }
7742
7743 gpointer
7744 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7745 {
7746         guint8 *code, *start;
7747         int i;
7748
7749         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7750                 return NULL;
7751
7752         /* FIXME: Support more cases */
7753         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7754                 return NULL;
7755
7756         if (has_target) {
7757                 static guint8* cached = NULL;
7758
7759                 if (cached)
7760                         return cached;
7761
7762                 if (mono_aot_only)
7763                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7764                 else
7765                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7766
7767                 mono_memory_barrier ();
7768
7769                 cached = start;
7770         } else {
7771                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7772                 for (i = 0; i < sig->param_count; ++i)
7773                         if (!mono_is_regsize_var (sig->params [i]))
7774                                 return NULL;
7775                 if (sig->param_count > 4)
7776                         return NULL;
7777
7778                 code = cache [sig->param_count];
7779                 if (code)
7780                         return code;
7781
7782                 if (mono_aot_only) {
7783                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7784                         start = mono_aot_get_trampoline (name);
7785                         g_free (name);
7786                 } else {
7787                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7788                 }
7789
7790                 mono_memory_barrier ();
7791
7792                 cache [sig->param_count] = start;
7793         }
7794
7795         return start;
7796 }
7797
7798 gpointer
7799 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7800 {
7801         guint8 *code, *start;
7802         int size = 20;
7803
7804         start = code = mono_global_codeman_reserve (size);
7805
7806         /* Replace the this argument with the target */
7807         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7808         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7809
7810         if (load_imt_reg) {
7811                 /* Load the IMT reg */
7812                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7813         }
7814
7815         /* Load the vtable */
7816         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7817         amd64_jump_membase (code, AMD64_RAX, offset);
7818
7819         return start;
7820 }
7821
7822 void
7823 mono_arch_finish_init (void)
7824 {
7825 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7826         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7827 #endif
7828 }
7829
7830 void
7831 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7832 {
7833 }
7834
7835 #if defined(__default_codegen__)
7836 #define CMP_SIZE (6 + 1)
7837 #define CMP_REG_REG_SIZE (4 + 1)
7838 #define BR_SMALL_SIZE 2
7839 #define BR_LARGE_SIZE 6
7840 #define MOV_REG_IMM_SIZE 10
7841 #define MOV_REG_IMM_32BIT_SIZE 6
7842 #define JUMP_REG_SIZE (2 + 1)
7843 #elif defined(__native_client_codegen__)
7844 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7845 #define CMP_SIZE ((6 + 1) * 2 - 1)
7846 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7847 #define BR_SMALL_SIZE (2 * 2 - 1)
7848 #define BR_LARGE_SIZE (6 * 2 - 1)
7849 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7850 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7851 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7852 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7853 /* Jump membase's size is large and unpredictable    */
7854 /* in native client, just pad it out a whole bundle. */
7855 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7856 #endif
7857
7858 static int
7859 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7860 {
7861         int i, distance = 0;
7862         for (i = start; i < target; ++i)
7863                 distance += imt_entries [i]->chunk_size;
7864         return distance;
7865 }
7866
7867 /*
7868  * LOCKING: called with the domain lock held
7869  */
7870 gpointer
7871 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7872         gpointer fail_tramp)
7873 {
7874         int i;
7875         int size = 0;
7876         guint8 *code, *start;
7877         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7878
7879         for (i = 0; i < count; ++i) {
7880                 MonoIMTCheckItem *item = imt_entries [i];
7881                 if (item->is_equals) {
7882                         if (item->check_target_idx) {
7883                                 if (!item->compare_done) {
7884                                         if (amd64_is_imm32 (item->key))
7885                                                 item->chunk_size += CMP_SIZE;
7886                                         else
7887                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7888                                 }
7889                                 if (item->has_target_code) {
7890                                         item->chunk_size += MOV_REG_IMM_SIZE;
7891                                 } else {
7892                                         if (vtable_is_32bit)
7893                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7894                                         else
7895                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7896 #ifdef __native_client_codegen__
7897                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7898 #endif
7899                                 }
7900                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7901                         } else {
7902                                 if (fail_tramp) {
7903                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7904                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7905                                 } else {
7906                                         if (vtable_is_32bit)
7907                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7908                                         else
7909                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7910                                         item->chunk_size += JUMP_REG_SIZE;
7911                                         /* with assert below:
7912                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7913                                          */
7914 #ifdef __native_client_codegen__
7915                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7916 #endif
7917                                 }
7918                         }
7919                 } else {
7920                         if (amd64_is_imm32 (item->key))
7921                                 item->chunk_size += CMP_SIZE;
7922                         else
7923                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7924                         item->chunk_size += BR_LARGE_SIZE;
7925                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7926                 }
7927                 size += item->chunk_size;
7928         }
7929 #if defined(__native_client__) && defined(__native_client_codegen__)
7930         /* In Native Client, we don't re-use thunks, allocate from the */
7931         /* normal code manager paths. */
7932         code = mono_domain_code_reserve (domain, size);
7933 #else
7934         if (fail_tramp)
7935                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7936         else
7937                 code = mono_domain_code_reserve (domain, size);
7938 #endif
7939         start = code;
7940         for (i = 0; i < count; ++i) {
7941                 MonoIMTCheckItem *item = imt_entries [i];
7942                 item->code_target = code;
7943                 if (item->is_equals) {
7944                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7945
7946                         if (item->check_target_idx || fail_case) {
7947                                 if (!item->compare_done || fail_case) {
7948                                         if (amd64_is_imm32 (item->key))
7949                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7950                                         else {
7951                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7952                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7953                                         }
7954                                 }
7955                                 item->jmp_code = code;
7956                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7957                                 if (item->has_target_code) {
7958                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7959                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7960                                 } else {
7961                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7962                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7963                                 }
7964
7965                                 if (fail_case) {
7966                                         amd64_patch (item->jmp_code, code);
7967                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7968                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7969                                         item->jmp_code = NULL;
7970                                 }
7971                         } else {
7972                                 /* enable the commented code to assert on wrong method */
7973 #if 0
7974                                 if (amd64_is_imm32 (item->key))
7975                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7976                                 else {
7977                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7978                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7979                                 }
7980                                 item->jmp_code = code;
7981                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7982                                 /* See the comment below about R10 */
7983                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7984                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7985                                 amd64_patch (item->jmp_code, code);
7986                                 amd64_breakpoint (code);
7987                                 item->jmp_code = NULL;
7988 #else
7989                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7990                                    needs to be preserved.  R10 needs
7991                                    to be preserved for calls which
7992                                    require a runtime generic context,
7993                                    but interface calls don't. */
7994                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7995                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7996 #endif
7997                         }
7998                 } else {
7999                         if (amd64_is_imm32 (item->key))
8000                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8001                         else {
8002                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8003                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8004                         }
8005                         item->jmp_code = code;
8006                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8007                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8008                         else
8009                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8010                 }
8011                 g_assert (code - item->code_target <= item->chunk_size);
8012         }
8013         /* patch the branches to get to the target items */
8014         for (i = 0; i < count; ++i) {
8015                 MonoIMTCheckItem *item = imt_entries [i];
8016                 if (item->jmp_code) {
8017                         if (item->check_target_idx) {
8018                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8019                         }
8020                 }
8021         }
8022
8023         if (!fail_tramp)
8024                 mono_stats.imt_thunks_size += code - start;
8025         g_assert (code - start <= size);
8026
8027         nacl_domain_code_validate(domain, &start, size, &code);
8028
8029         return start;
8030 }
8031
8032 MonoMethod*
8033 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8034 {
8035         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8036 }
8037
8038 MonoVTable*
8039 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8040 {
8041         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8042 }
8043
8044 GSList*
8045 mono_arch_get_cie_program (void)
8046 {
8047         GSList *l = NULL;
8048
8049         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8050         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8051
8052         return l;
8053 }
8054
8055 MonoInst*
8056 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8057 {
8058         MonoInst *ins = NULL;
8059         int opcode = 0;
8060
8061         if (cmethod->klass == mono_defaults.math_class) {
8062                 if (strcmp (cmethod->name, "Sin") == 0) {
8063                         opcode = OP_SIN;
8064                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8065                         opcode = OP_COS;
8066                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8067                         opcode = OP_SQRT;
8068                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8069                         opcode = OP_ABS;
8070                 }
8071
8072                 if (opcode) {
8073                         MONO_INST_NEW (cfg, ins, opcode);
8074                         ins->type = STACK_R8;
8075                         ins->dreg = mono_alloc_freg (cfg);
8076                         ins->sreg1 = args [0]->dreg;
8077                         MONO_ADD_INS (cfg->cbb, ins);
8078                 }
8079
8080                 opcode = 0;
8081                 if (cfg->opt & MONO_OPT_CMOV) {
8082                         if (strcmp (cmethod->name, "Min") == 0) {
8083                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8084                                         opcode = OP_IMIN;
8085                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8086                                         opcode = OP_IMIN_UN;
8087                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8088                                         opcode = OP_LMIN;
8089                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8090                                         opcode = OP_LMIN_UN;
8091                         } else if (strcmp (cmethod->name, "Max") == 0) {
8092                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8093                                         opcode = OP_IMAX;
8094                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8095                                         opcode = OP_IMAX_UN;
8096                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8097                                         opcode = OP_LMAX;
8098                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8099                                         opcode = OP_LMAX_UN;
8100                         }
8101                 }
8102
8103                 if (opcode) {
8104                         MONO_INST_NEW (cfg, ins, opcode);
8105                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8106                         ins->dreg = mono_alloc_ireg (cfg);
8107                         ins->sreg1 = args [0]->dreg;
8108                         ins->sreg2 = args [1]->dreg;
8109                         MONO_ADD_INS (cfg->cbb, ins);
8110                 }
8111
8112 #if 0
8113                 /* OP_FREM is not IEEE compatible */
8114                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8115                         MONO_INST_NEW (cfg, ins, OP_FREM);
8116                         ins->inst_i0 = args [0];
8117                         ins->inst_i1 = args [1];
8118                 }
8119 #endif
8120         }
8121
8122         /*
8123          * Can't implement CompareExchange methods this way since they have
8124          * three arguments.
8125          */
8126
8127         return ins;
8128 }
8129
8130 gboolean
8131 mono_arch_print_tree (MonoInst *tree, int arity)
8132 {
8133         return 0;
8134 }
8135
8136 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8137
8138 mgreg_t
8139 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8140 {
8141         switch (reg) {
8142         case AMD64_RCX: return ctx->rcx;
8143         case AMD64_RDX: return ctx->rdx;
8144         case AMD64_RBX: return ctx->rbx;
8145         case AMD64_RBP: return ctx->rbp;
8146         case AMD64_RSP: return ctx->rsp;
8147         default:
8148                 return _CTX_REG (ctx, rax, reg);
8149         }
8150 }
8151
8152 void
8153 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8154 {
8155         switch (reg) {
8156         case AMD64_RCX:
8157                 ctx->rcx = val;
8158                 break;
8159         case AMD64_RDX:
8160                 ctx->rdx = val;
8161                 break;
8162         case AMD64_RBX:
8163                 ctx->rbx = val;
8164                 break;
8165         case AMD64_RBP:
8166                 ctx->rbp = val;
8167                 break;
8168         case AMD64_RSP:
8169                 ctx->rsp = val;
8170                 break;
8171         default:
8172                 _CTX_REG (ctx, rax, reg) = val;
8173         }
8174 }
8175
8176 gpointer
8177 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8178 {
8179         gpointer *sp, old_value;
8180         char *bp;
8181
8182         /*Load the spvar*/
8183         bp = MONO_CONTEXT_GET_BP (ctx);
8184         sp = *(gpointer*)(bp + clause->exvar_offset);
8185
8186         old_value = *sp;
8187         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8188                 return old_value;
8189
8190         *sp = new_value;
8191
8192         return old_value;
8193 }
8194
8195 /*
8196  * mono_arch_emit_load_aotconst:
8197  *
8198  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8199  * TARGET from the mscorlib GOT in full-aot code.
8200  * On AMD64, the result is placed into R11.
8201  */
8202 guint8*
8203 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8204 {
8205         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8206         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8207
8208         return code;
8209 }
8210
8211 /*
8212  * mono_arch_get_trampolines:
8213  *
8214  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8215  * for AOT.
8216  */
8217 GSList *
8218 mono_arch_get_trampolines (gboolean aot)
8219 {
8220         return mono_amd64_get_exception_trampolines (aot);
8221 }
8222
8223 /* Soft Debug support */
8224 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8225
8226 /*
8227  * mono_arch_set_breakpoint:
8228  *
8229  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8230  * The location should contain code emitted by OP_SEQ_POINT.
8231  */
8232 void
8233 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8234 {
8235         guint8 *code = ip;
8236         guint8 *orig_code = code;
8237
8238         if (ji->from_aot) {
8239                 guint32 native_offset = ip - (guint8*)ji->code_start;
8240                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8241
8242                 g_assert (info->bp_addrs [native_offset] == 0);
8243                 info->bp_addrs [native_offset] = bp_trigger_page;
8244         } else {
8245                 /*
8246                  * In production, we will use int3 (has to fix the size in the md
8247                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8248                  * instead.
8249                  */
8250                 g_assert (code [0] == 0x90);
8251                 if (breakpoint_size == 8) {
8252                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8253                 } else {
8254                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8255                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8256                 }
8257
8258                 g_assert (code - orig_code == breakpoint_size);
8259         }
8260 }
8261
8262 /*
8263  * mono_arch_clear_breakpoint:
8264  *
8265  *   Clear the breakpoint at IP.
8266  */
8267 void
8268 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8269 {
8270         guint8 *code = ip;
8271         int i;
8272
8273         if (ji->from_aot) {
8274                 guint32 native_offset = ip - (guint8*)ji->code_start;
8275                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8276
8277                 g_assert (info->bp_addrs [native_offset] == 0);
8278                 info->bp_addrs [native_offset] = info;
8279         } else {
8280                 for (i = 0; i < breakpoint_size; ++i)
8281                         x86_nop (code);
8282         }
8283 }
8284
8285 gboolean
8286 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8287 {
8288 #ifdef HOST_WIN32
8289         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8290         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8291                 return TRUE;
8292         else
8293                 return FALSE;
8294 #else
8295         siginfo_t* sinfo = (siginfo_t*) info;
8296         /* Sometimes the address is off by 4 */
8297         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8298                 return TRUE;
8299         else
8300                 return FALSE;
8301 #endif
8302 }
8303
8304 /*
8305  * mono_arch_skip_breakpoint:
8306  *
8307  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8308  * we resume, the instruction is not executed again.
8309  */
8310 void
8311 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8312 {
8313         if (ji->from_aot) {
8314                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8315                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8316         } else {
8317                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8318         }
8319 }
8320
8321 /*
8322  * mono_arch_start_single_stepping:
8323  *
8324  *   Start single stepping.
8325  */
8326 void
8327 mono_arch_start_single_stepping (void)
8328 {
8329         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8330 }
8331
8332 /*
8333  * mono_arch_stop_single_stepping:
8334  *
8335  *   Stop single stepping.
8336  */
8337 void
8338 mono_arch_stop_single_stepping (void)
8339 {
8340         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8341 }
8342
8343 /*
8344  * mono_arch_is_single_step_event:
8345  *
8346  *   Return whenever the machine state in SIGCTX corresponds to a single
8347  * step event.
8348  */
8349 gboolean
8350 mono_arch_is_single_step_event (void *info, void *sigctx)
8351 {
8352 #ifdef HOST_WIN32
8353         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8354         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8355                 return TRUE;
8356         else
8357                 return FALSE;
8358 #else
8359         siginfo_t* sinfo = (siginfo_t*) info;
8360         /* Sometimes the address is off by 4 */
8361         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8362                 return TRUE;
8363         else
8364                 return FALSE;
8365 #endif
8366 }
8367
8368 /*
8369  * mono_arch_skip_single_step:
8370  *
8371  *   Modify CTX so the ip is placed after the single step trigger instruction,
8372  * we resume, the instruction is not executed again.
8373  */
8374 void
8375 mono_arch_skip_single_step (MonoContext *ctx)
8376 {
8377         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8378 }
8379
8380 /*
8381  * mono_arch_create_seq_point_info:
8382  *
8383  *   Return a pointer to a data structure which is used by the sequence
8384  * point implementation in AOTed code.
8385  */
8386 gpointer
8387 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8388 {
8389         SeqPointInfo *info;
8390         MonoJitInfo *ji;
8391         int i;
8392
8393         // FIXME: Add a free function
8394
8395         mono_domain_lock (domain);
8396         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8397                                                                 code);
8398         mono_domain_unlock (domain);
8399
8400         if (!info) {
8401                 ji = mono_jit_info_table_find (domain, (char*)code);
8402                 g_assert (ji);
8403
8404                 // FIXME: Optimize the size
8405                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8406
8407                 info->ss_trigger_page = ss_trigger_page;
8408                 info->bp_trigger_page = bp_trigger_page;
8409                 /* Initialize to a valid address */
8410                 for (i = 0; i < ji->code_size; ++i)
8411                         info->bp_addrs [i] = info;
8412
8413                 mono_domain_lock (domain);
8414                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8415                                                          code, info);
8416                 mono_domain_unlock (domain);
8417         }
8418
8419         return info;
8420 }
8421
8422 void
8423 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8424 {
8425         ext->lmf.previous_lmf = prev_lmf;
8426         /* Mark that this is a MonoLMFExt */
8427         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8428         ext->lmf.rsp = (gssize)ext;
8429 }
8430
8431 #endif
8432
8433 gboolean
8434 mono_arch_opcode_supported (int opcode)
8435 {
8436         switch (opcode) {
8437         case OP_ATOMIC_ADD_I4:
8438         case OP_ATOMIC_ADD_I8:
8439         case OP_ATOMIC_EXCHANGE_I4:
8440         case OP_ATOMIC_EXCHANGE_I8:
8441         case OP_ATOMIC_CAS_I4:
8442         case OP_ATOMIC_CAS_I8:
8443                 return TRUE;
8444         default:
8445                 return FALSE;
8446         }
8447 }