2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
11 * Johan Lorensson (lateralusx.github@gmail.com)
13 * (C) 2003 Ximian, Inc.
14 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
15 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
16 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
25 #include <mono/metadata/abi-details.h>
26 #include <mono/metadata/appdomain.h>
27 #include <mono/metadata/debug-helpers.h>
28 #include <mono/metadata/threads.h>
29 #include <mono/metadata/profiler-private.h>
30 #include <mono/metadata/mono-debug.h>
31 #include <mono/metadata/gc-internals.h>
32 #include <mono/utils/mono-math.h>
33 #include <mono/utils/mono-mmap.h>
34 #include <mono/utils/mono-memory-model.h>
35 #include <mono/utils/mono-tls.h>
36 #include <mono/utils/mono-hwcap.h>
37 #include <mono/utils/mono-threads.h>
41 #include "mini-amd64.h"
42 #include "cpu-amd64.h"
43 #include "debugger-agent.h"
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
59 /* Under windows, the calling convention is never stdcall */
60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
65 /* This mutex protects architecture specific caches */
66 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
67 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
68 static mono_mutex_t mini_arch_mutex;
70 /* The single step trampoline */
71 static gpointer ss_trampoline;
73 /* The breakpoint trampoline */
74 static gpointer bp_trampoline;
76 /* Offset between fp and the first argument in the callee */
77 #define ARGS_OFFSET 16
78 #define GP_SCRATCH_REG AMD64_R11
81 * AMD64 register usage:
82 * - callee saved registers are used for global register allocation
83 * - %r11 is used for materializing 64 bit constants in opcodes
84 * - the rest is used for local allocation
88 * Floating point comparison results:
98 mono_arch_regname (int reg)
101 case AMD64_RAX: return "%rax";
102 case AMD64_RBX: return "%rbx";
103 case AMD64_RCX: return "%rcx";
104 case AMD64_RDX: return "%rdx";
105 case AMD64_RSP: return "%rsp";
106 case AMD64_RBP: return "%rbp";
107 case AMD64_RDI: return "%rdi";
108 case AMD64_RSI: return "%rsi";
109 case AMD64_R8: return "%r8";
110 case AMD64_R9: return "%r9";
111 case AMD64_R10: return "%r10";
112 case AMD64_R11: return "%r11";
113 case AMD64_R12: return "%r12";
114 case AMD64_R13: return "%r13";
115 case AMD64_R14: return "%r14";
116 case AMD64_R15: return "%r15";
121 static const char * packed_xmmregs [] = {
122 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
123 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
126 static const char * single_xmmregs [] = {
127 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
128 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
132 mono_arch_fregname (int reg)
134 if (reg < AMD64_XMM_NREG)
135 return single_xmmregs [reg];
141 mono_arch_xregname (int reg)
143 if (reg < AMD64_XMM_NREG)
144 return packed_xmmregs [reg];
153 return mono_debug_count ();
159 static inline gboolean
160 amd64_is_near_call (guint8 *code)
163 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
166 return code [0] == 0xe8;
169 static inline gboolean
170 amd64_use_imm32 (gint64 val)
172 if (mini_get_debug_options()->single_imm_size)
175 return amd64_is_imm32 (val);
179 amd64_patch (unsigned char* code, gpointer target)
184 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
189 if ((code [0] & 0xf8) == 0xb8) {
190 /* amd64_set_reg_template */
191 *(guint64*)(code + 1) = (guint64)target;
193 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
194 /* mov 0(%rip), %dreg */
195 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
197 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
198 /* call *<OFFSET>(%rip) */
199 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
201 else if (code [0] == 0xe8) {
203 gint64 disp = (guint8*)target - (guint8*)code;
204 g_assert (amd64_is_imm32 (disp));
205 x86_patch (code, (unsigned char*)target);
208 x86_patch (code, (unsigned char*)target);
212 mono_amd64_patch (unsigned char* code, gpointer target)
214 amd64_patch (code, target);
217 #define DEBUG(a) if (cfg->verbose_level > 1) a
220 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
222 ainfo->offset = *stack_size;
224 if (*gr >= PARAM_REGS) {
225 ainfo->storage = ArgOnStack;
226 ainfo->arg_size = sizeof (mgreg_t);
227 /* Since the same stack slot size is used for all arg */
228 /* types, it needs to be big enough to hold them all */
229 (*stack_size) += sizeof(mgreg_t);
232 ainfo->storage = ArgInIReg;
233 ainfo->reg = param_regs [*gr];
239 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
241 ainfo->offset = *stack_size;
243 if (*gr >= FLOAT_PARAM_REGS) {
244 ainfo->storage = ArgOnStack;
245 ainfo->arg_size = sizeof (mgreg_t);
246 /* Since the same stack slot size is used for both float */
247 /* types, it needs to be big enough to hold them both */
248 (*stack_size) += sizeof(mgreg_t);
251 /* A double register */
253 ainfo->storage = ArgInDoubleSSEReg;
255 ainfo->storage = ArgInFloatSSEReg;
261 typedef enum ArgumentClass {
269 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
271 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
274 ptype = mini_get_underlying_type (type);
275 switch (ptype->type) {
284 case MONO_TYPE_STRING:
285 case MONO_TYPE_OBJECT:
286 case MONO_TYPE_CLASS:
287 case MONO_TYPE_SZARRAY:
289 case MONO_TYPE_FNPTR:
290 case MONO_TYPE_ARRAY:
293 class2 = ARG_CLASS_INTEGER;
298 class2 = ARG_CLASS_INTEGER;
300 class2 = ARG_CLASS_SSE;
304 case MONO_TYPE_TYPEDBYREF:
305 g_assert_not_reached ();
307 case MONO_TYPE_GENERICINST:
308 if (!mono_type_generic_inst_is_valuetype (ptype)) {
309 class2 = ARG_CLASS_INTEGER;
313 case MONO_TYPE_VALUETYPE: {
314 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
317 for (i = 0; i < info->num_fields; ++i) {
319 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
324 g_assert_not_reached ();
328 if (class1 == class2)
330 else if (class1 == ARG_CLASS_NO_CLASS)
332 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
333 class1 = ARG_CLASS_MEMORY;
334 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
335 class1 = ARG_CLASS_INTEGER;
337 class1 = ARG_CLASS_SSE;
343 count_fields_nested (MonoClass *klass, gboolean pinvoke)
345 MonoMarshalType *info;
350 info = mono_marshal_load_type_info (klass);
352 for (i = 0; i < info->num_fields; ++i) {
353 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
354 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type), pinvoke);
360 MonoClassField *field;
363 while ((field = mono_class_get_fields (klass, &iter))) {
364 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
366 if (MONO_TYPE_ISSTRUCT (field->type))
367 count += count_fields_nested (mono_class_from_mono_type (field->type), pinvoke);
381 * collect_field_info_nested:
383 * Collect field info from KLASS recursively into FIELDS.
386 collect_field_info_nested (MonoClass *klass, StructFieldInfo *fields, int index, int offset, gboolean pinvoke, gboolean unicode)
388 MonoMarshalType *info;
392 info = mono_marshal_load_type_info (klass);
394 for (i = 0; i < info->num_fields; ++i) {
395 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
396 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset, pinvoke, unicode);
400 fields [index].type = info->fields [i].field->type;
401 fields [index].size = mono_marshal_type_size (info->fields [i].field->type,
402 info->fields [i].mspec,
403 &align, TRUE, unicode);
404 fields [index].offset = offset + info->fields [i].offset;
405 if (i == info->num_fields - 1 && fields [index].size + fields [index].offset < info->native_size) {
406 /* This can happen with .pack directives eg. 'fixed' arrays */
407 fields [index].size = info->native_size - fields [index].offset;
414 MonoClassField *field;
417 while ((field = mono_class_get_fields (klass, &iter))) {
418 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
420 if (MONO_TYPE_ISSTRUCT (field->type)) {
421 index = collect_field_info_nested (mono_class_from_mono_type (field->type), fields, index, field->offset - sizeof (MonoObject), pinvoke, unicode);
425 fields [index].type = field->type;
426 fields [index].size = mono_type_size (field->type, &align);
427 fields [index].offset = field->offset - sizeof (MonoObject) + offset;
437 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
438 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
441 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
443 gboolean result = FALSE;
445 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
446 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
448 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
449 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
450 arg_info->pair_size [0] = 0;
451 arg_info->pair_size [1] = 0;
454 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
455 /* Pass parameter in integer register. */
456 arg_info->pair_storage [0] = ArgInIReg;
457 arg_info->pair_regs [0] = int_regs [*current_int_reg];
458 (*current_int_reg) ++;
460 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
461 /* Pass parameter in float register. */
462 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
463 arg_info->pair_regs [0] = float_regs [*current_float_reg];
464 (*current_float_reg) ++;
468 if (result == TRUE) {
469 arg_info->pair_size [0] = arg_size;
476 static inline gboolean
477 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
479 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
482 static inline gboolean
483 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
485 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
489 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
490 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
492 /* Windows x64 value type ABI.
494 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
496 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
497 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
498 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
499 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
501 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
503 * Integers/Float types smaller than or equal to 8 bytes
504 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
505 * Properly sized struct/unions (1,2,4,8)
506 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
507 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
508 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
511 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
515 /* Parameter cases. */
516 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
517 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
519 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
520 arg_info->storage = ArgValuetypeInReg;
521 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
522 /* No more registers, fallback passing parameter on stack as value. */
523 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
525 /* Passing value directly on stack, so use size of value. */
526 arg_info->storage = ArgOnStack;
527 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
528 arg_info->offset = *stack_size;
529 arg_info->arg_size = arg_size;
530 *stack_size += arg_size;
533 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
534 arg_info->storage = ArgValuetypeAddrInIReg;
535 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
536 /* No more registers, fallback passing address to parameter on stack. */
537 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
539 /* Passing an address to value on stack, so use size of register as argument size. */
540 arg_info->storage = ArgValuetypeAddrOnStack;
541 arg_size = sizeof (mgreg_t);
542 arg_info->offset = *stack_size;
543 arg_info->arg_size = arg_size;
544 *stack_size += arg_size;
548 /* Return value cases. */
549 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
550 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
552 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
553 arg_info->storage = ArgValuetypeInReg;
554 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
556 /* Only RAX/XMM0 should be used to return valuetype. */
557 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
559 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
560 arg_info->storage = ArgValuetypeAddrInIReg;
561 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
563 /* Only RAX should be used to return valuetype address. */
564 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
566 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
567 arg_info->offset = *stack_size;
568 *stack_size += arg_size;
574 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
577 *arg_class = ARG_CLASS_NO_CLASS;
579 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
582 /* Calculate argument class type and size of marshalled type. */
583 MonoMarshalType *info = mono_marshal_load_type_info (klass);
584 *arg_size = info->native_size;
586 /* Calculate argument class type and size of managed type. */
587 *arg_size = mono_class_value_size (klass, NULL);
590 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
591 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
593 if (*arg_class == ARG_CLASS_MEMORY) {
594 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
595 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
599 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
600 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
601 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
602 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
603 * it must be represented in call and cannot be dropped.
605 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
606 arg_info->pass_empty_struct = TRUE;
607 *arg_size = SIZEOF_REGISTER;
608 *arg_class = ARG_CLASS_INTEGER;
611 assert (*arg_class != ARG_CLASS_NO_CLASS);
615 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
616 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
618 guint32 arg_size = SIZEOF_REGISTER;
619 MonoClass *klass = NULL;
620 ArgumentClass arg_class;
622 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
624 klass = mono_class_from_mono_type (type);
625 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
627 /* Only drop value type if its not an empty struct as input that must be represented in call */
628 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
629 arg_info->storage = ArgValuetypeInReg;
630 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
632 /* Alocate storage for value type. */
633 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
637 #endif /* TARGET_WIN32 */
640 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
642 guint32 *gr, guint32 *fr, guint32 *stack_size)
645 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
647 guint32 size, quad, nquads, i, nfields;
648 /* Keep track of the size used in each quad so we can */
649 /* use the right size when copying args/return vars. */
650 guint32 quadsize [2] = {8, 8};
651 ArgumentClass args [2];
652 StructFieldInfo *fields = NULL;
654 gboolean pass_on_stack = FALSE;
657 klass = mono_class_from_mono_type (type);
658 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
660 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
661 /* We pass and return vtypes of size 8 in a register */
662 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
663 pass_on_stack = TRUE;
666 /* If this struct can't be split up naturally into 8-byte */
667 /* chunks (registers), pass it on the stack. */
669 MonoMarshalType *info = mono_marshal_load_type_info (klass);
671 struct_size = info->native_size;
673 struct_size = mono_class_value_size (klass, NULL);
676 * Collect field information recursively to be able to
677 * handle nested structures.
679 nfields = count_fields_nested (klass, sig->pinvoke);
680 fields = g_new0 (StructFieldInfo, nfields);
681 collect_field_info_nested (klass, fields, 0, 0, sig->pinvoke, klass->unicode);
683 for (i = 0; i < nfields; ++i) {
684 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
685 pass_on_stack = TRUE;
691 ainfo->storage = ArgValuetypeInReg;
692 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
697 /* Allways pass in memory */
698 ainfo->offset = *stack_size;
699 *stack_size += ALIGN_TO (size, 8);
700 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
702 ainfo->arg_size = ALIGN_TO (size, 8);
714 int n = mono_class_value_size (klass, NULL);
716 quadsize [0] = n >= 8 ? 8 : n;
717 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
719 /* Always pass in 1 or 2 integer registers */
720 args [0] = ARG_CLASS_INTEGER;
721 args [1] = ARG_CLASS_INTEGER;
722 /* Only the simplest cases are supported */
723 if (is_return && nquads != 1) {
724 args [0] = ARG_CLASS_MEMORY;
725 args [1] = ARG_CLASS_MEMORY;
729 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
730 * The X87 and SSEUP stuff is left out since there are no such types in
734 ainfo->storage = ArgValuetypeInReg;
735 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
739 if (struct_size > 16) {
740 ainfo->offset = *stack_size;
741 *stack_size += ALIGN_TO (struct_size, 8);
742 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
744 ainfo->arg_size = ALIGN_TO (struct_size, 8);
750 args [0] = ARG_CLASS_NO_CLASS;
751 args [1] = ARG_CLASS_NO_CLASS;
752 for (quad = 0; quad < nquads; ++quad) {
753 ArgumentClass class1;
756 class1 = ARG_CLASS_MEMORY;
758 class1 = ARG_CLASS_NO_CLASS;
759 for (i = 0; i < nfields; ++i) {
760 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
761 /* Unaligned field */
765 /* Skip fields in other quad */
766 if ((quad == 0) && (fields [i].offset >= 8))
768 if ((quad == 1) && (fields [i].offset < 8))
771 /* How far into this quad this data extends.*/
772 /* (8 is size of quad) */
773 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
775 class1 = merge_argument_class_from_type (fields [i].type, class1);
777 /* Empty structs have a nonzero size, causing this assert to be hit */
779 g_assert (class1 != ARG_CLASS_NO_CLASS);
780 args [quad] = class1;
786 /* Post merger cleanup */
787 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
788 args [0] = args [1] = ARG_CLASS_MEMORY;
790 /* Allocate registers */
795 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
797 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
800 ainfo->storage = ArgValuetypeInReg;
801 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
802 g_assert (quadsize [0] <= 8);
803 g_assert (quadsize [1] <= 8);
804 ainfo->pair_size [0] = quadsize [0];
805 ainfo->pair_size [1] = quadsize [1];
806 ainfo->nregs = nquads;
807 for (quad = 0; quad < nquads; ++quad) {
808 switch (args [quad]) {
809 case ARG_CLASS_INTEGER:
810 if (*gr >= PARAM_REGS)
811 args [quad] = ARG_CLASS_MEMORY;
813 ainfo->pair_storage [quad] = ArgInIReg;
815 ainfo->pair_regs [quad] = return_regs [*gr];
817 ainfo->pair_regs [quad] = param_regs [*gr];
822 if (*fr >= FLOAT_PARAM_REGS)
823 args [quad] = ARG_CLASS_MEMORY;
825 if (quadsize[quad] <= 4)
826 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
827 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
828 ainfo->pair_regs [quad] = *fr;
832 case ARG_CLASS_MEMORY:
834 case ARG_CLASS_NO_CLASS:
837 g_assert_not_reached ();
841 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
843 /* Revert possible register assignments */
847 ainfo->offset = *stack_size;
849 arg_size = ALIGN_TO (struct_size, 8);
851 arg_size = nquads * sizeof(mgreg_t);
852 *stack_size += arg_size;
853 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
855 ainfo->arg_size = arg_size;
858 #endif /* !TARGET_WIN32 */
864 * Obtain information about a call according to the calling convention.
865 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
866 * Draft Version 0.23" document for more information.
867 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
868 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
871 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
873 guint32 i, gr, fr, pstart;
875 int n = sig->hasthis + sig->param_count;
876 guint32 stack_size = 0;
878 gboolean is_pinvoke = sig->pinvoke;
881 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
883 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
886 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
892 /* Reserve space where the callee can save the argument registers */
893 stack_size = 4 * sizeof (mgreg_t);
897 ret_type = mini_get_underlying_type (sig->ret);
898 switch (ret_type->type) {
908 case MONO_TYPE_FNPTR:
909 case MONO_TYPE_CLASS:
910 case MONO_TYPE_OBJECT:
911 case MONO_TYPE_SZARRAY:
912 case MONO_TYPE_ARRAY:
913 case MONO_TYPE_STRING:
914 cinfo->ret.storage = ArgInIReg;
915 cinfo->ret.reg = AMD64_RAX;
919 cinfo->ret.storage = ArgInIReg;
920 cinfo->ret.reg = AMD64_RAX;
923 cinfo->ret.storage = ArgInFloatSSEReg;
924 cinfo->ret.reg = AMD64_XMM0;
927 cinfo->ret.storage = ArgInDoubleSSEReg;
928 cinfo->ret.reg = AMD64_XMM0;
930 case MONO_TYPE_GENERICINST:
931 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
932 cinfo->ret.storage = ArgInIReg;
933 cinfo->ret.reg = AMD64_RAX;
936 if (mini_is_gsharedvt_type (ret_type)) {
937 cinfo->ret.storage = ArgGsharedvtVariableInReg;
941 case MONO_TYPE_VALUETYPE:
942 case MONO_TYPE_TYPEDBYREF: {
943 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
945 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
946 g_assert (cinfo->ret.storage != ArgInIReg);
951 g_assert (mini_is_gsharedvt_type (ret_type));
952 cinfo->ret.storage = ArgGsharedvtVariableInReg;
957 g_error ("Can't handle as return value 0x%x", ret_type->type);
962 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
963 * the first argument, allowing 'this' to be always passed in the first arg reg.
964 * Also do this if the first argument is a reference type, since virtual calls
965 * are sometimes made using calli without sig->hasthis set, like in the delegate
968 ArgStorage ret_storage = cinfo->ret.storage;
969 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
971 add_general (&gr, &stack_size, cinfo->args + 0);
973 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
976 add_general (&gr, &stack_size, &cinfo->ret);
977 cinfo->ret.storage = ret_storage;
978 cinfo->vret_arg_index = 1;
982 add_general (&gr, &stack_size, cinfo->args + 0);
984 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
985 add_general (&gr, &stack_size, &cinfo->ret);
986 cinfo->ret.storage = ret_storage;
990 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
992 fr = FLOAT_PARAM_REGS;
994 /* Emit the signature cookie just before the implicit arguments */
995 add_general (&gr, &stack_size, &cinfo->sig_cookie);
998 for (i = pstart; i < sig->param_count; ++i) {
999 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1003 /* The float param registers and other param registers must be the same index on Windows x64.*/
1010 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1011 /* We allways pass the sig cookie on the stack for simplicity */
1013 * Prevent implicit arguments + the sig cookie from being passed
1017 fr = FLOAT_PARAM_REGS;
1019 /* Emit the signature cookie just before the implicit arguments */
1020 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1023 ptype = mini_get_underlying_type (sig->params [i]);
1024 switch (ptype->type) {
1027 add_general (&gr, &stack_size, ainfo);
1031 add_general (&gr, &stack_size, ainfo);
1035 add_general (&gr, &stack_size, ainfo);
1040 case MONO_TYPE_FNPTR:
1041 case MONO_TYPE_CLASS:
1042 case MONO_TYPE_OBJECT:
1043 case MONO_TYPE_STRING:
1044 case MONO_TYPE_SZARRAY:
1045 case MONO_TYPE_ARRAY:
1046 add_general (&gr, &stack_size, ainfo);
1048 case MONO_TYPE_GENERICINST:
1049 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1050 add_general (&gr, &stack_size, ainfo);
1053 if (mini_is_gsharedvt_variable_type (ptype)) {
1054 /* gsharedvt arguments are passed by ref */
1055 add_general (&gr, &stack_size, ainfo);
1056 if (ainfo->storage == ArgInIReg)
1057 ainfo->storage = ArgGSharedVtInReg;
1059 ainfo->storage = ArgGSharedVtOnStack;
1063 case MONO_TYPE_VALUETYPE:
1064 case MONO_TYPE_TYPEDBYREF:
1065 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1070 add_general (&gr, &stack_size, ainfo);
1073 add_float (&fr, &stack_size, ainfo, FALSE);
1076 add_float (&fr, &stack_size, ainfo, TRUE);
1079 case MONO_TYPE_MVAR:
1080 /* gsharedvt arguments are passed by ref */
1081 g_assert (mini_is_gsharedvt_type (ptype));
1082 add_general (&gr, &stack_size, ainfo);
1083 if (ainfo->storage == ArgInIReg)
1084 ainfo->storage = ArgGSharedVtInReg;
1086 ainfo->storage = ArgGSharedVtOnStack;
1089 g_assert_not_reached ();
1093 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1095 fr = FLOAT_PARAM_REGS;
1097 /* Emit the signature cookie just before the implicit arguments */
1098 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1101 cinfo->stack_usage = stack_size;
1102 cinfo->reg_usage = gr;
1103 cinfo->freg_usage = fr;
1108 * mono_arch_get_argument_info:
1109 * @csig: a method signature
1110 * @param_count: the number of parameters to consider
1111 * @arg_info: an array to store the result infos
1113 * Gathers information on parameters such as size, alignment and
1114 * padding. arg_info should be large enought to hold param_count + 1 entries.
1116 * Returns the size of the argument area on the stack.
1119 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1122 CallInfo *cinfo = get_call_info (NULL, csig);
1123 guint32 args_size = cinfo->stack_usage;
1125 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1126 if (csig->hasthis) {
1127 arg_info [0].offset = 0;
1130 for (k = 0; k < param_count; k++) {
1131 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1133 arg_info [k + 1].size = 0;
1142 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1146 MonoType *callee_ret;
1148 c1 = get_call_info (NULL, caller_sig);
1149 c2 = get_call_info (NULL, callee_sig);
1150 res = c1->stack_usage >= c2->stack_usage;
1151 callee_ret = mini_get_underlying_type (callee_sig->ret);
1152 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1153 /* An address on the callee's stack is passed as the first argument */
1163 * Initialize the cpu to execute managed code.
1166 mono_arch_cpu_init (void)
1171 /* spec compliance requires running with double precision */
1172 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1173 fpcw &= ~X86_FPCW_PRECC_MASK;
1174 fpcw |= X86_FPCW_PREC_DOUBLE;
1175 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1176 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1178 /* TODO: This is crashing on Win64 right now.
1179 * _control87 (_PC_53, MCW_PC);
1185 * Initialize architecture specific code.
1188 mono_arch_init (void)
1190 mono_os_mutex_init_recursive (&mini_arch_mutex);
1192 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1193 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1194 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1195 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1196 mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1198 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1199 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1203 bp_trampoline = mini_get_breakpoint_trampoline ();
1207 * Cleanup architecture specific code.
1210 mono_arch_cleanup (void)
1212 mono_os_mutex_destroy (&mini_arch_mutex);
1216 * This function returns the optimizations supported on this cpu.
1219 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1225 if (mono_hwcap_x86_has_cmov) {
1226 opts |= MONO_OPT_CMOV;
1228 if (mono_hwcap_x86_has_fcmov)
1229 opts |= MONO_OPT_FCMOV;
1231 *exclude_mask |= MONO_OPT_FCMOV;
1233 *exclude_mask |= MONO_OPT_CMOV;
1237 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1238 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1239 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1240 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1241 /* will now have a reference to an argument that won't be fully decomposed. */
1242 *exclude_mask |= MONO_OPT_SIMD;
1249 * This function test for all SSE functions supported.
1251 * Returns a bitmask corresponding to all supported versions.
1255 mono_arch_cpu_enumerate_simd_versions (void)
1257 guint32 sse_opts = 0;
1259 if (mono_hwcap_x86_has_sse1)
1260 sse_opts |= SIMD_VERSION_SSE1;
1262 if (mono_hwcap_x86_has_sse2)
1263 sse_opts |= SIMD_VERSION_SSE2;
1265 if (mono_hwcap_x86_has_sse3)
1266 sse_opts |= SIMD_VERSION_SSE3;
1268 if (mono_hwcap_x86_has_ssse3)
1269 sse_opts |= SIMD_VERSION_SSSE3;
1271 if (mono_hwcap_x86_has_sse41)
1272 sse_opts |= SIMD_VERSION_SSE41;
1274 if (mono_hwcap_x86_has_sse42)
1275 sse_opts |= SIMD_VERSION_SSE42;
1277 if (mono_hwcap_x86_has_sse4a)
1278 sse_opts |= SIMD_VERSION_SSE4a;
1286 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1291 for (i = 0; i < cfg->num_varinfo; i++) {
1292 MonoInst *ins = cfg->varinfo [i];
1293 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1296 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1299 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1300 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1303 if (mono_is_regsize_var (ins->inst_vtype)) {
1304 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1305 g_assert (i == vmv->idx);
1306 vars = g_list_prepend (vars, vmv);
1310 vars = mono_varlist_sort (cfg, vars, 0);
1316 * mono_arch_compute_omit_fp:
1318 * Determine whenever the frame pointer can be eliminated.
1321 mono_arch_compute_omit_fp (MonoCompile *cfg)
1323 MonoMethodSignature *sig;
1324 MonoMethodHeader *header;
1328 if (cfg->arch.omit_fp_computed)
1331 header = cfg->header;
1333 sig = mono_method_signature (cfg->method);
1335 if (!cfg->arch.cinfo)
1336 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1337 cinfo = (CallInfo *)cfg->arch.cinfo;
1340 * FIXME: Remove some of the restrictions.
1342 cfg->arch.omit_fp = TRUE;
1343 cfg->arch.omit_fp_computed = TRUE;
1345 if (cfg->disable_omit_fp)
1346 cfg->arch.omit_fp = FALSE;
1348 if (!debug_omit_fp ())
1349 cfg->arch.omit_fp = FALSE;
1351 if (cfg->method->save_lmf)
1352 cfg->arch.omit_fp = FALSE;
1354 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1355 cfg->arch.omit_fp = FALSE;
1356 if (header->num_clauses)
1357 cfg->arch.omit_fp = FALSE;
1358 if (cfg->param_area)
1359 cfg->arch.omit_fp = FALSE;
1360 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1361 cfg->arch.omit_fp = FALSE;
1362 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1363 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1364 cfg->arch.omit_fp = FALSE;
1365 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1366 ArgInfo *ainfo = &cinfo->args [i];
1368 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1370 * The stack offset can only be determined when the frame
1373 cfg->arch.omit_fp = FALSE;
1378 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1379 MonoInst *ins = cfg->varinfo [i];
1382 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1387 mono_arch_get_global_int_regs (MonoCompile *cfg)
1391 mono_arch_compute_omit_fp (cfg);
1393 if (cfg->arch.omit_fp)
1394 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1396 /* We use the callee saved registers for global allocation */
1397 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1398 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1399 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1400 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1401 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1403 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1404 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1411 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1416 /* All XMM registers */
1417 for (i = 0; i < 16; ++i)
1418 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1424 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1426 static GList *r = NULL;
1431 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1432 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1433 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1434 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1435 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1436 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1438 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1439 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1440 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1441 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1442 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1443 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1444 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1445 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1447 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1454 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1457 static GList *r = NULL;
1462 for (i = 0; i < AMD64_XMM_NREG; ++i)
1463 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1465 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1472 * mono_arch_regalloc_cost:
1474 * Return the cost, in number of memory references, of the action of
1475 * allocating the variable VMV into a register during global register
1479 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1481 MonoInst *ins = cfg->varinfo [vmv->idx];
1483 if (cfg->method->save_lmf)
1484 /* The register is already saved */
1485 /* substract 1 for the invisible store in the prolog */
1486 return (ins->opcode == OP_ARG) ? 0 : 1;
1489 return (ins->opcode == OP_ARG) ? 1 : 2;
1493 * mono_arch_fill_argument_info:
1495 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1499 mono_arch_fill_argument_info (MonoCompile *cfg)
1502 MonoMethodSignature *sig;
1507 sig = mono_method_signature (cfg->method);
1509 cinfo = (CallInfo *)cfg->arch.cinfo;
1510 sig_ret = mini_get_underlying_type (sig->ret);
1513 * Contrary to mono_arch_allocate_vars (), the information should describe
1514 * where the arguments are at the beginning of the method, not where they can be
1515 * accessed during the execution of the method. The later makes no sense for the
1516 * global register allocator, since a variable can be in more than one location.
1518 switch (cinfo->ret.storage) {
1520 case ArgInFloatSSEReg:
1521 case ArgInDoubleSSEReg:
1522 cfg->ret->opcode = OP_REGVAR;
1523 cfg->ret->inst_c0 = cinfo->ret.reg;
1525 case ArgValuetypeInReg:
1526 cfg->ret->opcode = OP_REGOFFSET;
1527 cfg->ret->inst_basereg = -1;
1528 cfg->ret->inst_offset = -1;
1533 g_assert_not_reached ();
1536 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1537 ArgInfo *ainfo = &cinfo->args [i];
1539 ins = cfg->args [i];
1541 switch (ainfo->storage) {
1543 case ArgInFloatSSEReg:
1544 case ArgInDoubleSSEReg:
1545 ins->opcode = OP_REGVAR;
1546 ins->inst_c0 = ainfo->reg;
1549 ins->opcode = OP_REGOFFSET;
1550 ins->inst_basereg = -1;
1551 ins->inst_offset = -1;
1553 case ArgValuetypeInReg:
1555 ins->opcode = OP_NOP;
1558 g_assert_not_reached ();
1564 mono_arch_allocate_vars (MonoCompile *cfg)
1567 MonoMethodSignature *sig;
1570 guint32 locals_stack_size, locals_stack_align;
1574 sig = mono_method_signature (cfg->method);
1576 cinfo = (CallInfo *)cfg->arch.cinfo;
1577 sig_ret = mini_get_underlying_type (sig->ret);
1579 mono_arch_compute_omit_fp (cfg);
1582 * We use the ABI calling conventions for managed code as well.
1583 * Exception: valuetypes are only sometimes passed or returned in registers.
1587 * The stack looks like this:
1588 * <incoming arguments passed on the stack>
1590 * <lmf/caller saved registers>
1593 * <localloc area> -> grows dynamically
1597 if (cfg->arch.omit_fp) {
1598 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1599 cfg->frame_reg = AMD64_RSP;
1602 /* Locals are allocated backwards from %fp */
1603 cfg->frame_reg = AMD64_RBP;
1607 cfg->arch.saved_iregs = cfg->used_int_regs;
1608 if (cfg->method->save_lmf) {
1609 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1610 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1611 cfg->arch.saved_iregs |= iregs_to_save;
1614 if (cfg->arch.omit_fp)
1615 cfg->arch.reg_save_area_offset = offset;
1616 /* Reserve space for callee saved registers */
1617 for (i = 0; i < AMD64_NREG; ++i)
1618 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1619 offset += sizeof(mgreg_t);
1621 if (!cfg->arch.omit_fp)
1622 cfg->arch.reg_save_area_offset = -offset;
1624 if (sig_ret->type != MONO_TYPE_VOID) {
1625 switch (cinfo->ret.storage) {
1627 case ArgInFloatSSEReg:
1628 case ArgInDoubleSSEReg:
1629 cfg->ret->opcode = OP_REGVAR;
1630 cfg->ret->inst_c0 = cinfo->ret.reg;
1631 cfg->ret->dreg = cinfo->ret.reg;
1633 case ArgValuetypeAddrInIReg:
1634 case ArgGsharedvtVariableInReg:
1635 /* The register is volatile */
1636 cfg->vret_addr->opcode = OP_REGOFFSET;
1637 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1638 if (cfg->arch.omit_fp) {
1639 cfg->vret_addr->inst_offset = offset;
1643 cfg->vret_addr->inst_offset = -offset;
1645 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1646 printf ("vret_addr =");
1647 mono_print_ins (cfg->vret_addr);
1650 case ArgValuetypeInReg:
1651 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1652 cfg->ret->opcode = OP_REGOFFSET;
1653 cfg->ret->inst_basereg = cfg->frame_reg;
1654 if (cfg->arch.omit_fp) {
1655 cfg->ret->inst_offset = offset;
1656 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1658 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1659 cfg->ret->inst_offset = - offset;
1663 g_assert_not_reached ();
1667 /* Allocate locals */
1668 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1669 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1670 char *mname = mono_method_full_name (cfg->method, TRUE);
1671 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1676 if (locals_stack_align) {
1677 offset += (locals_stack_align - 1);
1678 offset &= ~(locals_stack_align - 1);
1680 if (cfg->arch.omit_fp) {
1681 cfg->locals_min_stack_offset = offset;
1682 cfg->locals_max_stack_offset = offset + locals_stack_size;
1684 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1685 cfg->locals_max_stack_offset = - offset;
1688 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1689 if (offsets [i] != -1) {
1690 MonoInst *ins = cfg->varinfo [i];
1691 ins->opcode = OP_REGOFFSET;
1692 ins->inst_basereg = cfg->frame_reg;
1693 if (cfg->arch.omit_fp)
1694 ins->inst_offset = (offset + offsets [i]);
1696 ins->inst_offset = - (offset + offsets [i]);
1697 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1700 offset += locals_stack_size;
1702 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1703 g_assert (!cfg->arch.omit_fp);
1704 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1705 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1708 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1709 ins = cfg->args [i];
1710 if (ins->opcode != OP_REGVAR) {
1711 ArgInfo *ainfo = &cinfo->args [i];
1712 gboolean inreg = TRUE;
1714 /* FIXME: Allocate volatile arguments to registers */
1715 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1719 * Under AMD64, all registers used to pass arguments to functions
1720 * are volatile across calls.
1721 * FIXME: Optimize this.
1723 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1726 ins->opcode = OP_REGOFFSET;
1728 switch (ainfo->storage) {
1730 case ArgInFloatSSEReg:
1731 case ArgInDoubleSSEReg:
1732 case ArgGSharedVtInReg:
1734 ins->opcode = OP_REGVAR;
1735 ins->dreg = ainfo->reg;
1739 case ArgGSharedVtOnStack:
1740 g_assert (!cfg->arch.omit_fp);
1741 ins->opcode = OP_REGOFFSET;
1742 ins->inst_basereg = cfg->frame_reg;
1743 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1745 case ArgValuetypeInReg:
1747 case ArgValuetypeAddrInIReg:
1748 case ArgValuetypeAddrOnStack: {
1750 g_assert (!cfg->arch.omit_fp);
1751 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1752 MONO_INST_NEW (cfg, indir, 0);
1754 indir->opcode = OP_REGOFFSET;
1755 if (ainfo->pair_storage [0] == ArgInIReg) {
1756 indir->inst_basereg = cfg->frame_reg;
1757 offset = ALIGN_TO (offset, sizeof (gpointer));
1758 offset += (sizeof (gpointer));
1759 indir->inst_offset = - offset;
1762 indir->inst_basereg = cfg->frame_reg;
1763 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1766 ins->opcode = OP_VTARG_ADDR;
1767 ins->inst_left = indir;
1775 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1776 ins->opcode = OP_REGOFFSET;
1777 ins->inst_basereg = cfg->frame_reg;
1778 /* These arguments are saved to the stack in the prolog */
1779 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1780 if (cfg->arch.omit_fp) {
1781 ins->inst_offset = offset;
1782 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1783 // Arguments are yet supported by the stack map creation code
1784 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1786 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1787 ins->inst_offset = - offset;
1788 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1794 cfg->stack_offset = offset;
1798 mono_arch_create_vars (MonoCompile *cfg)
1800 MonoMethodSignature *sig;
1804 sig = mono_method_signature (cfg->method);
1806 if (!cfg->arch.cinfo)
1807 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1808 cinfo = (CallInfo *)cfg->arch.cinfo;
1810 if (cinfo->ret.storage == ArgValuetypeInReg)
1811 cfg->ret_var_is_local = TRUE;
1813 sig_ret = mini_get_underlying_type (sig->ret);
1814 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1815 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1816 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1817 printf ("vret_addr = ");
1818 mono_print_ins (cfg->vret_addr);
1822 if (cfg->gen_sdb_seq_points) {
1825 if (cfg->compile_aot) {
1826 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1827 ins->flags |= MONO_INST_VOLATILE;
1828 cfg->arch.seq_point_info_var = ins;
1830 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1831 ins->flags |= MONO_INST_VOLATILE;
1832 cfg->arch.ss_tramp_var = ins;
1834 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1835 ins->flags |= MONO_INST_VOLATILE;
1836 cfg->arch.bp_tramp_var = ins;
1839 if (cfg->method->save_lmf)
1840 cfg->create_lmf_var = TRUE;
1842 if (cfg->method->save_lmf) {
1844 #if !defined(TARGET_WIN32)
1845 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1846 cfg->lmf_ir_mono_lmf = TRUE;
1852 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1858 MONO_INST_NEW (cfg, ins, OP_MOVE);
1859 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1860 ins->sreg1 = tree->dreg;
1861 MONO_ADD_INS (cfg->cbb, ins);
1862 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1864 case ArgInFloatSSEReg:
1865 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1866 ins->dreg = mono_alloc_freg (cfg);
1867 ins->sreg1 = tree->dreg;
1868 MONO_ADD_INS (cfg->cbb, ins);
1870 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1872 case ArgInDoubleSSEReg:
1873 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1874 ins->dreg = mono_alloc_freg (cfg);
1875 ins->sreg1 = tree->dreg;
1876 MONO_ADD_INS (cfg->cbb, ins);
1878 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1882 g_assert_not_reached ();
1887 arg_storage_to_load_membase (ArgStorage storage)
1891 #if defined(__mono_ilp32__)
1892 return OP_LOADI8_MEMBASE;
1894 return OP_LOAD_MEMBASE;
1896 case ArgInDoubleSSEReg:
1897 return OP_LOADR8_MEMBASE;
1898 case ArgInFloatSSEReg:
1899 return OP_LOADR4_MEMBASE;
1901 g_assert_not_reached ();
1908 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1910 MonoMethodSignature *tmp_sig;
1913 if (call->tail_call)
1916 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1919 * mono_ArgIterator_Setup assumes the signature cookie is
1920 * passed first and all the arguments which were before it are
1921 * passed on the stack after the signature. So compensate by
1922 * passing a different signature.
1924 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1925 tmp_sig->param_count -= call->signature->sentinelpos;
1926 tmp_sig->sentinelpos = 0;
1927 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1929 sig_reg = mono_alloc_ireg (cfg);
1930 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1932 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1936 static inline LLVMArgStorage
1937 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1941 return LLVMArgInIReg;
1944 case ArgGSharedVtInReg:
1945 case ArgGSharedVtOnStack:
1946 return LLVMArgGSharedVt;
1948 g_assert_not_reached ();
1954 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1960 LLVMCallInfo *linfo;
1961 MonoType *t, *sig_ret;
1963 n = sig->param_count + sig->hasthis;
1964 sig_ret = mini_get_underlying_type (sig->ret);
1966 cinfo = get_call_info (cfg->mempool, sig);
1968 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1971 * LLVM always uses the native ABI while we use our own ABI, the
1972 * only difference is the handling of vtypes:
1973 * - we only pass/receive them in registers in some cases, and only
1974 * in 1 or 2 integer registers.
1976 switch (cinfo->ret.storage) {
1978 linfo->ret.storage = LLVMArgNone;
1981 case ArgInFloatSSEReg:
1982 case ArgInDoubleSSEReg:
1983 linfo->ret.storage = LLVMArgNormal;
1985 case ArgValuetypeInReg: {
1986 ainfo = &cinfo->ret;
1989 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1990 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1991 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1992 cfg->disable_llvm = TRUE;
1996 linfo->ret.storage = LLVMArgVtypeInReg;
1997 for (j = 0; j < 2; ++j)
1998 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2001 case ArgValuetypeAddrInIReg:
2002 case ArgGsharedvtVariableInReg:
2003 /* Vtype returned using a hidden argument */
2004 linfo->ret.storage = LLVMArgVtypeRetAddr;
2005 linfo->vret_arg_index = cinfo->vret_arg_index;
2008 g_assert_not_reached ();
2012 for (i = 0; i < n; ++i) {
2013 ainfo = cinfo->args + i;
2015 if (i >= sig->hasthis)
2016 t = sig->params [i - sig->hasthis];
2018 t = &mono_defaults.int_class->byval_arg;
2019 t = mini_type_get_underlying_type (t);
2021 linfo->args [i].storage = LLVMArgNone;
2023 switch (ainfo->storage) {
2025 linfo->args [i].storage = LLVMArgNormal;
2027 case ArgInDoubleSSEReg:
2028 case ArgInFloatSSEReg:
2029 linfo->args [i].storage = LLVMArgNormal;
2032 if (MONO_TYPE_ISSTRUCT (t))
2033 linfo->args [i].storage = LLVMArgVtypeByVal;
2035 linfo->args [i].storage = LLVMArgNormal;
2037 case ArgValuetypeInReg:
2039 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2040 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2041 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2042 cfg->disable_llvm = TRUE;
2046 linfo->args [i].storage = LLVMArgVtypeInReg;
2047 for (j = 0; j < 2; ++j)
2048 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2050 case ArgGSharedVtInReg:
2051 case ArgGSharedVtOnStack:
2052 linfo->args [i].storage = LLVMArgGSharedVt;
2055 cfg->exception_message = g_strdup ("ainfo->storage");
2056 cfg->disable_llvm = TRUE;
2066 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2069 MonoMethodSignature *sig;
2075 sig = call->signature;
2076 n = sig->param_count + sig->hasthis;
2078 cinfo = get_call_info (cfg->mempool, sig);
2082 if (COMPILE_LLVM (cfg)) {
2083 /* We shouldn't be called in the llvm case */
2084 cfg->disable_llvm = TRUE;
2089 * Emit all arguments which are passed on the stack to prevent register
2090 * allocation problems.
2092 for (i = 0; i < n; ++i) {
2094 ainfo = cinfo->args + i;
2096 in = call->args [i];
2098 if (sig->hasthis && i == 0)
2099 t = &mono_defaults.object_class->byval_arg;
2101 t = sig->params [i - sig->hasthis];
2103 t = mini_get_underlying_type (t);
2104 //XXX what about ArgGSharedVtOnStack here?
2105 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2107 if (t->type == MONO_TYPE_R4)
2108 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2109 else if (t->type == MONO_TYPE_R8)
2110 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2112 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2114 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2116 if (cfg->compute_gc_maps) {
2119 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2125 * Emit all parameters passed in registers in non-reverse order for better readability
2126 * and to help the optimization in emit_prolog ().
2128 for (i = 0; i < n; ++i) {
2129 ainfo = cinfo->args + i;
2131 in = call->args [i];
2133 if (ainfo->storage == ArgInIReg)
2134 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2137 for (i = n - 1; i >= 0; --i) {
2140 ainfo = cinfo->args + i;
2142 in = call->args [i];
2144 if (sig->hasthis && i == 0)
2145 t = &mono_defaults.object_class->byval_arg;
2147 t = sig->params [i - sig->hasthis];
2148 t = mini_get_underlying_type (t);
2150 switch (ainfo->storage) {
2154 case ArgInFloatSSEReg:
2155 case ArgInDoubleSSEReg:
2156 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2159 case ArgValuetypeInReg:
2160 case ArgValuetypeAddrInIReg:
2161 case ArgValuetypeAddrOnStack:
2162 case ArgGSharedVtInReg:
2163 case ArgGSharedVtOnStack: {
2164 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2165 /* Already emitted above */
2167 //FIXME what about ArgGSharedVtOnStack ?
2168 if (ainfo->storage == ArgOnStack && call->tail_call) {
2169 MonoInst *call_inst = (MonoInst*)call;
2170 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2171 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2179 size = mono_type_native_stack_size (t, &align);
2182 * Other backends use mono_type_stack_size (), but that
2183 * aligns the size to 8, which is larger than the size of
2184 * the source, leading to reads of invalid memory if the
2185 * source is at the end of address space.
2187 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2190 if (size >= 10000) {
2191 /* Avoid asserts in emit_memcpy () */
2192 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2193 /* Continue normally */
2196 if (size > 0 || ainfo->pass_empty_struct) {
2197 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2198 arg->sreg1 = in->dreg;
2199 arg->klass = mono_class_from_mono_type (t);
2200 arg->backend.size = size;
2201 arg->inst_p0 = call;
2202 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2203 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2205 MONO_ADD_INS (cfg->cbb, arg);
2210 g_assert_not_reached ();
2213 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2214 /* Emit the signature cookie just before the implicit arguments */
2215 emit_sig_cookie (cfg, call, cinfo);
2218 /* Handle the case where there are no implicit arguments */
2219 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2220 emit_sig_cookie (cfg, call, cinfo);
2222 switch (cinfo->ret.storage) {
2223 case ArgValuetypeInReg:
2224 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2226 * Tell the JIT to use a more efficient calling convention: call using
2227 * OP_CALL, compute the result location after the call, and save the
2230 call->vret_in_reg = TRUE;
2232 * Nullify the instruction computing the vret addr to enable
2233 * future optimizations.
2236 NULLIFY_INS (call->vret_var);
2238 if (call->tail_call)
2241 * The valuetype is in RAX:RDX after the call, need to be copied to
2242 * the stack. Push the address here, so the call instruction can
2245 if (!cfg->arch.vret_addr_loc) {
2246 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2247 /* Prevent it from being register allocated or optimized away */
2248 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2251 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2254 case ArgValuetypeAddrInIReg:
2255 case ArgGsharedvtVariableInReg: {
2257 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2258 vtarg->sreg1 = call->vret_var->dreg;
2259 vtarg->dreg = mono_alloc_preg (cfg);
2260 MONO_ADD_INS (cfg->cbb, vtarg);
2262 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2269 if (cfg->method->save_lmf) {
2270 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2271 MONO_ADD_INS (cfg->cbb, arg);
2274 call->stack_usage = cinfo->stack_usage;
2278 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2281 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2282 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2283 int size = ins->backend.size;
2285 switch (ainfo->storage) {
2286 case ArgValuetypeInReg: {
2290 for (part = 0; part < 2; ++part) {
2291 if (ainfo->pair_storage [part] == ArgNone)
2294 if (ainfo->pass_empty_struct) {
2295 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2296 NEW_ICONST (cfg, load, 0);
2299 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2300 load->inst_basereg = src->dreg;
2301 load->inst_offset = part * sizeof(mgreg_t);
2303 switch (ainfo->pair_storage [part]) {
2305 load->dreg = mono_alloc_ireg (cfg);
2307 case ArgInDoubleSSEReg:
2308 case ArgInFloatSSEReg:
2309 load->dreg = mono_alloc_freg (cfg);
2312 g_assert_not_reached ();
2316 MONO_ADD_INS (cfg->cbb, load);
2318 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2322 case ArgValuetypeAddrInIReg:
2323 case ArgValuetypeAddrOnStack: {
2324 MonoInst *vtaddr, *load;
2326 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2328 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2330 MONO_INST_NEW (cfg, load, OP_LDADDR);
2331 cfg->has_indirection = TRUE;
2332 load->inst_p0 = vtaddr;
2333 vtaddr->flags |= MONO_INST_INDIRECT;
2334 load->type = STACK_MP;
2335 load->klass = vtaddr->klass;
2336 load->dreg = mono_alloc_ireg (cfg);
2337 MONO_ADD_INS (cfg->cbb, load);
2338 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2340 if (ainfo->pair_storage [0] == ArgInIReg) {
2341 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2342 arg->dreg = mono_alloc_ireg (cfg);
2343 arg->sreg1 = load->dreg;
2345 MONO_ADD_INS (cfg->cbb, arg);
2346 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2348 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2352 case ArgGSharedVtInReg:
2354 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2356 case ArgGSharedVtOnStack:
2357 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2361 int dreg = mono_alloc_ireg (cfg);
2363 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2364 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2365 } else if (size <= 40) {
2366 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2368 // FIXME: Code growth
2369 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2372 if (cfg->compute_gc_maps) {
2374 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2380 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2382 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2384 if (ret->type == MONO_TYPE_R4) {
2385 if (COMPILE_LLVM (cfg))
2386 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2388 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2390 } else if (ret->type == MONO_TYPE_R8) {
2391 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2395 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2398 #endif /* DISABLE_JIT */
2400 #define EMIT_COND_BRANCH(ins,cond,sign) \
2401 if (ins->inst_true_bb->native_offset) { \
2402 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2404 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2405 if ((cfg->opt & MONO_OPT_BRANCH) && \
2406 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2407 x86_branch8 (code, cond, 0, sign); \
2409 x86_branch32 (code, cond, 0, sign); \
2413 MonoMethodSignature *sig;
2418 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2422 switch (cinfo->ret.storage) {
2425 case ArgInFloatSSEReg:
2426 case ArgInDoubleSSEReg:
2427 case ArgValuetypeAddrInIReg:
2428 case ArgValuetypeInReg:
2434 for (i = 0; i < cinfo->nargs; ++i) {
2435 ArgInfo *ainfo = &cinfo->args [i];
2436 switch (ainfo->storage) {
2438 case ArgInFloatSSEReg:
2439 case ArgInDoubleSSEReg:
2440 case ArgValuetypeInReg:
2443 if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2455 * mono_arch_dyn_call_prepare:
2457 * Return a pointer to an arch-specific structure which contains information
2458 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2459 * supported for SIG.
2460 * This function is equivalent to ffi_prep_cif in libffi.
2463 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2465 ArchDynCallInfo *info;
2468 cinfo = get_call_info (NULL, sig);
2470 if (!dyn_call_supported (sig, cinfo)) {
2475 info = g_new0 (ArchDynCallInfo, 1);
2476 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2478 info->cinfo = cinfo;
2480 return (MonoDynCallInfo*)info;
2484 * mono_arch_dyn_call_free:
2486 * Free a MonoDynCallInfo structure.
2489 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2491 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2493 g_free (ainfo->cinfo);
2497 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2498 #define GREG_TO_PTR(greg) (gpointer)(greg)
2501 * mono_arch_get_start_dyn_call:
2503 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2504 * store the result into BUF.
2505 * ARGS should be an array of pointers pointing to the arguments.
2506 * RET should point to a memory buffer large enought to hold the result of the
2508 * This function should be as fast as possible, any work which does not depend
2509 * on the actual values of the arguments should be done in
2510 * mono_arch_dyn_call_prepare ().
2511 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2515 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2517 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2518 DynCallArgs *p = (DynCallArgs*)buf;
2519 int arg_index, greg, freg, i, pindex;
2520 MonoMethodSignature *sig = dinfo->sig;
2521 int buffer_offset = 0;
2522 static int param_reg_to_index [16];
2523 static gboolean param_reg_to_index_inited;
2525 if (!param_reg_to_index_inited) {
2526 for (i = 0; i < PARAM_REGS; ++i)
2527 param_reg_to_index [param_regs [i]] = i;
2528 mono_memory_barrier ();
2529 param_reg_to_index_inited = 1;
2532 g_assert (buf_len >= sizeof (DynCallArgs));
2542 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2543 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2548 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2549 p->regs [greg ++] = PTR_TO_GREG(ret);
2551 for (; pindex < sig->param_count; pindex++) {
2552 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2553 gpointer *arg = args [arg_index ++];
2554 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2557 if (ainfo->storage == ArgOnStack) {
2558 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2560 slot = param_reg_to_index [ainfo->reg];
2564 p->regs [slot] = PTR_TO_GREG(*(arg));
2570 case MONO_TYPE_STRING:
2571 case MONO_TYPE_CLASS:
2572 case MONO_TYPE_ARRAY:
2573 case MONO_TYPE_SZARRAY:
2574 case MONO_TYPE_OBJECT:
2578 #if !defined(__mono_ilp32__)
2582 p->regs [slot] = PTR_TO_GREG(*(arg));
2584 #if defined(__mono_ilp32__)
2587 p->regs [slot] = *(guint64*)(arg);
2591 p->regs [slot] = *(guint8*)(arg);
2594 p->regs [slot] = *(gint8*)(arg);
2597 p->regs [slot] = *(gint16*)(arg);
2600 p->regs [slot] = *(guint16*)(arg);
2603 p->regs [slot] = *(gint32*)(arg);
2606 p->regs [slot] = *(guint32*)(arg);
2608 case MONO_TYPE_R4: {
2611 *(float*)&d = *(float*)(arg);
2613 p->fregs [freg ++] = d;
2618 p->fregs [freg ++] = *(double*)(arg);
2620 case MONO_TYPE_GENERICINST:
2621 if (MONO_TYPE_IS_REFERENCE (t)) {
2622 p->regs [slot] = PTR_TO_GREG(*(arg));
2624 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2625 MonoClass *klass = mono_class_from_mono_type (t);
2626 guint8 *nullable_buf;
2629 size = mono_class_value_size (klass, NULL);
2630 nullable_buf = p->buffer + buffer_offset;
2631 buffer_offset += size;
2632 g_assert (buffer_offset <= 256);
2634 /* The argument pointed to by arg is either a boxed vtype or null */
2635 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2637 arg = (gpointer*)nullable_buf;
2643 case MONO_TYPE_VALUETYPE: {
2644 switch (ainfo->storage) {
2645 case ArgValuetypeInReg:
2646 for (i = 0; i < 2; ++i) {
2647 switch (ainfo->pair_storage [i]) {
2651 slot = param_reg_to_index [ainfo->pair_regs [i]];
2652 p->regs [slot] = ((mgreg_t*)(arg))[i];
2654 case ArgInDoubleSSEReg:
2656 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2659 g_assert_not_reached ();
2665 for (i = 0; i < ainfo->arg_size / 8; ++i)
2666 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2669 g_assert_not_reached ();
2675 g_assert_not_reached ();
2681 * mono_arch_finish_dyn_call:
2683 * Store the result of a dyn call into the return value buffer passed to
2684 * start_dyn_call ().
2685 * This function should be as fast as possible, any work which does not depend
2686 * on the actual values of the arguments should be done in
2687 * mono_arch_dyn_call_prepare ().
2690 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2692 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2693 MonoMethodSignature *sig = dinfo->sig;
2694 DynCallArgs *dargs = (DynCallArgs*)buf;
2695 guint8 *ret = dargs->ret;
2696 mgreg_t res = dargs->res;
2697 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2700 switch (sig_ret->type) {
2701 case MONO_TYPE_VOID:
2702 *(gpointer*)ret = NULL;
2704 case MONO_TYPE_STRING:
2705 case MONO_TYPE_CLASS:
2706 case MONO_TYPE_ARRAY:
2707 case MONO_TYPE_SZARRAY:
2708 case MONO_TYPE_OBJECT:
2712 *(gpointer*)ret = GREG_TO_PTR(res);
2718 *(guint8*)ret = res;
2721 *(gint16*)ret = res;
2724 *(guint16*)ret = res;
2727 *(gint32*)ret = res;
2730 *(guint32*)ret = res;
2733 *(gint64*)ret = res;
2736 *(guint64*)ret = res;
2739 *(float*)ret = *(float*)&(dargs->fregs [0]);
2742 *(double*)ret = dargs->fregs [0];
2744 case MONO_TYPE_GENERICINST:
2745 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2746 *(gpointer*)ret = GREG_TO_PTR(res);
2751 case MONO_TYPE_VALUETYPE:
2752 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2755 ArgInfo *ainfo = &dinfo->cinfo->ret;
2757 g_assert (ainfo->storage == ArgValuetypeInReg);
2759 for (i = 0; i < 2; ++i) {
2760 switch (ainfo->pair_storage [0]) {
2762 ((mgreg_t*)ret)[i] = res;
2764 case ArgInDoubleSSEReg:
2765 ((double*)ret)[i] = dargs->fregs [i];
2770 g_assert_not_reached ();
2777 g_assert_not_reached ();
2781 /* emit an exception if condition is fail */
2782 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2784 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2785 if (tins == NULL) { \
2786 mono_add_patch_info (cfg, code - cfg->native_code, \
2787 MONO_PATCH_INFO_EXC, exc_name); \
2788 x86_branch32 (code, cond, 0, signed); \
2790 EMIT_COND_BRANCH (tins, cond, signed); \
2794 #define EMIT_FPCOMPARE(code) do { \
2795 amd64_fcompp (code); \
2796 amd64_fnstsw (code); \
2799 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2800 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2801 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2802 amd64_ ##op (code); \
2803 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2804 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2808 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2810 gboolean no_patch = FALSE;
2813 * FIXME: Add support for thunks
2816 gboolean near_call = FALSE;
2819 * Indirect calls are expensive so try to make a near call if possible.
2820 * The caller memory is allocated by the code manager so it is
2821 * guaranteed to be at a 32 bit offset.
2824 if (patch_type != MONO_PATCH_INFO_ABS) {
2825 /* The target is in memory allocated using the code manager */
2828 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2829 if (((MonoMethod*)data)->klass->image->aot_module)
2830 /* The callee might be an AOT method */
2832 if (((MonoMethod*)data)->dynamic)
2833 /* The target is in malloc-ed memory */
2837 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2839 * The call might go directly to a native function without
2842 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2844 gconstpointer target = mono_icall_get_wrapper (mi);
2845 if ((((guint64)target) >> 32) != 0)
2851 MonoJumpInfo *jinfo = NULL;
2853 if (cfg->abs_patches)
2854 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2856 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2857 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2858 if (mi && (((guint64)mi->func) >> 32) == 0)
2863 * This is not really an optimization, but required because the
2864 * generic class init trampolines use R11 to pass the vtable.
2869 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2871 if (info->func == info->wrapper) {
2873 if ((((guint64)info->func) >> 32) == 0)
2877 /* See the comment in mono_codegen () */
2878 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2882 else if ((((guint64)data) >> 32) == 0) {
2889 if (cfg->method->dynamic)
2890 /* These methods are allocated using malloc */
2893 #ifdef MONO_ARCH_NOMAP32BIT
2896 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2897 if (optimize_for_xen)
2900 if (cfg->compile_aot) {
2907 * Align the call displacement to an address divisible by 4 so it does
2908 * not span cache lines. This is required for code patching to work on SMP
2911 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2912 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2913 amd64_padding (code, pad_size);
2915 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2916 amd64_call_code (code, 0);
2919 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2920 amd64_set_reg_template (code, GP_SCRATCH_REG);
2921 amd64_call_reg (code, GP_SCRATCH_REG);
2928 static inline guint8*
2929 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2932 if (win64_adjust_stack)
2933 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2935 code = emit_call_body (cfg, code, patch_type, data);
2937 if (win64_adjust_stack)
2938 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2945 store_membase_imm_to_store_membase_reg (int opcode)
2948 case OP_STORE_MEMBASE_IMM:
2949 return OP_STORE_MEMBASE_REG;
2950 case OP_STOREI4_MEMBASE_IMM:
2951 return OP_STOREI4_MEMBASE_REG;
2952 case OP_STOREI8_MEMBASE_IMM:
2953 return OP_STOREI8_MEMBASE_REG;
2961 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2964 * mono_arch_peephole_pass_1:
2966 * Perform peephole opts which should/can be performed before local regalloc
2969 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2973 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2974 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2976 switch (ins->opcode) {
2980 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2982 * X86_LEA is like ADD, but doesn't have the
2983 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2984 * its operand to 64 bit.
2986 ins->opcode = OP_X86_LEA_MEMBASE;
2987 ins->inst_basereg = ins->sreg1;
2992 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2996 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2997 * the latter has length 2-3 instead of 6 (reverse constant
2998 * propagation). These instruction sequences are very common
2999 * in the initlocals bblock.
3001 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3002 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3003 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3004 ins2->sreg1 = ins->dreg;
3005 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3007 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3010 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3018 case OP_COMPARE_IMM:
3019 case OP_LCOMPARE_IMM:
3020 /* OP_COMPARE_IMM (reg, 0)
3022 * OP_AMD64_TEST_NULL (reg)
3025 ins->opcode = OP_AMD64_TEST_NULL;
3027 case OP_ICOMPARE_IMM:
3029 ins->opcode = OP_X86_TEST_NULL;
3031 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3033 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3034 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3036 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3037 * OP_COMPARE_IMM reg, imm
3039 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3041 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3042 ins->inst_basereg == last_ins->inst_destbasereg &&
3043 ins->inst_offset == last_ins->inst_offset) {
3044 ins->opcode = OP_ICOMPARE_IMM;
3045 ins->sreg1 = last_ins->sreg1;
3047 /* check if we can remove cmp reg,0 with test null */
3049 ins->opcode = OP_X86_TEST_NULL;
3055 mono_peephole_ins (bb, ins);
3060 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3064 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3065 switch (ins->opcode) {
3068 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3069 /* reg = 0 -> XOR (reg, reg) */
3070 /* XOR sets cflags on x86, so we cant do it always */
3071 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3072 ins->opcode = OP_LXOR;
3073 ins->sreg1 = ins->dreg;
3074 ins->sreg2 = ins->dreg;
3082 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3083 * 0 result into 64 bits.
3085 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3086 ins->opcode = OP_IXOR;
3090 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3094 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3095 * the latter has length 2-3 instead of 6 (reverse constant
3096 * propagation). These instruction sequences are very common
3097 * in the initlocals bblock.
3099 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3100 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3101 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3102 ins2->sreg1 = ins->dreg;
3103 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3105 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3108 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3117 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3118 ins->opcode = OP_X86_INC_REG;
3121 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3122 ins->opcode = OP_X86_DEC_REG;
3126 mono_peephole_ins (bb, ins);
3130 #define NEW_INS(cfg,ins,dest,op) do { \
3131 MONO_INST_NEW ((cfg), (dest), (op)); \
3132 (dest)->cil_code = (ins)->cil_code; \
3133 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3137 * mono_arch_lowering_pass:
3139 * Converts complex opcodes into simpler ones so that each IR instruction
3140 * corresponds to one machine instruction.
3143 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3145 MonoInst *ins, *n, *temp;
3148 * FIXME: Need to add more instructions, but the current machine
3149 * description can't model some parts of the composite instructions like
3152 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3153 switch (ins->opcode) {
3157 case OP_IDIV_UN_IMM:
3158 case OP_IREM_UN_IMM:
3161 mono_decompose_op_imm (cfg, bb, ins);
3163 case OP_COMPARE_IMM:
3164 case OP_LCOMPARE_IMM:
3165 if (!amd64_use_imm32 (ins->inst_imm)) {
3166 NEW_INS (cfg, ins, temp, OP_I8CONST);
3167 temp->inst_c0 = ins->inst_imm;
3168 temp->dreg = mono_alloc_ireg (cfg);
3169 ins->opcode = OP_COMPARE;
3170 ins->sreg2 = temp->dreg;
3173 #ifndef __mono_ilp32__
3174 case OP_LOAD_MEMBASE:
3176 case OP_LOADI8_MEMBASE:
3177 /* Don't generate memindex opcodes (to simplify */
3178 /* read sandboxing) */
3179 if (!amd64_use_imm32 (ins->inst_offset)) {
3180 NEW_INS (cfg, ins, temp, OP_I8CONST);
3181 temp->inst_c0 = ins->inst_offset;
3182 temp->dreg = mono_alloc_ireg (cfg);
3183 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3184 ins->inst_indexreg = temp->dreg;
3187 #ifndef __mono_ilp32__
3188 case OP_STORE_MEMBASE_IMM:
3190 case OP_STOREI8_MEMBASE_IMM:
3191 if (!amd64_use_imm32 (ins->inst_imm)) {
3192 NEW_INS (cfg, ins, temp, OP_I8CONST);
3193 temp->inst_c0 = ins->inst_imm;
3194 temp->dreg = mono_alloc_ireg (cfg);
3195 ins->opcode = OP_STOREI8_MEMBASE_REG;
3196 ins->sreg1 = temp->dreg;
3199 #ifdef MONO_ARCH_SIMD_INTRINSICS
3200 case OP_EXPAND_I1: {
3201 int temp_reg1 = mono_alloc_ireg (cfg);
3202 int temp_reg2 = mono_alloc_ireg (cfg);
3203 int original_reg = ins->sreg1;
3205 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3206 temp->sreg1 = original_reg;
3207 temp->dreg = temp_reg1;
3209 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3210 temp->sreg1 = temp_reg1;
3211 temp->dreg = temp_reg2;
3214 NEW_INS (cfg, ins, temp, OP_LOR);
3215 temp->sreg1 = temp->dreg = temp_reg2;
3216 temp->sreg2 = temp_reg1;
3218 ins->opcode = OP_EXPAND_I2;
3219 ins->sreg1 = temp_reg2;
3228 bb->max_vreg = cfg->next_vreg;
3232 branch_cc_table [] = {
3233 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3234 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3235 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3238 /* Maps CMP_... constants to X86_CC_... constants */
3241 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3242 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3246 cc_signed_table [] = {
3247 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3248 FALSE, FALSE, FALSE, FALSE
3251 /*#include "cprop.c"*/
3253 static unsigned char*
3254 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3257 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3259 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3262 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3264 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3268 static unsigned char*
3269 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3271 int sreg = tree->sreg1;
3272 int need_touch = FALSE;
3274 #if defined(TARGET_WIN32)
3276 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3277 if (!tree->flags & MONO_INST_INIT)
3286 * If requested stack size is larger than one page,
3287 * perform stack-touch operation
3290 * Generate stack probe code.
3291 * Under Windows, it is necessary to allocate one page at a time,
3292 * "touching" stack after each successful sub-allocation. This is
3293 * because of the way stack growth is implemented - there is a
3294 * guard page before the lowest stack page that is currently commited.
3295 * Stack normally grows sequentially so OS traps access to the
3296 * guard page and commits more pages when needed.
3298 amd64_test_reg_imm (code, sreg, ~0xFFF);
3299 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3301 br[2] = code; /* loop */
3302 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3303 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3304 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3305 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3306 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3307 amd64_patch (br[3], br[2]);
3308 amd64_test_reg_reg (code, sreg, sreg);
3309 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3310 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3312 br[1] = code; x86_jump8 (code, 0);
3314 amd64_patch (br[0], code);
3315 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3316 amd64_patch (br[1], code);
3317 amd64_patch (br[4], code);
3320 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3322 if (tree->flags & MONO_INST_INIT) {
3324 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3325 amd64_push_reg (code, AMD64_RAX);
3328 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3329 amd64_push_reg (code, AMD64_RCX);
3332 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3333 amd64_push_reg (code, AMD64_RDI);
3337 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3338 if (sreg != AMD64_RCX)
3339 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3340 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3342 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3343 if (cfg->param_area)
3344 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3346 amd64_prefix (code, X86_REP_PREFIX);
3349 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3350 amd64_pop_reg (code, AMD64_RDI);
3351 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3352 amd64_pop_reg (code, AMD64_RCX);
3353 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3354 amd64_pop_reg (code, AMD64_RAX);
3360 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3365 /* Move return value to the target register */
3366 /* FIXME: do this in the local reg allocator */
3367 switch (ins->opcode) {
3370 case OP_CALL_MEMBASE:
3373 case OP_LCALL_MEMBASE:
3374 g_assert (ins->dreg == AMD64_RAX);
3378 case OP_FCALL_MEMBASE: {
3379 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3380 if (rtype->type == MONO_TYPE_R4) {
3381 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3384 if (ins->dreg != AMD64_XMM0)
3385 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3391 case OP_RCALL_MEMBASE:
3392 if (ins->dreg != AMD64_XMM0)
3393 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3397 case OP_VCALL_MEMBASE:
3400 case OP_VCALL2_MEMBASE:
3401 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3402 if (cinfo->ret.storage == ArgValuetypeInReg) {
3403 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3405 /* Load the destination address */
3406 g_assert (loc->opcode == OP_REGOFFSET);
3407 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3409 for (quad = 0; quad < 2; quad ++) {
3410 switch (cinfo->ret.pair_storage [quad]) {
3412 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3414 case ArgInFloatSSEReg:
3415 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3417 case ArgInDoubleSSEReg:
3418 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3433 #endif /* DISABLE_JIT */
3436 static int tls_gs_offset;
3440 mono_amd64_have_tls_get (void)
3443 static gboolean have_tls_get = FALSE;
3444 static gboolean inited = FALSE;
3447 return have_tls_get;
3449 #if MONO_HAVE_FAST_TLS
3450 guint8 *ins = (guint8*)pthread_getspecific;
3453 * We're looking for these two instructions:
3455 * mov %gs:[offset](,%rdi,8),%rax
3458 have_tls_get = ins [0] == 0x65 &&
3468 tls_gs_offset = ins[5];
3471 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3472 * For that version we're looking for these instructions:
3476 * mov %gs:[offset](,%rdi,8),%rax
3480 if (!have_tls_get) {
3481 have_tls_get = ins [0] == 0x55 &&
3496 tls_gs_offset = ins[9];
3502 return have_tls_get;
3503 #elif defined(TARGET_ANDROID)
3511 mono_amd64_get_tls_gs_offset (void)
3514 return tls_gs_offset;
3516 g_assert_not_reached ();
3522 * mono_amd64_emit_tls_get:
3523 * @code: buffer to store code to
3524 * @dreg: hard register where to place the result
3525 * @tls_offset: offset info
3527 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3528 * the dreg register the item in the thread local storage identified
3531 * Returns: a pointer to the end of the stored code
3534 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3537 if (tls_offset < 64) {
3538 x86_prefix (code, X86_GS_PREFIX);
3539 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3543 g_assert (tls_offset < 0x440);
3544 /* Load TEB->TlsExpansionSlots */
3545 x86_prefix (code, X86_GS_PREFIX);
3546 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3547 amd64_test_reg_reg (code, dreg, dreg);
3549 amd64_branch (code, X86_CC_EQ, code, TRUE);
3550 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3551 amd64_patch (buf [0], code);
3553 #elif defined(__APPLE__)
3554 x86_prefix (code, X86_GS_PREFIX);
3555 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3557 if (optimize_for_xen) {
3558 x86_prefix (code, X86_FS_PREFIX);
3559 amd64_mov_reg_mem (code, dreg, 0, 8);
3560 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3562 x86_prefix (code, X86_FS_PREFIX);
3563 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3571 #define MAX_TEB_TLS_SLOTS 64
3572 #define TEB_TLS_SLOTS_OFFSET 0x1480
3573 #define TEB_TLS_EXPANSION_SLOTS_OFFSET 0x1780
3576 emit_tls_get_reg_windows (guint8* code, int dreg, int offset_reg)
3579 guint8 * more_than_64_slots = NULL;
3580 guint8 * empty_slot = NULL;
3581 guint8 * tls_get_reg_done = NULL;
3583 //Use temporary register for offset calculation?
3584 if (dreg == offset_reg) {
3585 tmp_reg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3586 amd64_push_reg (code, tmp_reg);
3587 amd64_mov_reg_reg (code, tmp_reg, offset_reg, sizeof (gpointer));
3588 offset_reg = tmp_reg;
3591 //TEB TLS slot array only contains MAX_TEB_TLS_SLOTS items, if more is used the expansion slots must be addressed.
3592 amd64_alu_reg_imm (code, X86_CMP, offset_reg, MAX_TEB_TLS_SLOTS);
3593 more_than_64_slots = code;
3594 amd64_branch8 (code, X86_CC_GE, 0, TRUE);
3596 //TLS slot array, _TEB.TlsSlots, is at offset TEB_TLS_SLOTS_OFFSET and index is offset * 8 in Windows 64-bit _TEB structure.
3597 amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3598 amd64_alu_reg_imm (code, X86_ADD, offset_reg, TEB_TLS_SLOTS_OFFSET);
3600 //TEB pointer is stored in GS segment register on Windows x64. TLS slot is located at calculated offset from that pointer.
3601 x86_prefix (code, X86_GS_PREFIX);
3602 amd64_mov_reg_membase (code, dreg, offset_reg, 0, sizeof (gpointer));
3604 tls_get_reg_done = code;
3605 amd64_jump8 (code, 0);
3607 amd64_patch (more_than_64_slots, code);
3609 //TLS expansion slots, _TEB.TlsExpansionSlots, is at offset TEB_TLS_EXPANSION_SLOTS_OFFSET in Windows 64-bit _TEB structure.
3610 x86_prefix (code, X86_GS_PREFIX);
3611 amd64_mov_reg_mem (code, dreg, TEB_TLS_EXPANSION_SLOTS_OFFSET, sizeof (gpointer));
3613 //Check for NULL in _TEB.TlsExpansionSlots.
3614 amd64_test_reg_reg (code, dreg, dreg);
3616 amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
3618 //TLS expansion slots are at index offset into the expansion array.
3619 //Calculate for the MAX_TEB_TLS_SLOTS offsets, since the interessting offset is offset_reg - MAX_TEB_TLS_SLOTS.
3620 amd64_alu_reg_imm (code, X86_SUB, offset_reg, MAX_TEB_TLS_SLOTS);
3621 amd64_shift_reg_imm (code, X86_SHL, offset_reg, 3);
3623 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, sizeof (gpointer));
3625 amd64_patch (empty_slot, code);
3626 amd64_patch (tls_get_reg_done, code);
3629 amd64_pop_reg (code, tmp_reg);
3637 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3639 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3641 if (dreg != offset_reg)
3642 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3643 amd64_prefix (code, X86_GS_PREFIX);
3644 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3645 #elif defined(__linux__)
3648 if (dreg == offset_reg) {
3649 /* Use a temporary reg by saving it to the redzone */
3650 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3651 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3652 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3653 offset_reg = tmpreg;
3655 x86_prefix (code, X86_FS_PREFIX);
3656 amd64_mov_reg_mem (code, dreg, 0, 8);
3657 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3659 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3660 #elif defined(TARGET_WIN32)
3661 code = emit_tls_get_reg_windows (code, dreg, offset_reg);
3663 g_assert_not_reached ();
3669 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3672 g_assert_not_reached ();
3673 #elif defined(__APPLE__)
3674 x86_prefix (code, X86_GS_PREFIX);
3675 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3677 g_assert (!optimize_for_xen);
3678 x86_prefix (code, X86_FS_PREFIX);
3679 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3685 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3687 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3689 g_assert_not_reached ();
3690 #elif defined(__APPLE__)
3691 x86_prefix (code, X86_GS_PREFIX);
3692 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3694 x86_prefix (code, X86_FS_PREFIX);
3695 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3701 * mono_arch_translate_tls_offset:
3703 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3706 mono_arch_translate_tls_offset (int offset)
3709 return tls_gs_offset + (offset * 8);
3718 * Emit code to initialize an LMF structure at LMF_OFFSET.
3721 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3724 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3727 * sp is saved right before calls but we need to save it here too so
3728 * async stack walks would work.
3730 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3732 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3733 if (cfg->arch.omit_fp && cfa_offset != -1)
3734 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3736 /* These can't contain refs */
3737 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3738 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3739 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3740 /* These are handled automatically by the stack marking code */
3741 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3748 #define TEB_LAST_ERROR_OFFSET 0x068
3751 emit_get_last_error (guint8* code, int dreg)
3753 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3754 x86_prefix (code, X86_GS_PREFIX);
3755 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3763 emit_get_last_error (guint8* code, int dreg)
3765 g_assert_not_reached ();
3770 /* benchmark and set based on cpu */
3771 #define LOOP_ALIGNMENT 8
3772 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3776 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3781 guint8 *code = cfg->native_code + cfg->code_len;
3784 /* Fix max_offset estimate for each successor bb */
3785 if (cfg->opt & MONO_OPT_BRANCH) {
3786 int current_offset = cfg->code_len;
3787 MonoBasicBlock *current_bb;
3788 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3789 current_bb->max_offset = current_offset;
3790 current_offset += current_bb->max_length;
3794 if (cfg->opt & MONO_OPT_LOOP) {
3795 int pad, align = LOOP_ALIGNMENT;
3796 /* set alignment depending on cpu */
3797 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3799 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3800 amd64_padding (code, pad);
3801 cfg->code_len += pad;
3802 bb->native_offset = cfg->code_len;
3806 if (cfg->verbose_level > 2)
3807 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3809 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3810 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3811 g_assert (!cfg->compile_aot);
3813 cov->data [bb->dfn].cil_code = bb->cil_code;
3814 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3815 /* this is not thread save, but good enough */
3816 amd64_inc_membase (code, AMD64_R11, 0);
3819 offset = code - cfg->native_code;
3821 mono_debug_open_block (cfg, bb, offset);
3823 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3824 x86_breakpoint (code);
3826 MONO_BB_FOR_EACH_INS (bb, ins) {
3827 offset = code - cfg->native_code;
3829 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3831 #define EXTRA_CODE_SPACE (16)
3833 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3834 cfg->code_size *= 2;
3835 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3836 code = cfg->native_code + offset;
3837 cfg->stat_code_reallocs++;
3840 if (cfg->debug_info)
3841 mono_debug_record_line_number (cfg, ins, offset);
3843 switch (ins->opcode) {
3845 amd64_mul_reg (code, ins->sreg2, TRUE);
3848 amd64_mul_reg (code, ins->sreg2, FALSE);
3850 case OP_X86_SETEQ_MEMBASE:
3851 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3853 case OP_STOREI1_MEMBASE_IMM:
3854 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3856 case OP_STOREI2_MEMBASE_IMM:
3857 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3859 case OP_STOREI4_MEMBASE_IMM:
3860 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3862 case OP_STOREI1_MEMBASE_REG:
3863 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3865 case OP_STOREI2_MEMBASE_REG:
3866 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3868 /* In AMD64 NaCl, pointers are 4 bytes, */
3869 /* so STORE_* != STOREI8_*. Likewise below. */
3870 case OP_STORE_MEMBASE_REG:
3871 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3873 case OP_STOREI8_MEMBASE_REG:
3874 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3876 case OP_STOREI4_MEMBASE_REG:
3877 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3879 case OP_STORE_MEMBASE_IMM:
3880 /* In NaCl, this could be a PCONST type, which could */
3881 /* mean a pointer type was copied directly into the */
3882 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3883 /* the value would be 0x00000000FFFFFFFF which is */
3884 /* not proper for an imm32 unless you cast it. */
3885 g_assert (amd64_is_imm32 (ins->inst_imm));
3886 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3888 case OP_STOREI8_MEMBASE_IMM:
3889 g_assert (amd64_is_imm32 (ins->inst_imm));
3890 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3893 #ifdef __mono_ilp32__
3894 /* In ILP32, pointers are 4 bytes, so separate these */
3895 /* cases, use literal 8 below where we really want 8 */
3896 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3897 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3901 // FIXME: Decompose this earlier
3902 if (amd64_use_imm32 (ins->inst_imm))
3903 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3905 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3906 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3910 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3911 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3914 // FIXME: Decompose this earlier
3915 if (amd64_use_imm32 (ins->inst_imm))
3916 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3918 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3919 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3923 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3924 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3927 /* For NaCl, pointers are 4 bytes, so separate these */
3928 /* cases, use literal 8 below where we really want 8 */
3929 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3930 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3932 case OP_LOAD_MEMBASE:
3933 g_assert (amd64_is_imm32 (ins->inst_offset));
3934 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3936 case OP_LOADI8_MEMBASE:
3937 /* Use literal 8 instead of sizeof pointer or */
3938 /* register, we really want 8 for this opcode */
3939 g_assert (amd64_is_imm32 (ins->inst_offset));
3940 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3942 case OP_LOADI4_MEMBASE:
3943 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3945 case OP_LOADU4_MEMBASE:
3946 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3948 case OP_LOADU1_MEMBASE:
3949 /* The cpu zero extends the result into 64 bits */
3950 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3952 case OP_LOADI1_MEMBASE:
3953 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3955 case OP_LOADU2_MEMBASE:
3956 /* The cpu zero extends the result into 64 bits */
3957 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3959 case OP_LOADI2_MEMBASE:
3960 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3962 case OP_AMD64_LOADI8_MEMINDEX:
3963 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3965 case OP_LCONV_TO_I1:
3966 case OP_ICONV_TO_I1:
3968 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3970 case OP_LCONV_TO_I2:
3971 case OP_ICONV_TO_I2:
3973 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3975 case OP_LCONV_TO_U1:
3976 case OP_ICONV_TO_U1:
3977 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3979 case OP_LCONV_TO_U2:
3980 case OP_ICONV_TO_U2:
3981 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3984 /* Clean out the upper word */
3985 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3988 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3992 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3994 case OP_COMPARE_IMM:
3995 #if defined(__mono_ilp32__)
3996 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3997 g_assert (amd64_is_imm32 (ins->inst_imm));
3998 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4001 case OP_LCOMPARE_IMM:
4002 g_assert (amd64_is_imm32 (ins->inst_imm));
4003 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4005 case OP_X86_COMPARE_REG_MEMBASE:
4006 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4008 case OP_X86_TEST_NULL:
4009 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4011 case OP_AMD64_TEST_NULL:
4012 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4015 case OP_X86_ADD_REG_MEMBASE:
4016 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4018 case OP_X86_SUB_REG_MEMBASE:
4019 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4021 case OP_X86_AND_REG_MEMBASE:
4022 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4024 case OP_X86_OR_REG_MEMBASE:
4025 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4027 case OP_X86_XOR_REG_MEMBASE:
4028 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4031 case OP_X86_ADD_MEMBASE_IMM:
4032 /* FIXME: Make a 64 version too */
4033 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4035 case OP_X86_SUB_MEMBASE_IMM:
4036 g_assert (amd64_is_imm32 (ins->inst_imm));
4037 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4039 case OP_X86_AND_MEMBASE_IMM:
4040 g_assert (amd64_is_imm32 (ins->inst_imm));
4041 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4043 case OP_X86_OR_MEMBASE_IMM:
4044 g_assert (amd64_is_imm32 (ins->inst_imm));
4045 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4047 case OP_X86_XOR_MEMBASE_IMM:
4048 g_assert (amd64_is_imm32 (ins->inst_imm));
4049 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4051 case OP_X86_ADD_MEMBASE_REG:
4052 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4054 case OP_X86_SUB_MEMBASE_REG:
4055 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4057 case OP_X86_AND_MEMBASE_REG:
4058 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4060 case OP_X86_OR_MEMBASE_REG:
4061 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4063 case OP_X86_XOR_MEMBASE_REG:
4064 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4066 case OP_X86_INC_MEMBASE:
4067 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4069 case OP_X86_INC_REG:
4070 amd64_inc_reg_size (code, ins->dreg, 4);
4072 case OP_X86_DEC_MEMBASE:
4073 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4075 case OP_X86_DEC_REG:
4076 amd64_dec_reg_size (code, ins->dreg, 4);
4078 case OP_X86_MUL_REG_MEMBASE:
4079 case OP_X86_MUL_MEMBASE_REG:
4080 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4082 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4083 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4085 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4086 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4088 case OP_AMD64_COMPARE_MEMBASE_REG:
4089 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4091 case OP_AMD64_COMPARE_MEMBASE_IMM:
4092 g_assert (amd64_is_imm32 (ins->inst_imm));
4093 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4095 case OP_X86_COMPARE_MEMBASE8_IMM:
4096 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4098 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4099 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4101 case OP_AMD64_COMPARE_REG_MEMBASE:
4102 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4105 case OP_AMD64_ADD_REG_MEMBASE:
4106 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4108 case OP_AMD64_SUB_REG_MEMBASE:
4109 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4111 case OP_AMD64_AND_REG_MEMBASE:
4112 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4114 case OP_AMD64_OR_REG_MEMBASE:
4115 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4117 case OP_AMD64_XOR_REG_MEMBASE:
4118 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4121 case OP_AMD64_ADD_MEMBASE_REG:
4122 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4124 case OP_AMD64_SUB_MEMBASE_REG:
4125 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4127 case OP_AMD64_AND_MEMBASE_REG:
4128 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4130 case OP_AMD64_OR_MEMBASE_REG:
4131 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4133 case OP_AMD64_XOR_MEMBASE_REG:
4134 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4137 case OP_AMD64_ADD_MEMBASE_IMM:
4138 g_assert (amd64_is_imm32 (ins->inst_imm));
4139 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4141 case OP_AMD64_SUB_MEMBASE_IMM:
4142 g_assert (amd64_is_imm32 (ins->inst_imm));
4143 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4145 case OP_AMD64_AND_MEMBASE_IMM:
4146 g_assert (amd64_is_imm32 (ins->inst_imm));
4147 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4149 case OP_AMD64_OR_MEMBASE_IMM:
4150 g_assert (amd64_is_imm32 (ins->inst_imm));
4151 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4153 case OP_AMD64_XOR_MEMBASE_IMM:
4154 g_assert (amd64_is_imm32 (ins->inst_imm));
4155 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4159 amd64_breakpoint (code);
4161 case OP_RELAXED_NOP:
4162 x86_prefix (code, X86_REP_PREFIX);
4170 case OP_DUMMY_STORE:
4171 case OP_DUMMY_ICONST:
4172 case OP_DUMMY_R8CONST:
4173 case OP_NOT_REACHED:
4176 case OP_IL_SEQ_POINT:
4177 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4179 case OP_SEQ_POINT: {
4180 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4181 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4184 /* Load ss_tramp_var */
4185 /* This is equal to &ss_trampoline */
4186 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4187 /* Load the trampoline address */
4188 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4189 /* Call it if it is non-null */
4190 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4192 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4193 amd64_call_reg (code, AMD64_R11);
4194 amd64_patch (label, code);
4198 * This is the address which is saved in seq points,
4200 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4202 if (cfg->compile_aot) {
4203 guint32 offset = code - cfg->native_code;
4205 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4209 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4210 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4211 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4212 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4213 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4215 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4216 /* Call the trampoline */
4217 amd64_call_reg (code, AMD64_R11);
4218 amd64_patch (label, code);
4220 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4224 * Emit a test+branch against a constant, the constant will be overwritten
4225 * by mono_arch_set_breakpoint () to cause the test to fail.
4227 amd64_mov_reg_imm (code, AMD64_R11, 0);
4228 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4230 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4233 g_assert (var->opcode == OP_REGOFFSET);
4234 /* Load bp_tramp_var */
4235 /* This is equal to &bp_trampoline */
4236 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4237 /* Call the trampoline */
4238 amd64_call_membase (code, AMD64_R11, 0);
4239 amd64_patch (label, code);
4242 * Add an additional nop so skipping the bp doesn't cause the ip to point
4243 * to another IL offset.
4251 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4254 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4258 g_assert (amd64_is_imm32 (ins->inst_imm));
4259 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4262 g_assert (amd64_is_imm32 (ins->inst_imm));
4263 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4268 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4271 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4275 g_assert (amd64_is_imm32 (ins->inst_imm));
4276 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4279 g_assert (amd64_is_imm32 (ins->inst_imm));
4280 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4283 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4287 g_assert (amd64_is_imm32 (ins->inst_imm));
4288 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4291 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4296 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4298 switch (ins->inst_imm) {
4302 if (ins->dreg != ins->sreg1)
4303 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4304 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4307 /* LEA r1, [r2 + r2*2] */
4308 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4311 /* LEA r1, [r2 + r2*4] */
4312 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4315 /* LEA r1, [r2 + r2*2] */
4317 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4318 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4321 /* LEA r1, [r2 + r2*8] */
4322 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4325 /* LEA r1, [r2 + r2*4] */
4327 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4328 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4331 /* LEA r1, [r2 + r2*2] */
4333 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4334 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4337 /* LEA r1, [r2 + r2*4] */
4338 /* LEA r1, [r1 + r1*4] */
4339 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4340 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4343 /* LEA r1, [r2 + r2*4] */
4345 /* LEA r1, [r1 + r1*4] */
4346 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4347 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4348 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4351 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4358 /* Regalloc magic makes the div/rem cases the same */
4359 if (ins->sreg2 == AMD64_RDX) {
4360 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4362 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4365 amd64_div_reg (code, ins->sreg2, TRUE);
4370 if (ins->sreg2 == AMD64_RDX) {
4371 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4372 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4373 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4375 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4376 amd64_div_reg (code, ins->sreg2, FALSE);
4381 if (ins->sreg2 == AMD64_RDX) {
4382 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4383 amd64_cdq_size (code, 4);
4384 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4386 amd64_cdq_size (code, 4);
4387 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4392 if (ins->sreg2 == AMD64_RDX) {
4393 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4394 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4395 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4397 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4398 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4402 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4403 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4406 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4410 g_assert (amd64_is_imm32 (ins->inst_imm));
4411 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4414 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4418 g_assert (amd64_is_imm32 (ins->inst_imm));
4419 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4422 g_assert (ins->sreg2 == AMD64_RCX);
4423 amd64_shift_reg (code, X86_SHL, ins->dreg);
4426 g_assert (ins->sreg2 == AMD64_RCX);
4427 amd64_shift_reg (code, X86_SAR, ins->dreg);
4431 g_assert (amd64_is_imm32 (ins->inst_imm));
4432 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4435 g_assert (amd64_is_imm32 (ins->inst_imm));
4436 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4438 case OP_LSHR_UN_IMM:
4439 g_assert (amd64_is_imm32 (ins->inst_imm));
4440 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4443 g_assert (ins->sreg2 == AMD64_RCX);
4444 amd64_shift_reg (code, X86_SHR, ins->dreg);
4448 g_assert (amd64_is_imm32 (ins->inst_imm));
4449 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4454 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4457 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4460 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4463 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4467 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4470 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4473 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4476 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4479 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4482 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4485 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4488 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4491 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4494 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4497 amd64_neg_reg_size (code, ins->sreg1, 4);
4500 amd64_not_reg_size (code, ins->sreg1, 4);
4503 g_assert (ins->sreg2 == AMD64_RCX);
4504 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4507 g_assert (ins->sreg2 == AMD64_RCX);
4508 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4511 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4513 case OP_ISHR_UN_IMM:
4514 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4517 g_assert (ins->sreg2 == AMD64_RCX);
4518 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4521 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4524 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4527 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4528 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4530 case OP_IMUL_OVF_UN:
4531 case OP_LMUL_OVF_UN: {
4532 /* the mul operation and the exception check should most likely be split */
4533 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4534 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4535 /*g_assert (ins->sreg2 == X86_EAX);
4536 g_assert (ins->dreg == X86_EAX);*/
4537 if (ins->sreg2 == X86_EAX) {
4538 non_eax_reg = ins->sreg1;
4539 } else if (ins->sreg1 == X86_EAX) {
4540 non_eax_reg = ins->sreg2;
4542 /* no need to save since we're going to store to it anyway */
4543 if (ins->dreg != X86_EAX) {
4545 amd64_push_reg (code, X86_EAX);
4547 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4548 non_eax_reg = ins->sreg2;
4550 if (ins->dreg == X86_EDX) {
4553 amd64_push_reg (code, X86_EAX);
4557 amd64_push_reg (code, X86_EDX);
4559 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4560 /* save before the check since pop and mov don't change the flags */
4561 if (ins->dreg != X86_EAX)
4562 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4564 amd64_pop_reg (code, X86_EDX);
4566 amd64_pop_reg (code, X86_EAX);
4567 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4571 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4573 case OP_ICOMPARE_IMM:
4574 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4596 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4604 case OP_CMOV_INE_UN:
4605 case OP_CMOV_IGE_UN:
4606 case OP_CMOV_IGT_UN:
4607 case OP_CMOV_ILE_UN:
4608 case OP_CMOV_ILT_UN:
4614 case OP_CMOV_LNE_UN:
4615 case OP_CMOV_LGE_UN:
4616 case OP_CMOV_LGT_UN:
4617 case OP_CMOV_LLE_UN:
4618 case OP_CMOV_LLT_UN:
4619 g_assert (ins->dreg == ins->sreg1);
4620 /* This needs to operate on 64 bit values */
4621 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4625 amd64_not_reg (code, ins->sreg1);
4628 amd64_neg_reg (code, ins->sreg1);
4633 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4634 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4636 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4639 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4640 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4643 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4644 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4647 if (ins->dreg != ins->sreg1)
4648 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4650 case OP_AMD64_SET_XMMREG_R4: {
4652 if (ins->dreg != ins->sreg1)
4653 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4655 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4659 case OP_AMD64_SET_XMMREG_R8: {
4660 if (ins->dreg != ins->sreg1)
4661 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4665 MonoCallInst *call = (MonoCallInst*)ins;
4666 int i, save_area_offset;
4668 g_assert (!cfg->method->save_lmf);
4670 /* Restore callee saved registers */
4671 save_area_offset = cfg->arch.reg_save_area_offset;
4672 for (i = 0; i < AMD64_NREG; ++i)
4673 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4674 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4675 save_area_offset += 8;
4678 if (cfg->arch.omit_fp) {
4679 if (cfg->arch.stack_alloc_size)
4680 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4682 if (call->stack_usage)
4685 /* Copy arguments on the stack to our argument area */
4686 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4687 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4688 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4694 offset = code - cfg->native_code;
4695 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4696 if (cfg->compile_aot)
4697 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4699 amd64_set_reg_template (code, AMD64_R11);
4700 amd64_jump_reg (code, AMD64_R11);
4701 ins->flags |= MONO_INST_GC_CALLSITE;
4702 ins->backend.pc_offset = code - cfg->native_code;
4706 /* ensure ins->sreg1 is not NULL */
4707 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4710 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4711 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4721 call = (MonoCallInst*)ins;
4723 * The AMD64 ABI forces callers to know about varargs.
4725 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4726 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4727 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4729 * Since the unmanaged calling convention doesn't contain a
4730 * 'vararg' entry, we have to treat every pinvoke call as a
4731 * potential vararg call.
4735 for (i = 0; i < AMD64_XMM_NREG; ++i)
4736 if (call->used_fregs & (1 << i))
4739 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4741 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4744 if (ins->flags & MONO_INST_HAS_METHOD)
4745 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4747 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4748 ins->flags |= MONO_INST_GC_CALLSITE;
4749 ins->backend.pc_offset = code - cfg->native_code;
4750 code = emit_move_return_value (cfg, ins, code);
4757 case OP_VOIDCALL_REG:
4759 call = (MonoCallInst*)ins;
4761 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4762 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4763 ins->sreg1 = AMD64_R11;
4767 * The AMD64 ABI forces callers to know about varargs.
4769 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4770 if (ins->sreg1 == AMD64_RAX) {
4771 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4772 ins->sreg1 = AMD64_R11;
4774 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4775 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4777 * Since the unmanaged calling convention doesn't contain a
4778 * 'vararg' entry, we have to treat every pinvoke call as a
4779 * potential vararg call.
4783 for (i = 0; i < AMD64_XMM_NREG; ++i)
4784 if (call->used_fregs & (1 << i))
4786 if (ins->sreg1 == AMD64_RAX) {
4787 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4788 ins->sreg1 = AMD64_R11;
4791 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4793 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4796 amd64_call_reg (code, ins->sreg1);
4797 ins->flags |= MONO_INST_GC_CALLSITE;
4798 ins->backend.pc_offset = code - cfg->native_code;
4799 code = emit_move_return_value (cfg, ins, code);
4801 case OP_FCALL_MEMBASE:
4802 case OP_RCALL_MEMBASE:
4803 case OP_LCALL_MEMBASE:
4804 case OP_VCALL_MEMBASE:
4805 case OP_VCALL2_MEMBASE:
4806 case OP_VOIDCALL_MEMBASE:
4807 case OP_CALL_MEMBASE:
4808 call = (MonoCallInst*)ins;
4810 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4811 ins->flags |= MONO_INST_GC_CALLSITE;
4812 ins->backend.pc_offset = code - cfg->native_code;
4813 code = emit_move_return_value (cfg, ins, code);
4817 MonoInst *var = cfg->dyn_call_var;
4820 g_assert (var->opcode == OP_REGOFFSET);
4822 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4823 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4825 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4827 /* Save args buffer */
4828 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4830 /* Set fp arg regs */
4831 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4832 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4834 amd64_branch8 (code, X86_CC_Z, -1, 1);
4835 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4836 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4837 amd64_patch (label, code);
4839 /* Set stack args */
4840 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4841 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4842 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4845 /* Set argument registers */
4846 for (i = 0; i < PARAM_REGS; ++i)
4847 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4850 amd64_call_reg (code, AMD64_R10);
4852 ins->flags |= MONO_INST_GC_CALLSITE;
4853 ins->backend.pc_offset = code - cfg->native_code;
4856 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4857 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4858 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4859 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4862 case OP_AMD64_SAVE_SP_TO_LMF: {
4863 MonoInst *lmf_var = cfg->lmf_var;
4864 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4868 g_assert_not_reached ();
4869 amd64_push_reg (code, ins->sreg1);
4871 case OP_X86_PUSH_IMM:
4872 g_assert_not_reached ();
4873 g_assert (amd64_is_imm32 (ins->inst_imm));
4874 amd64_push_imm (code, ins->inst_imm);
4876 case OP_X86_PUSH_MEMBASE:
4877 g_assert_not_reached ();
4878 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4880 case OP_X86_PUSH_OBJ: {
4881 int size = ALIGN_TO (ins->inst_imm, 8);
4883 g_assert_not_reached ();
4885 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4886 amd64_push_reg (code, AMD64_RDI);
4887 amd64_push_reg (code, AMD64_RSI);
4888 amd64_push_reg (code, AMD64_RCX);
4889 if (ins->inst_offset)
4890 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4892 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4893 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4894 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4896 amd64_prefix (code, X86_REP_PREFIX);
4898 amd64_pop_reg (code, AMD64_RCX);
4899 amd64_pop_reg (code, AMD64_RSI);
4900 amd64_pop_reg (code, AMD64_RDI);
4903 case OP_GENERIC_CLASS_INIT: {
4904 static int byte_offset = -1;
4905 static guint8 bitmask;
4908 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4910 if (byte_offset < 0)
4911 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4913 amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4915 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4917 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4918 ins->flags |= MONO_INST_GC_CALLSITE;
4919 ins->backend.pc_offset = code - cfg->native_code;
4921 x86_patch (jump, code);
4926 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4928 case OP_X86_LEA_MEMBASE:
4929 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4932 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4935 /* keep alignment */
4936 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4937 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4938 code = mono_emit_stack_alloc (cfg, code, ins);
4939 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4940 if (cfg->param_area)
4941 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4943 case OP_LOCALLOC_IMM: {
4944 guint32 size = ins->inst_imm;
4945 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4947 if (ins->flags & MONO_INST_INIT) {
4951 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4952 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4954 for (i = 0; i < size; i += 8)
4955 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4956 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4958 amd64_mov_reg_imm (code, ins->dreg, size);
4959 ins->sreg1 = ins->dreg;
4961 code = mono_emit_stack_alloc (cfg, code, ins);
4962 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4965 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4966 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4968 if (cfg->param_area)
4969 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4973 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4974 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4975 (gpointer)"mono_arch_throw_exception", FALSE);
4976 ins->flags |= MONO_INST_GC_CALLSITE;
4977 ins->backend.pc_offset = code - cfg->native_code;
4981 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4982 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4983 (gpointer)"mono_arch_rethrow_exception", FALSE);
4984 ins->flags |= MONO_INST_GC_CALLSITE;
4985 ins->backend.pc_offset = code - cfg->native_code;
4988 case OP_CALL_HANDLER:
4990 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4991 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4992 amd64_call_imm (code, 0);
4993 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4994 /* Restore stack alignment */
4995 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4997 case OP_START_HANDLER: {
4998 /* Even though we're saving RSP, use sizeof */
4999 /* gpointer because spvar is of type IntPtr */
5000 /* see: mono_create_spvar_for_region */
5001 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5002 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5004 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5005 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5007 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5011 case OP_ENDFINALLY: {
5012 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5013 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5017 case OP_ENDFILTER: {
5018 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5019 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5020 /* The local allocator will put the result into RAX */
5025 if (ins->dreg != AMD64_RAX)
5026 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5029 ins->inst_c0 = code - cfg->native_code;
5032 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5033 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5035 if (ins->inst_target_bb->native_offset) {
5036 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5038 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5039 if ((cfg->opt & MONO_OPT_BRANCH) &&
5040 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5041 x86_jump8 (code, 0);
5043 x86_jump32 (code, 0);
5047 amd64_jump_reg (code, ins->sreg1);
5070 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5071 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5073 case OP_COND_EXC_EQ:
5074 case OP_COND_EXC_NE_UN:
5075 case OP_COND_EXC_LT:
5076 case OP_COND_EXC_LT_UN:
5077 case OP_COND_EXC_GT:
5078 case OP_COND_EXC_GT_UN:
5079 case OP_COND_EXC_GE:
5080 case OP_COND_EXC_GE_UN:
5081 case OP_COND_EXC_LE:
5082 case OP_COND_EXC_LE_UN:
5083 case OP_COND_EXC_IEQ:
5084 case OP_COND_EXC_INE_UN:
5085 case OP_COND_EXC_ILT:
5086 case OP_COND_EXC_ILT_UN:
5087 case OP_COND_EXC_IGT:
5088 case OP_COND_EXC_IGT_UN:
5089 case OP_COND_EXC_IGE:
5090 case OP_COND_EXC_IGE_UN:
5091 case OP_COND_EXC_ILE:
5092 case OP_COND_EXC_ILE_UN:
5093 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5095 case OP_COND_EXC_OV:
5096 case OP_COND_EXC_NO:
5098 case OP_COND_EXC_NC:
5099 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5100 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5102 case OP_COND_EXC_IOV:
5103 case OP_COND_EXC_INO:
5104 case OP_COND_EXC_IC:
5105 case OP_COND_EXC_INC:
5106 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5107 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5110 /* floating point opcodes */
5112 double d = *(double *)ins->inst_p0;
5114 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5115 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5118 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5119 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5124 float f = *(float *)ins->inst_p0;
5126 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5128 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5130 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5133 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5134 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5136 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5140 case OP_STORER8_MEMBASE_REG:
5141 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5143 case OP_LOADR8_MEMBASE:
5144 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5146 case OP_STORER4_MEMBASE_REG:
5148 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5150 /* This requires a double->single conversion */
5151 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5152 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5155 case OP_LOADR4_MEMBASE:
5157 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5159 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5160 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5163 case OP_ICONV_TO_R4:
5165 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5167 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5168 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5171 case OP_ICONV_TO_R8:
5172 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5174 case OP_LCONV_TO_R4:
5176 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5178 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5179 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5182 case OP_LCONV_TO_R8:
5183 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5185 case OP_FCONV_TO_R4:
5187 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5189 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5190 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5193 case OP_FCONV_TO_I1:
5194 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5196 case OP_FCONV_TO_U1:
5197 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5199 case OP_FCONV_TO_I2:
5200 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5202 case OP_FCONV_TO_U2:
5203 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5205 case OP_FCONV_TO_U4:
5206 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5208 case OP_FCONV_TO_I4:
5210 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5212 case OP_FCONV_TO_I8:
5213 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5216 case OP_RCONV_TO_I1:
5217 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5218 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5220 case OP_RCONV_TO_U1:
5221 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5222 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5224 case OP_RCONV_TO_I2:
5225 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5226 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5228 case OP_RCONV_TO_U2:
5229 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5230 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5232 case OP_RCONV_TO_I4:
5233 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5235 case OP_RCONV_TO_U4:
5236 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5238 case OP_RCONV_TO_I8:
5239 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5241 case OP_RCONV_TO_R8:
5242 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5244 case OP_RCONV_TO_R4:
5245 if (ins->dreg != ins->sreg1)
5246 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5249 case OP_LCONV_TO_R_UN: {
5252 /* Based on gcc code */
5253 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5254 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5257 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5258 br [1] = code; x86_jump8 (code, 0);
5259 amd64_patch (br [0], code);
5262 /* Save to the red zone */
5263 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5264 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5265 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5266 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5267 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5268 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5269 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5270 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5271 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5273 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5274 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5275 amd64_patch (br [1], code);
5278 case OP_LCONV_TO_OVF_U4:
5279 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5280 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5281 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5283 case OP_LCONV_TO_OVF_I4_UN:
5284 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5285 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5286 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5289 if (ins->dreg != ins->sreg1)
5290 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5293 if (ins->dreg != ins->sreg1)
5294 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5296 case OP_MOVE_F_TO_I4:
5298 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5300 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5301 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5304 case OP_MOVE_I4_TO_F:
5305 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5307 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5309 case OP_MOVE_F_TO_I8:
5310 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5312 case OP_MOVE_I8_TO_F:
5313 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5316 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5319 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5322 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5325 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5328 static double r8_0 = -0.0;
5330 g_assert (ins->sreg1 == ins->dreg);
5332 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5333 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5337 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5340 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5343 static guint64 d = 0x7fffffffffffffffUL;
5345 g_assert (ins->sreg1 == ins->dreg);
5347 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5348 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5352 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5356 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5359 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5362 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5365 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5368 static float r4_0 = -0.0;
5370 g_assert (ins->sreg1 == ins->dreg);
5372 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5373 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5374 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5379 g_assert (cfg->opt & MONO_OPT_CMOV);
5380 g_assert (ins->dreg == ins->sreg1);
5381 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5382 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5385 g_assert (cfg->opt & MONO_OPT_CMOV);
5386 g_assert (ins->dreg == ins->sreg1);
5387 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5388 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5391 g_assert (cfg->opt & MONO_OPT_CMOV);
5392 g_assert (ins->dreg == ins->sreg1);
5393 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5394 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5397 g_assert (cfg->opt & MONO_OPT_CMOV);
5398 g_assert (ins->dreg == ins->sreg1);
5399 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5400 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5403 g_assert (cfg->opt & MONO_OPT_CMOV);
5404 g_assert (ins->dreg == ins->sreg1);
5405 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5406 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5409 g_assert (cfg->opt & MONO_OPT_CMOV);
5410 g_assert (ins->dreg == ins->sreg1);
5411 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5412 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5415 g_assert (cfg->opt & MONO_OPT_CMOV);
5416 g_assert (ins->dreg == ins->sreg1);
5417 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5418 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5421 g_assert (cfg->opt & MONO_OPT_CMOV);
5422 g_assert (ins->dreg == ins->sreg1);
5423 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5424 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5430 * The two arguments are swapped because the fbranch instructions
5431 * depend on this for the non-sse case to work.
5433 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5437 * FIXME: Get rid of this.
5438 * The two arguments are swapped because the fbranch instructions
5439 * depend on this for the non-sse case to work.
5441 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5445 /* zeroing the register at the start results in
5446 * shorter and faster code (we can also remove the widening op)
5448 guchar *unordered_check;
5450 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5451 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5452 unordered_check = code;
5453 x86_branch8 (code, X86_CC_P, 0, FALSE);
5455 if (ins->opcode == OP_FCEQ) {
5456 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5457 amd64_patch (unordered_check, code);
5459 guchar *jump_to_end;
5460 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5462 x86_jump8 (code, 0);
5463 amd64_patch (unordered_check, code);
5464 amd64_inc_reg (code, ins->dreg);
5465 amd64_patch (jump_to_end, code);
5471 /* zeroing the register at the start results in
5472 * shorter and faster code (we can also remove the widening op)
5474 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5475 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5476 if (ins->opcode == OP_FCLT_UN) {
5477 guchar *unordered_check = code;
5478 guchar *jump_to_end;
5479 x86_branch8 (code, X86_CC_P, 0, FALSE);
5480 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5482 x86_jump8 (code, 0);
5483 amd64_patch (unordered_check, code);
5484 amd64_inc_reg (code, ins->dreg);
5485 amd64_patch (jump_to_end, code);
5487 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5492 guchar *unordered_check;
5493 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5494 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5495 unordered_check = code;
5496 x86_branch8 (code, X86_CC_P, 0, FALSE);
5497 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5498 amd64_patch (unordered_check, code);
5503 /* zeroing the register at the start results in
5504 * shorter and faster code (we can also remove the widening op)
5506 guchar *unordered_check;
5508 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5509 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5510 if (ins->opcode == OP_FCGT) {
5511 unordered_check = code;
5512 x86_branch8 (code, X86_CC_P, 0, FALSE);
5513 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5514 amd64_patch (unordered_check, code);
5516 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5521 guchar *unordered_check;
5522 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5523 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5524 unordered_check = code;
5525 x86_branch8 (code, X86_CC_P, 0, FALSE);
5526 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5527 amd64_patch (unordered_check, code);
5537 gboolean unordered = FALSE;
5539 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5540 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5542 switch (ins->opcode) {
5544 x86_cond = X86_CC_EQ;
5547 x86_cond = X86_CC_LT;
5550 x86_cond = X86_CC_GT;
5553 x86_cond = X86_CC_GT;
5557 x86_cond = X86_CC_LT;
5561 g_assert_not_reached ();
5566 guchar *unordered_check;
5567 guchar *jump_to_end;
5569 unordered_check = code;
5570 x86_branch8 (code, X86_CC_P, 0, FALSE);
5571 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5573 x86_jump8 (code, 0);
5574 amd64_patch (unordered_check, code);
5575 amd64_inc_reg (code, ins->dreg);
5576 amd64_patch (jump_to_end, code);
5578 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5582 case OP_FCLT_MEMBASE:
5583 case OP_FCGT_MEMBASE:
5584 case OP_FCLT_UN_MEMBASE:
5585 case OP_FCGT_UN_MEMBASE:
5586 case OP_FCEQ_MEMBASE: {
5587 guchar *unordered_check, *jump_to_end;
5590 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5591 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5593 switch (ins->opcode) {
5594 case OP_FCEQ_MEMBASE:
5595 x86_cond = X86_CC_EQ;
5597 case OP_FCLT_MEMBASE:
5598 case OP_FCLT_UN_MEMBASE:
5599 x86_cond = X86_CC_LT;
5601 case OP_FCGT_MEMBASE:
5602 case OP_FCGT_UN_MEMBASE:
5603 x86_cond = X86_CC_GT;
5606 g_assert_not_reached ();
5609 unordered_check = code;
5610 x86_branch8 (code, X86_CC_P, 0, FALSE);
5611 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5613 switch (ins->opcode) {
5614 case OP_FCEQ_MEMBASE:
5615 case OP_FCLT_MEMBASE:
5616 case OP_FCGT_MEMBASE:
5617 amd64_patch (unordered_check, code);
5619 case OP_FCLT_UN_MEMBASE:
5620 case OP_FCGT_UN_MEMBASE:
5622 x86_jump8 (code, 0);
5623 amd64_patch (unordered_check, code);
5624 amd64_inc_reg (code, ins->dreg);
5625 amd64_patch (jump_to_end, code);
5633 guchar *jump = code;
5634 x86_branch8 (code, X86_CC_P, 0, TRUE);
5635 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5636 amd64_patch (jump, code);
5640 /* Branch if C013 != 100 */
5641 /* branch if !ZF or (PF|CF) */
5642 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5643 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5644 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5647 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5650 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5651 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5655 if (ins->opcode == OP_FBGT) {
5658 /* skip branch if C1=1 */
5660 x86_branch8 (code, X86_CC_P, 0, FALSE);
5661 /* branch if (C0 | C3) = 1 */
5662 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5663 amd64_patch (br1, code);
5666 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5670 /* Branch if C013 == 100 or 001 */
5673 /* skip branch if C1=1 */
5675 x86_branch8 (code, X86_CC_P, 0, FALSE);
5676 /* branch if (C0 | C3) = 1 */
5677 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5678 amd64_patch (br1, code);
5682 /* Branch if C013 == 000 */
5683 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5686 /* Branch if C013=000 or 100 */
5689 /* skip branch if C1=1 */
5691 x86_branch8 (code, X86_CC_P, 0, FALSE);
5692 /* branch if C0=0 */
5693 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5694 amd64_patch (br1, code);
5698 /* Branch if C013 != 001 */
5699 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5700 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5703 /* Transfer value to the fp stack */
5704 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5705 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5706 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5708 amd64_push_reg (code, AMD64_RAX);
5710 amd64_fnstsw (code);
5711 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5712 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5713 amd64_pop_reg (code, AMD64_RAX);
5714 amd64_fstp (code, 0);
5715 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5716 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5719 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5722 case OP_TLS_GET_REG:
5723 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5726 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5729 case OP_TLS_SET_REG: {
5730 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5733 case OP_MEMORY_BARRIER: {
5734 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5738 case OP_ATOMIC_ADD_I4:
5739 case OP_ATOMIC_ADD_I8: {
5740 int dreg = ins->dreg;
5741 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5743 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5746 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5747 amd64_prefix (code, X86_LOCK_PREFIX);
5748 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5749 /* dreg contains the old value, add with sreg2 value */
5750 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5752 if (ins->dreg != dreg)
5753 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5757 case OP_ATOMIC_EXCHANGE_I4:
5758 case OP_ATOMIC_EXCHANGE_I8: {
5759 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5761 /* LOCK prefix is implied. */
5762 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5763 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5764 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5767 case OP_ATOMIC_CAS_I4:
5768 case OP_ATOMIC_CAS_I8: {
5771 if (ins->opcode == OP_ATOMIC_CAS_I8)
5777 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5778 * an explanation of how this works.
5780 g_assert (ins->sreg3 == AMD64_RAX);
5781 g_assert (ins->sreg1 != AMD64_RAX);
5782 g_assert (ins->sreg1 != ins->sreg2);
5784 amd64_prefix (code, X86_LOCK_PREFIX);
5785 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5787 if (ins->dreg != AMD64_RAX)
5788 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5791 case OP_ATOMIC_LOAD_I1: {
5792 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5795 case OP_ATOMIC_LOAD_U1: {
5796 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5799 case OP_ATOMIC_LOAD_I2: {
5800 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5803 case OP_ATOMIC_LOAD_U2: {
5804 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5807 case OP_ATOMIC_LOAD_I4: {
5808 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5811 case OP_ATOMIC_LOAD_U4:
5812 case OP_ATOMIC_LOAD_I8:
5813 case OP_ATOMIC_LOAD_U8: {
5814 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5817 case OP_ATOMIC_LOAD_R4: {
5818 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5819 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5822 case OP_ATOMIC_LOAD_R8: {
5823 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5826 case OP_ATOMIC_STORE_I1:
5827 case OP_ATOMIC_STORE_U1:
5828 case OP_ATOMIC_STORE_I2:
5829 case OP_ATOMIC_STORE_U2:
5830 case OP_ATOMIC_STORE_I4:
5831 case OP_ATOMIC_STORE_U4:
5832 case OP_ATOMIC_STORE_I8:
5833 case OP_ATOMIC_STORE_U8: {
5836 switch (ins->opcode) {
5837 case OP_ATOMIC_STORE_I1:
5838 case OP_ATOMIC_STORE_U1:
5841 case OP_ATOMIC_STORE_I2:
5842 case OP_ATOMIC_STORE_U2:
5845 case OP_ATOMIC_STORE_I4:
5846 case OP_ATOMIC_STORE_U4:
5849 case OP_ATOMIC_STORE_I8:
5850 case OP_ATOMIC_STORE_U8:
5855 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5857 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5861 case OP_ATOMIC_STORE_R4: {
5862 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5863 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5865 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5869 case OP_ATOMIC_STORE_R8: {
5872 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5876 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5880 case OP_CARD_TABLE_WBARRIER: {
5881 int ptr = ins->sreg1;
5882 int value = ins->sreg2;
5884 int nursery_shift, card_table_shift;
5885 gpointer card_table_mask;
5886 size_t nursery_size;
5888 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5889 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5890 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5892 /*If either point to the stack we can simply avoid the WB. This happens due to
5893 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5895 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5899 * We need one register we can clobber, we choose EDX and make sreg1
5900 * fixed EAX to work around limitations in the local register allocator.
5901 * sreg2 might get allocated to EDX, but that is not a problem since
5902 * we use it before clobbering EDX.
5904 g_assert (ins->sreg1 == AMD64_RAX);
5907 * This is the code we produce:
5910 * edx >>= nursery_shift
5911 * cmp edx, (nursery_start >> nursery_shift)
5914 * edx >>= card_table_shift
5920 if (mono_gc_card_table_nursery_check ()) {
5921 if (value != AMD64_RDX)
5922 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5923 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5924 if (shifted_nursery_start >> 31) {
5926 * The value we need to compare against is 64 bits, so we need
5927 * another spare register. We use RBX, which we save and
5930 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5931 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5932 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5933 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5935 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5937 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5939 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5940 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5941 if (card_table_mask)
5942 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5944 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5945 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5947 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5949 if (mono_gc_card_table_nursery_check ())
5950 x86_patch (br, code);
5953 #ifdef MONO_ARCH_SIMD_INTRINSICS
5954 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5956 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5959 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5962 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5965 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5968 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5971 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5974 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5975 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5978 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5981 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5984 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5987 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5990 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5993 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5996 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5999 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6005 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6008 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6011 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6014 case OP_PSHUFLEW_HIGH:
6015 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6016 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6018 case OP_PSHUFLEW_LOW:
6019 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6020 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6023 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6024 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6027 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6028 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6031 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6032 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6036 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6039 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6042 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6045 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6048 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6051 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6054 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6055 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6058 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6061 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6064 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6067 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6070 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6073 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6076 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6079 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6082 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6085 case OP_EXTRACT_MASK:
6086 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6090 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6093 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6096 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6100 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6103 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6106 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6109 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6113 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6116 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6119 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6122 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6126 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6129 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6132 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6136 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6139 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6142 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6146 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6149 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6153 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6156 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6159 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6163 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6166 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6169 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6173 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6176 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6179 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6182 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6186 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6189 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6192 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6195 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6198 case OP_PSUM_ABS_DIFF:
6199 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6202 case OP_UNPACK_LOWB:
6203 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6205 case OP_UNPACK_LOWW:
6206 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6208 case OP_UNPACK_LOWD:
6209 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6211 case OP_UNPACK_LOWQ:
6212 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6214 case OP_UNPACK_LOWPS:
6215 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6217 case OP_UNPACK_LOWPD:
6218 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6221 case OP_UNPACK_HIGHB:
6222 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6224 case OP_UNPACK_HIGHW:
6225 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6227 case OP_UNPACK_HIGHD:
6228 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6230 case OP_UNPACK_HIGHQ:
6231 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6233 case OP_UNPACK_HIGHPS:
6234 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6236 case OP_UNPACK_HIGHPD:
6237 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6241 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6244 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6247 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6250 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6253 case OP_PADDB_SAT_UN:
6254 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6256 case OP_PSUBB_SAT_UN:
6257 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6259 case OP_PADDW_SAT_UN:
6260 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6262 case OP_PSUBW_SAT_UN:
6263 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6267 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6270 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6273 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6276 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6280 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6283 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6286 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6288 case OP_PMULW_HIGH_UN:
6289 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6292 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6296 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6299 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6303 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6306 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6310 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6313 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6317 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6320 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6324 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6327 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6331 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6334 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6338 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6341 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6344 /*TODO: This is appart of the sse spec but not added
6346 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6349 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6354 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6357 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6360 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6363 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6366 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6369 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6372 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6375 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6378 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6381 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6385 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6388 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6392 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6393 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6395 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6400 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6402 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6403 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6407 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6409 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6410 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6411 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6415 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6417 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6420 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6422 case OP_EXTRACTX_U2:
6423 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6425 case OP_INSERTX_U1_SLOW:
6426 /*sreg1 is the extracted ireg (scratch)
6427 /sreg2 is the to be inserted ireg (scratch)
6428 /dreg is the xreg to receive the value*/
6430 /*clear the bits from the extracted word*/
6431 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6432 /*shift the value to insert if needed*/
6433 if (ins->inst_c0 & 1)
6434 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6435 /*join them together*/
6436 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6437 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6439 case OP_INSERTX_I4_SLOW:
6440 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6441 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6442 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6444 case OP_INSERTX_I8_SLOW:
6445 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6447 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6449 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6452 case OP_INSERTX_R4_SLOW:
6453 switch (ins->inst_c0) {
6456 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6458 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6461 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6463 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6465 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6466 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6469 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6471 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6473 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6474 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6477 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6479 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6481 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6482 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6486 case OP_INSERTX_R8_SLOW:
6488 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6490 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6492 case OP_STOREX_MEMBASE_REG:
6493 case OP_STOREX_MEMBASE:
6494 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6496 case OP_LOADX_MEMBASE:
6497 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6499 case OP_LOADX_ALIGNED_MEMBASE:
6500 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6502 case OP_STOREX_ALIGNED_MEMBASE_REG:
6503 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6505 case OP_STOREX_NTA_MEMBASE_REG:
6506 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6508 case OP_PREFETCH_MEMBASE:
6509 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6513 /*FIXME the peephole pass should have killed this*/
6514 if (ins->dreg != ins->sreg1)
6515 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6518 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6520 case OP_ICONV_TO_R4_RAW:
6521 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6524 case OP_FCONV_TO_R8_X:
6525 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6528 case OP_XCONV_R8_TO_I4:
6529 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6530 switch (ins->backend.source_opcode) {
6531 case OP_FCONV_TO_I1:
6532 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6534 case OP_FCONV_TO_U1:
6535 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6537 case OP_FCONV_TO_I2:
6538 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6540 case OP_FCONV_TO_U2:
6541 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6547 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6548 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6549 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6552 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6553 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6556 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6557 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6561 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6563 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6564 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6566 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6569 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6570 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6573 case OP_LIVERANGE_START: {
6574 if (cfg->verbose_level > 1)
6575 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6576 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6579 case OP_LIVERANGE_END: {
6580 if (cfg->verbose_level > 1)
6581 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6582 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6585 case OP_GC_SAFE_POINT: {
6588 g_assert (mono_threads_is_coop_enabled ());
6590 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6591 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6592 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6593 amd64_patch (br[0], code);
6597 case OP_GC_LIVENESS_DEF:
6598 case OP_GC_LIVENESS_USE:
6599 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6600 ins->backend.pc_offset = code - cfg->native_code;
6602 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6603 ins->backend.pc_offset = code - cfg->native_code;
6604 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6606 case OP_GET_LAST_ERROR:
6607 emit_get_last_error(code, ins->dreg);
6610 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6611 g_assert_not_reached ();
6614 if ((code - cfg->native_code - offset) > max_len) {
6615 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6616 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6617 g_assert_not_reached ();
6621 cfg->code_len = code - cfg->native_code;
6624 #endif /* DISABLE_JIT */
6627 mono_arch_register_lowlevel_calls (void)
6629 /* The signature doesn't matter */
6630 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6634 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6636 unsigned char *ip = ji->ip.i + code;
6639 * Debug code to help track down problems where the target of a near call is
6642 if (amd64_is_near_call (ip)) {
6643 gint64 disp = (guint8*)target - (guint8*)ip;
6645 if (!amd64_is_imm32 (disp)) {
6646 printf ("TYPE: %d\n", ji->type);
6648 case MONO_PATCH_INFO_INTERNAL_METHOD:
6649 printf ("V: %s\n", ji->data.name);
6651 case MONO_PATCH_INFO_METHOD_JUMP:
6652 case MONO_PATCH_INFO_METHOD:
6653 printf ("V: %s\n", ji->data.method->name);
6661 amd64_patch (ip, (gpointer)target);
6667 get_max_epilog_size (MonoCompile *cfg)
6669 int max_epilog_size = 16;
6671 if (cfg->method->save_lmf)
6672 max_epilog_size += 256;
6674 if (mono_jit_trace_calls != NULL)
6675 max_epilog_size += 50;
6677 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6678 max_epilog_size += 50;
6680 max_epilog_size += (AMD64_NREG * 2);
6682 return max_epilog_size;
6686 * This macro is used for testing whenever the unwinder works correctly at every point
6687 * where an async exception can happen.
6689 /* This will generate a SIGSEGV at the given point in the code */
6690 #define async_exc_point(code) do { \
6691 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6692 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6693 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6694 cfg->arch.async_point_count ++; \
6699 mono_arch_emit_prolog (MonoCompile *cfg)
6701 MonoMethod *method = cfg->method;
6703 MonoMethodSignature *sig;
6705 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6708 MonoInst *lmf_var = cfg->lmf_var;
6709 gboolean args_clobbered = FALSE;
6710 gboolean trace = FALSE;
6712 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6714 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6716 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6719 /* Amount of stack space allocated by register saving code */
6722 /* Offset between RSP and the CFA */
6726 * The prolog consists of the following parts:
6728 * - push rbp, mov rbp, rsp
6729 * - save callee saved regs using pushes
6731 * - save rgctx if needed
6732 * - save lmf if needed
6735 * - save rgctx if needed
6736 * - save lmf if needed
6737 * - save callee saved regs using moves
6742 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6743 // IP saved at CFA - 8
6744 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6745 async_exc_point (code);
6746 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6748 if (!cfg->arch.omit_fp) {
6749 amd64_push_reg (code, AMD64_RBP);
6751 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6752 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6753 async_exc_point (code);
6755 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6757 /* These are handled automatically by the stack marking code */
6758 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6760 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6761 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6762 async_exc_point (code);
6764 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6768 /* The param area is always at offset 0 from sp */
6769 /* This needs to be allocated here, since it has to come after the spill area */
6770 if (cfg->param_area) {
6771 if (cfg->arch.omit_fp)
6773 g_assert_not_reached ();
6774 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6777 if (cfg->arch.omit_fp) {
6779 * On enter, the stack is misaligned by the pushing of the return
6780 * address. It is either made aligned by the pushing of %rbp, or by
6783 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6784 if ((alloc_size % 16) == 0) {
6786 /* Mark the padding slot as NOREF */
6787 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6790 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6791 if (cfg->stack_offset != alloc_size) {
6792 /* Mark the padding slot as NOREF */
6793 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6795 cfg->arch.sp_fp_offset = alloc_size;
6799 cfg->arch.stack_alloc_size = alloc_size;
6801 /* Allocate stack frame */
6803 /* See mono_emit_stack_alloc */
6804 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6805 guint32 remaining_size = alloc_size;
6806 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6807 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6808 guint32 offset = code - cfg->native_code;
6809 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6810 while (required_code_size >= (cfg->code_size - offset))
6811 cfg->code_size *= 2;
6812 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6813 code = cfg->native_code + offset;
6814 cfg->stat_code_reallocs++;
6817 while (remaining_size >= 0x1000) {
6818 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6819 if (cfg->arch.omit_fp) {
6820 cfa_offset += 0x1000;
6821 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6823 async_exc_point (code);
6825 if (cfg->arch.omit_fp)
6826 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6829 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6830 remaining_size -= 0x1000;
6832 if (remaining_size) {
6833 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6834 if (cfg->arch.omit_fp) {
6835 cfa_offset += remaining_size;
6836 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6837 async_exc_point (code);
6840 if (cfg->arch.omit_fp)
6841 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6845 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6846 if (cfg->arch.omit_fp) {
6847 cfa_offset += alloc_size;
6848 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6849 async_exc_point (code);
6854 /* Stack alignment check */
6859 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6860 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6861 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6863 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6864 amd64_breakpoint (code);
6865 amd64_patch (buf, code);
6869 if (mini_get_debug_options ()->init_stacks) {
6870 /* Fill the stack frame with a dummy value to force deterministic behavior */
6872 /* Save registers to the red zone */
6873 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6874 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6876 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6877 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6878 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6881 amd64_prefix (code, X86_REP_PREFIX);
6884 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6885 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6889 if (method->save_lmf)
6890 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6892 /* Save callee saved registers */
6893 if (cfg->arch.omit_fp) {
6894 save_area_offset = cfg->arch.reg_save_area_offset;
6895 /* Save caller saved registers after sp is adjusted */
6896 /* The registers are saved at the bottom of the frame */
6897 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6899 /* The registers are saved just below the saved rbp */
6900 save_area_offset = cfg->arch.reg_save_area_offset;
6903 for (i = 0; i < AMD64_NREG; ++i) {
6904 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6905 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6907 if (cfg->arch.omit_fp) {
6908 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6909 /* These are handled automatically by the stack marking code */
6910 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6912 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6916 save_area_offset += 8;
6917 async_exc_point (code);
6921 /* store runtime generic context */
6922 if (cfg->rgctx_var) {
6923 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6924 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6926 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6928 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6929 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6932 /* compute max_length in order to use short forward jumps */
6933 max_epilog_size = get_max_epilog_size (cfg);
6934 if (cfg->opt & MONO_OPT_BRANCH) {
6935 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6939 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6941 /* max alignment for loops */
6942 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6943 max_length += LOOP_ALIGNMENT;
6945 MONO_BB_FOR_EACH_INS (bb, ins) {
6946 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6949 /* Take prolog and epilog instrumentation into account */
6950 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6951 max_length += max_epilog_size;
6953 bb->max_length = max_length;
6957 sig = mono_method_signature (method);
6960 cinfo = (CallInfo *)cfg->arch.cinfo;
6962 if (sig->ret->type != MONO_TYPE_VOID) {
6963 /* Save volatile arguments to the stack */
6964 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6965 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6968 /* Keep this in sync with emit_load_volatile_arguments */
6969 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6970 ArgInfo *ainfo = cinfo->args + i;
6972 ins = cfg->args [i];
6974 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6975 /* Unused arguments */
6978 /* Save volatile arguments to the stack */
6979 if (ins->opcode != OP_REGVAR) {
6980 switch (ainfo->storage) {
6986 if (stack_offset & 0x1)
6988 else if (stack_offset & 0x2)
6990 else if (stack_offset & 0x4)
6995 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6998 * Save the original location of 'this',
6999 * get_generic_info_from_stack_frame () needs this to properly look up
7000 * the argument value during the handling of async exceptions.
7002 if (ins == cfg->args [0]) {
7003 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7004 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7008 case ArgInFloatSSEReg:
7009 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7011 case ArgInDoubleSSEReg:
7012 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7014 case ArgValuetypeInReg:
7015 for (quad = 0; quad < 2; quad ++) {
7016 switch (ainfo->pair_storage [quad]) {
7018 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7020 case ArgInFloatSSEReg:
7021 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7023 case ArgInDoubleSSEReg:
7024 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7029 g_assert_not_reached ();
7033 case ArgValuetypeAddrInIReg:
7034 if (ainfo->pair_storage [0] == ArgInIReg)
7035 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7037 case ArgValuetypeAddrOnStack:
7039 case ArgGSharedVtInReg:
7040 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7046 /* Argument allocated to (non-volatile) register */
7047 switch (ainfo->storage) {
7049 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7052 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7055 g_assert_not_reached ();
7058 if (ins == cfg->args [0]) {
7059 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7060 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7065 if (cfg->method->save_lmf)
7066 args_clobbered = TRUE;
7069 args_clobbered = TRUE;
7070 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7073 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7074 args_clobbered = TRUE;
7077 * Optimize the common case of the first bblock making a call with the same
7078 * arguments as the method. This works because the arguments are still in their
7079 * original argument registers.
7080 * FIXME: Generalize this
7082 if (!args_clobbered) {
7083 MonoBasicBlock *first_bb = cfg->bb_entry;
7085 int filter = FILTER_IL_SEQ_POINT;
7087 next = mono_bb_first_inst (first_bb, filter);
7088 if (!next && first_bb->next_bb) {
7089 first_bb = first_bb->next_bb;
7090 next = mono_bb_first_inst (first_bb, filter);
7093 if (first_bb->in_count > 1)
7096 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7097 ArgInfo *ainfo = cinfo->args + i;
7098 gboolean match = FALSE;
7100 ins = cfg->args [i];
7101 if (ins->opcode != OP_REGVAR) {
7102 switch (ainfo->storage) {
7104 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7105 if (next->dreg == ainfo->reg) {
7109 next->opcode = OP_MOVE;
7110 next->sreg1 = ainfo->reg;
7111 /* Only continue if the instruction doesn't change argument regs */
7112 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7122 /* Argument allocated to (non-volatile) register */
7123 switch (ainfo->storage) {
7125 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7136 next = mono_inst_next (next, filter);
7137 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7144 if (cfg->gen_sdb_seq_points) {
7145 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7147 /* Initialize seq_point_info_var */
7148 if (cfg->compile_aot) {
7149 /* Initialize the variable from a GOT slot */
7150 /* Same as OP_AOTCONST */
7151 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7152 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7153 g_assert (info_var->opcode == OP_REGOFFSET);
7154 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7157 if (cfg->compile_aot) {
7158 /* Initialize ss_tramp_var */
7159 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7160 g_assert (ins->opcode == OP_REGOFFSET);
7162 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7163 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7164 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7166 /* Initialize ss_tramp_var */
7167 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7168 g_assert (ins->opcode == OP_REGOFFSET);
7170 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7171 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7173 /* Initialize bp_tramp_var */
7174 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7175 g_assert (ins->opcode == OP_REGOFFSET);
7177 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7178 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7182 cfg->code_len = code - cfg->native_code;
7184 g_assert (cfg->code_len < cfg->code_size);
7190 mono_arch_emit_epilog (MonoCompile *cfg)
7192 MonoMethod *method = cfg->method;
7195 int max_epilog_size;
7197 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7198 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7200 max_epilog_size = get_max_epilog_size (cfg);
7202 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7203 cfg->code_size *= 2;
7204 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7205 cfg->stat_code_reallocs++;
7207 code = cfg->native_code + cfg->code_len;
7209 cfg->has_unwind_info_for_epilog = TRUE;
7211 /* Mark the start of the epilog */
7212 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7214 /* Save the uwind state which is needed by the out-of-line code */
7215 mono_emit_unwind_op_remember_state (cfg, code);
7217 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7218 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7220 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7222 if (method->save_lmf) {
7223 /* check if we need to restore protection of the stack after a stack overflow */
7224 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7226 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7227 /* we load the value in a separate instruction: this mechanism may be
7228 * used later as a safer way to do thread interruption
7230 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7231 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7233 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7234 /* note that the call trampoline will preserve eax/edx */
7235 x86_call_reg (code, X86_ECX);
7236 x86_patch (patch, code);
7238 /* FIXME: maybe save the jit tls in the prolog */
7240 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7241 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7245 /* Restore callee saved regs */
7246 for (i = 0; i < AMD64_NREG; ++i) {
7247 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7248 /* Restore only used_int_regs, not arch.saved_iregs */
7249 #if defined(MONO_SUPPORT_TASKLETS)
7252 int restore_reg=(cfg->used_int_regs & (1 << i));
7255 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7256 mono_emit_unwind_op_same_value (cfg, code, i);
7257 async_exc_point (code);
7259 save_area_offset += 8;
7263 /* Load returned vtypes into registers if needed */
7264 cinfo = (CallInfo *)cfg->arch.cinfo;
7265 if (cinfo->ret.storage == ArgValuetypeInReg) {
7266 ArgInfo *ainfo = &cinfo->ret;
7267 MonoInst *inst = cfg->ret;
7269 for (quad = 0; quad < 2; quad ++) {
7270 switch (ainfo->pair_storage [quad]) {
7272 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7274 case ArgInFloatSSEReg:
7275 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7277 case ArgInDoubleSSEReg:
7278 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7283 g_assert_not_reached ();
7288 if (cfg->arch.omit_fp) {
7289 if (cfg->arch.stack_alloc_size) {
7290 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7294 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7296 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7297 async_exc_point (code);
7300 /* Restore the unwind state to be the same as before the epilog */
7301 mono_emit_unwind_op_restore_state (cfg, code);
7303 cfg->code_len = code - cfg->native_code;
7305 g_assert (cfg->code_len < cfg->code_size);
7309 mono_arch_emit_exceptions (MonoCompile *cfg)
7311 MonoJumpInfo *patch_info;
7314 MonoClass *exc_classes [16];
7315 guint8 *exc_throw_start [16], *exc_throw_end [16];
7316 guint32 code_size = 0;
7318 /* Compute needed space */
7319 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7320 if (patch_info->type == MONO_PATCH_INFO_EXC)
7322 if (patch_info->type == MONO_PATCH_INFO_R8)
7323 code_size += 8 + 15; /* sizeof (double) + alignment */
7324 if (patch_info->type == MONO_PATCH_INFO_R4)
7325 code_size += 4 + 15; /* sizeof (float) + alignment */
7326 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7327 code_size += 8 + 7; /*sizeof (void*) + alignment */
7330 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7331 cfg->code_size *= 2;
7332 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7333 cfg->stat_code_reallocs++;
7336 code = cfg->native_code + cfg->code_len;
7338 /* add code to raise exceptions */
7340 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7341 switch (patch_info->type) {
7342 case MONO_PATCH_INFO_EXC: {
7343 MonoClass *exc_class;
7347 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7349 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7350 throw_ip = patch_info->ip.i;
7352 //x86_breakpoint (code);
7353 /* Find a throw sequence for the same exception class */
7354 for (i = 0; i < nthrows; ++i)
7355 if (exc_classes [i] == exc_class)
7358 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7359 x86_jump_code (code, exc_throw_start [i]);
7360 patch_info->type = MONO_PATCH_INFO_NONE;
7364 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7368 exc_classes [nthrows] = exc_class;
7369 exc_throw_start [nthrows] = code;
7371 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7373 patch_info->type = MONO_PATCH_INFO_NONE;
7375 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7377 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7382 exc_throw_end [nthrows] = code;
7392 g_assert(code < cfg->native_code + cfg->code_size);
7395 /* Handle relocations with RIP relative addressing */
7396 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7397 gboolean remove = FALSE;
7398 guint8 *orig_code = code;
7400 switch (patch_info->type) {
7401 case MONO_PATCH_INFO_R8:
7402 case MONO_PATCH_INFO_R4: {
7403 guint8 *pos, *patch_pos;
7406 /* The SSE opcodes require a 16 byte alignment */
7407 code = (guint8*)ALIGN_TO (code, 16);
7409 pos = cfg->native_code + patch_info->ip.i;
7410 if (IS_REX (pos [1])) {
7411 patch_pos = pos + 5;
7412 target_pos = code - pos - 9;
7415 patch_pos = pos + 4;
7416 target_pos = code - pos - 8;
7419 if (patch_info->type == MONO_PATCH_INFO_R8) {
7420 *(double*)code = *(double*)patch_info->data.target;
7421 code += sizeof (double);
7423 *(float*)code = *(float*)patch_info->data.target;
7424 code += sizeof (float);
7427 *(guint32*)(patch_pos) = target_pos;
7432 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7435 if (cfg->compile_aot)
7438 /*loading is faster against aligned addresses.*/
7439 code = (guint8*)ALIGN_TO (code, 8);
7440 memset (orig_code, 0, code - orig_code);
7442 pos = cfg->native_code + patch_info->ip.i;
7444 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7445 if (IS_REX (pos [1]))
7446 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7448 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7450 *(gpointer*)code = (gpointer)patch_info->data.target;
7451 code += sizeof (gpointer);
7461 if (patch_info == cfg->patch_info)
7462 cfg->patch_info = patch_info->next;
7466 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7468 tmp->next = patch_info->next;
7471 g_assert (code < cfg->native_code + cfg->code_size);
7474 cfg->code_len = code - cfg->native_code;
7476 g_assert (cfg->code_len < cfg->code_size);
7480 #endif /* DISABLE_JIT */
7483 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7485 guchar *code = (guchar *)p;
7486 MonoMethodSignature *sig;
7488 int i, n, stack_area = 0;
7490 /* Keep this in sync with mono_arch_get_argument_info */
7492 if (enable_arguments) {
7493 /* Allocate a new area on the stack and save arguments there */
7494 sig = mono_method_signature (cfg->method);
7496 n = sig->param_count + sig->hasthis;
7498 stack_area = ALIGN_TO (n * 8, 16);
7500 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7502 for (i = 0; i < n; ++i) {
7503 inst = cfg->args [i];
7505 if (inst->opcode == OP_REGVAR)
7506 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7508 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7509 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7514 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7515 amd64_set_reg_template (code, AMD64_ARG_REG1);
7516 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7517 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7519 if (enable_arguments)
7520 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7534 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7536 guchar *code = (guchar *)p;
7537 int save_mode = SAVE_NONE;
7538 MonoMethod *method = cfg->method;
7539 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7542 switch (ret_type->type) {
7543 case MONO_TYPE_VOID:
7544 /* special case string .ctor icall */
7545 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7546 save_mode = SAVE_EAX;
7548 save_mode = SAVE_NONE;
7552 save_mode = SAVE_EAX;
7556 save_mode = SAVE_XMM;
7558 case MONO_TYPE_GENERICINST:
7559 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7560 save_mode = SAVE_EAX;
7564 case MONO_TYPE_VALUETYPE:
7565 save_mode = SAVE_STRUCT;
7568 save_mode = SAVE_EAX;
7572 /* Save the result and copy it into the proper argument register */
7573 switch (save_mode) {
7575 amd64_push_reg (code, AMD64_RAX);
7577 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7578 if (enable_arguments)
7579 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7583 if (enable_arguments)
7584 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7587 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7588 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7590 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7592 * The result is already in the proper argument register so no copying
7599 g_assert_not_reached ();
7602 /* Set %al since this is a varargs call */
7603 if (save_mode == SAVE_XMM)
7604 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7606 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7608 if (preserve_argument_registers) {
7609 for (i = 0; i < PARAM_REGS; ++i)
7610 amd64_push_reg (code, param_regs [i]);
7613 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7614 amd64_set_reg_template (code, AMD64_ARG_REG1);
7615 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7617 if (preserve_argument_registers) {
7618 for (i = PARAM_REGS - 1; i >= 0; --i)
7619 amd64_pop_reg (code, param_regs [i]);
7622 /* Restore result */
7623 switch (save_mode) {
7625 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7626 amd64_pop_reg (code, AMD64_RAX);
7632 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7633 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7634 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7639 g_assert_not_reached ();
7646 mono_arch_flush_icache (guint8 *code, gint size)
7652 mono_arch_flush_register_windows (void)
7657 mono_arch_is_inst_imm (gint64 imm)
7659 return amd64_use_imm32 (imm);
7663 * Determine whenever the trap whose info is in SIGINFO is caused by
7667 mono_arch_is_int_overflow (void *sigctx, void *info)
7674 mono_sigctx_to_monoctx (sigctx, &ctx);
7676 rip = (guint8*)ctx.gregs [AMD64_RIP];
7678 if (IS_REX (rip [0])) {
7679 reg = amd64_rex_b (rip [0]);
7685 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7687 reg += x86_modrm_rm (rip [1]);
7689 value = ctx.gregs [reg];
7699 mono_arch_get_patch_offset (guint8 *code)
7705 * mono_breakpoint_clean_code:
7707 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7708 * breakpoints in the original code, they are removed in the copy.
7710 * Returns TRUE if no sw breakpoint was present.
7713 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7716 * If method_start is non-NULL we need to perform bound checks, since we access memory
7717 * at code - offset we could go before the start of the method and end up in a different
7718 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7721 if (!method_start || code - offset >= method_start) {
7722 memcpy (buf, code - offset, size);
7724 int diff = code - method_start;
7725 memset (buf, 0, size);
7726 memcpy (buf + offset - diff, method_start, diff + size - offset);
7732 mono_arch_get_this_arg_reg (guint8 *code)
7734 return AMD64_ARG_REG1;
7738 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7740 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7743 #define MAX_ARCH_DELEGATE_PARAMS 10
7746 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7748 guint8 *code, *start;
7749 GSList *unwind_ops = NULL;
7752 unwind_ops = mono_arch_get_cie_program ();
7755 start = code = (guint8 *)mono_global_codeman_reserve (64);
7757 /* Replace the this argument with the target */
7758 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7759 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7760 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7762 g_assert ((code - start) < 64);
7764 start = code = (guint8 *)mono_global_codeman_reserve (64);
7766 if (param_count == 0) {
7767 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7769 /* We have to shift the arguments left */
7770 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7771 for (i = 0; i < param_count; ++i) {
7774 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7776 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7778 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7782 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7784 g_assert ((code - start) < 64);
7787 mono_arch_flush_icache (start, code - start);
7790 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7792 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7793 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7797 if (mono_jit_map_is_enabled ()) {
7800 buff = (char*)"delegate_invoke_has_target";
7802 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7803 mono_emit_jit_tramp (start, code - start, buff);
7807 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7812 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7815 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7817 guint8 *code, *start;
7822 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7825 start = code = (guint8 *)mono_global_codeman_reserve (size);
7827 unwind_ops = mono_arch_get_cie_program ();
7829 /* Replace the this argument with the target */
7830 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7831 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7834 /* Load the IMT reg */
7835 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7838 /* Load the vtable */
7839 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7840 amd64_jump_membase (code, AMD64_RAX, offset);
7841 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7843 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7844 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7845 g_free (tramp_name);
7851 * mono_arch_get_delegate_invoke_impls:
7853 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7857 mono_arch_get_delegate_invoke_impls (void)
7860 MonoTrampInfo *info;
7863 get_delegate_invoke_impl (&info, TRUE, 0);
7864 res = g_slist_prepend (res, info);
7866 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7867 get_delegate_invoke_impl (&info, FALSE, i);
7868 res = g_slist_prepend (res, info);
7871 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7872 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7873 res = g_slist_prepend (res, info);
7876 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7877 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7878 res = g_slist_prepend (res, info);
7879 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7880 res = g_slist_prepend (res, info);
7887 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7889 guint8 *code, *start;
7892 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7895 /* FIXME: Support more cases */
7896 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7900 static guint8* cached = NULL;
7905 if (mono_aot_only) {
7906 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7908 MonoTrampInfo *info;
7909 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7910 mono_tramp_info_register (info, NULL);
7913 mono_memory_barrier ();
7917 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7918 for (i = 0; i < sig->param_count; ++i)
7919 if (!mono_is_regsize_var (sig->params [i]))
7921 if (sig->param_count > 4)
7924 code = cache [sig->param_count];
7928 if (mono_aot_only) {
7929 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7930 start = (guint8 *)mono_aot_get_trampoline (name);
7933 MonoTrampInfo *info;
7934 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7935 mono_tramp_info_register (info, NULL);
7938 mono_memory_barrier ();
7940 cache [sig->param_count] = start;
7947 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7949 MonoTrampInfo *info;
7952 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7954 mono_tramp_info_register (info, NULL);
7959 mono_arch_finish_init (void)
7961 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7962 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7967 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7971 #define CMP_SIZE (6 + 1)
7972 #define CMP_REG_REG_SIZE (4 + 1)
7973 #define BR_SMALL_SIZE 2
7974 #define BR_LARGE_SIZE 6
7975 #define MOV_REG_IMM_SIZE 10
7976 #define MOV_REG_IMM_32BIT_SIZE 6
7977 #define JUMP_REG_SIZE (2 + 1)
7980 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7982 int i, distance = 0;
7983 for (i = start; i < target; ++i)
7984 distance += imt_entries [i]->chunk_size;
7989 * LOCKING: called with the domain lock held
7992 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7993 gpointer fail_tramp)
7997 guint8 *code, *start;
7998 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8001 for (i = 0; i < count; ++i) {
8002 MonoIMTCheckItem *item = imt_entries [i];
8003 if (item->is_equals) {
8004 if (item->check_target_idx) {
8005 if (!item->compare_done) {
8006 if (amd64_use_imm32 ((gint64)item->key))
8007 item->chunk_size += CMP_SIZE;
8009 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8011 if (item->has_target_code) {
8012 item->chunk_size += MOV_REG_IMM_SIZE;
8014 if (vtable_is_32bit)
8015 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8017 item->chunk_size += MOV_REG_IMM_SIZE;
8019 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8022 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8023 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8025 if (vtable_is_32bit)
8026 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8028 item->chunk_size += MOV_REG_IMM_SIZE;
8029 item->chunk_size += JUMP_REG_SIZE;
8030 /* with assert below:
8031 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8036 if (amd64_use_imm32 ((gint64)item->key))
8037 item->chunk_size += CMP_SIZE;
8039 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8040 item->chunk_size += BR_LARGE_SIZE;
8041 imt_entries [item->check_target_idx]->compare_done = TRUE;
8043 size += item->chunk_size;
8046 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size);
8048 code = (guint8 *)mono_domain_code_reserve (domain, size);
8051 unwind_ops = mono_arch_get_cie_program ();
8053 for (i = 0; i < count; ++i) {
8054 MonoIMTCheckItem *item = imt_entries [i];
8055 item->code_target = code;
8056 if (item->is_equals) {
8057 gboolean fail_case = !item->check_target_idx && fail_tramp;
8059 if (item->check_target_idx || fail_case) {
8060 if (!item->compare_done || fail_case) {
8061 if (amd64_use_imm32 ((gint64)item->key))
8062 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8064 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8065 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8068 item->jmp_code = code;
8069 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8070 if (item->has_target_code) {
8071 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8072 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8074 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8075 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8079 amd64_patch (item->jmp_code, code);
8080 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8081 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8082 item->jmp_code = NULL;
8085 /* enable the commented code to assert on wrong method */
8087 if (amd64_is_imm32 (item->key))
8088 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8090 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8091 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8093 item->jmp_code = code;
8094 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8095 /* See the comment below about R10 */
8096 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8097 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8098 amd64_patch (item->jmp_code, code);
8099 amd64_breakpoint (code);
8100 item->jmp_code = NULL;
8102 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8103 needs to be preserved. R10 needs
8104 to be preserved for calls which
8105 require a runtime generic context,
8106 but interface calls don't. */
8107 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8108 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8112 if (amd64_use_imm32 ((gint64)item->key))
8113 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8115 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8116 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8118 item->jmp_code = code;
8119 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8120 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8122 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8124 g_assert (code - item->code_target <= item->chunk_size);
8126 /* patch the branches to get to the target items */
8127 for (i = 0; i < count; ++i) {
8128 MonoIMTCheckItem *item = imt_entries [i];
8129 if (item->jmp_code) {
8130 if (item->check_target_idx) {
8131 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8137 mono_stats.imt_trampolines_size += code - start;
8138 g_assert (code - start <= size);
8140 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8142 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8148 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8150 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8154 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8156 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8160 mono_arch_get_cie_program (void)
8164 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8165 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8173 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8175 MonoInst *ins = NULL;
8178 if (cmethod->klass == mono_defaults.math_class) {
8179 if (strcmp (cmethod->name, "Sin") == 0) {
8181 } else if (strcmp (cmethod->name, "Cos") == 0) {
8183 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8185 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8189 if (opcode && fsig->param_count == 1) {
8190 MONO_INST_NEW (cfg, ins, opcode);
8191 ins->type = STACK_R8;
8192 ins->dreg = mono_alloc_freg (cfg);
8193 ins->sreg1 = args [0]->dreg;
8194 MONO_ADD_INS (cfg->cbb, ins);
8198 if (cfg->opt & MONO_OPT_CMOV) {
8199 if (strcmp (cmethod->name, "Min") == 0) {
8200 if (fsig->params [0]->type == MONO_TYPE_I4)
8202 if (fsig->params [0]->type == MONO_TYPE_U4)
8203 opcode = OP_IMIN_UN;
8204 else if (fsig->params [0]->type == MONO_TYPE_I8)
8206 else if (fsig->params [0]->type == MONO_TYPE_U8)
8207 opcode = OP_LMIN_UN;
8208 } else if (strcmp (cmethod->name, "Max") == 0) {
8209 if (fsig->params [0]->type == MONO_TYPE_I4)
8211 if (fsig->params [0]->type == MONO_TYPE_U4)
8212 opcode = OP_IMAX_UN;
8213 else if (fsig->params [0]->type == MONO_TYPE_I8)
8215 else if (fsig->params [0]->type == MONO_TYPE_U8)
8216 opcode = OP_LMAX_UN;
8220 if (opcode && fsig->param_count == 2) {
8221 MONO_INST_NEW (cfg, ins, opcode);
8222 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8223 ins->dreg = mono_alloc_ireg (cfg);
8224 ins->sreg1 = args [0]->dreg;
8225 ins->sreg2 = args [1]->dreg;
8226 MONO_ADD_INS (cfg->cbb, ins);
8230 /* OP_FREM is not IEEE compatible */
8231 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8232 MONO_INST_NEW (cfg, ins, OP_FREM);
8233 ins->inst_i0 = args [0];
8234 ins->inst_i1 = args [1];
8244 mono_arch_print_tree (MonoInst *tree, int arity)
8250 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8252 return ctx->gregs [reg];
8256 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8258 ctx->gregs [reg] = val;
8262 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8264 gpointer *sp, old_value;
8268 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8269 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8272 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8281 * mono_arch_emit_load_aotconst:
8283 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8284 * TARGET from the mscorlib GOT in full-aot code.
8285 * On AMD64, the result is placed into R11.
8288 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8290 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8291 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8297 * mono_arch_get_trampolines:
8299 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8303 mono_arch_get_trampolines (gboolean aot)
8305 return mono_amd64_get_exception_trampolines (aot);
8308 /* Soft Debug support */
8309 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8312 * mono_arch_set_breakpoint:
8314 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8315 * The location should contain code emitted by OP_SEQ_POINT.
8318 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8323 guint32 native_offset = ip - (guint8*)ji->code_start;
8324 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8326 g_assert (info->bp_addrs [native_offset] == 0);
8327 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8329 /* ip points to a mov r11, 0 */
8330 g_assert (code [0] == 0x41);
8331 g_assert (code [1] == 0xbb);
8332 amd64_mov_reg_imm (code, AMD64_R11, 1);
8337 * mono_arch_clear_breakpoint:
8339 * Clear the breakpoint at IP.
8342 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8347 guint32 native_offset = ip - (guint8*)ji->code_start;
8348 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8350 info->bp_addrs [native_offset] = NULL;
8352 amd64_mov_reg_imm (code, AMD64_R11, 0);
8357 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8359 /* We use soft breakpoints on amd64 */
8364 * mono_arch_skip_breakpoint:
8366 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8367 * we resume, the instruction is not executed again.
8370 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8372 g_assert_not_reached ();
8376 * mono_arch_start_single_stepping:
8378 * Start single stepping.
8381 mono_arch_start_single_stepping (void)
8383 ss_trampoline = mini_get_single_step_trampoline ();
8387 * mono_arch_stop_single_stepping:
8389 * Stop single stepping.
8392 mono_arch_stop_single_stepping (void)
8394 ss_trampoline = NULL;
8398 * mono_arch_is_single_step_event:
8400 * Return whenever the machine state in SIGCTX corresponds to a single
8404 mono_arch_is_single_step_event (void *info, void *sigctx)
8406 /* We use soft breakpoints on amd64 */
8411 * mono_arch_skip_single_step:
8413 * Modify CTX so the ip is placed after the single step trigger instruction,
8414 * we resume, the instruction is not executed again.
8417 mono_arch_skip_single_step (MonoContext *ctx)
8419 g_assert_not_reached ();
8423 * mono_arch_create_seq_point_info:
8425 * Return a pointer to a data structure which is used by the sequence
8426 * point implementation in AOTed code.
8429 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8434 // FIXME: Add a free function
8436 mono_domain_lock (domain);
8437 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8439 mono_domain_unlock (domain);
8442 ji = mono_jit_info_table_find (domain, (char*)code);
8445 // FIXME: Optimize the size
8446 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8448 info->ss_tramp_addr = &ss_trampoline;
8450 mono_domain_lock (domain);
8451 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8453 mono_domain_unlock (domain);
8460 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8462 ext->lmf.previous_lmf = prev_lmf;
8463 /* Mark that this is a MonoLMFExt */
8464 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8465 ext->lmf.rsp = (gssize)ext;
8471 mono_arch_opcode_supported (int opcode)
8474 case OP_ATOMIC_ADD_I4:
8475 case OP_ATOMIC_ADD_I8:
8476 case OP_ATOMIC_EXCHANGE_I4:
8477 case OP_ATOMIC_EXCHANGE_I8:
8478 case OP_ATOMIC_CAS_I4:
8479 case OP_ATOMIC_CAS_I8:
8480 case OP_ATOMIC_LOAD_I1:
8481 case OP_ATOMIC_LOAD_I2:
8482 case OP_ATOMIC_LOAD_I4:
8483 case OP_ATOMIC_LOAD_I8:
8484 case OP_ATOMIC_LOAD_U1:
8485 case OP_ATOMIC_LOAD_U2:
8486 case OP_ATOMIC_LOAD_U4:
8487 case OP_ATOMIC_LOAD_U8:
8488 case OP_ATOMIC_LOAD_R4:
8489 case OP_ATOMIC_LOAD_R8:
8490 case OP_ATOMIC_STORE_I1:
8491 case OP_ATOMIC_STORE_I2:
8492 case OP_ATOMIC_STORE_I4:
8493 case OP_ATOMIC_STORE_I8:
8494 case OP_ATOMIC_STORE_U1:
8495 case OP_ATOMIC_STORE_U2:
8496 case OP_ATOMIC_STORE_U4:
8497 case OP_ATOMIC_STORE_U8:
8498 case OP_ATOMIC_STORE_R4:
8499 case OP_ATOMIC_STORE_R8:
8507 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8509 return get_call_info (mp, sig);