3 * AMD64 backend for the Mono code generator
8 * Paolo Molaro (lupus@ximian.com)
9 * Dietmar Maurer (dietmar@ximian.com)
11 * Zoltan Varga (vargaz@gmail.com)
12 * Johan Lorensson (lateralusx.github@gmail.com)
14 * (C) 2003 Ximian, Inc.
15 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
16 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
17 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
27 #include <mono/metadata/abi-details.h>
28 #include <mono/metadata/appdomain.h>
29 #include <mono/metadata/debug-helpers.h>
30 #include <mono/metadata/threads.h>
31 #include <mono/metadata/profiler-private.h>
32 #include <mono/metadata/mono-debug.h>
33 #include <mono/metadata/gc-internals.h>
34 #include <mono/utils/mono-math.h>
35 #include <mono/utils/mono-mmap.h>
36 #include <mono/utils/mono-memory-model.h>
37 #include <mono/utils/mono-tls.h>
38 #include <mono/utils/mono-hwcap.h>
39 #include <mono/utils/mono-threads.h>
40 #include <mono/utils/unlocked.h>
44 #include "mini-amd64.h"
45 #include "cpu-amd64.h"
46 #include "debugger-agent.h"
50 static gboolean optimize_for_xen = TRUE;
52 #define optimize_for_xen 0
55 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
59 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
62 /* Under windows, the calling convention is never stdcall */
63 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
65 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
68 /* This mutex protects architecture specific caches */
69 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
70 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
71 static mono_mutex_t mini_arch_mutex;
73 /* The single step trampoline */
74 static gpointer ss_trampoline;
76 /* The breakpoint trampoline */
77 static gpointer bp_trampoline;
79 /* Offset between fp and the first argument in the callee */
80 #define ARGS_OFFSET 16
81 #define GP_SCRATCH_REG AMD64_R11
84 * AMD64 register usage:
85 * - callee saved registers are used for global register allocation
86 * - %r11 is used for materializing 64 bit constants in opcodes
87 * - the rest is used for local allocation
91 * Floating point comparison results:
101 mono_arch_regname (int reg)
104 case AMD64_RAX: return "%rax";
105 case AMD64_RBX: return "%rbx";
106 case AMD64_RCX: return "%rcx";
107 case AMD64_RDX: return "%rdx";
108 case AMD64_RSP: return "%rsp";
109 case AMD64_RBP: return "%rbp";
110 case AMD64_RDI: return "%rdi";
111 case AMD64_RSI: return "%rsi";
112 case AMD64_R8: return "%r8";
113 case AMD64_R9: return "%r9";
114 case AMD64_R10: return "%r10";
115 case AMD64_R11: return "%r11";
116 case AMD64_R12: return "%r12";
117 case AMD64_R13: return "%r13";
118 case AMD64_R14: return "%r14";
119 case AMD64_R15: return "%r15";
124 static const char * packed_xmmregs [] = {
125 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
126 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
129 static const char * single_xmmregs [] = {
130 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
131 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
135 mono_arch_fregname (int reg)
137 if (reg < AMD64_XMM_NREG)
138 return single_xmmregs [reg];
144 mono_arch_xregname (int reg)
146 if (reg < AMD64_XMM_NREG)
147 return packed_xmmregs [reg];
156 return mono_debug_count ();
162 static inline gboolean
163 amd64_is_near_call (guint8 *code)
166 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
169 return code [0] == 0xe8;
172 static inline gboolean
173 amd64_use_imm32 (gint64 val)
175 if (mini_get_debug_options()->single_imm_size)
178 return amd64_is_imm32 (val);
182 amd64_patch (unsigned char* code, gpointer target)
187 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
192 if ((code [0] & 0xf8) == 0xb8) {
193 /* amd64_set_reg_template */
194 *(guint64*)(code + 1) = (guint64)target;
196 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
197 /* mov 0(%rip), %dreg */
198 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
200 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
201 /* call *<OFFSET>(%rip) */
202 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
204 else if (code [0] == 0xe8) {
206 gint64 disp = (guint8*)target - (guint8*)code;
207 g_assert (amd64_is_imm32 (disp));
208 x86_patch (code, (unsigned char*)target);
211 x86_patch (code, (unsigned char*)target);
215 mono_amd64_patch (unsigned char* code, gpointer target)
217 amd64_patch (code, target);
220 #define DEBUG(a) if (cfg->verbose_level > 1) a
223 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
225 ainfo->offset = *stack_size;
227 if (*gr >= PARAM_REGS) {
228 ainfo->storage = ArgOnStack;
229 ainfo->arg_size = sizeof (mgreg_t);
230 /* Since the same stack slot size is used for all arg */
231 /* types, it needs to be big enough to hold them all */
232 (*stack_size) += sizeof(mgreg_t);
235 ainfo->storage = ArgInIReg;
236 ainfo->reg = param_regs [*gr];
242 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
244 ainfo->offset = *stack_size;
246 if (*gr >= FLOAT_PARAM_REGS) {
247 ainfo->storage = ArgOnStack;
248 ainfo->arg_size = sizeof (mgreg_t);
249 /* Since the same stack slot size is used for both float */
250 /* types, it needs to be big enough to hold them both */
251 (*stack_size) += sizeof(mgreg_t);
254 /* A double register */
256 ainfo->storage = ArgInDoubleSSEReg;
258 ainfo->storage = ArgInFloatSSEReg;
264 typedef enum ArgumentClass {
272 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
274 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
277 ptype = mini_get_underlying_type (type);
278 switch (ptype->type) {
287 case MONO_TYPE_OBJECT:
289 case MONO_TYPE_FNPTR:
292 class2 = ARG_CLASS_INTEGER;
297 class2 = ARG_CLASS_INTEGER;
299 class2 = ARG_CLASS_SSE;
303 case MONO_TYPE_TYPEDBYREF:
304 g_assert_not_reached ();
306 case MONO_TYPE_GENERICINST:
307 if (!mono_type_generic_inst_is_valuetype (ptype)) {
308 class2 = ARG_CLASS_INTEGER;
312 case MONO_TYPE_VALUETYPE: {
313 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
316 for (i = 0; i < info->num_fields; ++i) {
318 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
323 g_assert_not_reached ();
327 if (class1 == class2)
329 else if (class1 == ARG_CLASS_NO_CLASS)
331 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
332 class1 = ARG_CLASS_MEMORY;
333 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
334 class1 = ARG_CLASS_INTEGER;
336 class1 = ARG_CLASS_SSE;
347 * collect_field_info_nested:
349 * Collect field info from KLASS recursively into FIELDS.
352 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
354 MonoMarshalType *info;
358 info = mono_marshal_load_type_info (klass);
360 for (i = 0; i < info->num_fields; ++i) {
361 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
362 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
367 f.type = info->fields [i].field->type;
368 f.size = mono_marshal_type_size (info->fields [i].field->type,
369 info->fields [i].mspec,
370 &align, TRUE, unicode);
371 f.offset = offset + info->fields [i].offset;
372 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
373 /* This can happen with .pack directives eg. 'fixed' arrays */
374 if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
375 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
376 g_array_append_val (fields_array, f);
377 while (f.size + f.offset < info->native_size) {
379 g_array_append_val (fields_array, f);
382 f.size = info->native_size - f.offset;
383 g_array_append_val (fields_array, f);
386 g_array_append_val (fields_array, f);
392 MonoClassField *field;
395 while ((field = mono_class_get_fields (klass, &iter))) {
396 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
398 if (MONO_TYPE_ISSTRUCT (field->type)) {
399 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
404 f.type = field->type;
405 f.size = mono_type_size (field->type, &align);
406 f.offset = field->offset - sizeof (MonoObject) + offset;
408 g_array_append_val (fields_array, f);
416 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
417 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
420 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
422 gboolean result = FALSE;
424 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
425 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
427 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
428 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
429 arg_info->pair_size [0] = 0;
430 arg_info->pair_size [1] = 0;
433 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
434 /* Pass parameter in integer register. */
435 arg_info->pair_storage [0] = ArgInIReg;
436 arg_info->pair_regs [0] = int_regs [*current_int_reg];
437 (*current_int_reg) ++;
439 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
440 /* Pass parameter in float register. */
441 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
442 arg_info->pair_regs [0] = float_regs [*current_float_reg];
443 (*current_float_reg) ++;
447 if (result == TRUE) {
448 arg_info->pair_size [0] = arg_size;
455 static inline gboolean
456 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
458 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
461 static inline gboolean
462 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
464 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
468 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
469 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
471 /* Windows x64 value type ABI.
473 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
475 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
476 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
477 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
478 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
480 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
482 * Integers/Float types smaller than or equal to 8 bytes
483 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
484 * Properly sized struct/unions (1,2,4,8)
485 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
486 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
487 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
490 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
494 /* Parameter cases. */
495 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
496 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
498 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
499 arg_info->storage = ArgValuetypeInReg;
500 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
501 /* No more registers, fallback passing parameter on stack as value. */
502 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
504 /* Passing value directly on stack, so use size of value. */
505 arg_info->storage = ArgOnStack;
506 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
507 arg_info->offset = *stack_size;
508 arg_info->arg_size = arg_size;
509 *stack_size += arg_size;
512 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
513 arg_info->storage = ArgValuetypeAddrInIReg;
514 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
515 /* No more registers, fallback passing address to parameter on stack. */
516 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
518 /* Passing an address to value on stack, so use size of register as argument size. */
519 arg_info->storage = ArgValuetypeAddrOnStack;
520 arg_size = sizeof (mgreg_t);
521 arg_info->offset = *stack_size;
522 arg_info->arg_size = arg_size;
523 *stack_size += arg_size;
527 /* Return value cases. */
528 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
529 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
531 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
532 arg_info->storage = ArgValuetypeInReg;
533 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
535 /* Only RAX/XMM0 should be used to return valuetype. */
536 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
538 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
539 arg_info->storage = ArgValuetypeAddrInIReg;
540 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
542 /* Only RAX should be used to return valuetype address. */
543 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
545 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
546 arg_info->offset = *stack_size;
547 *stack_size += arg_size;
553 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
556 *arg_class = ARG_CLASS_NO_CLASS;
558 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
561 /* Calculate argument class type and size of marshalled type. */
562 MonoMarshalType *info = mono_marshal_load_type_info (klass);
563 *arg_size = info->native_size;
565 /* Calculate argument class type and size of managed type. */
566 *arg_size = mono_class_value_size (klass, NULL);
569 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
570 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
572 if (*arg_class == ARG_CLASS_MEMORY) {
573 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
574 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
578 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
579 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
580 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
581 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
582 * it must be represented in call and cannot be dropped.
584 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
585 arg_info->pass_empty_struct = TRUE;
586 *arg_size = SIZEOF_REGISTER;
587 *arg_class = ARG_CLASS_INTEGER;
590 assert (*arg_class != ARG_CLASS_NO_CLASS);
594 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
595 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
597 guint32 arg_size = SIZEOF_REGISTER;
598 MonoClass *klass = NULL;
599 ArgumentClass arg_class;
601 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
603 klass = mono_class_from_mono_type (type);
604 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
606 /* Only drop value type if its not an empty struct as input that must be represented in call */
607 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
608 arg_info->storage = ArgValuetypeInReg;
609 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
611 /* Alocate storage for value type. */
612 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
616 #endif /* TARGET_WIN32 */
619 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
621 guint32 *gr, guint32 *fr, guint32 *stack_size)
624 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
626 guint32 size, quad, nquads, i, nfields;
627 /* Keep track of the size used in each quad so we can */
628 /* use the right size when copying args/return vars. */
629 guint32 quadsize [2] = {8, 8};
630 ArgumentClass args [2];
631 StructFieldInfo *fields = NULL;
632 GArray *fields_array;
634 gboolean pass_on_stack = FALSE;
637 klass = mono_class_from_mono_type (type);
638 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
640 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
641 /* We pass and return vtypes of size 8 in a register */
642 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
643 pass_on_stack = TRUE;
646 /* If this struct can't be split up naturally into 8-byte */
647 /* chunks (registers), pass it on the stack. */
649 MonoMarshalType *info = mono_marshal_load_type_info (klass);
651 struct_size = info->native_size;
653 struct_size = mono_class_value_size (klass, NULL);
656 * Collect field information recursively to be able to
657 * handle nested structures.
659 fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
660 collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
661 fields = (StructFieldInfo*)fields_array->data;
662 nfields = fields_array->len;
664 for (i = 0; i < nfields; ++i) {
665 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
666 pass_on_stack = TRUE;
672 ainfo->storage = ArgValuetypeInReg;
673 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
678 /* Allways pass in memory */
679 ainfo->offset = *stack_size;
680 *stack_size += ALIGN_TO (size, 8);
681 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
683 ainfo->arg_size = ALIGN_TO (size, 8);
685 g_array_free (fields_array, TRUE);
695 int n = mono_class_value_size (klass, NULL);
697 quadsize [0] = n >= 8 ? 8 : n;
698 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
700 /* Always pass in 1 or 2 integer registers */
701 args [0] = ARG_CLASS_INTEGER;
702 args [1] = ARG_CLASS_INTEGER;
703 /* Only the simplest cases are supported */
704 if (is_return && nquads != 1) {
705 args [0] = ARG_CLASS_MEMORY;
706 args [1] = ARG_CLASS_MEMORY;
710 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
711 * The X87 and SSEUP stuff is left out since there are no such types in
715 ainfo->storage = ArgValuetypeInReg;
716 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
720 if (struct_size > 16) {
721 ainfo->offset = *stack_size;
722 *stack_size += ALIGN_TO (struct_size, 8);
723 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
725 ainfo->arg_size = ALIGN_TO (struct_size, 8);
727 g_array_free (fields_array, TRUE);
731 args [0] = ARG_CLASS_NO_CLASS;
732 args [1] = ARG_CLASS_NO_CLASS;
733 for (quad = 0; quad < nquads; ++quad) {
734 ArgumentClass class1;
737 class1 = ARG_CLASS_MEMORY;
739 class1 = ARG_CLASS_NO_CLASS;
740 for (i = 0; i < nfields; ++i) {
741 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
742 /* Unaligned field */
746 /* Skip fields in other quad */
747 if ((quad == 0) && (fields [i].offset >= 8))
749 if ((quad == 1) && (fields [i].offset < 8))
752 /* How far into this quad this data extends.*/
753 /* (8 is size of quad) */
754 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
756 class1 = merge_argument_class_from_type (fields [i].type, class1);
758 /* Empty structs have a nonzero size, causing this assert to be hit */
760 g_assert (class1 != ARG_CLASS_NO_CLASS);
761 args [quad] = class1;
765 g_array_free (fields_array, TRUE);
767 /* Post merger cleanup */
768 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
769 args [0] = args [1] = ARG_CLASS_MEMORY;
771 /* Allocate registers */
776 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
778 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
781 ainfo->storage = ArgValuetypeInReg;
782 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
783 g_assert (quadsize [0] <= 8);
784 g_assert (quadsize [1] <= 8);
785 ainfo->pair_size [0] = quadsize [0];
786 ainfo->pair_size [1] = quadsize [1];
787 ainfo->nregs = nquads;
788 for (quad = 0; quad < nquads; ++quad) {
789 switch (args [quad]) {
790 case ARG_CLASS_INTEGER:
791 if (*gr >= PARAM_REGS)
792 args [quad] = ARG_CLASS_MEMORY;
794 ainfo->pair_storage [quad] = ArgInIReg;
796 ainfo->pair_regs [quad] = return_regs [*gr];
798 ainfo->pair_regs [quad] = param_regs [*gr];
803 if (*fr >= FLOAT_PARAM_REGS)
804 args [quad] = ARG_CLASS_MEMORY;
806 if (quadsize[quad] <= 4)
807 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
808 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
809 ainfo->pair_regs [quad] = *fr;
813 case ARG_CLASS_MEMORY:
815 case ARG_CLASS_NO_CLASS:
818 g_assert_not_reached ();
822 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
824 /* Revert possible register assignments */
828 ainfo->offset = *stack_size;
830 arg_size = ALIGN_TO (struct_size, 8);
832 arg_size = nquads * sizeof(mgreg_t);
833 *stack_size += arg_size;
834 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
836 ainfo->arg_size = arg_size;
839 #endif /* !TARGET_WIN32 */
845 * Obtain information about a call according to the calling convention.
846 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
847 * Draft Version 0.23" document for more information.
848 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
849 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
852 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
854 guint32 i, gr, fr, pstart;
856 int n = sig->hasthis + sig->param_count;
857 guint32 stack_size = 0;
859 gboolean is_pinvoke = sig->pinvoke;
862 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
864 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
867 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
873 /* Reserve space where the callee can save the argument registers */
874 stack_size = 4 * sizeof (mgreg_t);
878 ret_type = mini_get_underlying_type (sig->ret);
879 switch (ret_type->type) {
889 case MONO_TYPE_FNPTR:
890 case MONO_TYPE_OBJECT:
891 cinfo->ret.storage = ArgInIReg;
892 cinfo->ret.reg = AMD64_RAX;
896 cinfo->ret.storage = ArgInIReg;
897 cinfo->ret.reg = AMD64_RAX;
900 cinfo->ret.storage = ArgInFloatSSEReg;
901 cinfo->ret.reg = AMD64_XMM0;
904 cinfo->ret.storage = ArgInDoubleSSEReg;
905 cinfo->ret.reg = AMD64_XMM0;
907 case MONO_TYPE_GENERICINST:
908 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
909 cinfo->ret.storage = ArgInIReg;
910 cinfo->ret.reg = AMD64_RAX;
913 if (mini_is_gsharedvt_type (ret_type)) {
914 cinfo->ret.storage = ArgGsharedvtVariableInReg;
918 case MONO_TYPE_VALUETYPE:
919 case MONO_TYPE_TYPEDBYREF: {
920 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
922 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
923 g_assert (cinfo->ret.storage != ArgInIReg);
928 g_assert (mini_is_gsharedvt_type (ret_type));
929 cinfo->ret.storage = ArgGsharedvtVariableInReg;
934 g_error ("Can't handle as return value 0x%x", ret_type->type);
939 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
940 * the first argument, allowing 'this' to be always passed in the first arg reg.
941 * Also do this if the first argument is a reference type, since virtual calls
942 * are sometimes made using calli without sig->hasthis set, like in the delegate
945 ArgStorage ret_storage = cinfo->ret.storage;
946 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
948 add_general (&gr, &stack_size, cinfo->args + 0);
950 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
953 add_general (&gr, &stack_size, &cinfo->ret);
954 cinfo->ret.storage = ret_storage;
955 cinfo->vret_arg_index = 1;
959 add_general (&gr, &stack_size, cinfo->args + 0);
961 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
962 add_general (&gr, &stack_size, &cinfo->ret);
963 cinfo->ret.storage = ret_storage;
967 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
969 fr = FLOAT_PARAM_REGS;
971 /* Emit the signature cookie just before the implicit arguments */
972 add_general (&gr, &stack_size, &cinfo->sig_cookie);
975 for (i = pstart; i < sig->param_count; ++i) {
976 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
980 /* The float param registers and other param registers must be the same index on Windows x64.*/
987 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
988 /* We allways pass the sig cookie on the stack for simplicity */
990 * Prevent implicit arguments + the sig cookie from being passed
994 fr = FLOAT_PARAM_REGS;
996 /* Emit the signature cookie just before the implicit arguments */
997 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1000 ptype = mini_get_underlying_type (sig->params [i]);
1001 switch (ptype->type) {
1004 add_general (&gr, &stack_size, ainfo);
1005 ainfo->byte_arg_size = 1;
1009 add_general (&gr, &stack_size, ainfo);
1010 ainfo->byte_arg_size = 2;
1014 add_general (&gr, &stack_size, ainfo);
1015 ainfo->byte_arg_size = 4;
1020 case MONO_TYPE_FNPTR:
1021 case MONO_TYPE_OBJECT:
1022 add_general (&gr, &stack_size, ainfo);
1024 case MONO_TYPE_GENERICINST:
1025 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1026 add_general (&gr, &stack_size, ainfo);
1029 if (mini_is_gsharedvt_variable_type (ptype)) {
1030 /* gsharedvt arguments are passed by ref */
1031 add_general (&gr, &stack_size, ainfo);
1032 if (ainfo->storage == ArgInIReg)
1033 ainfo->storage = ArgGSharedVtInReg;
1035 ainfo->storage = ArgGSharedVtOnStack;
1039 case MONO_TYPE_VALUETYPE:
1040 case MONO_TYPE_TYPEDBYREF:
1041 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1046 add_general (&gr, &stack_size, ainfo);
1049 add_float (&fr, &stack_size, ainfo, FALSE);
1052 add_float (&fr, &stack_size, ainfo, TRUE);
1055 case MONO_TYPE_MVAR:
1056 /* gsharedvt arguments are passed by ref */
1057 g_assert (mini_is_gsharedvt_type (ptype));
1058 add_general (&gr, &stack_size, ainfo);
1059 if (ainfo->storage == ArgInIReg)
1060 ainfo->storage = ArgGSharedVtInReg;
1062 ainfo->storage = ArgGSharedVtOnStack;
1065 g_assert_not_reached ();
1069 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1071 fr = FLOAT_PARAM_REGS;
1073 /* Emit the signature cookie just before the implicit arguments */
1074 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1077 cinfo->stack_usage = stack_size;
1078 cinfo->reg_usage = gr;
1079 cinfo->freg_usage = fr;
1084 * mono_arch_get_argument_info:
1085 * @csig: a method signature
1086 * @param_count: the number of parameters to consider
1087 * @arg_info: an array to store the result infos
1089 * Gathers information on parameters such as size, alignment and
1090 * padding. arg_info should be large enought to hold param_count + 1 entries.
1092 * Returns the size of the argument area on the stack.
1095 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1098 CallInfo *cinfo = get_call_info (NULL, csig);
1099 guint32 args_size = cinfo->stack_usage;
1101 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1102 if (csig->hasthis) {
1103 arg_info [0].offset = 0;
1106 for (k = 0; k < param_count; k++) {
1107 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1109 arg_info [k + 1].size = 0;
1118 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1122 MonoType *callee_ret;
1124 c1 = get_call_info (NULL, caller_sig);
1125 c2 = get_call_info (NULL, callee_sig);
1126 res = c1->stack_usage >= c2->stack_usage;
1127 callee_ret = mini_get_underlying_type (callee_sig->ret);
1128 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1129 /* An address on the callee's stack is passed as the first argument */
1139 * Initialize the cpu to execute managed code.
1142 mono_arch_cpu_init (void)
1147 /* spec compliance requires running with double precision */
1148 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1149 fpcw &= ~X86_FPCW_PRECC_MASK;
1150 fpcw |= X86_FPCW_PREC_DOUBLE;
1151 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1152 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1154 /* TODO: This is crashing on Win64 right now.
1155 * _control87 (_PC_53, MCW_PC);
1161 * Initialize architecture specific code.
1164 mono_arch_init (void)
1166 mono_os_mutex_init_recursive (&mini_arch_mutex);
1168 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1169 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1170 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1171 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1173 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1174 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1178 bp_trampoline = mini_get_breakpoint_trampoline ();
1182 * Cleanup architecture specific code.
1185 mono_arch_cleanup (void)
1187 mono_os_mutex_destroy (&mini_arch_mutex);
1191 * This function returns the optimizations supported on this cpu.
1194 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1200 if (mono_hwcap_x86_has_cmov) {
1201 opts |= MONO_OPT_CMOV;
1203 if (mono_hwcap_x86_has_fcmov)
1204 opts |= MONO_OPT_FCMOV;
1206 *exclude_mask |= MONO_OPT_FCMOV;
1208 *exclude_mask |= MONO_OPT_CMOV;
1212 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1213 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1214 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1215 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1216 /* will now have a reference to an argument that won't be fully decomposed. */
1217 *exclude_mask |= MONO_OPT_SIMD;
1224 * This function test for all SSE functions supported.
1226 * Returns a bitmask corresponding to all supported versions.
1230 mono_arch_cpu_enumerate_simd_versions (void)
1232 guint32 sse_opts = 0;
1234 if (mono_hwcap_x86_has_sse1)
1235 sse_opts |= SIMD_VERSION_SSE1;
1237 if (mono_hwcap_x86_has_sse2)
1238 sse_opts |= SIMD_VERSION_SSE2;
1240 if (mono_hwcap_x86_has_sse3)
1241 sse_opts |= SIMD_VERSION_SSE3;
1243 if (mono_hwcap_x86_has_ssse3)
1244 sse_opts |= SIMD_VERSION_SSSE3;
1246 if (mono_hwcap_x86_has_sse41)
1247 sse_opts |= SIMD_VERSION_SSE41;
1249 if (mono_hwcap_x86_has_sse42)
1250 sse_opts |= SIMD_VERSION_SSE42;
1252 if (mono_hwcap_x86_has_sse4a)
1253 sse_opts |= SIMD_VERSION_SSE4a;
1261 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1266 for (i = 0; i < cfg->num_varinfo; i++) {
1267 MonoInst *ins = cfg->varinfo [i];
1268 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1271 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1274 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1275 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1278 if (mono_is_regsize_var (ins->inst_vtype)) {
1279 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1280 g_assert (i == vmv->idx);
1281 vars = g_list_prepend (vars, vmv);
1285 vars = mono_varlist_sort (cfg, vars, 0);
1291 * mono_arch_compute_omit_fp:
1292 * Determine whether the frame pointer can be eliminated.
1295 mono_arch_compute_omit_fp (MonoCompile *cfg)
1297 MonoMethodSignature *sig;
1298 MonoMethodHeader *header;
1302 if (cfg->arch.omit_fp_computed)
1305 header = cfg->header;
1307 sig = mono_method_signature (cfg->method);
1309 if (!cfg->arch.cinfo)
1310 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1311 cinfo = (CallInfo *)cfg->arch.cinfo;
1314 * FIXME: Remove some of the restrictions.
1316 cfg->arch.omit_fp = TRUE;
1317 cfg->arch.omit_fp_computed = TRUE;
1319 if (cfg->disable_omit_fp)
1320 cfg->arch.omit_fp = FALSE;
1322 if (!debug_omit_fp ())
1323 cfg->arch.omit_fp = FALSE;
1325 if (cfg->method->save_lmf)
1326 cfg->arch.omit_fp = FALSE;
1328 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1329 cfg->arch.omit_fp = FALSE;
1330 if (header->num_clauses)
1331 cfg->arch.omit_fp = FALSE;
1332 if (cfg->param_area)
1333 cfg->arch.omit_fp = FALSE;
1334 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1335 cfg->arch.omit_fp = FALSE;
1336 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1337 cfg->arch.omit_fp = FALSE;
1338 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1339 ArgInfo *ainfo = &cinfo->args [i];
1341 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1343 * The stack offset can only be determined when the frame
1346 cfg->arch.omit_fp = FALSE;
1351 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1352 MonoInst *ins = cfg->varinfo [i];
1355 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1360 mono_arch_get_global_int_regs (MonoCompile *cfg)
1364 mono_arch_compute_omit_fp (cfg);
1366 if (cfg->arch.omit_fp)
1367 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1369 /* We use the callee saved registers for global allocation */
1370 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1371 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1372 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1373 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1374 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1376 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1377 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1384 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1389 /* All XMM registers */
1390 for (i = 0; i < 16; ++i)
1391 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1397 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1399 static GList *r = NULL;
1404 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1405 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1406 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1407 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1408 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1409 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1411 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1412 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1413 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1414 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1415 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1416 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1417 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1418 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1420 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1427 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1430 static GList *r = NULL;
1435 for (i = 0; i < AMD64_XMM_NREG; ++i)
1436 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1438 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1445 * mono_arch_regalloc_cost:
1447 * Return the cost, in number of memory references, of the action of
1448 * allocating the variable VMV into a register during global register
1452 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1454 MonoInst *ins = cfg->varinfo [vmv->idx];
1456 if (cfg->method->save_lmf)
1457 /* The register is already saved */
1458 /* substract 1 for the invisible store in the prolog */
1459 return (ins->opcode == OP_ARG) ? 0 : 1;
1462 return (ins->opcode == OP_ARG) ? 1 : 2;
1466 * mono_arch_fill_argument_info:
1468 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1472 mono_arch_fill_argument_info (MonoCompile *cfg)
1475 MonoMethodSignature *sig;
1480 sig = mono_method_signature (cfg->method);
1482 cinfo = (CallInfo *)cfg->arch.cinfo;
1483 sig_ret = mini_get_underlying_type (sig->ret);
1486 * Contrary to mono_arch_allocate_vars (), the information should describe
1487 * where the arguments are at the beginning of the method, not where they can be
1488 * accessed during the execution of the method. The later makes no sense for the
1489 * global register allocator, since a variable can be in more than one location.
1491 switch (cinfo->ret.storage) {
1493 case ArgInFloatSSEReg:
1494 case ArgInDoubleSSEReg:
1495 cfg->ret->opcode = OP_REGVAR;
1496 cfg->ret->inst_c0 = cinfo->ret.reg;
1498 case ArgValuetypeInReg:
1499 cfg->ret->opcode = OP_REGOFFSET;
1500 cfg->ret->inst_basereg = -1;
1501 cfg->ret->inst_offset = -1;
1506 g_assert_not_reached ();
1509 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1510 ArgInfo *ainfo = &cinfo->args [i];
1512 ins = cfg->args [i];
1514 switch (ainfo->storage) {
1516 case ArgInFloatSSEReg:
1517 case ArgInDoubleSSEReg:
1518 ins->opcode = OP_REGVAR;
1519 ins->inst_c0 = ainfo->reg;
1522 ins->opcode = OP_REGOFFSET;
1523 ins->inst_basereg = -1;
1524 ins->inst_offset = -1;
1526 case ArgValuetypeInReg:
1528 ins->opcode = OP_NOP;
1531 g_assert_not_reached ();
1537 mono_arch_allocate_vars (MonoCompile *cfg)
1540 MonoMethodSignature *sig;
1543 guint32 locals_stack_size, locals_stack_align;
1547 sig = mono_method_signature (cfg->method);
1549 cinfo = (CallInfo *)cfg->arch.cinfo;
1550 sig_ret = mini_get_underlying_type (sig->ret);
1552 mono_arch_compute_omit_fp (cfg);
1555 * We use the ABI calling conventions for managed code as well.
1556 * Exception: valuetypes are only sometimes passed or returned in registers.
1560 * The stack looks like this:
1561 * <incoming arguments passed on the stack>
1563 * <lmf/caller saved registers>
1566 * <localloc area> -> grows dynamically
1570 if (cfg->arch.omit_fp) {
1571 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1572 cfg->frame_reg = AMD64_RSP;
1575 /* Locals are allocated backwards from %fp */
1576 cfg->frame_reg = AMD64_RBP;
1580 cfg->arch.saved_iregs = cfg->used_int_regs;
1581 if (cfg->method->save_lmf) {
1582 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1583 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1584 cfg->arch.saved_iregs |= iregs_to_save;
1587 if (cfg->arch.omit_fp)
1588 cfg->arch.reg_save_area_offset = offset;
1589 /* Reserve space for callee saved registers */
1590 for (i = 0; i < AMD64_NREG; ++i)
1591 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1592 offset += sizeof(mgreg_t);
1594 if (!cfg->arch.omit_fp)
1595 cfg->arch.reg_save_area_offset = -offset;
1597 if (sig_ret->type != MONO_TYPE_VOID) {
1598 switch (cinfo->ret.storage) {
1600 case ArgInFloatSSEReg:
1601 case ArgInDoubleSSEReg:
1602 cfg->ret->opcode = OP_REGVAR;
1603 cfg->ret->inst_c0 = cinfo->ret.reg;
1604 cfg->ret->dreg = cinfo->ret.reg;
1606 case ArgValuetypeAddrInIReg:
1607 case ArgGsharedvtVariableInReg:
1608 /* The register is volatile */
1609 cfg->vret_addr->opcode = OP_REGOFFSET;
1610 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1611 if (cfg->arch.omit_fp) {
1612 cfg->vret_addr->inst_offset = offset;
1616 cfg->vret_addr->inst_offset = -offset;
1618 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1619 printf ("vret_addr =");
1620 mono_print_ins (cfg->vret_addr);
1623 case ArgValuetypeInReg:
1624 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1625 cfg->ret->opcode = OP_REGOFFSET;
1626 cfg->ret->inst_basereg = cfg->frame_reg;
1627 if (cfg->arch.omit_fp) {
1628 cfg->ret->inst_offset = offset;
1629 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1631 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1632 cfg->ret->inst_offset = - offset;
1636 g_assert_not_reached ();
1640 /* Allocate locals */
1641 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1642 if (locals_stack_align) {
1643 offset += (locals_stack_align - 1);
1644 offset &= ~(locals_stack_align - 1);
1646 if (cfg->arch.omit_fp) {
1647 cfg->locals_min_stack_offset = offset;
1648 cfg->locals_max_stack_offset = offset + locals_stack_size;
1650 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1651 cfg->locals_max_stack_offset = - offset;
1654 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1655 if (offsets [i] != -1) {
1656 MonoInst *ins = cfg->varinfo [i];
1657 ins->opcode = OP_REGOFFSET;
1658 ins->inst_basereg = cfg->frame_reg;
1659 if (cfg->arch.omit_fp)
1660 ins->inst_offset = (offset + offsets [i]);
1662 ins->inst_offset = - (offset + offsets [i]);
1663 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1666 offset += locals_stack_size;
1668 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1669 g_assert (!cfg->arch.omit_fp);
1670 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1671 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1674 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1675 ins = cfg->args [i];
1676 if (ins->opcode != OP_REGVAR) {
1677 ArgInfo *ainfo = &cinfo->args [i];
1678 gboolean inreg = TRUE;
1680 /* FIXME: Allocate volatile arguments to registers */
1681 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1685 * Under AMD64, all registers used to pass arguments to functions
1686 * are volatile across calls.
1687 * FIXME: Optimize this.
1689 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1692 ins->opcode = OP_REGOFFSET;
1694 switch (ainfo->storage) {
1696 case ArgInFloatSSEReg:
1697 case ArgInDoubleSSEReg:
1698 case ArgGSharedVtInReg:
1700 ins->opcode = OP_REGVAR;
1701 ins->dreg = ainfo->reg;
1705 case ArgGSharedVtOnStack:
1706 g_assert (!cfg->arch.omit_fp);
1707 ins->opcode = OP_REGOFFSET;
1708 ins->inst_basereg = cfg->frame_reg;
1709 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1711 case ArgValuetypeInReg:
1713 case ArgValuetypeAddrInIReg:
1714 case ArgValuetypeAddrOnStack: {
1716 g_assert (!cfg->arch.omit_fp);
1717 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1718 MONO_INST_NEW (cfg, indir, 0);
1720 indir->opcode = OP_REGOFFSET;
1721 if (ainfo->pair_storage [0] == ArgInIReg) {
1722 indir->inst_basereg = cfg->frame_reg;
1723 offset = ALIGN_TO (offset, sizeof (gpointer));
1724 offset += (sizeof (gpointer));
1725 indir->inst_offset = - offset;
1728 indir->inst_basereg = cfg->frame_reg;
1729 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1732 ins->opcode = OP_VTARG_ADDR;
1733 ins->inst_left = indir;
1741 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1742 ins->opcode = OP_REGOFFSET;
1743 ins->inst_basereg = cfg->frame_reg;
1744 /* These arguments are saved to the stack in the prolog */
1745 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1746 if (cfg->arch.omit_fp) {
1747 ins->inst_offset = offset;
1748 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1749 // Arguments are yet supported by the stack map creation code
1750 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1752 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1753 ins->inst_offset = - offset;
1754 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1760 cfg->stack_offset = offset;
1764 mono_arch_create_vars (MonoCompile *cfg)
1766 MonoMethodSignature *sig;
1770 sig = mono_method_signature (cfg->method);
1772 if (!cfg->arch.cinfo)
1773 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1774 cinfo = (CallInfo *)cfg->arch.cinfo;
1776 if (cinfo->ret.storage == ArgValuetypeInReg)
1777 cfg->ret_var_is_local = TRUE;
1779 sig_ret = mini_get_underlying_type (sig->ret);
1780 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1781 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1782 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1783 printf ("vret_addr = ");
1784 mono_print_ins (cfg->vret_addr);
1788 if (cfg->gen_sdb_seq_points) {
1791 if (cfg->compile_aot) {
1792 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1793 ins->flags |= MONO_INST_VOLATILE;
1794 cfg->arch.seq_point_info_var = ins;
1796 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1797 ins->flags |= MONO_INST_VOLATILE;
1798 cfg->arch.ss_tramp_var = ins;
1800 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1801 ins->flags |= MONO_INST_VOLATILE;
1802 cfg->arch.bp_tramp_var = ins;
1805 if (cfg->method->save_lmf)
1806 cfg->create_lmf_var = TRUE;
1808 if (cfg->method->save_lmf) {
1814 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1820 MONO_INST_NEW (cfg, ins, OP_MOVE);
1821 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1822 ins->sreg1 = tree->dreg;
1823 MONO_ADD_INS (cfg->cbb, ins);
1824 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1826 case ArgInFloatSSEReg:
1827 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1828 ins->dreg = mono_alloc_freg (cfg);
1829 ins->sreg1 = tree->dreg;
1830 MONO_ADD_INS (cfg->cbb, ins);
1832 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1834 case ArgInDoubleSSEReg:
1835 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1836 ins->dreg = mono_alloc_freg (cfg);
1837 ins->sreg1 = tree->dreg;
1838 MONO_ADD_INS (cfg->cbb, ins);
1840 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1844 g_assert_not_reached ();
1849 arg_storage_to_load_membase (ArgStorage storage)
1853 #if defined(__mono_ilp32__)
1854 return OP_LOADI8_MEMBASE;
1856 return OP_LOAD_MEMBASE;
1858 case ArgInDoubleSSEReg:
1859 return OP_LOADR8_MEMBASE;
1860 case ArgInFloatSSEReg:
1861 return OP_LOADR4_MEMBASE;
1863 g_assert_not_reached ();
1870 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1872 MonoMethodSignature *tmp_sig;
1875 if (call->tail_call)
1878 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1881 * mono_ArgIterator_Setup assumes the signature cookie is
1882 * passed first and all the arguments which were before it are
1883 * passed on the stack after the signature. So compensate by
1884 * passing a different signature.
1886 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1887 tmp_sig->param_count -= call->signature->sentinelpos;
1888 tmp_sig->sentinelpos = 0;
1889 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1891 sig_reg = mono_alloc_ireg (cfg);
1892 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1894 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1898 static inline LLVMArgStorage
1899 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1903 return LLVMArgInIReg;
1906 case ArgGSharedVtInReg:
1907 case ArgGSharedVtOnStack:
1908 return LLVMArgGSharedVt;
1910 g_assert_not_reached ();
1916 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1922 LLVMCallInfo *linfo;
1923 MonoType *t, *sig_ret;
1925 n = sig->param_count + sig->hasthis;
1926 sig_ret = mini_get_underlying_type (sig->ret);
1928 cinfo = get_call_info (cfg->mempool, sig);
1930 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1933 * LLVM always uses the native ABI while we use our own ABI, the
1934 * only difference is the handling of vtypes:
1935 * - we only pass/receive them in registers in some cases, and only
1936 * in 1 or 2 integer registers.
1938 switch (cinfo->ret.storage) {
1940 linfo->ret.storage = LLVMArgNone;
1943 case ArgInFloatSSEReg:
1944 case ArgInDoubleSSEReg:
1945 linfo->ret.storage = LLVMArgNormal;
1947 case ArgValuetypeInReg: {
1948 ainfo = &cinfo->ret;
1951 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1952 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1953 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1954 cfg->disable_llvm = TRUE;
1958 linfo->ret.storage = LLVMArgVtypeInReg;
1959 for (j = 0; j < 2; ++j)
1960 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1963 case ArgValuetypeAddrInIReg:
1964 case ArgGsharedvtVariableInReg:
1965 /* Vtype returned using a hidden argument */
1966 linfo->ret.storage = LLVMArgVtypeRetAddr;
1967 linfo->vret_arg_index = cinfo->vret_arg_index;
1970 g_assert_not_reached ();
1974 for (i = 0; i < n; ++i) {
1975 ainfo = cinfo->args + i;
1977 if (i >= sig->hasthis)
1978 t = sig->params [i - sig->hasthis];
1980 t = &mono_defaults.int_class->byval_arg;
1981 t = mini_type_get_underlying_type (t);
1983 linfo->args [i].storage = LLVMArgNone;
1985 switch (ainfo->storage) {
1987 linfo->args [i].storage = LLVMArgNormal;
1989 case ArgInDoubleSSEReg:
1990 case ArgInFloatSSEReg:
1991 linfo->args [i].storage = LLVMArgNormal;
1994 if (MONO_TYPE_ISSTRUCT (t))
1995 linfo->args [i].storage = LLVMArgVtypeByVal;
1997 linfo->args [i].storage = LLVMArgNormal;
1999 case ArgValuetypeInReg:
2001 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2002 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2003 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2004 cfg->disable_llvm = TRUE;
2008 linfo->args [i].storage = LLVMArgVtypeInReg;
2009 for (j = 0; j < 2; ++j)
2010 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2012 case ArgGSharedVtInReg:
2013 case ArgGSharedVtOnStack:
2014 linfo->args [i].storage = LLVMArgGSharedVt;
2017 cfg->exception_message = g_strdup ("ainfo->storage");
2018 cfg->disable_llvm = TRUE;
2028 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2031 MonoMethodSignature *sig;
2037 sig = call->signature;
2038 n = sig->param_count + sig->hasthis;
2040 cinfo = get_call_info (cfg->mempool, sig);
2044 if (COMPILE_LLVM (cfg)) {
2045 /* We shouldn't be called in the llvm case */
2046 cfg->disable_llvm = TRUE;
2051 * Emit all arguments which are passed on the stack to prevent register
2052 * allocation problems.
2054 for (i = 0; i < n; ++i) {
2056 ainfo = cinfo->args + i;
2058 in = call->args [i];
2060 if (sig->hasthis && i == 0)
2061 t = &mono_defaults.object_class->byval_arg;
2063 t = sig->params [i - sig->hasthis];
2065 t = mini_get_underlying_type (t);
2066 //XXX what about ArgGSharedVtOnStack here?
2067 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2069 if (t->type == MONO_TYPE_R4)
2070 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2071 else if (t->type == MONO_TYPE_R8)
2072 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2074 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2076 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2078 if (cfg->compute_gc_maps) {
2081 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2087 * Emit all parameters passed in registers in non-reverse order for better readability
2088 * and to help the optimization in emit_prolog ().
2090 for (i = 0; i < n; ++i) {
2091 ainfo = cinfo->args + i;
2093 in = call->args [i];
2095 if (ainfo->storage == ArgInIReg)
2096 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2099 for (i = n - 1; i >= 0; --i) {
2102 ainfo = cinfo->args + i;
2104 in = call->args [i];
2106 if (sig->hasthis && i == 0)
2107 t = &mono_defaults.object_class->byval_arg;
2109 t = sig->params [i - sig->hasthis];
2110 t = mini_get_underlying_type (t);
2112 switch (ainfo->storage) {
2116 case ArgInFloatSSEReg:
2117 case ArgInDoubleSSEReg:
2118 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2121 case ArgValuetypeInReg:
2122 case ArgValuetypeAddrInIReg:
2123 case ArgValuetypeAddrOnStack:
2124 case ArgGSharedVtInReg:
2125 case ArgGSharedVtOnStack: {
2126 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2127 /* Already emitted above */
2129 //FIXME what about ArgGSharedVtOnStack ?
2130 if (ainfo->storage == ArgOnStack && call->tail_call) {
2131 MonoInst *call_inst = (MonoInst*)call;
2132 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2133 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2141 size = mono_type_native_stack_size (t, &align);
2144 * Other backends use mono_type_stack_size (), but that
2145 * aligns the size to 8, which is larger than the size of
2146 * the source, leading to reads of invalid memory if the
2147 * source is at the end of address space.
2149 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2152 if (size >= 10000) {
2153 /* Avoid asserts in emit_memcpy () */
2154 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2155 /* Continue normally */
2158 if (size > 0 || ainfo->pass_empty_struct) {
2159 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2160 arg->sreg1 = in->dreg;
2161 arg->klass = mono_class_from_mono_type (t);
2162 arg->backend.size = size;
2163 arg->inst_p0 = call;
2164 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2165 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2167 MONO_ADD_INS (cfg->cbb, arg);
2172 g_assert_not_reached ();
2175 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2176 /* Emit the signature cookie just before the implicit arguments */
2177 emit_sig_cookie (cfg, call, cinfo);
2180 /* Handle the case where there are no implicit arguments */
2181 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2182 emit_sig_cookie (cfg, call, cinfo);
2184 switch (cinfo->ret.storage) {
2185 case ArgValuetypeInReg:
2186 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2188 * Tell the JIT to use a more efficient calling convention: call using
2189 * OP_CALL, compute the result location after the call, and save the
2192 call->vret_in_reg = TRUE;
2194 * Nullify the instruction computing the vret addr to enable
2195 * future optimizations.
2198 NULLIFY_INS (call->vret_var);
2200 if (call->tail_call)
2203 * The valuetype is in RAX:RDX after the call, need to be copied to
2204 * the stack. Push the address here, so the call instruction can
2207 if (!cfg->arch.vret_addr_loc) {
2208 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2209 /* Prevent it from being register allocated or optimized away */
2210 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2213 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2216 case ArgValuetypeAddrInIReg:
2217 case ArgGsharedvtVariableInReg: {
2219 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2220 vtarg->sreg1 = call->vret_var->dreg;
2221 vtarg->dreg = mono_alloc_preg (cfg);
2222 MONO_ADD_INS (cfg->cbb, vtarg);
2224 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2231 if (cfg->method->save_lmf) {
2232 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2233 MONO_ADD_INS (cfg->cbb, arg);
2236 call->stack_usage = cinfo->stack_usage;
2240 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2243 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2244 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2245 int size = ins->backend.size;
2247 switch (ainfo->storage) {
2248 case ArgValuetypeInReg: {
2252 for (part = 0; part < 2; ++part) {
2253 if (ainfo->pair_storage [part] == ArgNone)
2256 if (ainfo->pass_empty_struct) {
2257 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2258 NEW_ICONST (cfg, load, 0);
2261 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2262 load->inst_basereg = src->dreg;
2263 load->inst_offset = part * sizeof(mgreg_t);
2265 switch (ainfo->pair_storage [part]) {
2267 load->dreg = mono_alloc_ireg (cfg);
2269 case ArgInDoubleSSEReg:
2270 case ArgInFloatSSEReg:
2271 load->dreg = mono_alloc_freg (cfg);
2274 g_assert_not_reached ();
2278 MONO_ADD_INS (cfg->cbb, load);
2280 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2284 case ArgValuetypeAddrInIReg:
2285 case ArgValuetypeAddrOnStack: {
2286 MonoInst *vtaddr, *load;
2288 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2290 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2292 MONO_INST_NEW (cfg, load, OP_LDADDR);
2293 cfg->has_indirection = TRUE;
2294 load->inst_p0 = vtaddr;
2295 vtaddr->flags |= MONO_INST_INDIRECT;
2296 load->type = STACK_MP;
2297 load->klass = vtaddr->klass;
2298 load->dreg = mono_alloc_ireg (cfg);
2299 MONO_ADD_INS (cfg->cbb, load);
2300 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, SIZEOF_VOID_P);
2302 if (ainfo->pair_storage [0] == ArgInIReg) {
2303 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2304 arg->dreg = mono_alloc_ireg (cfg);
2305 arg->sreg1 = load->dreg;
2307 MONO_ADD_INS (cfg->cbb, arg);
2308 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2310 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2314 case ArgGSharedVtInReg:
2316 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2318 case ArgGSharedVtOnStack:
2319 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2323 int dreg = mono_alloc_ireg (cfg);
2325 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2326 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2327 } else if (size <= 40) {
2328 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2330 // FIXME: Code growth
2331 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2334 if (cfg->compute_gc_maps) {
2336 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2342 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2344 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2346 if (ret->type == MONO_TYPE_R4) {
2347 if (COMPILE_LLVM (cfg))
2348 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2350 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2352 } else if (ret->type == MONO_TYPE_R8) {
2353 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2357 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2360 #endif /* DISABLE_JIT */
2362 #define EMIT_COND_BRANCH(ins,cond,sign) \
2363 if (ins->inst_true_bb->native_offset) { \
2364 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2366 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2367 if ((cfg->opt & MONO_OPT_BRANCH) && \
2368 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2369 x86_branch8 (code, cond, 0, sign); \
2371 x86_branch32 (code, cond, 0, sign); \
2375 MonoMethodSignature *sig;
2381 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2385 switch (cinfo->ret.storage) {
2388 case ArgInFloatSSEReg:
2389 case ArgInDoubleSSEReg:
2390 case ArgValuetypeAddrInIReg:
2391 case ArgValuetypeInReg:
2397 for (i = 0; i < cinfo->nargs; ++i) {
2398 ArgInfo *ainfo = &cinfo->args [i];
2399 switch (ainfo->storage) {
2401 case ArgInFloatSSEReg:
2402 case ArgInDoubleSSEReg:
2403 case ArgValuetypeInReg:
2415 * mono_arch_dyn_call_prepare:
2417 * Return a pointer to an arch-specific structure which contains information
2418 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2419 * supported for SIG.
2420 * This function is equivalent to ffi_prep_cif in libffi.
2423 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2425 ArchDynCallInfo *info;
2429 cinfo = get_call_info (NULL, sig);
2431 if (!dyn_call_supported (sig, cinfo)) {
2436 info = g_new0 (ArchDynCallInfo, 1);
2437 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2439 info->cinfo = cinfo;
2440 info->nstack_args = 0;
2442 for (i = 0; i < cinfo->nargs; ++i) {
2443 ArgInfo *ainfo = &cinfo->args [i];
2444 switch (ainfo->storage) {
2446 info->nstack_args = MAX (info->nstack_args, ainfo->offset + (ainfo->arg_size / 8));
2452 /* Align to 16 bytes */
2453 if (info->nstack_args & 1)
2454 info->nstack_args ++;
2456 return (MonoDynCallInfo*)info;
2460 * mono_arch_dyn_call_free:
2462 * Free a MonoDynCallInfo structure.
2465 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2467 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2469 g_free (ainfo->cinfo);
2474 mono_arch_dyn_call_get_buf_size (MonoDynCallInfo *info)
2476 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2478 /* Extend the 'regs' field dynamically */
2479 return sizeof (DynCallArgs) + (ainfo->nstack_args * sizeof (mgreg_t));
2482 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2483 #define GREG_TO_PTR(greg) (gpointer)(greg)
2486 * mono_arch_get_start_dyn_call:
2488 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2489 * store the result into BUF.
2490 * ARGS should be an array of pointers pointing to the arguments.
2491 * RET should point to a memory buffer large enought to hold the result of the
2493 * This function should be as fast as possible, any work which does not depend
2494 * on the actual values of the arguments should be done in
2495 * mono_arch_dyn_call_prepare ().
2496 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2500 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf)
2502 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2503 DynCallArgs *p = (DynCallArgs*)buf;
2504 int arg_index, greg, freg, i, pindex;
2505 MonoMethodSignature *sig = dinfo->sig;
2506 int buffer_offset = 0;
2507 static int param_reg_to_index [16];
2508 static gboolean param_reg_to_index_inited;
2510 if (!param_reg_to_index_inited) {
2511 for (i = 0; i < PARAM_REGS; ++i)
2512 param_reg_to_index [param_regs [i]] = i;
2513 mono_memory_barrier ();
2514 param_reg_to_index_inited = 1;
2519 p->nstack_args = dinfo->nstack_args;
2526 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2527 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2532 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2533 p->regs [greg ++] = PTR_TO_GREG(ret);
2535 for (; pindex < sig->param_count; pindex++) {
2536 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2537 gpointer *arg = args [arg_index ++];
2538 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2541 if (ainfo->storage == ArgOnStack) {
2542 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2544 slot = param_reg_to_index [ainfo->reg];
2548 p->regs [slot] = PTR_TO_GREG(*(arg));
2554 case MONO_TYPE_OBJECT:
2558 #if !defined(__mono_ilp32__)
2562 p->regs [slot] = PTR_TO_GREG(*(arg));
2564 #if defined(__mono_ilp32__)
2567 p->regs [slot] = *(guint64*)(arg);
2571 p->regs [slot] = *(guint8*)(arg);
2574 p->regs [slot] = *(gint8*)(arg);
2577 p->regs [slot] = *(gint16*)(arg);
2580 p->regs [slot] = *(guint16*)(arg);
2583 p->regs [slot] = *(gint32*)(arg);
2586 p->regs [slot] = *(guint32*)(arg);
2588 case MONO_TYPE_R4: {
2591 *(float*)&d = *(float*)(arg);
2593 p->fregs [freg ++] = d;
2598 p->fregs [freg ++] = *(double*)(arg);
2600 case MONO_TYPE_GENERICINST:
2601 if (MONO_TYPE_IS_REFERENCE (t)) {
2602 p->regs [slot] = PTR_TO_GREG(*(arg));
2604 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2605 MonoClass *klass = mono_class_from_mono_type (t);
2606 guint8 *nullable_buf;
2609 size = mono_class_value_size (klass, NULL);
2610 nullable_buf = p->buffer + buffer_offset;
2611 buffer_offset += size;
2612 g_assert (buffer_offset <= 256);
2614 /* The argument pointed to by arg is either a boxed vtype or null */
2615 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2617 arg = (gpointer*)nullable_buf;
2623 case MONO_TYPE_VALUETYPE: {
2624 switch (ainfo->storage) {
2625 case ArgValuetypeInReg:
2626 for (i = 0; i < 2; ++i) {
2627 switch (ainfo->pair_storage [i]) {
2631 slot = param_reg_to_index [ainfo->pair_regs [i]];
2632 p->regs [slot] = ((mgreg_t*)(arg))[i];
2634 case ArgInDoubleSSEReg:
2636 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2639 g_assert_not_reached ();
2645 for (i = 0; i < ainfo->arg_size / 8; ++i)
2646 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2649 g_assert_not_reached ();
2655 g_assert_not_reached ();
2661 * mono_arch_finish_dyn_call:
2663 * Store the result of a dyn call into the return value buffer passed to
2664 * start_dyn_call ().
2665 * This function should be as fast as possible, any work which does not depend
2666 * on the actual values of the arguments should be done in
2667 * mono_arch_dyn_call_prepare ().
2670 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2672 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2673 MonoMethodSignature *sig = dinfo->sig;
2674 DynCallArgs *dargs = (DynCallArgs*)buf;
2675 guint8 *ret = dargs->ret;
2676 mgreg_t res = dargs->res;
2677 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2680 switch (sig_ret->type) {
2681 case MONO_TYPE_VOID:
2682 *(gpointer*)ret = NULL;
2684 case MONO_TYPE_OBJECT:
2688 *(gpointer*)ret = GREG_TO_PTR(res);
2694 *(guint8*)ret = res;
2697 *(gint16*)ret = res;
2700 *(guint16*)ret = res;
2703 *(gint32*)ret = res;
2706 *(guint32*)ret = res;
2709 *(gint64*)ret = res;
2712 *(guint64*)ret = res;
2715 *(float*)ret = *(float*)&(dargs->fregs [0]);
2718 *(double*)ret = dargs->fregs [0];
2720 case MONO_TYPE_GENERICINST:
2721 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2722 *(gpointer*)ret = GREG_TO_PTR(res);
2727 case MONO_TYPE_VALUETYPE:
2728 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2731 ArgInfo *ainfo = &dinfo->cinfo->ret;
2733 g_assert (ainfo->storage == ArgValuetypeInReg);
2735 for (i = 0; i < 2; ++i) {
2736 switch (ainfo->pair_storage [0]) {
2738 ((mgreg_t*)ret)[i] = res;
2740 case ArgInDoubleSSEReg:
2741 ((double*)ret)[i] = dargs->fregs [i];
2746 g_assert_not_reached ();
2753 g_assert_not_reached ();
2757 /* emit an exception if condition is fail */
2758 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2760 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2761 if (tins == NULL) { \
2762 mono_add_patch_info (cfg, code - cfg->native_code, \
2763 MONO_PATCH_INFO_EXC, exc_name); \
2764 x86_branch32 (code, cond, 0, signed); \
2766 EMIT_COND_BRANCH (tins, cond, signed); \
2770 #define EMIT_FPCOMPARE(code) do { \
2771 amd64_fcompp (code); \
2772 amd64_fnstsw (code); \
2775 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2776 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2777 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2778 amd64_ ##op (code); \
2779 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2780 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2784 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2786 gboolean no_patch = FALSE;
2789 * FIXME: Add support for thunks
2792 gboolean near_call = FALSE;
2795 * Indirect calls are expensive so try to make a near call if possible.
2796 * The caller memory is allocated by the code manager so it is
2797 * guaranteed to be at a 32 bit offset.
2800 if (patch_type != MONO_PATCH_INFO_ABS) {
2801 /* The target is in memory allocated using the code manager */
2804 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2805 if (((MonoMethod*)data)->klass->image->aot_module)
2806 /* The callee might be an AOT method */
2808 if (((MonoMethod*)data)->dynamic)
2809 /* The target is in malloc-ed memory */
2813 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2815 * The call might go directly to a native function without
2818 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2820 gconstpointer target = mono_icall_get_wrapper (mi);
2821 if ((((guint64)target) >> 32) != 0)
2827 MonoJumpInfo *jinfo = NULL;
2829 if (cfg->abs_patches)
2830 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2832 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2833 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2834 if (mi && (((guint64)mi->func) >> 32) == 0)
2839 * This is not really an optimization, but required because the
2840 * generic class init trampolines use R11 to pass the vtable.
2845 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2847 if (info->func == info->wrapper) {
2849 if ((((guint64)info->func) >> 32) == 0)
2853 /* See the comment in mono_codegen () */
2854 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2858 else if ((((guint64)data) >> 32) == 0) {
2865 if (cfg->method->dynamic)
2866 /* These methods are allocated using malloc */
2869 #ifdef MONO_ARCH_NOMAP32BIT
2872 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2873 if (optimize_for_xen)
2876 if (cfg->compile_aot) {
2883 * Align the call displacement to an address divisible by 4 so it does
2884 * not span cache lines. This is required for code patching to work on SMP
2887 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2888 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2889 amd64_padding (code, pad_size);
2891 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2892 amd64_call_code (code, 0);
2895 if (!no_patch && ((guint32)(code + 2 - cfg->native_code) % 8) != 0) {
2896 guint32 pad_size = 8 - ((guint32)(code + 2 - cfg->native_code) % 8);
2897 amd64_padding (code, pad_size);
2898 g_assert ((guint64)(code + 2 - cfg->native_code) % 8 == 0);
2900 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2901 amd64_set_reg_template (code, GP_SCRATCH_REG);
2902 amd64_call_reg (code, GP_SCRATCH_REG);
2909 static inline guint8*
2910 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2913 if (win64_adjust_stack)
2914 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2916 code = emit_call_body (cfg, code, patch_type, data);
2918 if (win64_adjust_stack)
2919 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2926 store_membase_imm_to_store_membase_reg (int opcode)
2929 case OP_STORE_MEMBASE_IMM:
2930 return OP_STORE_MEMBASE_REG;
2931 case OP_STOREI4_MEMBASE_IMM:
2932 return OP_STOREI4_MEMBASE_REG;
2933 case OP_STOREI8_MEMBASE_IMM:
2934 return OP_STOREI8_MEMBASE_REG;
2942 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2945 * mono_arch_peephole_pass_1:
2947 * Perform peephole opts which should/can be performed before local regalloc
2950 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2954 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2955 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2957 switch (ins->opcode) {
2961 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2963 * X86_LEA is like ADD, but doesn't have the
2964 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2965 * its operand to 64 bit.
2967 ins->opcode = OP_X86_LEA_MEMBASE;
2968 ins->inst_basereg = ins->sreg1;
2973 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2977 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2978 * the latter has length 2-3 instead of 6 (reverse constant
2979 * propagation). These instruction sequences are very common
2980 * in the initlocals bblock.
2982 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2983 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2984 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2985 ins2->sreg1 = ins->dreg;
2986 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2988 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2991 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2999 case OP_COMPARE_IMM:
3000 case OP_LCOMPARE_IMM:
3001 /* OP_COMPARE_IMM (reg, 0)
3003 * OP_AMD64_TEST_NULL (reg)
3006 ins->opcode = OP_AMD64_TEST_NULL;
3008 case OP_ICOMPARE_IMM:
3010 ins->opcode = OP_X86_TEST_NULL;
3012 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3014 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3015 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3017 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3018 * OP_COMPARE_IMM reg, imm
3020 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3022 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3023 ins->inst_basereg == last_ins->inst_destbasereg &&
3024 ins->inst_offset == last_ins->inst_offset) {
3025 ins->opcode = OP_ICOMPARE_IMM;
3026 ins->sreg1 = last_ins->sreg1;
3028 /* check if we can remove cmp reg,0 with test null */
3030 ins->opcode = OP_X86_TEST_NULL;
3036 mono_peephole_ins (bb, ins);
3041 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3045 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3046 switch (ins->opcode) {
3049 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3050 /* reg = 0 -> XOR (reg, reg) */
3051 /* XOR sets cflags on x86, so we cant do it always */
3052 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3053 ins->opcode = OP_LXOR;
3054 ins->sreg1 = ins->dreg;
3055 ins->sreg2 = ins->dreg;
3063 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3064 * 0 result into 64 bits.
3066 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3067 ins->opcode = OP_IXOR;
3071 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3075 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3076 * the latter has length 2-3 instead of 6 (reverse constant
3077 * propagation). These instruction sequences are very common
3078 * in the initlocals bblock.
3080 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3081 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3082 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3083 ins2->sreg1 = ins->dreg;
3084 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3086 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3089 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3098 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3099 ins->opcode = OP_X86_INC_REG;
3102 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3103 ins->opcode = OP_X86_DEC_REG;
3107 mono_peephole_ins (bb, ins);
3111 #define NEW_INS(cfg,ins,dest,op) do { \
3112 MONO_INST_NEW ((cfg), (dest), (op)); \
3113 (dest)->cil_code = (ins)->cil_code; \
3114 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3118 * mono_arch_lowering_pass:
3120 * Converts complex opcodes into simpler ones so that each IR instruction
3121 * corresponds to one machine instruction.
3124 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3126 MonoInst *ins, *n, *temp;
3129 * FIXME: Need to add more instructions, but the current machine
3130 * description can't model some parts of the composite instructions like
3133 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3134 switch (ins->opcode) {
3138 case OP_IDIV_UN_IMM:
3139 case OP_IREM_UN_IMM:
3142 mono_decompose_op_imm (cfg, bb, ins);
3144 case OP_COMPARE_IMM:
3145 case OP_LCOMPARE_IMM:
3146 if (!amd64_use_imm32 (ins->inst_imm)) {
3147 NEW_INS (cfg, ins, temp, OP_I8CONST);
3148 temp->inst_c0 = ins->inst_imm;
3149 temp->dreg = mono_alloc_ireg (cfg);
3150 ins->opcode = OP_COMPARE;
3151 ins->sreg2 = temp->dreg;
3154 #ifndef __mono_ilp32__
3155 case OP_LOAD_MEMBASE:
3157 case OP_LOADI8_MEMBASE:
3158 /* Don't generate memindex opcodes (to simplify */
3159 /* read sandboxing) */
3160 if (!amd64_use_imm32 (ins->inst_offset)) {
3161 NEW_INS (cfg, ins, temp, OP_I8CONST);
3162 temp->inst_c0 = ins->inst_offset;
3163 temp->dreg = mono_alloc_ireg (cfg);
3164 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3165 ins->inst_indexreg = temp->dreg;
3168 #ifndef __mono_ilp32__
3169 case OP_STORE_MEMBASE_IMM:
3171 case OP_STOREI8_MEMBASE_IMM:
3172 if (!amd64_use_imm32 (ins->inst_imm)) {
3173 NEW_INS (cfg, ins, temp, OP_I8CONST);
3174 temp->inst_c0 = ins->inst_imm;
3175 temp->dreg = mono_alloc_ireg (cfg);
3176 ins->opcode = OP_STOREI8_MEMBASE_REG;
3177 ins->sreg1 = temp->dreg;
3180 #ifdef MONO_ARCH_SIMD_INTRINSICS
3181 case OP_EXPAND_I1: {
3182 int temp_reg1 = mono_alloc_ireg (cfg);
3183 int temp_reg2 = mono_alloc_ireg (cfg);
3184 int original_reg = ins->sreg1;
3186 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3187 temp->sreg1 = original_reg;
3188 temp->dreg = temp_reg1;
3190 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3191 temp->sreg1 = temp_reg1;
3192 temp->dreg = temp_reg2;
3195 NEW_INS (cfg, ins, temp, OP_LOR);
3196 temp->sreg1 = temp->dreg = temp_reg2;
3197 temp->sreg2 = temp_reg1;
3199 ins->opcode = OP_EXPAND_I2;
3200 ins->sreg1 = temp_reg2;
3209 bb->max_vreg = cfg->next_vreg;
3213 branch_cc_table [] = {
3214 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3215 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3216 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3219 /* Maps CMP_... constants to X86_CC_... constants */
3222 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3223 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3227 cc_signed_table [] = {
3228 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3229 FALSE, FALSE, FALSE, FALSE
3232 /*#include "cprop.c"*/
3234 static unsigned char*
3235 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3238 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3240 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3243 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3245 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3249 static unsigned char*
3250 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3252 int sreg = tree->sreg1;
3253 int need_touch = FALSE;
3255 #if defined(TARGET_WIN32)
3257 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3258 if (!(tree->flags & MONO_INST_INIT))
3267 * If requested stack size is larger than one page,
3268 * perform stack-touch operation
3271 * Generate stack probe code.
3272 * Under Windows, it is necessary to allocate one page at a time,
3273 * "touching" stack after each successful sub-allocation. This is
3274 * because of the way stack growth is implemented - there is a
3275 * guard page before the lowest stack page that is currently commited.
3276 * Stack normally grows sequentially so OS traps access to the
3277 * guard page and commits more pages when needed.
3279 amd64_test_reg_imm (code, sreg, ~0xFFF);
3280 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3282 br[2] = code; /* loop */
3283 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3284 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3285 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3286 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3287 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3288 amd64_patch (br[3], br[2]);
3289 amd64_test_reg_reg (code, sreg, sreg);
3290 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3291 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3293 br[1] = code; x86_jump8 (code, 0);
3295 amd64_patch (br[0], code);
3296 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3297 amd64_patch (br[1], code);
3298 amd64_patch (br[4], code);
3301 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3303 if (tree->flags & MONO_INST_INIT) {
3305 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3306 amd64_push_reg (code, AMD64_RAX);
3309 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3310 amd64_push_reg (code, AMD64_RCX);
3313 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3314 amd64_push_reg (code, AMD64_RDI);
3318 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3319 if (sreg != AMD64_RCX)
3320 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3321 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3323 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3324 if (cfg->param_area)
3325 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3327 amd64_prefix (code, X86_REP_PREFIX);
3330 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3331 amd64_pop_reg (code, AMD64_RDI);
3332 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3333 amd64_pop_reg (code, AMD64_RCX);
3334 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3335 amd64_pop_reg (code, AMD64_RAX);
3341 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3346 /* Move return value to the target register */
3347 /* FIXME: do this in the local reg allocator */
3348 switch (ins->opcode) {
3351 case OP_CALL_MEMBASE:
3354 case OP_LCALL_MEMBASE:
3355 g_assert (ins->dreg == AMD64_RAX);
3359 case OP_FCALL_MEMBASE: {
3360 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3361 if (rtype->type == MONO_TYPE_R4) {
3362 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3365 if (ins->dreg != AMD64_XMM0)
3366 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3372 case OP_RCALL_MEMBASE:
3373 if (ins->dreg != AMD64_XMM0)
3374 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3378 case OP_VCALL_MEMBASE:
3381 case OP_VCALL2_MEMBASE:
3382 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3383 if (cinfo->ret.storage == ArgValuetypeInReg) {
3384 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3386 /* Load the destination address */
3387 g_assert (loc->opcode == OP_REGOFFSET);
3388 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3390 for (quad = 0; quad < 2; quad ++) {
3391 switch (cinfo->ret.pair_storage [quad]) {
3393 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3395 case ArgInFloatSSEReg:
3396 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3398 case ArgInDoubleSSEReg:
3399 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3414 #endif /* DISABLE_JIT */
3417 static int tls_gs_offset;
3421 mono_arch_have_fast_tls (void)
3424 static gboolean have_fast_tls = FALSE;
3425 static gboolean inited = FALSE;
3428 if (mini_get_debug_options ()->use_fallback_tls)
3432 return have_fast_tls;
3434 ins = (guint8*)pthread_getspecific;
3437 * We're looking for these two instructions:
3439 * mov %gs:[offset](,%rdi,8),%rax
3442 have_fast_tls = ins [0] == 0x65 &&
3452 tls_gs_offset = ins[5];
3455 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3456 * For that version we're looking for these instructions:
3460 * mov %gs:[offset](,%rdi,8),%rax
3464 if (!have_fast_tls) {
3465 have_fast_tls = ins [0] == 0x55 &&
3480 tls_gs_offset = ins[9];
3484 return have_fast_tls;
3485 #elif defined(TARGET_ANDROID)
3488 if (mini_get_debug_options ()->use_fallback_tls)
3495 mono_amd64_get_tls_gs_offset (void)
3498 return tls_gs_offset;
3500 g_assert_not_reached ();
3506 * \param code buffer to store code to
3507 * \param dreg hard register where to place the result
3508 * \param tls_offset offset info
3509 * \return a pointer to the end of the stored code
3511 * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3512 * the dreg register the item in the thread local storage identified
3516 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3519 if (tls_offset < 64) {
3520 x86_prefix (code, X86_GS_PREFIX);
3521 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3525 g_assert (tls_offset < 0x440);
3526 /* Load TEB->TlsExpansionSlots */
3527 x86_prefix (code, X86_GS_PREFIX);
3528 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3529 amd64_test_reg_reg (code, dreg, dreg);
3531 amd64_branch (code, X86_CC_EQ, code, TRUE);
3532 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3533 amd64_patch (buf [0], code);
3535 #elif defined(TARGET_MACH)
3536 x86_prefix (code, X86_GS_PREFIX);
3537 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3539 if (optimize_for_xen) {
3540 x86_prefix (code, X86_FS_PREFIX);
3541 amd64_mov_reg_mem (code, dreg, 0, 8);
3542 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3544 x86_prefix (code, X86_FS_PREFIX);
3545 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3552 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3555 g_assert_not_reached ();
3556 #elif defined(TARGET_MACH)
3557 x86_prefix (code, X86_GS_PREFIX);
3558 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3560 g_assert (!optimize_for_xen);
3561 x86_prefix (code, X86_FS_PREFIX);
3562 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3570 * Emit code to initialize an LMF structure at LMF_OFFSET.
3573 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3576 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3579 * sp is saved right before calls but we need to save it here too so
3580 * async stack walks would work.
3582 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3584 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3585 if (cfg->arch.omit_fp && cfa_offset != -1)
3586 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3588 /* These can't contain refs */
3589 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3590 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3591 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3592 /* These are handled automatically by the stack marking code */
3593 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3600 #define TEB_LAST_ERROR_OFFSET 0x068
3603 emit_get_last_error (guint8* code, int dreg)
3605 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3606 x86_prefix (code, X86_GS_PREFIX);
3607 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3615 emit_get_last_error (guint8* code, int dreg)
3617 g_assert_not_reached ();
3622 /* benchmark and set based on cpu */
3623 #define LOOP_ALIGNMENT 8
3624 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3628 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3633 guint8 *code = cfg->native_code + cfg->code_len;
3636 /* Fix max_offset estimate for each successor bb */
3637 if (cfg->opt & MONO_OPT_BRANCH) {
3638 int current_offset = cfg->code_len;
3639 MonoBasicBlock *current_bb;
3640 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3641 current_bb->max_offset = current_offset;
3642 current_offset += current_bb->max_length;
3646 if (cfg->opt & MONO_OPT_LOOP) {
3647 int pad, align = LOOP_ALIGNMENT;
3648 /* set alignment depending on cpu */
3649 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3651 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3652 amd64_padding (code, pad);
3653 cfg->code_len += pad;
3654 bb->native_offset = cfg->code_len;
3658 if (cfg->verbose_level > 2)
3659 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3661 offset = code - cfg->native_code;
3663 mono_debug_open_block (cfg, bb, offset);
3665 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3666 x86_breakpoint (code);
3668 MONO_BB_FOR_EACH_INS (bb, ins) {
3669 offset = code - cfg->native_code;
3671 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3673 #define EXTRA_CODE_SPACE (16)
3675 if (G_UNLIKELY ((offset + max_len + EXTRA_CODE_SPACE) > cfg->code_size)) {
3676 cfg->code_size *= 2;
3677 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3678 code = cfg->native_code + offset;
3679 cfg->stat_code_reallocs++;
3682 if (cfg->debug_info)
3683 mono_debug_record_line_number (cfg, ins, offset);
3685 switch (ins->opcode) {
3687 amd64_mul_reg (code, ins->sreg2, TRUE);
3690 amd64_mul_reg (code, ins->sreg2, FALSE);
3692 case OP_X86_SETEQ_MEMBASE:
3693 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3695 case OP_STOREI1_MEMBASE_IMM:
3696 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3698 case OP_STOREI2_MEMBASE_IMM:
3699 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3701 case OP_STOREI4_MEMBASE_IMM:
3702 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3704 case OP_STOREI1_MEMBASE_REG:
3705 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3707 case OP_STOREI2_MEMBASE_REG:
3708 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3710 /* In AMD64 NaCl, pointers are 4 bytes, */
3711 /* so STORE_* != STOREI8_*. Likewise below. */
3712 case OP_STORE_MEMBASE_REG:
3713 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3715 case OP_STOREI8_MEMBASE_REG:
3716 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3718 case OP_STOREI4_MEMBASE_REG:
3719 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3721 case OP_STORE_MEMBASE_IMM:
3722 /* In NaCl, this could be a PCONST type, which could */
3723 /* mean a pointer type was copied directly into the */
3724 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3725 /* the value would be 0x00000000FFFFFFFF which is */
3726 /* not proper for an imm32 unless you cast it. */
3727 g_assert (amd64_is_imm32 (ins->inst_imm));
3728 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3730 case OP_STOREI8_MEMBASE_IMM:
3731 g_assert (amd64_is_imm32 (ins->inst_imm));
3732 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3735 #ifdef __mono_ilp32__
3736 /* In ILP32, pointers are 4 bytes, so separate these */
3737 /* cases, use literal 8 below where we really want 8 */
3738 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3739 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3743 // FIXME: Decompose this earlier
3744 if (amd64_use_imm32 (ins->inst_imm))
3745 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3747 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3748 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3752 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3753 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3756 // FIXME: Decompose this earlier
3757 if (amd64_use_imm32 (ins->inst_imm))
3758 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3760 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3761 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3765 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3766 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3769 /* For NaCl, pointers are 4 bytes, so separate these */
3770 /* cases, use literal 8 below where we really want 8 */
3771 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3772 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3774 case OP_LOAD_MEMBASE:
3775 g_assert (amd64_is_imm32 (ins->inst_offset));
3776 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3778 case OP_LOADI8_MEMBASE:
3779 /* Use literal 8 instead of sizeof pointer or */
3780 /* register, we really want 8 for this opcode */
3781 g_assert (amd64_is_imm32 (ins->inst_offset));
3782 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3784 case OP_LOADI4_MEMBASE:
3785 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3787 case OP_LOADU4_MEMBASE:
3788 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3790 case OP_LOADU1_MEMBASE:
3791 /* The cpu zero extends the result into 64 bits */
3792 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3794 case OP_LOADI1_MEMBASE:
3795 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3797 case OP_LOADU2_MEMBASE:
3798 /* The cpu zero extends the result into 64 bits */
3799 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3801 case OP_LOADI2_MEMBASE:
3802 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3804 case OP_AMD64_LOADI8_MEMINDEX:
3805 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3807 case OP_LCONV_TO_I1:
3808 case OP_ICONV_TO_I1:
3810 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3812 case OP_LCONV_TO_I2:
3813 case OP_ICONV_TO_I2:
3815 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3817 case OP_LCONV_TO_U1:
3818 case OP_ICONV_TO_U1:
3819 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3821 case OP_LCONV_TO_U2:
3822 case OP_ICONV_TO_U2:
3823 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3826 /* Clean out the upper word */
3827 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3830 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3834 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3836 case OP_COMPARE_IMM:
3837 #if defined(__mono_ilp32__)
3838 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3839 g_assert (amd64_is_imm32 (ins->inst_imm));
3840 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3843 case OP_LCOMPARE_IMM:
3844 g_assert (amd64_is_imm32 (ins->inst_imm));
3845 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3847 case OP_X86_COMPARE_REG_MEMBASE:
3848 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3850 case OP_X86_TEST_NULL:
3851 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3853 case OP_AMD64_TEST_NULL:
3854 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3857 case OP_X86_ADD_REG_MEMBASE:
3858 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3860 case OP_X86_SUB_REG_MEMBASE:
3861 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3863 case OP_X86_AND_REG_MEMBASE:
3864 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3866 case OP_X86_OR_REG_MEMBASE:
3867 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3869 case OP_X86_XOR_REG_MEMBASE:
3870 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3873 case OP_X86_ADD_MEMBASE_IMM:
3874 /* FIXME: Make a 64 version too */
3875 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3877 case OP_X86_SUB_MEMBASE_IMM:
3878 g_assert (amd64_is_imm32 (ins->inst_imm));
3879 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3881 case OP_X86_AND_MEMBASE_IMM:
3882 g_assert (amd64_is_imm32 (ins->inst_imm));
3883 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3885 case OP_X86_OR_MEMBASE_IMM:
3886 g_assert (amd64_is_imm32 (ins->inst_imm));
3887 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3889 case OP_X86_XOR_MEMBASE_IMM:
3890 g_assert (amd64_is_imm32 (ins->inst_imm));
3891 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3893 case OP_X86_ADD_MEMBASE_REG:
3894 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3896 case OP_X86_SUB_MEMBASE_REG:
3897 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3899 case OP_X86_AND_MEMBASE_REG:
3900 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3902 case OP_X86_OR_MEMBASE_REG:
3903 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3905 case OP_X86_XOR_MEMBASE_REG:
3906 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3908 case OP_X86_INC_MEMBASE:
3909 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3911 case OP_X86_INC_REG:
3912 amd64_inc_reg_size (code, ins->dreg, 4);
3914 case OP_X86_DEC_MEMBASE:
3915 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3917 case OP_X86_DEC_REG:
3918 amd64_dec_reg_size (code, ins->dreg, 4);
3920 case OP_X86_MUL_REG_MEMBASE:
3921 case OP_X86_MUL_MEMBASE_REG:
3922 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3924 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3925 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3927 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3928 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3930 case OP_AMD64_COMPARE_MEMBASE_REG:
3931 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3933 case OP_AMD64_COMPARE_MEMBASE_IMM:
3934 g_assert (amd64_is_imm32 (ins->inst_imm));
3935 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3937 case OP_X86_COMPARE_MEMBASE8_IMM:
3938 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3940 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3941 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3943 case OP_AMD64_COMPARE_REG_MEMBASE:
3944 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3947 case OP_AMD64_ADD_REG_MEMBASE:
3948 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3950 case OP_AMD64_SUB_REG_MEMBASE:
3951 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3953 case OP_AMD64_AND_REG_MEMBASE:
3954 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3956 case OP_AMD64_OR_REG_MEMBASE:
3957 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3959 case OP_AMD64_XOR_REG_MEMBASE:
3960 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3963 case OP_AMD64_ADD_MEMBASE_REG:
3964 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3966 case OP_AMD64_SUB_MEMBASE_REG:
3967 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3969 case OP_AMD64_AND_MEMBASE_REG:
3970 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3972 case OP_AMD64_OR_MEMBASE_REG:
3973 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3975 case OP_AMD64_XOR_MEMBASE_REG:
3976 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3979 case OP_AMD64_ADD_MEMBASE_IMM:
3980 g_assert (amd64_is_imm32 (ins->inst_imm));
3981 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3983 case OP_AMD64_SUB_MEMBASE_IMM:
3984 g_assert (amd64_is_imm32 (ins->inst_imm));
3985 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3987 case OP_AMD64_AND_MEMBASE_IMM:
3988 g_assert (amd64_is_imm32 (ins->inst_imm));
3989 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3991 case OP_AMD64_OR_MEMBASE_IMM:
3992 g_assert (amd64_is_imm32 (ins->inst_imm));
3993 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3995 case OP_AMD64_XOR_MEMBASE_IMM:
3996 g_assert (amd64_is_imm32 (ins->inst_imm));
3997 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4001 amd64_breakpoint (code);
4003 case OP_RELAXED_NOP:
4004 x86_prefix (code, X86_REP_PREFIX);
4012 case OP_DUMMY_STORE:
4013 case OP_DUMMY_ICONST:
4014 case OP_DUMMY_R8CONST:
4015 case OP_NOT_REACHED:
4018 case OP_IL_SEQ_POINT:
4019 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4021 case OP_SEQ_POINT: {
4022 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4023 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4026 /* Load ss_tramp_var */
4027 /* This is equal to &ss_trampoline */
4028 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4029 /* Load the trampoline address */
4030 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4031 /* Call it if it is non-null */
4032 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4034 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4035 amd64_call_reg (code, AMD64_R11);
4036 amd64_patch (label, code);
4040 * This is the address which is saved in seq points,
4042 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4044 if (cfg->compile_aot) {
4045 guint32 offset = code - cfg->native_code;
4047 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4051 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4052 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4053 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4054 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4055 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4057 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4058 /* Call the trampoline */
4059 amd64_call_reg (code, AMD64_R11);
4060 amd64_patch (label, code);
4062 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4066 * Emit a test+branch against a constant, the constant will be overwritten
4067 * by mono_arch_set_breakpoint () to cause the test to fail.
4069 amd64_mov_reg_imm (code, AMD64_R11, 0);
4070 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4072 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4075 g_assert (var->opcode == OP_REGOFFSET);
4076 /* Load bp_tramp_var */
4077 /* This is equal to &bp_trampoline */
4078 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4079 /* Call the trampoline */
4080 amd64_call_membase (code, AMD64_R11, 0);
4081 amd64_patch (label, code);
4084 * Add an additional nop so skipping the bp doesn't cause the ip to point
4085 * to another IL offset.
4093 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4096 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4100 g_assert (amd64_is_imm32 (ins->inst_imm));
4101 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4104 g_assert (amd64_is_imm32 (ins->inst_imm));
4105 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4110 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4113 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4117 g_assert (amd64_is_imm32 (ins->inst_imm));
4118 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4121 g_assert (amd64_is_imm32 (ins->inst_imm));
4122 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4125 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4129 g_assert (amd64_is_imm32 (ins->inst_imm));
4130 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4133 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4138 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4140 switch (ins->inst_imm) {
4144 if (ins->dreg != ins->sreg1)
4145 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4146 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4149 /* LEA r1, [r2 + r2*2] */
4150 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4153 /* LEA r1, [r2 + r2*4] */
4154 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4157 /* LEA r1, [r2 + r2*2] */
4159 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4160 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4163 /* LEA r1, [r2 + r2*8] */
4164 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4167 /* LEA r1, [r2 + r2*4] */
4169 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4170 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4173 /* LEA r1, [r2 + r2*2] */
4175 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4176 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4179 /* LEA r1, [r2 + r2*4] */
4180 /* LEA r1, [r1 + r1*4] */
4181 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4182 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4185 /* LEA r1, [r2 + r2*4] */
4187 /* LEA r1, [r1 + r1*4] */
4188 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4189 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4190 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4193 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4200 /* Regalloc magic makes the div/rem cases the same */
4201 if (ins->sreg2 == AMD64_RDX) {
4202 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4204 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4207 amd64_div_reg (code, ins->sreg2, TRUE);
4212 if (ins->sreg2 == AMD64_RDX) {
4213 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4214 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4215 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4217 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4218 amd64_div_reg (code, ins->sreg2, FALSE);
4223 if (ins->sreg2 == AMD64_RDX) {
4224 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4225 amd64_cdq_size (code, 4);
4226 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4228 amd64_cdq_size (code, 4);
4229 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4234 if (ins->sreg2 == AMD64_RDX) {
4235 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4236 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4237 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4239 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4240 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4244 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4245 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4248 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4252 g_assert (amd64_is_imm32 (ins->inst_imm));
4253 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4256 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4260 g_assert (amd64_is_imm32 (ins->inst_imm));
4261 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4264 g_assert (ins->sreg2 == AMD64_RCX);
4265 amd64_shift_reg (code, X86_SHL, ins->dreg);
4268 g_assert (ins->sreg2 == AMD64_RCX);
4269 amd64_shift_reg (code, X86_SAR, ins->dreg);
4273 g_assert (amd64_is_imm32 (ins->inst_imm));
4274 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4277 g_assert (amd64_is_imm32 (ins->inst_imm));
4278 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4280 case OP_LSHR_UN_IMM:
4281 g_assert (amd64_is_imm32 (ins->inst_imm));
4282 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4285 g_assert (ins->sreg2 == AMD64_RCX);
4286 amd64_shift_reg (code, X86_SHR, ins->dreg);
4290 g_assert (amd64_is_imm32 (ins->inst_imm));
4291 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4296 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4299 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4302 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4305 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4309 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4312 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4315 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4318 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4321 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4324 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4327 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4330 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4333 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4336 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4339 amd64_neg_reg_size (code, ins->sreg1, 4);
4342 amd64_not_reg_size (code, ins->sreg1, 4);
4345 g_assert (ins->sreg2 == AMD64_RCX);
4346 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4349 g_assert (ins->sreg2 == AMD64_RCX);
4350 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4353 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4355 case OP_ISHR_UN_IMM:
4356 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4359 g_assert (ins->sreg2 == AMD64_RCX);
4360 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4363 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4366 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4369 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4370 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4372 case OP_IMUL_OVF_UN:
4373 case OP_LMUL_OVF_UN: {
4374 /* the mul operation and the exception check should most likely be split */
4375 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4376 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4377 /*g_assert (ins->sreg2 == X86_EAX);
4378 g_assert (ins->dreg == X86_EAX);*/
4379 if (ins->sreg2 == X86_EAX) {
4380 non_eax_reg = ins->sreg1;
4381 } else if (ins->sreg1 == X86_EAX) {
4382 non_eax_reg = ins->sreg2;
4384 /* no need to save since we're going to store to it anyway */
4385 if (ins->dreg != X86_EAX) {
4387 amd64_push_reg (code, X86_EAX);
4389 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4390 non_eax_reg = ins->sreg2;
4392 if (ins->dreg == X86_EDX) {
4395 amd64_push_reg (code, X86_EAX);
4399 amd64_push_reg (code, X86_EDX);
4401 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4402 /* save before the check since pop and mov don't change the flags */
4403 if (ins->dreg != X86_EAX)
4404 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4406 amd64_pop_reg (code, X86_EDX);
4408 amd64_pop_reg (code, X86_EAX);
4409 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4413 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4415 case OP_ICOMPARE_IMM:
4416 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4438 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4446 case OP_CMOV_INE_UN:
4447 case OP_CMOV_IGE_UN:
4448 case OP_CMOV_IGT_UN:
4449 case OP_CMOV_ILE_UN:
4450 case OP_CMOV_ILT_UN:
4456 case OP_CMOV_LNE_UN:
4457 case OP_CMOV_LGE_UN:
4458 case OP_CMOV_LGT_UN:
4459 case OP_CMOV_LLE_UN:
4460 case OP_CMOV_LLT_UN:
4461 g_assert (ins->dreg == ins->sreg1);
4462 /* This needs to operate on 64 bit values */
4463 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4467 amd64_not_reg (code, ins->sreg1);
4470 amd64_neg_reg (code, ins->sreg1);
4475 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4476 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4478 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4481 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4482 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4485 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4486 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4489 if (ins->dreg != ins->sreg1)
4490 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4492 case OP_AMD64_SET_XMMREG_R4: {
4494 if (ins->dreg != ins->sreg1)
4495 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4497 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4501 case OP_AMD64_SET_XMMREG_R8: {
4502 if (ins->dreg != ins->sreg1)
4503 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4507 MonoCallInst *call = (MonoCallInst*)ins;
4508 int i, save_area_offset;
4510 g_assert (!cfg->method->save_lmf);
4512 /* the size of the tailcall op depends on signature, let's check for enough
4513 * space in the code buffer here again */
4514 max_len += AMD64_NREG * 4 + call->stack_usage * 15 + EXTRA_CODE_SPACE;
4516 if (G_UNLIKELY (offset + max_len > cfg->code_size)) {
4517 cfg->code_size *= 2;
4518 cfg->native_code = (unsigned char *) mono_realloc_native_code(cfg);
4519 code = cfg->native_code + offset;
4520 cfg->stat_code_reallocs++;
4523 /* Restore callee saved registers */
4524 save_area_offset = cfg->arch.reg_save_area_offset;
4525 for (i = 0; i < AMD64_NREG; ++i)
4526 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4527 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4528 save_area_offset += 8;
4531 if (cfg->arch.omit_fp) {
4532 if (cfg->arch.stack_alloc_size)
4533 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4535 if (call->stack_usage)
4538 /* Copy arguments on the stack to our argument area */
4539 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4540 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4541 amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4545 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4546 amd64_pop_reg (code, AMD64_RBP);
4547 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4553 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4554 if (cfg->compile_aot)
4555 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4557 amd64_set_reg_template (code, AMD64_R11);
4558 amd64_jump_reg (code, AMD64_R11);
4559 ins->flags |= MONO_INST_GC_CALLSITE;
4560 ins->backend.pc_offset = code - cfg->native_code;
4564 /* ensure ins->sreg1 is not NULL */
4565 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4568 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4569 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4579 call = (MonoCallInst*)ins;
4581 * The AMD64 ABI forces callers to know about varargs.
4583 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4584 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4585 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4587 * Since the unmanaged calling convention doesn't contain a
4588 * 'vararg' entry, we have to treat every pinvoke call as a
4589 * potential vararg call.
4593 for (i = 0; i < AMD64_XMM_NREG; ++i)
4594 if (call->used_fregs & (1 << i))
4597 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4599 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4602 if (ins->flags & MONO_INST_HAS_METHOD)
4603 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4605 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4606 ins->flags |= MONO_INST_GC_CALLSITE;
4607 ins->backend.pc_offset = code - cfg->native_code;
4608 code = emit_move_return_value (cfg, ins, code);
4615 case OP_VOIDCALL_REG:
4617 call = (MonoCallInst*)ins;
4619 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4620 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4621 ins->sreg1 = AMD64_R11;
4625 * The AMD64 ABI forces callers to know about varargs.
4627 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4628 if (ins->sreg1 == AMD64_RAX) {
4629 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4630 ins->sreg1 = AMD64_R11;
4632 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4633 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4635 * Since the unmanaged calling convention doesn't contain a
4636 * 'vararg' entry, we have to treat every pinvoke call as a
4637 * potential vararg call.
4641 for (i = 0; i < AMD64_XMM_NREG; ++i)
4642 if (call->used_fregs & (1 << i))
4644 if (ins->sreg1 == AMD64_RAX) {
4645 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4646 ins->sreg1 = AMD64_R11;
4649 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4651 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4654 amd64_call_reg (code, ins->sreg1);
4655 ins->flags |= MONO_INST_GC_CALLSITE;
4656 ins->backend.pc_offset = code - cfg->native_code;
4657 code = emit_move_return_value (cfg, ins, code);
4659 case OP_FCALL_MEMBASE:
4660 case OP_RCALL_MEMBASE:
4661 case OP_LCALL_MEMBASE:
4662 case OP_VCALL_MEMBASE:
4663 case OP_VCALL2_MEMBASE:
4664 case OP_VOIDCALL_MEMBASE:
4665 case OP_CALL_MEMBASE:
4666 call = (MonoCallInst*)ins;
4668 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4669 ins->flags |= MONO_INST_GC_CALLSITE;
4670 ins->backend.pc_offset = code - cfg->native_code;
4671 code = emit_move_return_value (cfg, ins, code);
4674 int i, limit_reg, index_reg, src_reg, dst_reg;
4675 MonoInst *var = cfg->dyn_call_var;
4679 g_assert (var->opcode == OP_REGOFFSET);
4681 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4682 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4684 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4686 /* Save args buffer */
4687 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4689 /* Set fp arg regs */
4690 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4691 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4693 amd64_branch8 (code, X86_CC_Z, -1, 1);
4694 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4695 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4696 amd64_patch (label, code);
4698 /* Allocate param area */
4699 /* This doesn't need to be freed since OP_DYN_CALL is never called in a loop */
4700 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
4701 amd64_shift_reg_imm (code, X86_SHL, AMD64_RAX, 3);
4702 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, AMD64_RAX);
4703 /* Set stack args */
4704 /* rax/rcx/rdx/r8/r9 is scratch */
4705 limit_reg = AMD64_RAX;
4706 index_reg = AMD64_RCX;
4709 amd64_mov_reg_membase (code, limit_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
4710 amd64_mov_reg_imm (code, index_reg, 0);
4711 amd64_lea_membase (code, src_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS) * sizeof(mgreg_t)));
4712 amd64_mov_reg_reg (code, dst_reg, AMD64_RSP, 8);
4714 x86_jump8 (code, 0);
4716 amd64_mov_reg_membase (code, AMD64_RDX, src_reg, 0, 8);
4717 amd64_mov_membase_reg (code, dst_reg, 0, AMD64_RDX, 8);
4718 amd64_alu_reg_imm (code, X86_ADD, index_reg, 1);
4719 amd64_alu_reg_imm (code, X86_ADD, src_reg, 8);
4720 amd64_alu_reg_imm (code, X86_ADD, dst_reg, 8);
4721 amd64_patch (buf [0], code);
4722 amd64_alu_reg_reg (code, X86_CMP, index_reg, limit_reg);
4724 x86_branch8 (code, X86_CC_LT, 0, FALSE);
4725 amd64_patch (buf [2], buf [1]);
4727 /* Set argument registers */
4728 for (i = 0; i < PARAM_REGS; ++i)
4729 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + (i * sizeof(mgreg_t)), sizeof(mgreg_t));
4732 amd64_call_reg (code, AMD64_R10);
4734 ins->flags |= MONO_INST_GC_CALLSITE;
4735 ins->backend.pc_offset = code - cfg->native_code;
4738 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4739 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4740 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4741 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4744 case OP_AMD64_SAVE_SP_TO_LMF: {
4745 MonoInst *lmf_var = cfg->lmf_var;
4746 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4750 g_assert_not_reached ();
4751 amd64_push_reg (code, ins->sreg1);
4753 case OP_X86_PUSH_IMM:
4754 g_assert_not_reached ();
4755 g_assert (amd64_is_imm32 (ins->inst_imm));
4756 amd64_push_imm (code, ins->inst_imm);
4758 case OP_X86_PUSH_MEMBASE:
4759 g_assert_not_reached ();
4760 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4762 case OP_X86_PUSH_OBJ: {
4763 int size = ALIGN_TO (ins->inst_imm, 8);
4765 g_assert_not_reached ();
4767 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4768 amd64_push_reg (code, AMD64_RDI);
4769 amd64_push_reg (code, AMD64_RSI);
4770 amd64_push_reg (code, AMD64_RCX);
4771 if (ins->inst_offset)
4772 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4774 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4775 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4776 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4778 amd64_prefix (code, X86_REP_PREFIX);
4780 amd64_pop_reg (code, AMD64_RCX);
4781 amd64_pop_reg (code, AMD64_RSI);
4782 amd64_pop_reg (code, AMD64_RDI);
4785 case OP_GENERIC_CLASS_INIT: {
4788 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4790 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4792 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4794 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4795 ins->flags |= MONO_INST_GC_CALLSITE;
4796 ins->backend.pc_offset = code - cfg->native_code;
4798 x86_patch (jump, code);
4803 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4805 case OP_X86_LEA_MEMBASE:
4806 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4809 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4812 /* keep alignment */
4813 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4814 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4815 code = mono_emit_stack_alloc (cfg, code, ins);
4816 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4817 if (cfg->param_area)
4818 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4820 case OP_LOCALLOC_IMM: {
4821 guint32 size = ins->inst_imm;
4822 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4824 if (ins->flags & MONO_INST_INIT) {
4828 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4829 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4831 for (i = 0; i < size; i += 8)
4832 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4833 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4835 amd64_mov_reg_imm (code, ins->dreg, size);
4836 ins->sreg1 = ins->dreg;
4838 code = mono_emit_stack_alloc (cfg, code, ins);
4839 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4842 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4843 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4845 if (cfg->param_area)
4846 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4850 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4851 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4852 (gpointer)"mono_arch_throw_exception", FALSE);
4853 ins->flags |= MONO_INST_GC_CALLSITE;
4854 ins->backend.pc_offset = code - cfg->native_code;
4858 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4859 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4860 (gpointer)"mono_arch_rethrow_exception", FALSE);
4861 ins->flags |= MONO_INST_GC_CALLSITE;
4862 ins->backend.pc_offset = code - cfg->native_code;
4865 case OP_CALL_HANDLER:
4867 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4868 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4869 amd64_call_imm (code, 0);
4870 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4871 /* Restore stack alignment */
4872 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4874 case OP_START_HANDLER: {
4875 /* Even though we're saving RSP, use sizeof */
4876 /* gpointer because spvar is of type IntPtr */
4877 /* see: mono_create_spvar_for_region */
4878 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4879 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4881 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4882 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FILTER)) &&
4884 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4888 case OP_ENDFINALLY: {
4889 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4890 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4894 case OP_ENDFILTER: {
4895 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4896 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4897 /* The local allocator will put the result into RAX */
4902 if (ins->dreg != AMD64_RAX)
4903 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4906 ins->inst_c0 = code - cfg->native_code;
4909 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4910 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4912 if (ins->inst_target_bb->native_offset) {
4913 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4915 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4916 if ((cfg->opt & MONO_OPT_BRANCH) &&
4917 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4918 x86_jump8 (code, 0);
4920 x86_jump32 (code, 0);
4924 amd64_jump_reg (code, ins->sreg1);
4947 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4948 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4950 case OP_COND_EXC_EQ:
4951 case OP_COND_EXC_NE_UN:
4952 case OP_COND_EXC_LT:
4953 case OP_COND_EXC_LT_UN:
4954 case OP_COND_EXC_GT:
4955 case OP_COND_EXC_GT_UN:
4956 case OP_COND_EXC_GE:
4957 case OP_COND_EXC_GE_UN:
4958 case OP_COND_EXC_LE:
4959 case OP_COND_EXC_LE_UN:
4960 case OP_COND_EXC_IEQ:
4961 case OP_COND_EXC_INE_UN:
4962 case OP_COND_EXC_ILT:
4963 case OP_COND_EXC_ILT_UN:
4964 case OP_COND_EXC_IGT:
4965 case OP_COND_EXC_IGT_UN:
4966 case OP_COND_EXC_IGE:
4967 case OP_COND_EXC_IGE_UN:
4968 case OP_COND_EXC_ILE:
4969 case OP_COND_EXC_ILE_UN:
4970 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4972 case OP_COND_EXC_OV:
4973 case OP_COND_EXC_NO:
4975 case OP_COND_EXC_NC:
4976 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4977 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4979 case OP_COND_EXC_IOV:
4980 case OP_COND_EXC_INO:
4981 case OP_COND_EXC_IC:
4982 case OP_COND_EXC_INC:
4983 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4984 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4987 /* floating point opcodes */
4989 double d = *(double *)ins->inst_p0;
4991 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4992 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4995 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4996 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5001 float f = *(float *)ins->inst_p0;
5003 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5005 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5007 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5010 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5011 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5013 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5017 case OP_STORER8_MEMBASE_REG:
5018 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5020 case OP_LOADR8_MEMBASE:
5021 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5023 case OP_STORER4_MEMBASE_REG:
5025 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5027 /* This requires a double->single conversion */
5028 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5029 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5032 case OP_LOADR4_MEMBASE:
5034 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5036 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5037 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5040 case OP_ICONV_TO_R4:
5042 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5044 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5045 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5048 case OP_ICONV_TO_R8:
5049 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5051 case OP_LCONV_TO_R4:
5053 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5055 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5056 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5059 case OP_LCONV_TO_R8:
5060 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5062 case OP_FCONV_TO_R4:
5064 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5066 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5067 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5070 case OP_FCONV_TO_I1:
5071 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5073 case OP_FCONV_TO_U1:
5074 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5076 case OP_FCONV_TO_I2:
5077 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5079 case OP_FCONV_TO_U2:
5080 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5082 case OP_FCONV_TO_U4:
5083 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5085 case OP_FCONV_TO_I4:
5087 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5089 case OP_FCONV_TO_I8:
5090 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5093 case OP_RCONV_TO_I1:
5094 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5095 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5097 case OP_RCONV_TO_U1:
5098 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5099 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5101 case OP_RCONV_TO_I2:
5102 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5103 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5105 case OP_RCONV_TO_U2:
5106 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5107 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5109 case OP_RCONV_TO_I4:
5110 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5112 case OP_RCONV_TO_U4:
5113 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5115 case OP_RCONV_TO_I8:
5116 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5118 case OP_RCONV_TO_R8:
5119 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5121 case OP_RCONV_TO_R4:
5122 if (ins->dreg != ins->sreg1)
5123 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5126 case OP_LCONV_TO_R_UN: {
5129 /* Based on gcc code */
5130 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5131 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5134 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5135 br [1] = code; x86_jump8 (code, 0);
5136 amd64_patch (br [0], code);
5139 /* Save to the red zone */
5140 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5141 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5142 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5143 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5144 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5145 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5146 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5147 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5148 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5150 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5151 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5152 amd64_patch (br [1], code);
5155 case OP_LCONV_TO_OVF_U4:
5156 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5157 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5158 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5160 case OP_LCONV_TO_OVF_I4_UN:
5161 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5162 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5163 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5166 if (ins->dreg != ins->sreg1)
5167 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5170 if (ins->dreg != ins->sreg1)
5171 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5173 case OP_MOVE_F_TO_I4:
5175 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5177 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5178 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5181 case OP_MOVE_I4_TO_F:
5182 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5184 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5186 case OP_MOVE_F_TO_I8:
5187 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5189 case OP_MOVE_I8_TO_F:
5190 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5193 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5196 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5199 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5202 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5205 static double r8_0 = -0.0;
5207 g_assert (ins->sreg1 == ins->dreg);
5209 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5210 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5214 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5217 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5220 static guint64 d = 0x7fffffffffffffffUL;
5222 g_assert (ins->sreg1 == ins->dreg);
5224 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5225 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5229 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5233 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5236 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5239 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5242 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5245 static float r4_0 = -0.0;
5247 g_assert (ins->sreg1 == ins->dreg);
5249 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5250 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5251 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5256 g_assert (cfg->opt & MONO_OPT_CMOV);
5257 g_assert (ins->dreg == ins->sreg1);
5258 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5259 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5262 g_assert (cfg->opt & MONO_OPT_CMOV);
5263 g_assert (ins->dreg == ins->sreg1);
5264 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5265 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5268 g_assert (cfg->opt & MONO_OPT_CMOV);
5269 g_assert (ins->dreg == ins->sreg1);
5270 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5271 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5274 g_assert (cfg->opt & MONO_OPT_CMOV);
5275 g_assert (ins->dreg == ins->sreg1);
5276 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5277 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5280 g_assert (cfg->opt & MONO_OPT_CMOV);
5281 g_assert (ins->dreg == ins->sreg1);
5282 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5283 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5286 g_assert (cfg->opt & MONO_OPT_CMOV);
5287 g_assert (ins->dreg == ins->sreg1);
5288 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5289 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5292 g_assert (cfg->opt & MONO_OPT_CMOV);
5293 g_assert (ins->dreg == ins->sreg1);
5294 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5295 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5298 g_assert (cfg->opt & MONO_OPT_CMOV);
5299 g_assert (ins->dreg == ins->sreg1);
5300 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5301 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5307 * The two arguments are swapped because the fbranch instructions
5308 * depend on this for the non-sse case to work.
5310 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5314 * FIXME: Get rid of this.
5315 * The two arguments are swapped because the fbranch instructions
5316 * depend on this for the non-sse case to work.
5318 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5322 /* zeroing the register at the start results in
5323 * shorter and faster code (we can also remove the widening op)
5325 guchar *unordered_check;
5327 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5328 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5329 unordered_check = code;
5330 x86_branch8 (code, X86_CC_P, 0, FALSE);
5332 if (ins->opcode == OP_FCEQ) {
5333 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5334 amd64_patch (unordered_check, code);
5336 guchar *jump_to_end;
5337 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5339 x86_jump8 (code, 0);
5340 amd64_patch (unordered_check, code);
5341 amd64_inc_reg (code, ins->dreg);
5342 amd64_patch (jump_to_end, code);
5348 /* zeroing the register at the start results in
5349 * shorter and faster code (we can also remove the widening op)
5351 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5352 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5353 if (ins->opcode == OP_FCLT_UN) {
5354 guchar *unordered_check = code;
5355 guchar *jump_to_end;
5356 x86_branch8 (code, X86_CC_P, 0, FALSE);
5357 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5359 x86_jump8 (code, 0);
5360 amd64_patch (unordered_check, code);
5361 amd64_inc_reg (code, ins->dreg);
5362 amd64_patch (jump_to_end, code);
5364 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5369 guchar *unordered_check;
5370 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5371 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5372 unordered_check = code;
5373 x86_branch8 (code, X86_CC_P, 0, FALSE);
5374 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5375 amd64_patch (unordered_check, code);
5380 /* zeroing the register at the start results in
5381 * shorter and faster code (we can also remove the widening op)
5383 guchar *unordered_check;
5385 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5386 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5387 if (ins->opcode == OP_FCGT) {
5388 unordered_check = code;
5389 x86_branch8 (code, X86_CC_P, 0, FALSE);
5390 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5391 amd64_patch (unordered_check, code);
5393 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5398 guchar *unordered_check;
5399 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5400 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5401 unordered_check = code;
5402 x86_branch8 (code, X86_CC_P, 0, FALSE);
5403 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5404 amd64_patch (unordered_check, code);
5414 gboolean unordered = FALSE;
5416 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5417 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5419 switch (ins->opcode) {
5421 x86_cond = X86_CC_EQ;
5424 x86_cond = X86_CC_LT;
5427 x86_cond = X86_CC_GT;
5430 x86_cond = X86_CC_GT;
5434 x86_cond = X86_CC_LT;
5438 g_assert_not_reached ();
5443 guchar *unordered_check;
5444 guchar *jump_to_end;
5446 unordered_check = code;
5447 x86_branch8 (code, X86_CC_P, 0, FALSE);
5448 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5450 x86_jump8 (code, 0);
5451 amd64_patch (unordered_check, code);
5452 amd64_inc_reg (code, ins->dreg);
5453 amd64_patch (jump_to_end, code);
5455 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5459 case OP_FCLT_MEMBASE:
5460 case OP_FCGT_MEMBASE:
5461 case OP_FCLT_UN_MEMBASE:
5462 case OP_FCGT_UN_MEMBASE:
5463 case OP_FCEQ_MEMBASE: {
5464 guchar *unordered_check, *jump_to_end;
5467 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5468 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5470 switch (ins->opcode) {
5471 case OP_FCEQ_MEMBASE:
5472 x86_cond = X86_CC_EQ;
5474 case OP_FCLT_MEMBASE:
5475 case OP_FCLT_UN_MEMBASE:
5476 x86_cond = X86_CC_LT;
5478 case OP_FCGT_MEMBASE:
5479 case OP_FCGT_UN_MEMBASE:
5480 x86_cond = X86_CC_GT;
5483 g_assert_not_reached ();
5486 unordered_check = code;
5487 x86_branch8 (code, X86_CC_P, 0, FALSE);
5488 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5490 switch (ins->opcode) {
5491 case OP_FCEQ_MEMBASE:
5492 case OP_FCLT_MEMBASE:
5493 case OP_FCGT_MEMBASE:
5494 amd64_patch (unordered_check, code);
5496 case OP_FCLT_UN_MEMBASE:
5497 case OP_FCGT_UN_MEMBASE:
5499 x86_jump8 (code, 0);
5500 amd64_patch (unordered_check, code);
5501 amd64_inc_reg (code, ins->dreg);
5502 amd64_patch (jump_to_end, code);
5510 guchar *jump = code;
5511 x86_branch8 (code, X86_CC_P, 0, TRUE);
5512 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5513 amd64_patch (jump, code);
5517 /* Branch if C013 != 100 */
5518 /* branch if !ZF or (PF|CF) */
5519 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5520 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5521 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5524 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5527 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5528 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5532 if (ins->opcode == OP_FBGT) {
5535 /* skip branch if C1=1 */
5537 x86_branch8 (code, X86_CC_P, 0, FALSE);
5538 /* branch if (C0 | C3) = 1 */
5539 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5540 amd64_patch (br1, code);
5543 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5547 /* Branch if C013 == 100 or 001 */
5550 /* skip branch if C1=1 */
5552 x86_branch8 (code, X86_CC_P, 0, FALSE);
5553 /* branch if (C0 | C3) = 1 */
5554 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5555 amd64_patch (br1, code);
5559 /* Branch if C013 == 000 */
5560 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5563 /* Branch if C013=000 or 100 */
5566 /* skip branch if C1=1 */
5568 x86_branch8 (code, X86_CC_P, 0, FALSE);
5569 /* branch if C0=0 */
5570 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5571 amd64_patch (br1, code);
5575 /* Branch if C013 != 001 */
5576 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5577 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5580 /* Transfer value to the fp stack */
5581 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5582 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5583 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5585 amd64_push_reg (code, AMD64_RAX);
5587 amd64_fnstsw (code);
5588 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5589 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5590 amd64_pop_reg (code, AMD64_RAX);
5591 amd64_fstp (code, 0);
5592 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5593 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5596 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5600 code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5603 case OP_MEMORY_BARRIER: {
5604 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5608 case OP_ATOMIC_ADD_I4:
5609 case OP_ATOMIC_ADD_I8: {
5610 int dreg = ins->dreg;
5611 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5613 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5616 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5617 amd64_prefix (code, X86_LOCK_PREFIX);
5618 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5619 /* dreg contains the old value, add with sreg2 value */
5620 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5622 if (ins->dreg != dreg)
5623 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5627 case OP_ATOMIC_EXCHANGE_I4:
5628 case OP_ATOMIC_EXCHANGE_I8: {
5629 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5631 /* LOCK prefix is implied. */
5632 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5633 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5634 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5637 case OP_ATOMIC_CAS_I4:
5638 case OP_ATOMIC_CAS_I8: {
5641 if (ins->opcode == OP_ATOMIC_CAS_I8)
5647 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5648 * an explanation of how this works.
5650 g_assert (ins->sreg3 == AMD64_RAX);
5651 g_assert (ins->sreg1 != AMD64_RAX);
5652 g_assert (ins->sreg1 != ins->sreg2);
5654 amd64_prefix (code, X86_LOCK_PREFIX);
5655 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5657 if (ins->dreg != AMD64_RAX)
5658 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5661 case OP_ATOMIC_LOAD_I1: {
5662 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5665 case OP_ATOMIC_LOAD_U1: {
5666 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5669 case OP_ATOMIC_LOAD_I2: {
5670 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5673 case OP_ATOMIC_LOAD_U2: {
5674 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5677 case OP_ATOMIC_LOAD_I4: {
5678 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5681 case OP_ATOMIC_LOAD_U4:
5682 case OP_ATOMIC_LOAD_I8:
5683 case OP_ATOMIC_LOAD_U8: {
5684 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5687 case OP_ATOMIC_LOAD_R4: {
5688 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5689 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5692 case OP_ATOMIC_LOAD_R8: {
5693 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5696 case OP_ATOMIC_STORE_I1:
5697 case OP_ATOMIC_STORE_U1:
5698 case OP_ATOMIC_STORE_I2:
5699 case OP_ATOMIC_STORE_U2:
5700 case OP_ATOMIC_STORE_I4:
5701 case OP_ATOMIC_STORE_U4:
5702 case OP_ATOMIC_STORE_I8:
5703 case OP_ATOMIC_STORE_U8: {
5706 switch (ins->opcode) {
5707 case OP_ATOMIC_STORE_I1:
5708 case OP_ATOMIC_STORE_U1:
5711 case OP_ATOMIC_STORE_I2:
5712 case OP_ATOMIC_STORE_U2:
5715 case OP_ATOMIC_STORE_I4:
5716 case OP_ATOMIC_STORE_U4:
5719 case OP_ATOMIC_STORE_I8:
5720 case OP_ATOMIC_STORE_U8:
5725 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5727 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5731 case OP_ATOMIC_STORE_R4: {
5732 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5733 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5735 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5739 case OP_ATOMIC_STORE_R8: {
5742 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5746 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5750 case OP_CARD_TABLE_WBARRIER: {
5751 int ptr = ins->sreg1;
5752 int value = ins->sreg2;
5754 int nursery_shift, card_table_shift;
5755 gpointer card_table_mask;
5756 size_t nursery_size;
5758 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5759 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5760 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5762 /*If either point to the stack we can simply avoid the WB. This happens due to
5763 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5765 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5769 * We need one register we can clobber, we choose EDX and make sreg1
5770 * fixed EAX to work around limitations in the local register allocator.
5771 * sreg2 might get allocated to EDX, but that is not a problem since
5772 * we use it before clobbering EDX.
5774 g_assert (ins->sreg1 == AMD64_RAX);
5777 * This is the code we produce:
5780 * edx >>= nursery_shift
5781 * cmp edx, (nursery_start >> nursery_shift)
5784 * edx >>= card_table_shift
5790 if (mono_gc_card_table_nursery_check ()) {
5791 if (value != AMD64_RDX)
5792 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5793 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5794 if (shifted_nursery_start >> 31) {
5796 * The value we need to compare against is 64 bits, so we need
5797 * another spare register. We use RBX, which we save and
5800 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5801 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5802 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5803 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5805 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5807 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5809 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5810 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5811 if (card_table_mask)
5812 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5814 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5815 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5817 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5819 if (mono_gc_card_table_nursery_check ())
5820 x86_patch (br, code);
5823 #ifdef MONO_ARCH_SIMD_INTRINSICS
5824 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5826 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5829 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5832 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5835 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5838 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5841 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5844 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5845 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5848 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5851 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5854 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5857 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5860 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5863 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5866 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5869 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5872 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5875 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5878 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5881 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5884 case OP_PSHUFLEW_HIGH:
5885 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5886 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5888 case OP_PSHUFLEW_LOW:
5889 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5890 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5893 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5894 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5897 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5898 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5901 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5902 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5906 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5912 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5915 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5918 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5921 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5924 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5925 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5928 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5931 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5934 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5937 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5940 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5943 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5946 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5949 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5952 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5955 case OP_EXTRACT_MASK:
5956 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5960 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5963 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5966 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5970 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5973 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5976 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5979 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5983 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5986 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5989 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5992 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5996 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5999 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6006 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6016 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6019 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6023 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6026 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6029 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6033 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6036 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6039 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6043 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6046 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6049 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6052 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6056 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6059 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6062 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6065 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6068 case OP_PSUM_ABS_DIFF:
6069 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6072 case OP_UNPACK_LOWB:
6073 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6075 case OP_UNPACK_LOWW:
6076 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6078 case OP_UNPACK_LOWD:
6079 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6081 case OP_UNPACK_LOWQ:
6082 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6084 case OP_UNPACK_LOWPS:
6085 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6087 case OP_UNPACK_LOWPD:
6088 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6091 case OP_UNPACK_HIGHB:
6092 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6094 case OP_UNPACK_HIGHW:
6095 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6097 case OP_UNPACK_HIGHD:
6098 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6100 case OP_UNPACK_HIGHQ:
6101 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6103 case OP_UNPACK_HIGHPS:
6104 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6106 case OP_UNPACK_HIGHPD:
6107 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6111 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6114 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6117 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6120 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6123 case OP_PADDB_SAT_UN:
6124 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6126 case OP_PSUBB_SAT_UN:
6127 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6129 case OP_PADDW_SAT_UN:
6130 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6132 case OP_PSUBW_SAT_UN:
6133 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6137 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6140 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6143 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6146 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6150 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6153 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6156 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6158 case OP_PMULW_HIGH_UN:
6159 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6162 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6166 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6169 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6173 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6176 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6180 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6183 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6187 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6190 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6194 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6197 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6201 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6204 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6208 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6211 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6214 /*TODO: This is appart of the sse spec but not added
6216 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6219 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6224 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6227 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6230 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6233 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6236 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6239 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6242 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6245 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6248 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6251 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6255 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6258 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6262 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6263 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6265 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6270 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6272 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6273 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6277 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6279 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6280 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6281 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6285 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6287 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6290 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6292 case OP_EXTRACTX_U2:
6293 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6295 case OP_INSERTX_U1_SLOW:
6296 /*sreg1 is the extracted ireg (scratch)
6297 /sreg2 is the to be inserted ireg (scratch)
6298 /dreg is the xreg to receive the value*/
6300 /*clear the bits from the extracted word*/
6301 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6302 /*shift the value to insert if needed*/
6303 if (ins->inst_c0 & 1)
6304 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6305 /*join them together*/
6306 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6307 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6309 case OP_INSERTX_I4_SLOW:
6310 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6311 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6312 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6314 case OP_INSERTX_I8_SLOW:
6315 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6317 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6319 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6322 case OP_INSERTX_R4_SLOW:
6323 switch (ins->inst_c0) {
6326 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6328 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6331 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6333 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6335 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6336 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6339 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6341 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6343 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6344 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6347 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6349 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6351 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6352 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6356 case OP_INSERTX_R8_SLOW:
6358 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6360 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6362 case OP_STOREX_MEMBASE_REG:
6363 case OP_STOREX_MEMBASE:
6364 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6366 case OP_LOADX_MEMBASE:
6367 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6369 case OP_LOADX_ALIGNED_MEMBASE:
6370 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6372 case OP_STOREX_ALIGNED_MEMBASE_REG:
6373 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6375 case OP_STOREX_NTA_MEMBASE_REG:
6376 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6378 case OP_PREFETCH_MEMBASE:
6379 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6383 /*FIXME the peephole pass should have killed this*/
6384 if (ins->dreg != ins->sreg1)
6385 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6388 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6391 amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6393 case OP_ICONV_TO_R4_RAW:
6394 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6396 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6399 case OP_FCONV_TO_R8_X:
6400 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6403 case OP_XCONV_R8_TO_I4:
6404 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6405 switch (ins->backend.source_opcode) {
6406 case OP_FCONV_TO_I1:
6407 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6409 case OP_FCONV_TO_U1:
6410 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6412 case OP_FCONV_TO_I2:
6413 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6415 case OP_FCONV_TO_U2:
6416 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6422 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6423 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6424 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6427 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6428 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6431 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6432 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6436 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6438 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6439 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6441 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6444 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6445 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6448 case OP_LIVERANGE_START: {
6449 if (cfg->verbose_level > 1)
6450 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6451 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6454 case OP_LIVERANGE_END: {
6455 if (cfg->verbose_level > 1)
6456 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6457 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6460 case OP_GC_SAFE_POINT: {
6463 g_assert (mono_threads_is_coop_enabled ());
6465 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6466 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6467 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6468 amd64_patch (br[0], code);
6472 case OP_GC_LIVENESS_DEF:
6473 case OP_GC_LIVENESS_USE:
6474 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6475 ins->backend.pc_offset = code - cfg->native_code;
6477 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6478 ins->backend.pc_offset = code - cfg->native_code;
6479 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6481 case OP_GET_LAST_ERROR:
6482 emit_get_last_error(code, ins->dreg);
6484 case OP_FILL_PROF_CALL_CTX:
6485 for (int i = 0; i < AMD64_NREG; i++)
6486 if (AMD64_IS_CALLEE_SAVED_REG (i) || i == AMD64_RSP)
6487 amd64_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, gregs) + i * sizeof (mgreg_t), i, sizeof (mgreg_t));
6490 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6491 g_assert_not_reached ();
6494 if ((code - cfg->native_code - offset) > max_len) {
6495 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6496 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6497 g_assert_not_reached ();
6501 cfg->code_len = code - cfg->native_code;
6504 #endif /* DISABLE_JIT */
6507 mono_arch_register_lowlevel_calls (void)
6509 /* The signature doesn't matter */
6510 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6512 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6514 extern void __chkstk (void);
6515 mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6517 extern void ___chkstk_ms (void);
6518 mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6524 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6526 unsigned char *ip = ji->ip.i + code;
6529 * Debug code to help track down problems where the target of a near call is
6532 if (amd64_is_near_call (ip)) {
6533 gint64 disp = (guint8*)target - (guint8*)ip;
6535 if (!amd64_is_imm32 (disp)) {
6536 printf ("TYPE: %d\n", ji->type);
6538 case MONO_PATCH_INFO_INTERNAL_METHOD:
6539 printf ("V: %s\n", ji->data.name);
6541 case MONO_PATCH_INFO_METHOD_JUMP:
6542 case MONO_PATCH_INFO_METHOD:
6543 printf ("V: %s\n", ji->data.method->name);
6551 amd64_patch (ip, (gpointer)target);
6557 get_max_epilog_size (MonoCompile *cfg)
6559 int max_epilog_size = 16;
6561 if (cfg->method->save_lmf)
6562 max_epilog_size += 256;
6564 if (mono_jit_trace_calls != NULL)
6565 max_epilog_size += 50;
6567 max_epilog_size += (AMD64_NREG * 2);
6569 return max_epilog_size;
6573 * This macro is used for testing whenever the unwinder works correctly at every point
6574 * where an async exception can happen.
6576 /* This will generate a SIGSEGV at the given point in the code */
6577 #define async_exc_point(code) do { \
6578 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6579 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6580 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6581 cfg->arch.async_point_count ++; \
6587 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6589 int cfa_offset = *cfa_offset_input;
6591 /* Allocate windows stack frame using stack probing method */
6594 if (alloc_size >= 0x1000) {
6595 amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6596 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6599 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6600 if (cfg->arch.omit_fp) {
6601 cfa_offset += alloc_size;
6602 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6603 async_exc_point (code);
6606 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6607 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6608 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6609 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6610 // that will retrieve the expected results.
6611 if (cfg->arch.omit_fp)
6612 mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6615 *cfa_offset_input = cfa_offset;
6618 #endif /* TARGET_WIN32 */
6621 mono_arch_emit_prolog (MonoCompile *cfg)
6623 MonoMethod *method = cfg->method;
6625 MonoMethodSignature *sig;
6627 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6630 MonoInst *lmf_var = cfg->lmf_var;
6631 gboolean args_clobbered = FALSE;
6632 gboolean trace = FALSE;
6634 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6636 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6638 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6641 /* Amount of stack space allocated by register saving code */
6644 /* Offset between RSP and the CFA */
6648 * The prolog consists of the following parts:
6652 * - save callee saved regs using moves
6654 * - save rgctx if needed
6655 * - save lmf if needed
6658 * - save rgctx if needed
6659 * - save lmf if needed
6660 * - save callee saved regs using moves
6665 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6666 // IP saved at CFA - 8
6667 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6668 async_exc_point (code);
6669 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6671 if (!cfg->arch.omit_fp) {
6672 amd64_push_reg (code, AMD64_RBP);
6674 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6675 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6676 async_exc_point (code);
6677 /* These are handled automatically by the stack marking code */
6678 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6680 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6681 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6682 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6683 async_exc_point (code);
6686 /* The param area is always at offset 0 from sp */
6687 /* This needs to be allocated here, since it has to come after the spill area */
6688 if (cfg->param_area) {
6689 if (cfg->arch.omit_fp)
6691 g_assert_not_reached ();
6692 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6695 if (cfg->arch.omit_fp) {
6697 * On enter, the stack is misaligned by the pushing of the return
6698 * address. It is either made aligned by the pushing of %rbp, or by
6701 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6702 if ((alloc_size % 16) == 0) {
6704 /* Mark the padding slot as NOREF */
6705 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6708 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6709 if (cfg->stack_offset != alloc_size) {
6710 /* Mark the padding slot as NOREF */
6711 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6713 cfg->arch.sp_fp_offset = alloc_size;
6717 cfg->arch.stack_alloc_size = alloc_size;
6719 /* Allocate stack frame */
6721 code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6724 /* See mono_emit_stack_alloc */
6725 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6726 guint32 remaining_size = alloc_size;
6728 /* Use a loop for large sizes */
6729 if (remaining_size > 10 * 0x1000) {
6730 amd64_mov_reg_imm (code, X86_EAX, remaining_size / 0x1000);
6731 guint8 *label = code;
6732 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6733 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6734 amd64_alu_reg_imm (code, X86_SUB, AMD64_RAX, 1);
6735 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6736 guint8 *label2 = code;
6737 x86_branch8 (code, X86_CC_NE, 0, FALSE);
6738 amd64_patch (label2, label);
6739 if (cfg->arch.omit_fp) {
6740 cfa_offset += (remaining_size / 0x1000) * 0x1000;
6741 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6744 remaining_size = remaining_size % 0x1000;
6747 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6748 guint32 offset = code - cfg->native_code;
6749 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6750 while (required_code_size >= (cfg->code_size - offset))
6751 cfg->code_size *= 2;
6752 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6753 code = cfg->native_code + offset;
6754 cfg->stat_code_reallocs++;
6757 while (remaining_size >= 0x1000) {
6758 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6759 if (cfg->arch.omit_fp) {
6760 cfa_offset += 0x1000;
6761 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6763 async_exc_point (code);
6765 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6766 remaining_size -= 0x1000;
6768 if (remaining_size) {
6769 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6770 if (cfg->arch.omit_fp) {
6771 cfa_offset += remaining_size;
6772 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6773 async_exc_point (code);
6777 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6778 if (cfg->arch.omit_fp) {
6779 cfa_offset += alloc_size;
6780 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6781 async_exc_point (code);
6787 /* Stack alignment check */
6792 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6793 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6794 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6796 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6797 amd64_breakpoint (code);
6798 amd64_patch (buf, code);
6802 if (mini_get_debug_options ()->init_stacks) {
6803 /* Fill the stack frame with a dummy value to force deterministic behavior */
6805 /* Save registers to the red zone */
6806 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6807 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6809 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6810 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6811 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6814 amd64_prefix (code, X86_REP_PREFIX);
6817 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6818 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6822 if (method->save_lmf)
6823 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6825 /* Save callee saved registers */
6826 if (cfg->arch.omit_fp) {
6827 save_area_offset = cfg->arch.reg_save_area_offset;
6828 /* Save caller saved registers after sp is adjusted */
6829 /* The registers are saved at the bottom of the frame */
6830 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6832 /* The registers are saved just below the saved rbp */
6833 save_area_offset = cfg->arch.reg_save_area_offset;
6836 for (i = 0; i < AMD64_NREG; ++i) {
6837 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6838 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6840 if (cfg->arch.omit_fp) {
6841 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6842 /* These are handled automatically by the stack marking code */
6843 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6845 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6849 save_area_offset += 8;
6850 async_exc_point (code);
6854 /* store runtime generic context */
6855 if (cfg->rgctx_var) {
6856 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6857 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6859 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6861 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6862 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6865 /* compute max_length in order to use short forward jumps */
6866 max_epilog_size = get_max_epilog_size (cfg);
6867 if (cfg->opt & MONO_OPT_BRANCH) {
6868 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6872 /* max alignment for loops */
6873 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6874 max_length += LOOP_ALIGNMENT;
6876 MONO_BB_FOR_EACH_INS (bb, ins) {
6877 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6880 /* Take prolog and epilog instrumentation into account */
6881 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6882 max_length += max_epilog_size;
6884 bb->max_length = max_length;
6888 sig = mono_method_signature (method);
6891 cinfo = (CallInfo *)cfg->arch.cinfo;
6893 if (sig->ret->type != MONO_TYPE_VOID) {
6894 /* Save volatile arguments to the stack */
6895 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6896 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6899 /* Keep this in sync with emit_load_volatile_arguments */
6900 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6901 ArgInfo *ainfo = cinfo->args + i;
6903 ins = cfg->args [i];
6905 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6906 /* Unused arguments */
6909 /* Save volatile arguments to the stack */
6910 if (ins->opcode != OP_REGVAR) {
6911 switch (ainfo->storage) {
6917 if (stack_offset & 0x1)
6919 else if (stack_offset & 0x2)
6921 else if (stack_offset & 0x4)
6926 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6929 * Save the original location of 'this',
6930 * get_generic_info_from_stack_frame () needs this to properly look up
6931 * the argument value during the handling of async exceptions.
6933 if (ins == cfg->args [0]) {
6934 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6935 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6939 case ArgInFloatSSEReg:
6940 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6942 case ArgInDoubleSSEReg:
6943 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6945 case ArgValuetypeInReg:
6946 for (quad = 0; quad < 2; quad ++) {
6947 switch (ainfo->pair_storage [quad]) {
6949 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6951 case ArgInFloatSSEReg:
6952 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6954 case ArgInDoubleSSEReg:
6955 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6960 g_assert_not_reached ();
6964 case ArgValuetypeAddrInIReg:
6965 if (ainfo->pair_storage [0] == ArgInIReg)
6966 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6968 case ArgValuetypeAddrOnStack:
6970 case ArgGSharedVtInReg:
6971 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6977 /* Argument allocated to (non-volatile) register */
6978 switch (ainfo->storage) {
6980 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6983 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6986 g_assert_not_reached ();
6989 if (ins == cfg->args [0]) {
6990 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6991 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6996 if (cfg->method->save_lmf)
6997 args_clobbered = TRUE;
7000 args_clobbered = TRUE;
7001 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7005 * Optimize the common case of the first bblock making a call with the same
7006 * arguments as the method. This works because the arguments are still in their
7007 * original argument registers.
7008 * FIXME: Generalize this
7010 if (!args_clobbered) {
7011 MonoBasicBlock *first_bb = cfg->bb_entry;
7013 int filter = FILTER_IL_SEQ_POINT;
7015 next = mono_bb_first_inst (first_bb, filter);
7016 if (!next && first_bb->next_bb) {
7017 first_bb = first_bb->next_bb;
7018 next = mono_bb_first_inst (first_bb, filter);
7021 if (first_bb->in_count > 1)
7024 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7025 ArgInfo *ainfo = cinfo->args + i;
7026 gboolean match = FALSE;
7028 ins = cfg->args [i];
7029 if (ins->opcode != OP_REGVAR) {
7030 switch (ainfo->storage) {
7032 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7033 if (next->dreg == ainfo->reg) {
7037 next->opcode = OP_MOVE;
7038 next->sreg1 = ainfo->reg;
7039 /* Only continue if the instruction doesn't change argument regs */
7040 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7050 /* Argument allocated to (non-volatile) register */
7051 switch (ainfo->storage) {
7053 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7064 next = mono_inst_next (next, filter);
7065 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7072 if (cfg->gen_sdb_seq_points) {
7073 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7075 /* Initialize seq_point_info_var */
7076 if (cfg->compile_aot) {
7077 /* Initialize the variable from a GOT slot */
7078 /* Same as OP_AOTCONST */
7079 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7080 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7081 g_assert (info_var->opcode == OP_REGOFFSET);
7082 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7085 if (cfg->compile_aot) {
7086 /* Initialize ss_tramp_var */
7087 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7088 g_assert (ins->opcode == OP_REGOFFSET);
7090 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7091 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7092 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7094 /* Initialize ss_tramp_var */
7095 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7096 g_assert (ins->opcode == OP_REGOFFSET);
7098 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7099 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7101 /* Initialize bp_tramp_var */
7102 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7103 g_assert (ins->opcode == OP_REGOFFSET);
7105 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7106 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7110 cfg->code_len = code - cfg->native_code;
7112 g_assert (cfg->code_len < cfg->code_size);
7118 mono_arch_emit_epilog (MonoCompile *cfg)
7120 MonoMethod *method = cfg->method;
7123 int max_epilog_size;
7125 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7126 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7128 max_epilog_size = get_max_epilog_size (cfg);
7130 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7131 cfg->code_size *= 2;
7132 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7133 cfg->stat_code_reallocs++;
7135 code = cfg->native_code + cfg->code_len;
7137 cfg->has_unwind_info_for_epilog = TRUE;
7139 /* Mark the start of the epilog */
7140 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7142 /* Save the uwind state which is needed by the out-of-line code */
7143 mono_emit_unwind_op_remember_state (cfg, code);
7145 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7146 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7148 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7150 if (method->save_lmf) {
7151 /* check if we need to restore protection of the stack after a stack overflow */
7152 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7154 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7155 /* we load the value in a separate instruction: this mechanism may be
7156 * used later as a safer way to do thread interruption
7158 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7159 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7161 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7162 /* note that the call trampoline will preserve eax/edx */
7163 x86_call_reg (code, X86_ECX);
7164 x86_patch (patch, code);
7166 /* FIXME: maybe save the jit tls in the prolog */
7168 if (cfg->used_int_regs & (1 << AMD64_RBP))
7169 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7170 if (cfg->arch.omit_fp)
7172 * emit_setup_lmf () marks RBP as saved, we have to mark it as same value here before clearing up the stack
7173 * since its stack slot will become invalid.
7175 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7178 /* Restore callee saved regs */
7179 for (i = 0; i < AMD64_NREG; ++i) {
7180 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7181 /* Restore only used_int_regs, not arch.saved_iregs */
7182 #if defined(MONO_SUPPORT_TASKLETS)
7183 int restore_reg = 1;
7185 int restore_reg = (cfg->used_int_regs & (1 << i));
7188 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7189 mono_emit_unwind_op_same_value (cfg, code, i);
7190 async_exc_point (code);
7192 save_area_offset += 8;
7196 /* Load returned vtypes into registers if needed */
7197 cinfo = (CallInfo *)cfg->arch.cinfo;
7198 if (cinfo->ret.storage == ArgValuetypeInReg) {
7199 ArgInfo *ainfo = &cinfo->ret;
7200 MonoInst *inst = cfg->ret;
7202 for (quad = 0; quad < 2; quad ++) {
7203 switch (ainfo->pair_storage [quad]) {
7205 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7207 case ArgInFloatSSEReg:
7208 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7210 case ArgInDoubleSSEReg:
7211 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7216 g_assert_not_reached ();
7221 if (cfg->arch.omit_fp) {
7222 if (cfg->arch.stack_alloc_size) {
7223 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7227 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7228 amd64_pop_reg (code, AMD64_RBP);
7229 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7232 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7235 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7236 async_exc_point (code);
7239 /* Restore the unwind state to be the same as before the epilog */
7240 mono_emit_unwind_op_restore_state (cfg, code);
7242 cfg->code_len = code - cfg->native_code;
7244 g_assert (cfg->code_len < cfg->code_size);
7248 mono_arch_emit_exceptions (MonoCompile *cfg)
7250 MonoJumpInfo *patch_info;
7253 MonoClass *exc_classes [16];
7254 guint8 *exc_throw_start [16], *exc_throw_end [16];
7255 guint32 code_size = 0;
7257 /* Compute needed space */
7258 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7259 if (patch_info->type == MONO_PATCH_INFO_EXC)
7261 if (patch_info->type == MONO_PATCH_INFO_R8)
7262 code_size += 8 + 15; /* sizeof (double) + alignment */
7263 if (patch_info->type == MONO_PATCH_INFO_R4)
7264 code_size += 4 + 15; /* sizeof (float) + alignment */
7265 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7266 code_size += 8 + 7; /*sizeof (void*) + alignment */
7269 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7270 cfg->code_size *= 2;
7271 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7272 cfg->stat_code_reallocs++;
7275 code = cfg->native_code + cfg->code_len;
7277 /* add code to raise exceptions */
7279 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7280 switch (patch_info->type) {
7281 case MONO_PATCH_INFO_EXC: {
7282 MonoClass *exc_class;
7286 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7288 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7289 throw_ip = patch_info->ip.i;
7291 //x86_breakpoint (code);
7292 /* Find a throw sequence for the same exception class */
7293 for (i = 0; i < nthrows; ++i)
7294 if (exc_classes [i] == exc_class)
7297 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7298 x86_jump_code (code, exc_throw_start [i]);
7299 patch_info->type = MONO_PATCH_INFO_NONE;
7303 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7307 exc_classes [nthrows] = exc_class;
7308 exc_throw_start [nthrows] = code;
7310 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7312 patch_info->type = MONO_PATCH_INFO_NONE;
7314 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7316 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7321 exc_throw_end [nthrows] = code;
7331 g_assert(code < cfg->native_code + cfg->code_size);
7334 /* Handle relocations with RIP relative addressing */
7335 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7336 gboolean remove = FALSE;
7337 guint8 *orig_code = code;
7339 switch (patch_info->type) {
7340 case MONO_PATCH_INFO_R8:
7341 case MONO_PATCH_INFO_R4: {
7342 guint8 *pos, *patch_pos;
7345 /* The SSE opcodes require a 16 byte alignment */
7346 code = (guint8*)ALIGN_TO (code, 16);
7348 pos = cfg->native_code + patch_info->ip.i;
7349 if (IS_REX (pos [1])) {
7350 patch_pos = pos + 5;
7351 target_pos = code - pos - 9;
7354 patch_pos = pos + 4;
7355 target_pos = code - pos - 8;
7358 if (patch_info->type == MONO_PATCH_INFO_R8) {
7359 *(double*)code = *(double*)patch_info->data.target;
7360 code += sizeof (double);
7362 *(float*)code = *(float*)patch_info->data.target;
7363 code += sizeof (float);
7366 *(guint32*)(patch_pos) = target_pos;
7371 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7374 if (cfg->compile_aot)
7377 /*loading is faster against aligned addresses.*/
7378 code = (guint8*)ALIGN_TO (code, 8);
7379 memset (orig_code, 0, code - orig_code);
7381 pos = cfg->native_code + patch_info->ip.i;
7383 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7384 if (IS_REX (pos [1]))
7385 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7387 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7389 *(gpointer*)code = (gpointer)patch_info->data.target;
7390 code += sizeof (gpointer);
7400 if (patch_info == cfg->patch_info)
7401 cfg->patch_info = patch_info->next;
7405 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7407 tmp->next = patch_info->next;
7410 g_assert (code < cfg->native_code + cfg->code_size);
7413 cfg->code_len = code - cfg->native_code;
7415 g_assert (cfg->code_len < cfg->code_size);
7419 #endif /* DISABLE_JIT */
7422 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7424 guchar *code = (guchar *)p;
7425 MonoMethodSignature *sig;
7427 int i, n, stack_area = 0;
7429 /* Keep this in sync with mono_arch_get_argument_info */
7431 if (enable_arguments) {
7432 /* Allocate a new area on the stack and save arguments there */
7433 sig = mono_method_signature (cfg->method);
7435 n = sig->param_count + sig->hasthis;
7437 stack_area = ALIGN_TO (n * 8, 16);
7439 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7441 for (i = 0; i < n; ++i) {
7442 inst = cfg->args [i];
7444 if (inst->opcode == OP_REGVAR)
7445 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7447 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7448 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7453 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7454 amd64_set_reg_template (code, AMD64_ARG_REG1);
7455 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7456 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7458 if (enable_arguments)
7459 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7473 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7475 guchar *code = (guchar *)p;
7476 int save_mode = SAVE_NONE;
7477 MonoMethod *method = cfg->method;
7478 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7481 switch (ret_type->type) {
7482 case MONO_TYPE_VOID:
7483 /* special case string .ctor icall */
7484 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7485 save_mode = SAVE_EAX;
7487 save_mode = SAVE_NONE;
7491 save_mode = SAVE_EAX;
7495 save_mode = SAVE_XMM;
7497 case MONO_TYPE_GENERICINST:
7498 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7499 save_mode = SAVE_EAX;
7503 case MONO_TYPE_VALUETYPE:
7504 save_mode = SAVE_STRUCT;
7507 save_mode = SAVE_EAX;
7511 /* Save the result and copy it into the proper argument register */
7512 switch (save_mode) {
7514 amd64_push_reg (code, AMD64_RAX);
7516 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7517 if (enable_arguments)
7518 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7522 if (enable_arguments)
7523 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7526 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7527 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7529 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7531 * The result is already in the proper argument register so no copying
7538 g_assert_not_reached ();
7541 /* Set %al since this is a varargs call */
7542 if (save_mode == SAVE_XMM)
7543 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7545 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7547 if (preserve_argument_registers) {
7548 for (i = 0; i < PARAM_REGS; ++i)
7549 amd64_push_reg (code, param_regs [i]);
7552 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7553 amd64_set_reg_template (code, AMD64_ARG_REG1);
7554 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7556 if (preserve_argument_registers) {
7557 for (i = PARAM_REGS - 1; i >= 0; --i)
7558 amd64_pop_reg (code, param_regs [i]);
7561 /* Restore result */
7562 switch (save_mode) {
7564 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7565 amd64_pop_reg (code, AMD64_RAX);
7571 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7572 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7573 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7578 g_assert_not_reached ();
7585 mono_arch_flush_icache (guint8 *code, gint size)
7591 mono_arch_flush_register_windows (void)
7596 mono_arch_is_inst_imm (gint64 imm)
7598 return amd64_use_imm32 (imm);
7602 * Determine whenever the trap whose info is in SIGINFO is caused by
7606 mono_arch_is_int_overflow (void *sigctx, void *info)
7613 mono_sigctx_to_monoctx (sigctx, &ctx);
7615 rip = (guint8*)ctx.gregs [AMD64_RIP];
7617 if (IS_REX (rip [0])) {
7618 reg = amd64_rex_b (rip [0]);
7624 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7626 reg += x86_modrm_rm (rip [1]);
7628 value = ctx.gregs [reg];
7638 mono_arch_get_patch_offset (guint8 *code)
7644 * \return TRUE if no sw breakpoint was present.
7646 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7647 * breakpoints in the original code, they are removed in the copy.
7650 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7653 * If method_start is non-NULL we need to perform bound checks, since we access memory
7654 * at code - offset we could go before the start of the method and end up in a different
7655 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7658 if (!method_start || code - offset >= method_start) {
7659 memcpy (buf, code - offset, size);
7661 int diff = code - method_start;
7662 memset (buf, 0, size);
7663 memcpy (buf + offset - diff, method_start, diff + size - offset);
7669 mono_arch_get_this_arg_reg (guint8 *code)
7671 return AMD64_ARG_REG1;
7675 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7677 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7680 #define MAX_ARCH_DELEGATE_PARAMS 10
7683 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7685 guint8 *code, *start;
7686 GSList *unwind_ops = NULL;
7689 unwind_ops = mono_arch_get_cie_program ();
7692 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7694 /* Replace the this argument with the target */
7695 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7696 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7697 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7699 g_assert ((code - start) < 64);
7700 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7702 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7704 if (param_count == 0) {
7705 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7707 /* We have to shift the arguments left */
7708 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7709 for (i = 0; i < param_count; ++i) {
7712 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7714 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7716 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7720 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7722 g_assert ((code - start) < 64);
7723 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7726 mono_arch_flush_icache (start, code - start);
7729 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7731 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7732 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7736 if (mono_jit_map_is_enabled ()) {
7739 buff = (char*)"delegate_invoke_has_target";
7741 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7742 mono_emit_jit_tramp (start, code - start, buff);
7746 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7751 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7754 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7756 guint8 *code, *start;
7761 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7764 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7766 unwind_ops = mono_arch_get_cie_program ();
7768 /* Replace the this argument with the target */
7769 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7770 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7773 /* Load the IMT reg */
7774 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7777 /* Load the vtable */
7778 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7779 amd64_jump_membase (code, AMD64_RAX, offset);
7780 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7782 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7783 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7784 g_free (tramp_name);
7790 * mono_arch_get_delegate_invoke_impls:
7792 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7796 mono_arch_get_delegate_invoke_impls (void)
7799 MonoTrampInfo *info;
7802 get_delegate_invoke_impl (&info, TRUE, 0);
7803 res = g_slist_prepend (res, info);
7805 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7806 get_delegate_invoke_impl (&info, FALSE, i);
7807 res = g_slist_prepend (res, info);
7810 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7811 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7812 res = g_slist_prepend (res, info);
7815 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7816 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7817 res = g_slist_prepend (res, info);
7818 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7819 res = g_slist_prepend (res, info);
7826 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7828 guint8 *code, *start;
7831 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7834 /* FIXME: Support more cases */
7835 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7839 static guint8* cached = NULL;
7844 if (mono_aot_only) {
7845 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7847 MonoTrampInfo *info;
7848 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7849 mono_tramp_info_register (info, NULL);
7852 mono_memory_barrier ();
7856 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7857 for (i = 0; i < sig->param_count; ++i)
7858 if (!mono_is_regsize_var (sig->params [i]))
7860 if (sig->param_count > 4)
7863 code = cache [sig->param_count];
7867 if (mono_aot_only) {
7868 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7869 start = (guint8 *)mono_aot_get_trampoline (name);
7872 MonoTrampInfo *info;
7873 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7874 mono_tramp_info_register (info, NULL);
7877 mono_memory_barrier ();
7879 cache [sig->param_count] = start;
7886 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7888 MonoTrampInfo *info;
7891 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7893 mono_tramp_info_register (info, NULL);
7898 mono_arch_finish_init (void)
7900 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7901 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7906 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7910 #define CMP_SIZE (6 + 1)
7911 #define CMP_REG_REG_SIZE (4 + 1)
7912 #define BR_SMALL_SIZE 2
7913 #define BR_LARGE_SIZE 6
7914 #define MOV_REG_IMM_SIZE 10
7915 #define MOV_REG_IMM_32BIT_SIZE 6
7916 #define JUMP_REG_SIZE (2 + 1)
7919 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7921 int i, distance = 0;
7922 for (i = start; i < target; ++i)
7923 distance += imt_entries [i]->chunk_size;
7928 * LOCKING: called with the domain lock held
7931 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7932 gpointer fail_tramp)
7936 guint8 *code, *start;
7937 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7940 for (i = 0; i < count; ++i) {
7941 MonoIMTCheckItem *item = imt_entries [i];
7942 if (item->is_equals) {
7943 if (item->check_target_idx) {
7944 if (!item->compare_done) {
7945 if (amd64_use_imm32 ((gint64)item->key))
7946 item->chunk_size += CMP_SIZE;
7948 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7950 if (item->has_target_code) {
7951 item->chunk_size += MOV_REG_IMM_SIZE;
7953 if (vtable_is_32bit)
7954 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7956 item->chunk_size += MOV_REG_IMM_SIZE;
7958 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7961 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7962 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7964 if (vtable_is_32bit)
7965 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7967 item->chunk_size += MOV_REG_IMM_SIZE;
7968 item->chunk_size += JUMP_REG_SIZE;
7969 /* with assert below:
7970 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7975 if (amd64_use_imm32 ((gint64)item->key))
7976 item->chunk_size += CMP_SIZE;
7978 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7979 item->chunk_size += BR_LARGE_SIZE;
7980 imt_entries [item->check_target_idx]->compare_done = TRUE;
7982 size += item->chunk_size;
7985 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7987 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7990 unwind_ops = mono_arch_get_cie_program ();
7992 for (i = 0; i < count; ++i) {
7993 MonoIMTCheckItem *item = imt_entries [i];
7994 item->code_target = code;
7995 if (item->is_equals) {
7996 gboolean fail_case = !item->check_target_idx && fail_tramp;
7998 if (item->check_target_idx || fail_case) {
7999 if (!item->compare_done || fail_case) {
8000 if (amd64_use_imm32 ((gint64)item->key))
8001 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8003 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8004 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8007 item->jmp_code = code;
8008 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8009 if (item->has_target_code) {
8010 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8011 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8013 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8014 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8018 amd64_patch (item->jmp_code, code);
8019 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8020 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8021 item->jmp_code = NULL;
8024 /* enable the commented code to assert on wrong method */
8026 if (amd64_is_imm32 (item->key))
8027 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8029 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8030 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8032 item->jmp_code = code;
8033 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8034 /* See the comment below about R10 */
8035 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8036 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8037 amd64_patch (item->jmp_code, code);
8038 amd64_breakpoint (code);
8039 item->jmp_code = NULL;
8041 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8042 needs to be preserved. R10 needs
8043 to be preserved for calls which
8044 require a runtime generic context,
8045 but interface calls don't. */
8046 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8047 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8051 if (amd64_use_imm32 ((gint64)item->key))
8052 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8054 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8055 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8057 item->jmp_code = code;
8058 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8059 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8061 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8063 g_assert (code - item->code_target <= item->chunk_size);
8065 /* patch the branches to get to the target items */
8066 for (i = 0; i < count; ++i) {
8067 MonoIMTCheckItem *item = imt_entries [i];
8068 if (item->jmp_code) {
8069 if (item->check_target_idx) {
8070 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8076 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
8077 g_assert (code - start <= size);
8078 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8080 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
8082 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8088 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8090 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8094 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8096 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8100 mono_arch_get_cie_program (void)
8104 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8105 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8113 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8115 MonoInst *ins = NULL;
8118 if (cmethod->klass == mono_defaults.math_class) {
8119 if (strcmp (cmethod->name, "Sin") == 0) {
8121 } else if (strcmp (cmethod->name, "Cos") == 0) {
8123 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8125 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8129 if (opcode && fsig->param_count == 1) {
8130 MONO_INST_NEW (cfg, ins, opcode);
8131 ins->type = STACK_R8;
8132 ins->dreg = mono_alloc_freg (cfg);
8133 ins->sreg1 = args [0]->dreg;
8134 MONO_ADD_INS (cfg->cbb, ins);
8138 if (cfg->opt & MONO_OPT_CMOV) {
8139 if (strcmp (cmethod->name, "Min") == 0) {
8140 if (fsig->params [0]->type == MONO_TYPE_I4)
8142 if (fsig->params [0]->type == MONO_TYPE_U4)
8143 opcode = OP_IMIN_UN;
8144 else if (fsig->params [0]->type == MONO_TYPE_I8)
8146 else if (fsig->params [0]->type == MONO_TYPE_U8)
8147 opcode = OP_LMIN_UN;
8148 } else if (strcmp (cmethod->name, "Max") == 0) {
8149 if (fsig->params [0]->type == MONO_TYPE_I4)
8151 if (fsig->params [0]->type == MONO_TYPE_U4)
8152 opcode = OP_IMAX_UN;
8153 else if (fsig->params [0]->type == MONO_TYPE_I8)
8155 else if (fsig->params [0]->type == MONO_TYPE_U8)
8156 opcode = OP_LMAX_UN;
8160 if (opcode && fsig->param_count == 2) {
8161 MONO_INST_NEW (cfg, ins, opcode);
8162 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8163 ins->dreg = mono_alloc_ireg (cfg);
8164 ins->sreg1 = args [0]->dreg;
8165 ins->sreg2 = args [1]->dreg;
8166 MONO_ADD_INS (cfg->cbb, ins);
8170 /* OP_FREM is not IEEE compatible */
8171 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8172 MONO_INST_NEW (cfg, ins, OP_FREM);
8173 ins->inst_i0 = args [0];
8174 ins->inst_i1 = args [1];
8184 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8186 return ctx->gregs [reg];
8190 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8192 ctx->gregs [reg] = val;
8196 * mono_arch_emit_load_aotconst:
8198 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8199 * TARGET from the mscorlib GOT in full-aot code.
8200 * On AMD64, the result is placed into R11.
8203 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8205 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8206 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8212 * mono_arch_get_trampolines:
8214 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8218 mono_arch_get_trampolines (gboolean aot)
8220 return mono_amd64_get_exception_trampolines (aot);
8223 /* Soft Debug support */
8224 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8227 * mono_arch_set_breakpoint:
8229 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8230 * The location should contain code emitted by OP_SEQ_POINT.
8233 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8238 guint32 native_offset = ip - (guint8*)ji->code_start;
8239 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8241 g_assert (info->bp_addrs [native_offset] == 0);
8242 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8244 /* ip points to a mov r11, 0 */
8245 g_assert (code [0] == 0x41);
8246 g_assert (code [1] == 0xbb);
8247 amd64_mov_reg_imm (code, AMD64_R11, 1);
8252 * mono_arch_clear_breakpoint:
8254 * Clear the breakpoint at IP.
8257 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8262 guint32 native_offset = ip - (guint8*)ji->code_start;
8263 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8265 info->bp_addrs [native_offset] = NULL;
8267 amd64_mov_reg_imm (code, AMD64_R11, 0);
8272 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8274 /* We use soft breakpoints on amd64 */
8279 * mono_arch_skip_breakpoint:
8281 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8282 * we resume, the instruction is not executed again.
8285 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8287 g_assert_not_reached ();
8291 * mono_arch_start_single_stepping:
8293 * Start single stepping.
8296 mono_arch_start_single_stepping (void)
8298 ss_trampoline = mini_get_single_step_trampoline ();
8302 * mono_arch_stop_single_stepping:
8304 * Stop single stepping.
8307 mono_arch_stop_single_stepping (void)
8309 ss_trampoline = NULL;
8313 * mono_arch_is_single_step_event:
8315 * Return whenever the machine state in SIGCTX corresponds to a single
8319 mono_arch_is_single_step_event (void *info, void *sigctx)
8321 /* We use soft breakpoints on amd64 */
8326 * mono_arch_skip_single_step:
8328 * Modify CTX so the ip is placed after the single step trigger instruction,
8329 * we resume, the instruction is not executed again.
8332 mono_arch_skip_single_step (MonoContext *ctx)
8334 g_assert_not_reached ();
8338 * mono_arch_create_seq_point_info:
8340 * Return a pointer to a data structure which is used by the sequence
8341 * point implementation in AOTed code.
8344 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8349 // FIXME: Add a free function
8351 mono_domain_lock (domain);
8352 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8354 mono_domain_unlock (domain);
8357 ji = mono_jit_info_table_find (domain, (char*)code);
8360 // FIXME: Optimize the size
8361 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8363 info->ss_tramp_addr = &ss_trampoline;
8365 mono_domain_lock (domain);
8366 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8368 mono_domain_unlock (domain);
8375 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8377 ext->lmf.previous_lmf = prev_lmf;
8378 /* Mark that this is a MonoLMFExt */
8379 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8380 ext->lmf.rsp = (gssize)ext;
8386 mono_arch_opcode_supported (int opcode)
8389 case OP_ATOMIC_ADD_I4:
8390 case OP_ATOMIC_ADD_I8:
8391 case OP_ATOMIC_EXCHANGE_I4:
8392 case OP_ATOMIC_EXCHANGE_I8:
8393 case OP_ATOMIC_CAS_I4:
8394 case OP_ATOMIC_CAS_I8:
8395 case OP_ATOMIC_LOAD_I1:
8396 case OP_ATOMIC_LOAD_I2:
8397 case OP_ATOMIC_LOAD_I4:
8398 case OP_ATOMIC_LOAD_I8:
8399 case OP_ATOMIC_LOAD_U1:
8400 case OP_ATOMIC_LOAD_U2:
8401 case OP_ATOMIC_LOAD_U4:
8402 case OP_ATOMIC_LOAD_U8:
8403 case OP_ATOMIC_LOAD_R4:
8404 case OP_ATOMIC_LOAD_R8:
8405 case OP_ATOMIC_STORE_I1:
8406 case OP_ATOMIC_STORE_I2:
8407 case OP_ATOMIC_STORE_I4:
8408 case OP_ATOMIC_STORE_I8:
8409 case OP_ATOMIC_STORE_U1:
8410 case OP_ATOMIC_STORE_U2:
8411 case OP_ATOMIC_STORE_U4:
8412 case OP_ATOMIC_STORE_U8:
8413 case OP_ATOMIC_STORE_R4:
8414 case OP_ATOMIC_STORE_R8:
8422 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8424 return get_call_info (mp, sig);