3 * AMD64 backend for the Mono code generator
8 * Paolo Molaro (lupus@ximian.com)
9 * Dietmar Maurer (dietmar@ximian.com)
11 * Zoltan Varga (vargaz@gmail.com)
12 * Johan Lorensson (lateralusx.github@gmail.com)
14 * (C) 2003 Ximian, Inc.
15 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
16 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
17 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
27 #include <mono/metadata/abi-details.h>
28 #include <mono/metadata/appdomain.h>
29 #include <mono/metadata/debug-helpers.h>
30 #include <mono/metadata/threads.h>
31 #include <mono/metadata/profiler-private.h>
32 #include <mono/metadata/mono-debug.h>
33 #include <mono/metadata/gc-internals.h>
34 #include <mono/utils/mono-math.h>
35 #include <mono/utils/mono-mmap.h>
36 #include <mono/utils/mono-memory-model.h>
37 #include <mono/utils/mono-tls.h>
38 #include <mono/utils/mono-hwcap.h>
39 #include <mono/utils/mono-threads.h>
43 #include "mini-amd64.h"
44 #include "cpu-amd64.h"
45 #include "debugger-agent.h"
49 static gboolean optimize_for_xen = TRUE;
51 #define optimize_for_xen 0
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
56 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
58 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
61 /* Under windows, the calling convention is never stdcall */
62 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
64 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
67 /* This mutex protects architecture specific caches */
68 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
69 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
70 static mono_mutex_t mini_arch_mutex;
72 /* The single step trampoline */
73 static gpointer ss_trampoline;
75 /* The breakpoint trampoline */
76 static gpointer bp_trampoline;
78 /* Offset between fp and the first argument in the callee */
79 #define ARGS_OFFSET 16
80 #define GP_SCRATCH_REG AMD64_R11
83 * AMD64 register usage:
84 * - callee saved registers are used for global register allocation
85 * - %r11 is used for materializing 64 bit constants in opcodes
86 * - the rest is used for local allocation
90 * Floating point comparison results:
100 mono_arch_regname (int reg)
103 case AMD64_RAX: return "%rax";
104 case AMD64_RBX: return "%rbx";
105 case AMD64_RCX: return "%rcx";
106 case AMD64_RDX: return "%rdx";
107 case AMD64_RSP: return "%rsp";
108 case AMD64_RBP: return "%rbp";
109 case AMD64_RDI: return "%rdi";
110 case AMD64_RSI: return "%rsi";
111 case AMD64_R8: return "%r8";
112 case AMD64_R9: return "%r9";
113 case AMD64_R10: return "%r10";
114 case AMD64_R11: return "%r11";
115 case AMD64_R12: return "%r12";
116 case AMD64_R13: return "%r13";
117 case AMD64_R14: return "%r14";
118 case AMD64_R15: return "%r15";
123 static const char * packed_xmmregs [] = {
124 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
125 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
128 static const char * single_xmmregs [] = {
129 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
130 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
134 mono_arch_fregname (int reg)
136 if (reg < AMD64_XMM_NREG)
137 return single_xmmregs [reg];
143 mono_arch_xregname (int reg)
145 if (reg < AMD64_XMM_NREG)
146 return packed_xmmregs [reg];
155 return mono_debug_count ();
161 static inline gboolean
162 amd64_is_near_call (guint8 *code)
165 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
168 return code [0] == 0xe8;
171 static inline gboolean
172 amd64_use_imm32 (gint64 val)
174 if (mini_get_debug_options()->single_imm_size)
177 return amd64_is_imm32 (val);
181 amd64_patch (unsigned char* code, gpointer target)
186 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
191 if ((code [0] & 0xf8) == 0xb8) {
192 /* amd64_set_reg_template */
193 *(guint64*)(code + 1) = (guint64)target;
195 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
196 /* mov 0(%rip), %dreg */
197 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
199 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
200 /* call *<OFFSET>(%rip) */
201 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
203 else if (code [0] == 0xe8) {
205 gint64 disp = (guint8*)target - (guint8*)code;
206 g_assert (amd64_is_imm32 (disp));
207 x86_patch (code, (unsigned char*)target);
210 x86_patch (code, (unsigned char*)target);
214 mono_amd64_patch (unsigned char* code, gpointer target)
216 amd64_patch (code, target);
219 #define DEBUG(a) if (cfg->verbose_level > 1) a
222 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
224 ainfo->offset = *stack_size;
226 if (*gr >= PARAM_REGS) {
227 ainfo->storage = ArgOnStack;
228 ainfo->arg_size = sizeof (mgreg_t);
229 /* Since the same stack slot size is used for all arg */
230 /* types, it needs to be big enough to hold them all */
231 (*stack_size) += sizeof(mgreg_t);
234 ainfo->storage = ArgInIReg;
235 ainfo->reg = param_regs [*gr];
241 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
243 ainfo->offset = *stack_size;
245 if (*gr >= FLOAT_PARAM_REGS) {
246 ainfo->storage = ArgOnStack;
247 ainfo->arg_size = sizeof (mgreg_t);
248 /* Since the same stack slot size is used for both float */
249 /* types, it needs to be big enough to hold them both */
250 (*stack_size) += sizeof(mgreg_t);
253 /* A double register */
255 ainfo->storage = ArgInDoubleSSEReg;
257 ainfo->storage = ArgInFloatSSEReg;
263 typedef enum ArgumentClass {
271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
273 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
276 ptype = mini_get_underlying_type (type);
277 switch (ptype->type) {
286 case MONO_TYPE_STRING:
287 case MONO_TYPE_OBJECT:
288 case MONO_TYPE_CLASS:
289 case MONO_TYPE_SZARRAY:
291 case MONO_TYPE_FNPTR:
292 case MONO_TYPE_ARRAY:
295 class2 = ARG_CLASS_INTEGER;
300 class2 = ARG_CLASS_INTEGER;
302 class2 = ARG_CLASS_SSE;
306 case MONO_TYPE_TYPEDBYREF:
307 g_assert_not_reached ();
309 case MONO_TYPE_GENERICINST:
310 if (!mono_type_generic_inst_is_valuetype (ptype)) {
311 class2 = ARG_CLASS_INTEGER;
315 case MONO_TYPE_VALUETYPE: {
316 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
319 for (i = 0; i < info->num_fields; ++i) {
321 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
326 g_assert_not_reached ();
330 if (class1 == class2)
332 else if (class1 == ARG_CLASS_NO_CLASS)
334 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
335 class1 = ARG_CLASS_MEMORY;
336 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
337 class1 = ARG_CLASS_INTEGER;
339 class1 = ARG_CLASS_SSE;
350 * collect_field_info_nested:
352 * Collect field info from KLASS recursively into FIELDS.
355 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
357 MonoMarshalType *info;
361 info = mono_marshal_load_type_info (klass);
363 for (i = 0; i < info->num_fields; ++i) {
364 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
365 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
370 f.type = info->fields [i].field->type;
371 f.size = mono_marshal_type_size (info->fields [i].field->type,
372 info->fields [i].mspec,
373 &align, TRUE, unicode);
374 f.offset = offset + info->fields [i].offset;
375 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
376 /* This can happen with .pack directives eg. 'fixed' arrays */
377 if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
378 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
379 g_array_append_val (fields_array, f);
380 while (f.size + f.offset < info->native_size) {
382 g_array_append_val (fields_array, f);
385 f.size = info->native_size - f.offset;
386 g_array_append_val (fields_array, f);
389 g_array_append_val (fields_array, f);
395 MonoClassField *field;
398 while ((field = mono_class_get_fields (klass, &iter))) {
399 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
401 if (MONO_TYPE_ISSTRUCT (field->type)) {
402 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
407 f.type = field->type;
408 f.size = mono_type_size (field->type, &align);
409 f.offset = field->offset - sizeof (MonoObject) + offset;
411 g_array_append_val (fields_array, f);
419 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
420 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
423 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
425 gboolean result = FALSE;
427 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
428 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
430 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
431 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
432 arg_info->pair_size [0] = 0;
433 arg_info->pair_size [1] = 0;
436 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
437 /* Pass parameter in integer register. */
438 arg_info->pair_storage [0] = ArgInIReg;
439 arg_info->pair_regs [0] = int_regs [*current_int_reg];
440 (*current_int_reg) ++;
442 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
443 /* Pass parameter in float register. */
444 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
445 arg_info->pair_regs [0] = float_regs [*current_float_reg];
446 (*current_float_reg) ++;
450 if (result == TRUE) {
451 arg_info->pair_size [0] = arg_size;
458 static inline gboolean
459 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
461 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
464 static inline gboolean
465 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
467 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
471 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
472 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
474 /* Windows x64 value type ABI.
476 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
478 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
479 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
480 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
481 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
483 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
485 * Integers/Float types smaller than or equal to 8 bytes
486 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
487 * Properly sized struct/unions (1,2,4,8)
488 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
489 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
490 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
493 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
497 /* Parameter cases. */
498 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
499 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
501 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
502 arg_info->storage = ArgValuetypeInReg;
503 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
504 /* No more registers, fallback passing parameter on stack as value. */
505 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
507 /* Passing value directly on stack, so use size of value. */
508 arg_info->storage = ArgOnStack;
509 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
510 arg_info->offset = *stack_size;
511 arg_info->arg_size = arg_size;
512 *stack_size += arg_size;
515 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
516 arg_info->storage = ArgValuetypeAddrInIReg;
517 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
518 /* No more registers, fallback passing address to parameter on stack. */
519 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
521 /* Passing an address to value on stack, so use size of register as argument size. */
522 arg_info->storage = ArgValuetypeAddrOnStack;
523 arg_size = sizeof (mgreg_t);
524 arg_info->offset = *stack_size;
525 arg_info->arg_size = arg_size;
526 *stack_size += arg_size;
530 /* Return value cases. */
531 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
532 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
534 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
535 arg_info->storage = ArgValuetypeInReg;
536 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
538 /* Only RAX/XMM0 should be used to return valuetype. */
539 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
541 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
542 arg_info->storage = ArgValuetypeAddrInIReg;
543 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
545 /* Only RAX should be used to return valuetype address. */
546 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
548 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
549 arg_info->offset = *stack_size;
550 *stack_size += arg_size;
556 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
559 *arg_class = ARG_CLASS_NO_CLASS;
561 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
564 /* Calculate argument class type and size of marshalled type. */
565 MonoMarshalType *info = mono_marshal_load_type_info (klass);
566 *arg_size = info->native_size;
568 /* Calculate argument class type and size of managed type. */
569 *arg_size = mono_class_value_size (klass, NULL);
572 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
573 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
575 if (*arg_class == ARG_CLASS_MEMORY) {
576 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
577 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
581 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
582 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
583 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
584 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
585 * it must be represented in call and cannot be dropped.
587 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
588 arg_info->pass_empty_struct = TRUE;
589 *arg_size = SIZEOF_REGISTER;
590 *arg_class = ARG_CLASS_INTEGER;
593 assert (*arg_class != ARG_CLASS_NO_CLASS);
597 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
598 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
600 guint32 arg_size = SIZEOF_REGISTER;
601 MonoClass *klass = NULL;
602 ArgumentClass arg_class;
604 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
606 klass = mono_class_from_mono_type (type);
607 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
609 /* Only drop value type if its not an empty struct as input that must be represented in call */
610 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
611 arg_info->storage = ArgValuetypeInReg;
612 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
614 /* Alocate storage for value type. */
615 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
619 #endif /* TARGET_WIN32 */
622 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
624 guint32 *gr, guint32 *fr, guint32 *stack_size)
627 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
629 guint32 size, quad, nquads, i, nfields;
630 /* Keep track of the size used in each quad so we can */
631 /* use the right size when copying args/return vars. */
632 guint32 quadsize [2] = {8, 8};
633 ArgumentClass args [2];
634 StructFieldInfo *fields = NULL;
635 GArray *fields_array;
637 gboolean pass_on_stack = FALSE;
640 klass = mono_class_from_mono_type (type);
641 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
643 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
644 /* We pass and return vtypes of size 8 in a register */
645 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
646 pass_on_stack = TRUE;
649 /* If this struct can't be split up naturally into 8-byte */
650 /* chunks (registers), pass it on the stack. */
652 MonoMarshalType *info = mono_marshal_load_type_info (klass);
654 struct_size = info->native_size;
656 struct_size = mono_class_value_size (klass, NULL);
659 * Collect field information recursively to be able to
660 * handle nested structures.
662 fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
663 collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
664 fields = (StructFieldInfo*)fields_array->data;
665 nfields = fields_array->len;
667 for (i = 0; i < nfields; ++i) {
668 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
669 pass_on_stack = TRUE;
675 ainfo->storage = ArgValuetypeInReg;
676 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
681 /* Allways pass in memory */
682 ainfo->offset = *stack_size;
683 *stack_size += ALIGN_TO (size, 8);
684 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
686 ainfo->arg_size = ALIGN_TO (size, 8);
688 g_array_free (fields_array, TRUE);
698 int n = mono_class_value_size (klass, NULL);
700 quadsize [0] = n >= 8 ? 8 : n;
701 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
703 /* Always pass in 1 or 2 integer registers */
704 args [0] = ARG_CLASS_INTEGER;
705 args [1] = ARG_CLASS_INTEGER;
706 /* Only the simplest cases are supported */
707 if (is_return && nquads != 1) {
708 args [0] = ARG_CLASS_MEMORY;
709 args [1] = ARG_CLASS_MEMORY;
713 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
714 * The X87 and SSEUP stuff is left out since there are no such types in
718 ainfo->storage = ArgValuetypeInReg;
719 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
723 if (struct_size > 16) {
724 ainfo->offset = *stack_size;
725 *stack_size += ALIGN_TO (struct_size, 8);
726 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
728 ainfo->arg_size = ALIGN_TO (struct_size, 8);
730 g_array_free (fields_array, TRUE);
734 args [0] = ARG_CLASS_NO_CLASS;
735 args [1] = ARG_CLASS_NO_CLASS;
736 for (quad = 0; quad < nquads; ++quad) {
737 ArgumentClass class1;
740 class1 = ARG_CLASS_MEMORY;
742 class1 = ARG_CLASS_NO_CLASS;
743 for (i = 0; i < nfields; ++i) {
744 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
745 /* Unaligned field */
749 /* Skip fields in other quad */
750 if ((quad == 0) && (fields [i].offset >= 8))
752 if ((quad == 1) && (fields [i].offset < 8))
755 /* How far into this quad this data extends.*/
756 /* (8 is size of quad) */
757 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
759 class1 = merge_argument_class_from_type (fields [i].type, class1);
761 /* Empty structs have a nonzero size, causing this assert to be hit */
763 g_assert (class1 != ARG_CLASS_NO_CLASS);
764 args [quad] = class1;
768 g_array_free (fields_array, TRUE);
770 /* Post merger cleanup */
771 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
772 args [0] = args [1] = ARG_CLASS_MEMORY;
774 /* Allocate registers */
779 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
781 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
784 ainfo->storage = ArgValuetypeInReg;
785 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
786 g_assert (quadsize [0] <= 8);
787 g_assert (quadsize [1] <= 8);
788 ainfo->pair_size [0] = quadsize [0];
789 ainfo->pair_size [1] = quadsize [1];
790 ainfo->nregs = nquads;
791 for (quad = 0; quad < nquads; ++quad) {
792 switch (args [quad]) {
793 case ARG_CLASS_INTEGER:
794 if (*gr >= PARAM_REGS)
795 args [quad] = ARG_CLASS_MEMORY;
797 ainfo->pair_storage [quad] = ArgInIReg;
799 ainfo->pair_regs [quad] = return_regs [*gr];
801 ainfo->pair_regs [quad] = param_regs [*gr];
806 if (*fr >= FLOAT_PARAM_REGS)
807 args [quad] = ARG_CLASS_MEMORY;
809 if (quadsize[quad] <= 4)
810 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
811 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
812 ainfo->pair_regs [quad] = *fr;
816 case ARG_CLASS_MEMORY:
818 case ARG_CLASS_NO_CLASS:
821 g_assert_not_reached ();
825 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
827 /* Revert possible register assignments */
831 ainfo->offset = *stack_size;
833 arg_size = ALIGN_TO (struct_size, 8);
835 arg_size = nquads * sizeof(mgreg_t);
836 *stack_size += arg_size;
837 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
839 ainfo->arg_size = arg_size;
842 #endif /* !TARGET_WIN32 */
848 * Obtain information about a call according to the calling convention.
849 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
850 * Draft Version 0.23" document for more information.
851 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
852 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
855 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
857 guint32 i, gr, fr, pstart;
859 int n = sig->hasthis + sig->param_count;
860 guint32 stack_size = 0;
862 gboolean is_pinvoke = sig->pinvoke;
865 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
867 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
870 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
876 /* Reserve space where the callee can save the argument registers */
877 stack_size = 4 * sizeof (mgreg_t);
881 ret_type = mini_get_underlying_type (sig->ret);
882 switch (ret_type->type) {
892 case MONO_TYPE_FNPTR:
893 case MONO_TYPE_CLASS:
894 case MONO_TYPE_OBJECT:
895 case MONO_TYPE_SZARRAY:
896 case MONO_TYPE_ARRAY:
897 case MONO_TYPE_STRING:
898 cinfo->ret.storage = ArgInIReg;
899 cinfo->ret.reg = AMD64_RAX;
903 cinfo->ret.storage = ArgInIReg;
904 cinfo->ret.reg = AMD64_RAX;
907 cinfo->ret.storage = ArgInFloatSSEReg;
908 cinfo->ret.reg = AMD64_XMM0;
911 cinfo->ret.storage = ArgInDoubleSSEReg;
912 cinfo->ret.reg = AMD64_XMM0;
914 case MONO_TYPE_GENERICINST:
915 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
916 cinfo->ret.storage = ArgInIReg;
917 cinfo->ret.reg = AMD64_RAX;
920 if (mini_is_gsharedvt_type (ret_type)) {
921 cinfo->ret.storage = ArgGsharedvtVariableInReg;
925 case MONO_TYPE_VALUETYPE:
926 case MONO_TYPE_TYPEDBYREF: {
927 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
929 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
930 g_assert (cinfo->ret.storage != ArgInIReg);
935 g_assert (mini_is_gsharedvt_type (ret_type));
936 cinfo->ret.storage = ArgGsharedvtVariableInReg;
941 g_error ("Can't handle as return value 0x%x", ret_type->type);
946 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
947 * the first argument, allowing 'this' to be always passed in the first arg reg.
948 * Also do this if the first argument is a reference type, since virtual calls
949 * are sometimes made using calli without sig->hasthis set, like in the delegate
952 ArgStorage ret_storage = cinfo->ret.storage;
953 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
955 add_general (&gr, &stack_size, cinfo->args + 0);
957 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
960 add_general (&gr, &stack_size, &cinfo->ret);
961 cinfo->ret.storage = ret_storage;
962 cinfo->vret_arg_index = 1;
966 add_general (&gr, &stack_size, cinfo->args + 0);
968 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
969 add_general (&gr, &stack_size, &cinfo->ret);
970 cinfo->ret.storage = ret_storage;
974 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
976 fr = FLOAT_PARAM_REGS;
978 /* Emit the signature cookie just before the implicit arguments */
979 add_general (&gr, &stack_size, &cinfo->sig_cookie);
982 for (i = pstart; i < sig->param_count; ++i) {
983 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
987 /* The float param registers and other param registers must be the same index on Windows x64.*/
994 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
995 /* We allways pass the sig cookie on the stack for simplicity */
997 * Prevent implicit arguments + the sig cookie from being passed
1001 fr = FLOAT_PARAM_REGS;
1003 /* Emit the signature cookie just before the implicit arguments */
1004 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1007 ptype = mini_get_underlying_type (sig->params [i]);
1008 switch (ptype->type) {
1011 add_general (&gr, &stack_size, ainfo);
1015 add_general (&gr, &stack_size, ainfo);
1019 add_general (&gr, &stack_size, ainfo);
1024 case MONO_TYPE_FNPTR:
1025 case MONO_TYPE_CLASS:
1026 case MONO_TYPE_OBJECT:
1027 case MONO_TYPE_STRING:
1028 case MONO_TYPE_SZARRAY:
1029 case MONO_TYPE_ARRAY:
1030 add_general (&gr, &stack_size, ainfo);
1032 case MONO_TYPE_GENERICINST:
1033 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1034 add_general (&gr, &stack_size, ainfo);
1037 if (mini_is_gsharedvt_variable_type (ptype)) {
1038 /* gsharedvt arguments are passed by ref */
1039 add_general (&gr, &stack_size, ainfo);
1040 if (ainfo->storage == ArgInIReg)
1041 ainfo->storage = ArgGSharedVtInReg;
1043 ainfo->storage = ArgGSharedVtOnStack;
1047 case MONO_TYPE_VALUETYPE:
1048 case MONO_TYPE_TYPEDBYREF:
1049 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1054 add_general (&gr, &stack_size, ainfo);
1057 add_float (&fr, &stack_size, ainfo, FALSE);
1060 add_float (&fr, &stack_size, ainfo, TRUE);
1063 case MONO_TYPE_MVAR:
1064 /* gsharedvt arguments are passed by ref */
1065 g_assert (mini_is_gsharedvt_type (ptype));
1066 add_general (&gr, &stack_size, ainfo);
1067 if (ainfo->storage == ArgInIReg)
1068 ainfo->storage = ArgGSharedVtInReg;
1070 ainfo->storage = ArgGSharedVtOnStack;
1073 g_assert_not_reached ();
1077 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1079 fr = FLOAT_PARAM_REGS;
1081 /* Emit the signature cookie just before the implicit arguments */
1082 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1085 cinfo->stack_usage = stack_size;
1086 cinfo->reg_usage = gr;
1087 cinfo->freg_usage = fr;
1092 * mono_arch_get_argument_info:
1093 * @csig: a method signature
1094 * @param_count: the number of parameters to consider
1095 * @arg_info: an array to store the result infos
1097 * Gathers information on parameters such as size, alignment and
1098 * padding. arg_info should be large enought to hold param_count + 1 entries.
1100 * Returns the size of the argument area on the stack.
1103 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1106 CallInfo *cinfo = get_call_info (NULL, csig);
1107 guint32 args_size = cinfo->stack_usage;
1109 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1110 if (csig->hasthis) {
1111 arg_info [0].offset = 0;
1114 for (k = 0; k < param_count; k++) {
1115 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1117 arg_info [k + 1].size = 0;
1126 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1130 MonoType *callee_ret;
1132 c1 = get_call_info (NULL, caller_sig);
1133 c2 = get_call_info (NULL, callee_sig);
1134 res = c1->stack_usage >= c2->stack_usage;
1135 callee_ret = mini_get_underlying_type (callee_sig->ret);
1136 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1137 /* An address on the callee's stack is passed as the first argument */
1147 * Initialize the cpu to execute managed code.
1150 mono_arch_cpu_init (void)
1155 /* spec compliance requires running with double precision */
1156 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1157 fpcw &= ~X86_FPCW_PRECC_MASK;
1158 fpcw |= X86_FPCW_PREC_DOUBLE;
1159 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1160 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1162 /* TODO: This is crashing on Win64 right now.
1163 * _control87 (_PC_53, MCW_PC);
1169 * Initialize architecture specific code.
1172 mono_arch_init (void)
1174 mono_os_mutex_init_recursive (&mini_arch_mutex);
1176 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1177 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1178 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1179 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1180 mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1182 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1183 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1187 bp_trampoline = mini_get_breakpoint_trampoline ();
1191 * Cleanup architecture specific code.
1194 mono_arch_cleanup (void)
1196 mono_os_mutex_destroy (&mini_arch_mutex);
1200 * This function returns the optimizations supported on this cpu.
1203 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1209 if (mono_hwcap_x86_has_cmov) {
1210 opts |= MONO_OPT_CMOV;
1212 if (mono_hwcap_x86_has_fcmov)
1213 opts |= MONO_OPT_FCMOV;
1215 *exclude_mask |= MONO_OPT_FCMOV;
1217 *exclude_mask |= MONO_OPT_CMOV;
1221 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1222 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1223 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1224 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1225 /* will now have a reference to an argument that won't be fully decomposed. */
1226 *exclude_mask |= MONO_OPT_SIMD;
1233 * This function test for all SSE functions supported.
1235 * Returns a bitmask corresponding to all supported versions.
1239 mono_arch_cpu_enumerate_simd_versions (void)
1241 guint32 sse_opts = 0;
1243 if (mono_hwcap_x86_has_sse1)
1244 sse_opts |= SIMD_VERSION_SSE1;
1246 if (mono_hwcap_x86_has_sse2)
1247 sse_opts |= SIMD_VERSION_SSE2;
1249 if (mono_hwcap_x86_has_sse3)
1250 sse_opts |= SIMD_VERSION_SSE3;
1252 if (mono_hwcap_x86_has_ssse3)
1253 sse_opts |= SIMD_VERSION_SSSE3;
1255 if (mono_hwcap_x86_has_sse41)
1256 sse_opts |= SIMD_VERSION_SSE41;
1258 if (mono_hwcap_x86_has_sse42)
1259 sse_opts |= SIMD_VERSION_SSE42;
1261 if (mono_hwcap_x86_has_sse4a)
1262 sse_opts |= SIMD_VERSION_SSE4a;
1270 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1275 for (i = 0; i < cfg->num_varinfo; i++) {
1276 MonoInst *ins = cfg->varinfo [i];
1277 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1280 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1283 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1284 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1287 if (mono_is_regsize_var (ins->inst_vtype)) {
1288 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1289 g_assert (i == vmv->idx);
1290 vars = g_list_prepend (vars, vmv);
1294 vars = mono_varlist_sort (cfg, vars, 0);
1300 * mono_arch_compute_omit_fp:
1301 * Determine whether the frame pointer can be eliminated.
1304 mono_arch_compute_omit_fp (MonoCompile *cfg)
1306 MonoMethodSignature *sig;
1307 MonoMethodHeader *header;
1311 if (cfg->arch.omit_fp_computed)
1314 header = cfg->header;
1316 sig = mono_method_signature (cfg->method);
1318 if (!cfg->arch.cinfo)
1319 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1320 cinfo = (CallInfo *)cfg->arch.cinfo;
1323 * FIXME: Remove some of the restrictions.
1325 cfg->arch.omit_fp = TRUE;
1326 cfg->arch.omit_fp_computed = TRUE;
1328 if (cfg->disable_omit_fp)
1329 cfg->arch.omit_fp = FALSE;
1331 if (!debug_omit_fp ())
1332 cfg->arch.omit_fp = FALSE;
1334 if (cfg->method->save_lmf)
1335 cfg->arch.omit_fp = FALSE;
1337 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1338 cfg->arch.omit_fp = FALSE;
1339 if (header->num_clauses)
1340 cfg->arch.omit_fp = FALSE;
1341 if (cfg->param_area)
1342 cfg->arch.omit_fp = FALSE;
1343 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1344 cfg->arch.omit_fp = FALSE;
1345 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1346 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1347 cfg->arch.omit_fp = FALSE;
1348 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1349 ArgInfo *ainfo = &cinfo->args [i];
1351 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1353 * The stack offset can only be determined when the frame
1356 cfg->arch.omit_fp = FALSE;
1361 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1362 MonoInst *ins = cfg->varinfo [i];
1365 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1370 mono_arch_get_global_int_regs (MonoCompile *cfg)
1374 mono_arch_compute_omit_fp (cfg);
1376 if (cfg->arch.omit_fp)
1377 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1379 /* We use the callee saved registers for global allocation */
1380 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1381 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1382 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1383 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1384 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1386 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1387 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1394 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1399 /* All XMM registers */
1400 for (i = 0; i < 16; ++i)
1401 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1407 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1409 static GList *r = NULL;
1414 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1415 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1416 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1417 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1418 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1419 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1421 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1422 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1423 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1424 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1425 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1426 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1427 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1428 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1430 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1437 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1440 static GList *r = NULL;
1445 for (i = 0; i < AMD64_XMM_NREG; ++i)
1446 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1448 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1455 * mono_arch_regalloc_cost:
1457 * Return the cost, in number of memory references, of the action of
1458 * allocating the variable VMV into a register during global register
1462 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1464 MonoInst *ins = cfg->varinfo [vmv->idx];
1466 if (cfg->method->save_lmf)
1467 /* The register is already saved */
1468 /* substract 1 for the invisible store in the prolog */
1469 return (ins->opcode == OP_ARG) ? 0 : 1;
1472 return (ins->opcode == OP_ARG) ? 1 : 2;
1476 * mono_arch_fill_argument_info:
1478 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1482 mono_arch_fill_argument_info (MonoCompile *cfg)
1485 MonoMethodSignature *sig;
1490 sig = mono_method_signature (cfg->method);
1492 cinfo = (CallInfo *)cfg->arch.cinfo;
1493 sig_ret = mini_get_underlying_type (sig->ret);
1496 * Contrary to mono_arch_allocate_vars (), the information should describe
1497 * where the arguments are at the beginning of the method, not where they can be
1498 * accessed during the execution of the method. The later makes no sense for the
1499 * global register allocator, since a variable can be in more than one location.
1501 switch (cinfo->ret.storage) {
1503 case ArgInFloatSSEReg:
1504 case ArgInDoubleSSEReg:
1505 cfg->ret->opcode = OP_REGVAR;
1506 cfg->ret->inst_c0 = cinfo->ret.reg;
1508 case ArgValuetypeInReg:
1509 cfg->ret->opcode = OP_REGOFFSET;
1510 cfg->ret->inst_basereg = -1;
1511 cfg->ret->inst_offset = -1;
1516 g_assert_not_reached ();
1519 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1520 ArgInfo *ainfo = &cinfo->args [i];
1522 ins = cfg->args [i];
1524 switch (ainfo->storage) {
1526 case ArgInFloatSSEReg:
1527 case ArgInDoubleSSEReg:
1528 ins->opcode = OP_REGVAR;
1529 ins->inst_c0 = ainfo->reg;
1532 ins->opcode = OP_REGOFFSET;
1533 ins->inst_basereg = -1;
1534 ins->inst_offset = -1;
1536 case ArgValuetypeInReg:
1538 ins->opcode = OP_NOP;
1541 g_assert_not_reached ();
1547 mono_arch_allocate_vars (MonoCompile *cfg)
1550 MonoMethodSignature *sig;
1553 guint32 locals_stack_size, locals_stack_align;
1557 sig = mono_method_signature (cfg->method);
1559 cinfo = (CallInfo *)cfg->arch.cinfo;
1560 sig_ret = mini_get_underlying_type (sig->ret);
1562 mono_arch_compute_omit_fp (cfg);
1565 * We use the ABI calling conventions for managed code as well.
1566 * Exception: valuetypes are only sometimes passed or returned in registers.
1570 * The stack looks like this:
1571 * <incoming arguments passed on the stack>
1573 * <lmf/caller saved registers>
1576 * <localloc area> -> grows dynamically
1580 if (cfg->arch.omit_fp) {
1581 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1582 cfg->frame_reg = AMD64_RSP;
1585 /* Locals are allocated backwards from %fp */
1586 cfg->frame_reg = AMD64_RBP;
1590 cfg->arch.saved_iregs = cfg->used_int_regs;
1591 if (cfg->method->save_lmf) {
1592 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1593 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1594 cfg->arch.saved_iregs |= iregs_to_save;
1597 if (cfg->arch.omit_fp)
1598 cfg->arch.reg_save_area_offset = offset;
1599 /* Reserve space for callee saved registers */
1600 for (i = 0; i < AMD64_NREG; ++i)
1601 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1602 offset += sizeof(mgreg_t);
1604 if (!cfg->arch.omit_fp)
1605 cfg->arch.reg_save_area_offset = -offset;
1607 if (sig_ret->type != MONO_TYPE_VOID) {
1608 switch (cinfo->ret.storage) {
1610 case ArgInFloatSSEReg:
1611 case ArgInDoubleSSEReg:
1612 cfg->ret->opcode = OP_REGVAR;
1613 cfg->ret->inst_c0 = cinfo->ret.reg;
1614 cfg->ret->dreg = cinfo->ret.reg;
1616 case ArgValuetypeAddrInIReg:
1617 case ArgGsharedvtVariableInReg:
1618 /* The register is volatile */
1619 cfg->vret_addr->opcode = OP_REGOFFSET;
1620 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1621 if (cfg->arch.omit_fp) {
1622 cfg->vret_addr->inst_offset = offset;
1626 cfg->vret_addr->inst_offset = -offset;
1628 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1629 printf ("vret_addr =");
1630 mono_print_ins (cfg->vret_addr);
1633 case ArgValuetypeInReg:
1634 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1635 cfg->ret->opcode = OP_REGOFFSET;
1636 cfg->ret->inst_basereg = cfg->frame_reg;
1637 if (cfg->arch.omit_fp) {
1638 cfg->ret->inst_offset = offset;
1639 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1641 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1642 cfg->ret->inst_offset = - offset;
1646 g_assert_not_reached ();
1650 /* Allocate locals */
1651 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1652 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1653 char *mname = mono_method_full_name (cfg->method, TRUE);
1654 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1659 if (locals_stack_align) {
1660 offset += (locals_stack_align - 1);
1661 offset &= ~(locals_stack_align - 1);
1663 if (cfg->arch.omit_fp) {
1664 cfg->locals_min_stack_offset = offset;
1665 cfg->locals_max_stack_offset = offset + locals_stack_size;
1667 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1668 cfg->locals_max_stack_offset = - offset;
1671 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1672 if (offsets [i] != -1) {
1673 MonoInst *ins = cfg->varinfo [i];
1674 ins->opcode = OP_REGOFFSET;
1675 ins->inst_basereg = cfg->frame_reg;
1676 if (cfg->arch.omit_fp)
1677 ins->inst_offset = (offset + offsets [i]);
1679 ins->inst_offset = - (offset + offsets [i]);
1680 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1683 offset += locals_stack_size;
1685 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1686 g_assert (!cfg->arch.omit_fp);
1687 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1688 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1691 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1692 ins = cfg->args [i];
1693 if (ins->opcode != OP_REGVAR) {
1694 ArgInfo *ainfo = &cinfo->args [i];
1695 gboolean inreg = TRUE;
1697 /* FIXME: Allocate volatile arguments to registers */
1698 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1702 * Under AMD64, all registers used to pass arguments to functions
1703 * are volatile across calls.
1704 * FIXME: Optimize this.
1706 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1709 ins->opcode = OP_REGOFFSET;
1711 switch (ainfo->storage) {
1713 case ArgInFloatSSEReg:
1714 case ArgInDoubleSSEReg:
1715 case ArgGSharedVtInReg:
1717 ins->opcode = OP_REGVAR;
1718 ins->dreg = ainfo->reg;
1722 case ArgGSharedVtOnStack:
1723 g_assert (!cfg->arch.omit_fp);
1724 ins->opcode = OP_REGOFFSET;
1725 ins->inst_basereg = cfg->frame_reg;
1726 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1728 case ArgValuetypeInReg:
1730 case ArgValuetypeAddrInIReg:
1731 case ArgValuetypeAddrOnStack: {
1733 g_assert (!cfg->arch.omit_fp);
1734 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1735 MONO_INST_NEW (cfg, indir, 0);
1737 indir->opcode = OP_REGOFFSET;
1738 if (ainfo->pair_storage [0] == ArgInIReg) {
1739 indir->inst_basereg = cfg->frame_reg;
1740 offset = ALIGN_TO (offset, sizeof (gpointer));
1741 offset += (sizeof (gpointer));
1742 indir->inst_offset = - offset;
1745 indir->inst_basereg = cfg->frame_reg;
1746 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1749 ins->opcode = OP_VTARG_ADDR;
1750 ins->inst_left = indir;
1758 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1759 ins->opcode = OP_REGOFFSET;
1760 ins->inst_basereg = cfg->frame_reg;
1761 /* These arguments are saved to the stack in the prolog */
1762 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1763 if (cfg->arch.omit_fp) {
1764 ins->inst_offset = offset;
1765 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1766 // Arguments are yet supported by the stack map creation code
1767 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1769 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1770 ins->inst_offset = - offset;
1771 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1777 cfg->stack_offset = offset;
1781 mono_arch_create_vars (MonoCompile *cfg)
1783 MonoMethodSignature *sig;
1787 sig = mono_method_signature (cfg->method);
1789 if (!cfg->arch.cinfo)
1790 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1791 cinfo = (CallInfo *)cfg->arch.cinfo;
1793 if (cinfo->ret.storage == ArgValuetypeInReg)
1794 cfg->ret_var_is_local = TRUE;
1796 sig_ret = mini_get_underlying_type (sig->ret);
1797 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1798 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1799 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1800 printf ("vret_addr = ");
1801 mono_print_ins (cfg->vret_addr);
1805 if (cfg->gen_sdb_seq_points) {
1808 if (cfg->compile_aot) {
1809 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1810 ins->flags |= MONO_INST_VOLATILE;
1811 cfg->arch.seq_point_info_var = ins;
1813 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1814 ins->flags |= MONO_INST_VOLATILE;
1815 cfg->arch.ss_tramp_var = ins;
1817 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1818 ins->flags |= MONO_INST_VOLATILE;
1819 cfg->arch.bp_tramp_var = ins;
1822 if (cfg->method->save_lmf)
1823 cfg->create_lmf_var = TRUE;
1825 if (cfg->method->save_lmf) {
1831 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1837 MONO_INST_NEW (cfg, ins, OP_MOVE);
1838 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1839 ins->sreg1 = tree->dreg;
1840 MONO_ADD_INS (cfg->cbb, ins);
1841 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1843 case ArgInFloatSSEReg:
1844 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1845 ins->dreg = mono_alloc_freg (cfg);
1846 ins->sreg1 = tree->dreg;
1847 MONO_ADD_INS (cfg->cbb, ins);
1849 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1851 case ArgInDoubleSSEReg:
1852 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1853 ins->dreg = mono_alloc_freg (cfg);
1854 ins->sreg1 = tree->dreg;
1855 MONO_ADD_INS (cfg->cbb, ins);
1857 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1861 g_assert_not_reached ();
1866 arg_storage_to_load_membase (ArgStorage storage)
1870 #if defined(__mono_ilp32__)
1871 return OP_LOADI8_MEMBASE;
1873 return OP_LOAD_MEMBASE;
1875 case ArgInDoubleSSEReg:
1876 return OP_LOADR8_MEMBASE;
1877 case ArgInFloatSSEReg:
1878 return OP_LOADR4_MEMBASE;
1880 g_assert_not_reached ();
1887 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1889 MonoMethodSignature *tmp_sig;
1892 if (call->tail_call)
1895 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1898 * mono_ArgIterator_Setup assumes the signature cookie is
1899 * passed first and all the arguments which were before it are
1900 * passed on the stack after the signature. So compensate by
1901 * passing a different signature.
1903 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1904 tmp_sig->param_count -= call->signature->sentinelpos;
1905 tmp_sig->sentinelpos = 0;
1906 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1908 sig_reg = mono_alloc_ireg (cfg);
1909 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1911 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1915 static inline LLVMArgStorage
1916 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1920 return LLVMArgInIReg;
1923 case ArgGSharedVtInReg:
1924 case ArgGSharedVtOnStack:
1925 return LLVMArgGSharedVt;
1927 g_assert_not_reached ();
1933 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1939 LLVMCallInfo *linfo;
1940 MonoType *t, *sig_ret;
1942 n = sig->param_count + sig->hasthis;
1943 sig_ret = mini_get_underlying_type (sig->ret);
1945 cinfo = get_call_info (cfg->mempool, sig);
1947 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1950 * LLVM always uses the native ABI while we use our own ABI, the
1951 * only difference is the handling of vtypes:
1952 * - we only pass/receive them in registers in some cases, and only
1953 * in 1 or 2 integer registers.
1955 switch (cinfo->ret.storage) {
1957 linfo->ret.storage = LLVMArgNone;
1960 case ArgInFloatSSEReg:
1961 case ArgInDoubleSSEReg:
1962 linfo->ret.storage = LLVMArgNormal;
1964 case ArgValuetypeInReg: {
1965 ainfo = &cinfo->ret;
1968 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1969 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1970 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1971 cfg->disable_llvm = TRUE;
1975 linfo->ret.storage = LLVMArgVtypeInReg;
1976 for (j = 0; j < 2; ++j)
1977 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1980 case ArgValuetypeAddrInIReg:
1981 case ArgGsharedvtVariableInReg:
1982 /* Vtype returned using a hidden argument */
1983 linfo->ret.storage = LLVMArgVtypeRetAddr;
1984 linfo->vret_arg_index = cinfo->vret_arg_index;
1987 g_assert_not_reached ();
1991 for (i = 0; i < n; ++i) {
1992 ainfo = cinfo->args + i;
1994 if (i >= sig->hasthis)
1995 t = sig->params [i - sig->hasthis];
1997 t = &mono_defaults.int_class->byval_arg;
1998 t = mini_type_get_underlying_type (t);
2000 linfo->args [i].storage = LLVMArgNone;
2002 switch (ainfo->storage) {
2004 linfo->args [i].storage = LLVMArgNormal;
2006 case ArgInDoubleSSEReg:
2007 case ArgInFloatSSEReg:
2008 linfo->args [i].storage = LLVMArgNormal;
2011 if (MONO_TYPE_ISSTRUCT (t))
2012 linfo->args [i].storage = LLVMArgVtypeByVal;
2014 linfo->args [i].storage = LLVMArgNormal;
2016 case ArgValuetypeInReg:
2018 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2019 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2020 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2021 cfg->disable_llvm = TRUE;
2025 linfo->args [i].storage = LLVMArgVtypeInReg;
2026 for (j = 0; j < 2; ++j)
2027 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2029 case ArgGSharedVtInReg:
2030 case ArgGSharedVtOnStack:
2031 linfo->args [i].storage = LLVMArgGSharedVt;
2034 cfg->exception_message = g_strdup ("ainfo->storage");
2035 cfg->disable_llvm = TRUE;
2045 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2048 MonoMethodSignature *sig;
2054 sig = call->signature;
2055 n = sig->param_count + sig->hasthis;
2057 cinfo = get_call_info (cfg->mempool, sig);
2061 if (COMPILE_LLVM (cfg)) {
2062 /* We shouldn't be called in the llvm case */
2063 cfg->disable_llvm = TRUE;
2068 * Emit all arguments which are passed on the stack to prevent register
2069 * allocation problems.
2071 for (i = 0; i < n; ++i) {
2073 ainfo = cinfo->args + i;
2075 in = call->args [i];
2077 if (sig->hasthis && i == 0)
2078 t = &mono_defaults.object_class->byval_arg;
2080 t = sig->params [i - sig->hasthis];
2082 t = mini_get_underlying_type (t);
2083 //XXX what about ArgGSharedVtOnStack here?
2084 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2086 if (t->type == MONO_TYPE_R4)
2087 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2088 else if (t->type == MONO_TYPE_R8)
2089 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2091 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2093 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2095 if (cfg->compute_gc_maps) {
2098 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2104 * Emit all parameters passed in registers in non-reverse order for better readability
2105 * and to help the optimization in emit_prolog ().
2107 for (i = 0; i < n; ++i) {
2108 ainfo = cinfo->args + i;
2110 in = call->args [i];
2112 if (ainfo->storage == ArgInIReg)
2113 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2116 for (i = n - 1; i >= 0; --i) {
2119 ainfo = cinfo->args + i;
2121 in = call->args [i];
2123 if (sig->hasthis && i == 0)
2124 t = &mono_defaults.object_class->byval_arg;
2126 t = sig->params [i - sig->hasthis];
2127 t = mini_get_underlying_type (t);
2129 switch (ainfo->storage) {
2133 case ArgInFloatSSEReg:
2134 case ArgInDoubleSSEReg:
2135 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2138 case ArgValuetypeInReg:
2139 case ArgValuetypeAddrInIReg:
2140 case ArgValuetypeAddrOnStack:
2141 case ArgGSharedVtInReg:
2142 case ArgGSharedVtOnStack: {
2143 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2144 /* Already emitted above */
2146 //FIXME what about ArgGSharedVtOnStack ?
2147 if (ainfo->storage == ArgOnStack && call->tail_call) {
2148 MonoInst *call_inst = (MonoInst*)call;
2149 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2150 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2158 size = mono_type_native_stack_size (t, &align);
2161 * Other backends use mono_type_stack_size (), but that
2162 * aligns the size to 8, which is larger than the size of
2163 * the source, leading to reads of invalid memory if the
2164 * source is at the end of address space.
2166 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2169 if (size >= 10000) {
2170 /* Avoid asserts in emit_memcpy () */
2171 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2172 /* Continue normally */
2175 if (size > 0 || ainfo->pass_empty_struct) {
2176 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2177 arg->sreg1 = in->dreg;
2178 arg->klass = mono_class_from_mono_type (t);
2179 arg->backend.size = size;
2180 arg->inst_p0 = call;
2181 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2182 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2184 MONO_ADD_INS (cfg->cbb, arg);
2189 g_assert_not_reached ();
2192 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2193 /* Emit the signature cookie just before the implicit arguments */
2194 emit_sig_cookie (cfg, call, cinfo);
2197 /* Handle the case where there are no implicit arguments */
2198 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2199 emit_sig_cookie (cfg, call, cinfo);
2201 switch (cinfo->ret.storage) {
2202 case ArgValuetypeInReg:
2203 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2205 * Tell the JIT to use a more efficient calling convention: call using
2206 * OP_CALL, compute the result location after the call, and save the
2209 call->vret_in_reg = TRUE;
2211 * Nullify the instruction computing the vret addr to enable
2212 * future optimizations.
2215 NULLIFY_INS (call->vret_var);
2217 if (call->tail_call)
2220 * The valuetype is in RAX:RDX after the call, need to be copied to
2221 * the stack. Push the address here, so the call instruction can
2224 if (!cfg->arch.vret_addr_loc) {
2225 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2226 /* Prevent it from being register allocated or optimized away */
2227 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2230 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2233 case ArgValuetypeAddrInIReg:
2234 case ArgGsharedvtVariableInReg: {
2236 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2237 vtarg->sreg1 = call->vret_var->dreg;
2238 vtarg->dreg = mono_alloc_preg (cfg);
2239 MONO_ADD_INS (cfg->cbb, vtarg);
2241 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2248 if (cfg->method->save_lmf) {
2249 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2250 MONO_ADD_INS (cfg->cbb, arg);
2253 call->stack_usage = cinfo->stack_usage;
2257 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2260 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2261 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2262 int size = ins->backend.size;
2264 switch (ainfo->storage) {
2265 case ArgValuetypeInReg: {
2269 for (part = 0; part < 2; ++part) {
2270 if (ainfo->pair_storage [part] == ArgNone)
2273 if (ainfo->pass_empty_struct) {
2274 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2275 NEW_ICONST (cfg, load, 0);
2278 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2279 load->inst_basereg = src->dreg;
2280 load->inst_offset = part * sizeof(mgreg_t);
2282 switch (ainfo->pair_storage [part]) {
2284 load->dreg = mono_alloc_ireg (cfg);
2286 case ArgInDoubleSSEReg:
2287 case ArgInFloatSSEReg:
2288 load->dreg = mono_alloc_freg (cfg);
2291 g_assert_not_reached ();
2295 MONO_ADD_INS (cfg->cbb, load);
2297 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2301 case ArgValuetypeAddrInIReg:
2302 case ArgValuetypeAddrOnStack: {
2303 MonoInst *vtaddr, *load;
2305 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2307 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2309 MONO_INST_NEW (cfg, load, OP_LDADDR);
2310 cfg->has_indirection = TRUE;
2311 load->inst_p0 = vtaddr;
2312 vtaddr->flags |= MONO_INST_INDIRECT;
2313 load->type = STACK_MP;
2314 load->klass = vtaddr->klass;
2315 load->dreg = mono_alloc_ireg (cfg);
2316 MONO_ADD_INS (cfg->cbb, load);
2317 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2319 if (ainfo->pair_storage [0] == ArgInIReg) {
2320 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2321 arg->dreg = mono_alloc_ireg (cfg);
2322 arg->sreg1 = load->dreg;
2324 MONO_ADD_INS (cfg->cbb, arg);
2325 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2327 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2331 case ArgGSharedVtInReg:
2333 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2335 case ArgGSharedVtOnStack:
2336 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2340 int dreg = mono_alloc_ireg (cfg);
2342 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2343 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2344 } else if (size <= 40) {
2345 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2347 // FIXME: Code growth
2348 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2351 if (cfg->compute_gc_maps) {
2353 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2359 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2361 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2363 if (ret->type == MONO_TYPE_R4) {
2364 if (COMPILE_LLVM (cfg))
2365 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2367 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2369 } else if (ret->type == MONO_TYPE_R8) {
2370 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2374 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2377 #endif /* DISABLE_JIT */
2379 #define EMIT_COND_BRANCH(ins,cond,sign) \
2380 if (ins->inst_true_bb->native_offset) { \
2381 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2383 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2384 if ((cfg->opt & MONO_OPT_BRANCH) && \
2385 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2386 x86_branch8 (code, cond, 0, sign); \
2388 x86_branch32 (code, cond, 0, sign); \
2392 MonoMethodSignature *sig;
2397 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2401 switch (cinfo->ret.storage) {
2404 case ArgInFloatSSEReg:
2405 case ArgInDoubleSSEReg:
2406 case ArgValuetypeAddrInIReg:
2407 case ArgValuetypeInReg:
2413 for (i = 0; i < cinfo->nargs; ++i) {
2414 ArgInfo *ainfo = &cinfo->args [i];
2415 switch (ainfo->storage) {
2417 case ArgInFloatSSEReg:
2418 case ArgInDoubleSSEReg:
2419 case ArgValuetypeInReg:
2422 if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2434 * mono_arch_dyn_call_prepare:
2436 * Return a pointer to an arch-specific structure which contains information
2437 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2438 * supported for SIG.
2439 * This function is equivalent to ffi_prep_cif in libffi.
2442 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2444 ArchDynCallInfo *info;
2447 cinfo = get_call_info (NULL, sig);
2449 if (!dyn_call_supported (sig, cinfo)) {
2454 info = g_new0 (ArchDynCallInfo, 1);
2455 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2457 info->cinfo = cinfo;
2459 return (MonoDynCallInfo*)info;
2463 * mono_arch_dyn_call_free:
2465 * Free a MonoDynCallInfo structure.
2468 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2470 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2472 g_free (ainfo->cinfo);
2476 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2477 #define GREG_TO_PTR(greg) (gpointer)(greg)
2480 * mono_arch_get_start_dyn_call:
2482 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2483 * store the result into BUF.
2484 * ARGS should be an array of pointers pointing to the arguments.
2485 * RET should point to a memory buffer large enought to hold the result of the
2487 * This function should be as fast as possible, any work which does not depend
2488 * on the actual values of the arguments should be done in
2489 * mono_arch_dyn_call_prepare ().
2490 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2494 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2496 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2497 DynCallArgs *p = (DynCallArgs*)buf;
2498 int arg_index, greg, freg, i, pindex;
2499 MonoMethodSignature *sig = dinfo->sig;
2500 int buffer_offset = 0;
2501 static int param_reg_to_index [16];
2502 static gboolean param_reg_to_index_inited;
2504 if (!param_reg_to_index_inited) {
2505 for (i = 0; i < PARAM_REGS; ++i)
2506 param_reg_to_index [param_regs [i]] = i;
2507 mono_memory_barrier ();
2508 param_reg_to_index_inited = 1;
2511 g_assert (buf_len >= sizeof (DynCallArgs));
2521 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2522 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2527 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2528 p->regs [greg ++] = PTR_TO_GREG(ret);
2530 for (; pindex < sig->param_count; pindex++) {
2531 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2532 gpointer *arg = args [arg_index ++];
2533 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2536 if (ainfo->storage == ArgOnStack) {
2537 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2539 slot = param_reg_to_index [ainfo->reg];
2543 p->regs [slot] = PTR_TO_GREG(*(arg));
2549 case MONO_TYPE_STRING:
2550 case MONO_TYPE_CLASS:
2551 case MONO_TYPE_ARRAY:
2552 case MONO_TYPE_SZARRAY:
2553 case MONO_TYPE_OBJECT:
2557 #if !defined(__mono_ilp32__)
2561 p->regs [slot] = PTR_TO_GREG(*(arg));
2563 #if defined(__mono_ilp32__)
2566 p->regs [slot] = *(guint64*)(arg);
2570 p->regs [slot] = *(guint8*)(arg);
2573 p->regs [slot] = *(gint8*)(arg);
2576 p->regs [slot] = *(gint16*)(arg);
2579 p->regs [slot] = *(guint16*)(arg);
2582 p->regs [slot] = *(gint32*)(arg);
2585 p->regs [slot] = *(guint32*)(arg);
2587 case MONO_TYPE_R4: {
2590 *(float*)&d = *(float*)(arg);
2592 p->fregs [freg ++] = d;
2597 p->fregs [freg ++] = *(double*)(arg);
2599 case MONO_TYPE_GENERICINST:
2600 if (MONO_TYPE_IS_REFERENCE (t)) {
2601 p->regs [slot] = PTR_TO_GREG(*(arg));
2603 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2604 MonoClass *klass = mono_class_from_mono_type (t);
2605 guint8 *nullable_buf;
2608 size = mono_class_value_size (klass, NULL);
2609 nullable_buf = p->buffer + buffer_offset;
2610 buffer_offset += size;
2611 g_assert (buffer_offset <= 256);
2613 /* The argument pointed to by arg is either a boxed vtype or null */
2614 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2616 arg = (gpointer*)nullable_buf;
2622 case MONO_TYPE_VALUETYPE: {
2623 switch (ainfo->storage) {
2624 case ArgValuetypeInReg:
2625 for (i = 0; i < 2; ++i) {
2626 switch (ainfo->pair_storage [i]) {
2630 slot = param_reg_to_index [ainfo->pair_regs [i]];
2631 p->regs [slot] = ((mgreg_t*)(arg))[i];
2633 case ArgInDoubleSSEReg:
2635 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2638 g_assert_not_reached ();
2644 for (i = 0; i < ainfo->arg_size / 8; ++i)
2645 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2648 g_assert_not_reached ();
2654 g_assert_not_reached ();
2660 * mono_arch_finish_dyn_call:
2662 * Store the result of a dyn call into the return value buffer passed to
2663 * start_dyn_call ().
2664 * This function should be as fast as possible, any work which does not depend
2665 * on the actual values of the arguments should be done in
2666 * mono_arch_dyn_call_prepare ().
2669 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2671 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2672 MonoMethodSignature *sig = dinfo->sig;
2673 DynCallArgs *dargs = (DynCallArgs*)buf;
2674 guint8 *ret = dargs->ret;
2675 mgreg_t res = dargs->res;
2676 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2679 switch (sig_ret->type) {
2680 case MONO_TYPE_VOID:
2681 *(gpointer*)ret = NULL;
2683 case MONO_TYPE_STRING:
2684 case MONO_TYPE_CLASS:
2685 case MONO_TYPE_ARRAY:
2686 case MONO_TYPE_SZARRAY:
2687 case MONO_TYPE_OBJECT:
2691 *(gpointer*)ret = GREG_TO_PTR(res);
2697 *(guint8*)ret = res;
2700 *(gint16*)ret = res;
2703 *(guint16*)ret = res;
2706 *(gint32*)ret = res;
2709 *(guint32*)ret = res;
2712 *(gint64*)ret = res;
2715 *(guint64*)ret = res;
2718 *(float*)ret = *(float*)&(dargs->fregs [0]);
2721 *(double*)ret = dargs->fregs [0];
2723 case MONO_TYPE_GENERICINST:
2724 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2725 *(gpointer*)ret = GREG_TO_PTR(res);
2730 case MONO_TYPE_VALUETYPE:
2731 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2734 ArgInfo *ainfo = &dinfo->cinfo->ret;
2736 g_assert (ainfo->storage == ArgValuetypeInReg);
2738 for (i = 0; i < 2; ++i) {
2739 switch (ainfo->pair_storage [0]) {
2741 ((mgreg_t*)ret)[i] = res;
2743 case ArgInDoubleSSEReg:
2744 ((double*)ret)[i] = dargs->fregs [i];
2749 g_assert_not_reached ();
2756 g_assert_not_reached ();
2760 /* emit an exception if condition is fail */
2761 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2763 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2764 if (tins == NULL) { \
2765 mono_add_patch_info (cfg, code - cfg->native_code, \
2766 MONO_PATCH_INFO_EXC, exc_name); \
2767 x86_branch32 (code, cond, 0, signed); \
2769 EMIT_COND_BRANCH (tins, cond, signed); \
2773 #define EMIT_FPCOMPARE(code) do { \
2774 amd64_fcompp (code); \
2775 amd64_fnstsw (code); \
2778 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2779 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2780 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2781 amd64_ ##op (code); \
2782 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2783 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2787 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2789 gboolean no_patch = FALSE;
2792 * FIXME: Add support for thunks
2795 gboolean near_call = FALSE;
2798 * Indirect calls are expensive so try to make a near call if possible.
2799 * The caller memory is allocated by the code manager so it is
2800 * guaranteed to be at a 32 bit offset.
2803 if (patch_type != MONO_PATCH_INFO_ABS) {
2804 /* The target is in memory allocated using the code manager */
2807 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2808 if (((MonoMethod*)data)->klass->image->aot_module)
2809 /* The callee might be an AOT method */
2811 if (((MonoMethod*)data)->dynamic)
2812 /* The target is in malloc-ed memory */
2816 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2818 * The call might go directly to a native function without
2821 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2823 gconstpointer target = mono_icall_get_wrapper (mi);
2824 if ((((guint64)target) >> 32) != 0)
2830 MonoJumpInfo *jinfo = NULL;
2832 if (cfg->abs_patches)
2833 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2835 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2836 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2837 if (mi && (((guint64)mi->func) >> 32) == 0)
2842 * This is not really an optimization, but required because the
2843 * generic class init trampolines use R11 to pass the vtable.
2848 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2850 if (info->func == info->wrapper) {
2852 if ((((guint64)info->func) >> 32) == 0)
2856 /* See the comment in mono_codegen () */
2857 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2861 else if ((((guint64)data) >> 32) == 0) {
2868 if (cfg->method->dynamic)
2869 /* These methods are allocated using malloc */
2872 #ifdef MONO_ARCH_NOMAP32BIT
2875 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2876 if (optimize_for_xen)
2879 if (cfg->compile_aot) {
2886 * Align the call displacement to an address divisible by 4 so it does
2887 * not span cache lines. This is required for code patching to work on SMP
2890 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2891 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2892 amd64_padding (code, pad_size);
2894 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2895 amd64_call_code (code, 0);
2898 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2899 amd64_set_reg_template (code, GP_SCRATCH_REG);
2900 amd64_call_reg (code, GP_SCRATCH_REG);
2907 static inline guint8*
2908 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2911 if (win64_adjust_stack)
2912 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2914 code = emit_call_body (cfg, code, patch_type, data);
2916 if (win64_adjust_stack)
2917 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2924 store_membase_imm_to_store_membase_reg (int opcode)
2927 case OP_STORE_MEMBASE_IMM:
2928 return OP_STORE_MEMBASE_REG;
2929 case OP_STOREI4_MEMBASE_IMM:
2930 return OP_STOREI4_MEMBASE_REG;
2931 case OP_STOREI8_MEMBASE_IMM:
2932 return OP_STOREI8_MEMBASE_REG;
2940 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2943 * mono_arch_peephole_pass_1:
2945 * Perform peephole opts which should/can be performed before local regalloc
2948 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2952 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2953 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2955 switch (ins->opcode) {
2959 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2961 * X86_LEA is like ADD, but doesn't have the
2962 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2963 * its operand to 64 bit.
2965 ins->opcode = OP_X86_LEA_MEMBASE;
2966 ins->inst_basereg = ins->sreg1;
2971 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2975 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2976 * the latter has length 2-3 instead of 6 (reverse constant
2977 * propagation). These instruction sequences are very common
2978 * in the initlocals bblock.
2980 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2981 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2982 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2983 ins2->sreg1 = ins->dreg;
2984 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2986 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2989 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2997 case OP_COMPARE_IMM:
2998 case OP_LCOMPARE_IMM:
2999 /* OP_COMPARE_IMM (reg, 0)
3001 * OP_AMD64_TEST_NULL (reg)
3004 ins->opcode = OP_AMD64_TEST_NULL;
3006 case OP_ICOMPARE_IMM:
3008 ins->opcode = OP_X86_TEST_NULL;
3010 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3012 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3013 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3015 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3016 * OP_COMPARE_IMM reg, imm
3018 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3020 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3021 ins->inst_basereg == last_ins->inst_destbasereg &&
3022 ins->inst_offset == last_ins->inst_offset) {
3023 ins->opcode = OP_ICOMPARE_IMM;
3024 ins->sreg1 = last_ins->sreg1;
3026 /* check if we can remove cmp reg,0 with test null */
3028 ins->opcode = OP_X86_TEST_NULL;
3034 mono_peephole_ins (bb, ins);
3039 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3043 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3044 switch (ins->opcode) {
3047 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3048 /* reg = 0 -> XOR (reg, reg) */
3049 /* XOR sets cflags on x86, so we cant do it always */
3050 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3051 ins->opcode = OP_LXOR;
3052 ins->sreg1 = ins->dreg;
3053 ins->sreg2 = ins->dreg;
3061 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3062 * 0 result into 64 bits.
3064 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3065 ins->opcode = OP_IXOR;
3069 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3073 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3074 * the latter has length 2-3 instead of 6 (reverse constant
3075 * propagation). These instruction sequences are very common
3076 * in the initlocals bblock.
3078 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3079 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3080 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3081 ins2->sreg1 = ins->dreg;
3082 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3084 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3087 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3096 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3097 ins->opcode = OP_X86_INC_REG;
3100 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3101 ins->opcode = OP_X86_DEC_REG;
3105 mono_peephole_ins (bb, ins);
3109 #define NEW_INS(cfg,ins,dest,op) do { \
3110 MONO_INST_NEW ((cfg), (dest), (op)); \
3111 (dest)->cil_code = (ins)->cil_code; \
3112 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3116 * mono_arch_lowering_pass:
3118 * Converts complex opcodes into simpler ones so that each IR instruction
3119 * corresponds to one machine instruction.
3122 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3124 MonoInst *ins, *n, *temp;
3127 * FIXME: Need to add more instructions, but the current machine
3128 * description can't model some parts of the composite instructions like
3131 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3132 switch (ins->opcode) {
3136 case OP_IDIV_UN_IMM:
3137 case OP_IREM_UN_IMM:
3140 mono_decompose_op_imm (cfg, bb, ins);
3142 case OP_COMPARE_IMM:
3143 case OP_LCOMPARE_IMM:
3144 if (!amd64_use_imm32 (ins->inst_imm)) {
3145 NEW_INS (cfg, ins, temp, OP_I8CONST);
3146 temp->inst_c0 = ins->inst_imm;
3147 temp->dreg = mono_alloc_ireg (cfg);
3148 ins->opcode = OP_COMPARE;
3149 ins->sreg2 = temp->dreg;
3152 #ifndef __mono_ilp32__
3153 case OP_LOAD_MEMBASE:
3155 case OP_LOADI8_MEMBASE:
3156 /* Don't generate memindex opcodes (to simplify */
3157 /* read sandboxing) */
3158 if (!amd64_use_imm32 (ins->inst_offset)) {
3159 NEW_INS (cfg, ins, temp, OP_I8CONST);
3160 temp->inst_c0 = ins->inst_offset;
3161 temp->dreg = mono_alloc_ireg (cfg);
3162 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3163 ins->inst_indexreg = temp->dreg;
3166 #ifndef __mono_ilp32__
3167 case OP_STORE_MEMBASE_IMM:
3169 case OP_STOREI8_MEMBASE_IMM:
3170 if (!amd64_use_imm32 (ins->inst_imm)) {
3171 NEW_INS (cfg, ins, temp, OP_I8CONST);
3172 temp->inst_c0 = ins->inst_imm;
3173 temp->dreg = mono_alloc_ireg (cfg);
3174 ins->opcode = OP_STOREI8_MEMBASE_REG;
3175 ins->sreg1 = temp->dreg;
3178 #ifdef MONO_ARCH_SIMD_INTRINSICS
3179 case OP_EXPAND_I1: {
3180 int temp_reg1 = mono_alloc_ireg (cfg);
3181 int temp_reg2 = mono_alloc_ireg (cfg);
3182 int original_reg = ins->sreg1;
3184 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3185 temp->sreg1 = original_reg;
3186 temp->dreg = temp_reg1;
3188 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3189 temp->sreg1 = temp_reg1;
3190 temp->dreg = temp_reg2;
3193 NEW_INS (cfg, ins, temp, OP_LOR);
3194 temp->sreg1 = temp->dreg = temp_reg2;
3195 temp->sreg2 = temp_reg1;
3197 ins->opcode = OP_EXPAND_I2;
3198 ins->sreg1 = temp_reg2;
3207 bb->max_vreg = cfg->next_vreg;
3211 branch_cc_table [] = {
3212 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3213 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3214 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3217 /* Maps CMP_... constants to X86_CC_... constants */
3220 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3221 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3225 cc_signed_table [] = {
3226 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3227 FALSE, FALSE, FALSE, FALSE
3230 /*#include "cprop.c"*/
3232 static unsigned char*
3233 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3236 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3238 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3241 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3243 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3247 static unsigned char*
3248 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3250 int sreg = tree->sreg1;
3251 int need_touch = FALSE;
3253 #if defined(TARGET_WIN32)
3255 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3256 if (!tree->flags & MONO_INST_INIT)
3265 * If requested stack size is larger than one page,
3266 * perform stack-touch operation
3269 * Generate stack probe code.
3270 * Under Windows, it is necessary to allocate one page at a time,
3271 * "touching" stack after each successful sub-allocation. This is
3272 * because of the way stack growth is implemented - there is a
3273 * guard page before the lowest stack page that is currently commited.
3274 * Stack normally grows sequentially so OS traps access to the
3275 * guard page and commits more pages when needed.
3277 amd64_test_reg_imm (code, sreg, ~0xFFF);
3278 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3280 br[2] = code; /* loop */
3281 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3282 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3283 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3284 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3285 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3286 amd64_patch (br[3], br[2]);
3287 amd64_test_reg_reg (code, sreg, sreg);
3288 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3289 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3291 br[1] = code; x86_jump8 (code, 0);
3293 amd64_patch (br[0], code);
3294 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3295 amd64_patch (br[1], code);
3296 amd64_patch (br[4], code);
3299 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3301 if (tree->flags & MONO_INST_INIT) {
3303 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3304 amd64_push_reg (code, AMD64_RAX);
3307 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3308 amd64_push_reg (code, AMD64_RCX);
3311 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3312 amd64_push_reg (code, AMD64_RDI);
3316 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3317 if (sreg != AMD64_RCX)
3318 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3319 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3321 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3322 if (cfg->param_area)
3323 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3325 amd64_prefix (code, X86_REP_PREFIX);
3328 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3329 amd64_pop_reg (code, AMD64_RDI);
3330 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3331 amd64_pop_reg (code, AMD64_RCX);
3332 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3333 amd64_pop_reg (code, AMD64_RAX);
3339 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3344 /* Move return value to the target register */
3345 /* FIXME: do this in the local reg allocator */
3346 switch (ins->opcode) {
3349 case OP_CALL_MEMBASE:
3352 case OP_LCALL_MEMBASE:
3353 g_assert (ins->dreg == AMD64_RAX);
3357 case OP_FCALL_MEMBASE: {
3358 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3359 if (rtype->type == MONO_TYPE_R4) {
3360 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3363 if (ins->dreg != AMD64_XMM0)
3364 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3370 case OP_RCALL_MEMBASE:
3371 if (ins->dreg != AMD64_XMM0)
3372 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3376 case OP_VCALL_MEMBASE:
3379 case OP_VCALL2_MEMBASE:
3380 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3381 if (cinfo->ret.storage == ArgValuetypeInReg) {
3382 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3384 /* Load the destination address */
3385 g_assert (loc->opcode == OP_REGOFFSET);
3386 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3388 for (quad = 0; quad < 2; quad ++) {
3389 switch (cinfo->ret.pair_storage [quad]) {
3391 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3393 case ArgInFloatSSEReg:
3394 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3396 case ArgInDoubleSSEReg:
3397 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3412 #endif /* DISABLE_JIT */
3415 static int tls_gs_offset;
3419 mono_arch_have_fast_tls (void)
3422 static gboolean have_fast_tls = FALSE;
3423 static gboolean inited = FALSE;
3426 if (mini_get_debug_options ()->use_fallback_tls)
3430 return have_fast_tls;
3432 ins = (guint8*)pthread_getspecific;
3435 * We're looking for these two instructions:
3437 * mov %gs:[offset](,%rdi,8),%rax
3440 have_fast_tls = ins [0] == 0x65 &&
3450 tls_gs_offset = ins[5];
3453 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3454 * For that version we're looking for these instructions:
3458 * mov %gs:[offset](,%rdi,8),%rax
3462 if (!have_fast_tls) {
3463 have_fast_tls = ins [0] == 0x55 &&
3478 tls_gs_offset = ins[9];
3482 return have_fast_tls;
3483 #elif defined(TARGET_ANDROID)
3486 if (mini_get_debug_options ()->use_fallback_tls)
3493 mono_amd64_get_tls_gs_offset (void)
3496 return tls_gs_offset;
3498 g_assert_not_reached ();
3504 * \param code buffer to store code to
3505 * \param dreg hard register where to place the result
3506 * \param tls_offset offset info
3507 * \return a pointer to the end of the stored code
3509 * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3510 * the dreg register the item in the thread local storage identified
3514 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3517 if (tls_offset < 64) {
3518 x86_prefix (code, X86_GS_PREFIX);
3519 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3523 g_assert (tls_offset < 0x440);
3524 /* Load TEB->TlsExpansionSlots */
3525 x86_prefix (code, X86_GS_PREFIX);
3526 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3527 amd64_test_reg_reg (code, dreg, dreg);
3529 amd64_branch (code, X86_CC_EQ, code, TRUE);
3530 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3531 amd64_patch (buf [0], code);
3533 #elif defined(TARGET_MACH)
3534 x86_prefix (code, X86_GS_PREFIX);
3535 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3537 if (optimize_for_xen) {
3538 x86_prefix (code, X86_FS_PREFIX);
3539 amd64_mov_reg_mem (code, dreg, 0, 8);
3540 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3542 x86_prefix (code, X86_FS_PREFIX);
3543 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3550 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3553 g_assert_not_reached ();
3554 #elif defined(TARGET_MACH)
3555 x86_prefix (code, X86_GS_PREFIX);
3556 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3558 g_assert (!optimize_for_xen);
3559 x86_prefix (code, X86_FS_PREFIX);
3560 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3568 * Emit code to initialize an LMF structure at LMF_OFFSET.
3571 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3574 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3577 * sp is saved right before calls but we need to save it here too so
3578 * async stack walks would work.
3580 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3582 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3583 if (cfg->arch.omit_fp && cfa_offset != -1)
3584 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3586 /* These can't contain refs */
3587 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3588 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3589 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3590 /* These are handled automatically by the stack marking code */
3591 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3598 #define TEB_LAST_ERROR_OFFSET 0x068
3601 emit_get_last_error (guint8* code, int dreg)
3603 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3604 x86_prefix (code, X86_GS_PREFIX);
3605 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3613 emit_get_last_error (guint8* code, int dreg)
3615 g_assert_not_reached ();
3620 /* benchmark and set based on cpu */
3621 #define LOOP_ALIGNMENT 8
3622 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3626 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3631 guint8 *code = cfg->native_code + cfg->code_len;
3634 /* Fix max_offset estimate for each successor bb */
3635 if (cfg->opt & MONO_OPT_BRANCH) {
3636 int current_offset = cfg->code_len;
3637 MonoBasicBlock *current_bb;
3638 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3639 current_bb->max_offset = current_offset;
3640 current_offset += current_bb->max_length;
3644 if (cfg->opt & MONO_OPT_LOOP) {
3645 int pad, align = LOOP_ALIGNMENT;
3646 /* set alignment depending on cpu */
3647 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3649 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3650 amd64_padding (code, pad);
3651 cfg->code_len += pad;
3652 bb->native_offset = cfg->code_len;
3656 if (cfg->verbose_level > 2)
3657 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3659 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3660 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3661 g_assert (!cfg->compile_aot);
3663 cov->data [bb->dfn].cil_code = bb->cil_code;
3664 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3665 /* this is not thread save, but good enough */
3666 amd64_inc_membase (code, AMD64_R11, 0);
3669 offset = code - cfg->native_code;
3671 mono_debug_open_block (cfg, bb, offset);
3673 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3674 x86_breakpoint (code);
3676 MONO_BB_FOR_EACH_INS (bb, ins) {
3677 offset = code - cfg->native_code;
3679 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3681 #define EXTRA_CODE_SPACE (16)
3683 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3684 cfg->code_size *= 2;
3685 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3686 code = cfg->native_code + offset;
3687 cfg->stat_code_reallocs++;
3690 if (cfg->debug_info)
3691 mono_debug_record_line_number (cfg, ins, offset);
3693 switch (ins->opcode) {
3695 amd64_mul_reg (code, ins->sreg2, TRUE);
3698 amd64_mul_reg (code, ins->sreg2, FALSE);
3700 case OP_X86_SETEQ_MEMBASE:
3701 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3703 case OP_STOREI1_MEMBASE_IMM:
3704 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3706 case OP_STOREI2_MEMBASE_IMM:
3707 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3709 case OP_STOREI4_MEMBASE_IMM:
3710 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3712 case OP_STOREI1_MEMBASE_REG:
3713 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3715 case OP_STOREI2_MEMBASE_REG:
3716 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3718 /* In AMD64 NaCl, pointers are 4 bytes, */
3719 /* so STORE_* != STOREI8_*. Likewise below. */
3720 case OP_STORE_MEMBASE_REG:
3721 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3723 case OP_STOREI8_MEMBASE_REG:
3724 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3726 case OP_STOREI4_MEMBASE_REG:
3727 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3729 case OP_STORE_MEMBASE_IMM:
3730 /* In NaCl, this could be a PCONST type, which could */
3731 /* mean a pointer type was copied directly into the */
3732 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3733 /* the value would be 0x00000000FFFFFFFF which is */
3734 /* not proper for an imm32 unless you cast it. */
3735 g_assert (amd64_is_imm32 (ins->inst_imm));
3736 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3738 case OP_STOREI8_MEMBASE_IMM:
3739 g_assert (amd64_is_imm32 (ins->inst_imm));
3740 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3743 #ifdef __mono_ilp32__
3744 /* In ILP32, pointers are 4 bytes, so separate these */
3745 /* cases, use literal 8 below where we really want 8 */
3746 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3747 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3751 // FIXME: Decompose this earlier
3752 if (amd64_use_imm32 (ins->inst_imm))
3753 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3755 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3756 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3760 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3761 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3764 // FIXME: Decompose this earlier
3765 if (amd64_use_imm32 (ins->inst_imm))
3766 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3768 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3769 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3773 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3774 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3777 /* For NaCl, pointers are 4 bytes, so separate these */
3778 /* cases, use literal 8 below where we really want 8 */
3779 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3780 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3782 case OP_LOAD_MEMBASE:
3783 g_assert (amd64_is_imm32 (ins->inst_offset));
3784 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3786 case OP_LOADI8_MEMBASE:
3787 /* Use literal 8 instead of sizeof pointer or */
3788 /* register, we really want 8 for this opcode */
3789 g_assert (amd64_is_imm32 (ins->inst_offset));
3790 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3792 case OP_LOADI4_MEMBASE:
3793 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3795 case OP_LOADU4_MEMBASE:
3796 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3798 case OP_LOADU1_MEMBASE:
3799 /* The cpu zero extends the result into 64 bits */
3800 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3802 case OP_LOADI1_MEMBASE:
3803 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3805 case OP_LOADU2_MEMBASE:
3806 /* The cpu zero extends the result into 64 bits */
3807 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3809 case OP_LOADI2_MEMBASE:
3810 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3812 case OP_AMD64_LOADI8_MEMINDEX:
3813 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3815 case OP_LCONV_TO_I1:
3816 case OP_ICONV_TO_I1:
3818 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3820 case OP_LCONV_TO_I2:
3821 case OP_ICONV_TO_I2:
3823 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3825 case OP_LCONV_TO_U1:
3826 case OP_ICONV_TO_U1:
3827 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3829 case OP_LCONV_TO_U2:
3830 case OP_ICONV_TO_U2:
3831 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3834 /* Clean out the upper word */
3835 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3838 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3842 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3844 case OP_COMPARE_IMM:
3845 #if defined(__mono_ilp32__)
3846 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3847 g_assert (amd64_is_imm32 (ins->inst_imm));
3848 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3851 case OP_LCOMPARE_IMM:
3852 g_assert (amd64_is_imm32 (ins->inst_imm));
3853 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3855 case OP_X86_COMPARE_REG_MEMBASE:
3856 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3858 case OP_X86_TEST_NULL:
3859 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3861 case OP_AMD64_TEST_NULL:
3862 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3865 case OP_X86_ADD_REG_MEMBASE:
3866 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3868 case OP_X86_SUB_REG_MEMBASE:
3869 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3871 case OP_X86_AND_REG_MEMBASE:
3872 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3874 case OP_X86_OR_REG_MEMBASE:
3875 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3877 case OP_X86_XOR_REG_MEMBASE:
3878 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3881 case OP_X86_ADD_MEMBASE_IMM:
3882 /* FIXME: Make a 64 version too */
3883 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3885 case OP_X86_SUB_MEMBASE_IMM:
3886 g_assert (amd64_is_imm32 (ins->inst_imm));
3887 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3889 case OP_X86_AND_MEMBASE_IMM:
3890 g_assert (amd64_is_imm32 (ins->inst_imm));
3891 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3893 case OP_X86_OR_MEMBASE_IMM:
3894 g_assert (amd64_is_imm32 (ins->inst_imm));
3895 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3897 case OP_X86_XOR_MEMBASE_IMM:
3898 g_assert (amd64_is_imm32 (ins->inst_imm));
3899 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3901 case OP_X86_ADD_MEMBASE_REG:
3902 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3904 case OP_X86_SUB_MEMBASE_REG:
3905 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3907 case OP_X86_AND_MEMBASE_REG:
3908 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3910 case OP_X86_OR_MEMBASE_REG:
3911 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3913 case OP_X86_XOR_MEMBASE_REG:
3914 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3916 case OP_X86_INC_MEMBASE:
3917 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3919 case OP_X86_INC_REG:
3920 amd64_inc_reg_size (code, ins->dreg, 4);
3922 case OP_X86_DEC_MEMBASE:
3923 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3925 case OP_X86_DEC_REG:
3926 amd64_dec_reg_size (code, ins->dreg, 4);
3928 case OP_X86_MUL_REG_MEMBASE:
3929 case OP_X86_MUL_MEMBASE_REG:
3930 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3932 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3933 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3935 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3936 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3938 case OP_AMD64_COMPARE_MEMBASE_REG:
3939 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3941 case OP_AMD64_COMPARE_MEMBASE_IMM:
3942 g_assert (amd64_is_imm32 (ins->inst_imm));
3943 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3945 case OP_X86_COMPARE_MEMBASE8_IMM:
3946 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3948 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3949 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3951 case OP_AMD64_COMPARE_REG_MEMBASE:
3952 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3955 case OP_AMD64_ADD_REG_MEMBASE:
3956 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3958 case OP_AMD64_SUB_REG_MEMBASE:
3959 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3961 case OP_AMD64_AND_REG_MEMBASE:
3962 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3964 case OP_AMD64_OR_REG_MEMBASE:
3965 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3967 case OP_AMD64_XOR_REG_MEMBASE:
3968 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3971 case OP_AMD64_ADD_MEMBASE_REG:
3972 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3974 case OP_AMD64_SUB_MEMBASE_REG:
3975 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3977 case OP_AMD64_AND_MEMBASE_REG:
3978 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3980 case OP_AMD64_OR_MEMBASE_REG:
3981 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3983 case OP_AMD64_XOR_MEMBASE_REG:
3984 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3987 case OP_AMD64_ADD_MEMBASE_IMM:
3988 g_assert (amd64_is_imm32 (ins->inst_imm));
3989 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3991 case OP_AMD64_SUB_MEMBASE_IMM:
3992 g_assert (amd64_is_imm32 (ins->inst_imm));
3993 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3995 case OP_AMD64_AND_MEMBASE_IMM:
3996 g_assert (amd64_is_imm32 (ins->inst_imm));
3997 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3999 case OP_AMD64_OR_MEMBASE_IMM:
4000 g_assert (amd64_is_imm32 (ins->inst_imm));
4001 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4003 case OP_AMD64_XOR_MEMBASE_IMM:
4004 g_assert (amd64_is_imm32 (ins->inst_imm));
4005 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4009 amd64_breakpoint (code);
4011 case OP_RELAXED_NOP:
4012 x86_prefix (code, X86_REP_PREFIX);
4020 case OP_DUMMY_STORE:
4021 case OP_DUMMY_ICONST:
4022 case OP_DUMMY_R8CONST:
4023 case OP_NOT_REACHED:
4026 case OP_IL_SEQ_POINT:
4027 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4029 case OP_SEQ_POINT: {
4030 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4031 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4034 /* Load ss_tramp_var */
4035 /* This is equal to &ss_trampoline */
4036 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4037 /* Load the trampoline address */
4038 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4039 /* Call it if it is non-null */
4040 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4042 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4043 amd64_call_reg (code, AMD64_R11);
4044 amd64_patch (label, code);
4048 * This is the address which is saved in seq points,
4050 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4052 if (cfg->compile_aot) {
4053 guint32 offset = code - cfg->native_code;
4055 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4059 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4060 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4061 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4062 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4063 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4065 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4066 /* Call the trampoline */
4067 amd64_call_reg (code, AMD64_R11);
4068 amd64_patch (label, code);
4070 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4074 * Emit a test+branch against a constant, the constant will be overwritten
4075 * by mono_arch_set_breakpoint () to cause the test to fail.
4077 amd64_mov_reg_imm (code, AMD64_R11, 0);
4078 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4080 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4083 g_assert (var->opcode == OP_REGOFFSET);
4084 /* Load bp_tramp_var */
4085 /* This is equal to &bp_trampoline */
4086 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4087 /* Call the trampoline */
4088 amd64_call_membase (code, AMD64_R11, 0);
4089 amd64_patch (label, code);
4092 * Add an additional nop so skipping the bp doesn't cause the ip to point
4093 * to another IL offset.
4101 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4104 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4108 g_assert (amd64_is_imm32 (ins->inst_imm));
4109 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4112 g_assert (amd64_is_imm32 (ins->inst_imm));
4113 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4118 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4121 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4125 g_assert (amd64_is_imm32 (ins->inst_imm));
4126 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4129 g_assert (amd64_is_imm32 (ins->inst_imm));
4130 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4133 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4137 g_assert (amd64_is_imm32 (ins->inst_imm));
4138 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4141 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4146 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4148 switch (ins->inst_imm) {
4152 if (ins->dreg != ins->sreg1)
4153 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4154 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4157 /* LEA r1, [r2 + r2*2] */
4158 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4161 /* LEA r1, [r2 + r2*4] */
4162 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4165 /* LEA r1, [r2 + r2*2] */
4167 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4168 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4171 /* LEA r1, [r2 + r2*8] */
4172 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4175 /* LEA r1, [r2 + r2*4] */
4177 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4178 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4181 /* LEA r1, [r2 + r2*2] */
4183 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4184 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4187 /* LEA r1, [r2 + r2*4] */
4188 /* LEA r1, [r1 + r1*4] */
4189 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4190 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4193 /* LEA r1, [r2 + r2*4] */
4195 /* LEA r1, [r1 + r1*4] */
4196 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4197 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4198 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4201 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4208 /* Regalloc magic makes the div/rem cases the same */
4209 if (ins->sreg2 == AMD64_RDX) {
4210 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4212 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4215 amd64_div_reg (code, ins->sreg2, TRUE);
4220 if (ins->sreg2 == AMD64_RDX) {
4221 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4222 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4223 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4225 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4226 amd64_div_reg (code, ins->sreg2, FALSE);
4231 if (ins->sreg2 == AMD64_RDX) {
4232 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4233 amd64_cdq_size (code, 4);
4234 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4236 amd64_cdq_size (code, 4);
4237 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4242 if (ins->sreg2 == AMD64_RDX) {
4243 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4244 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4245 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4247 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4248 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4252 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4253 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4256 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4260 g_assert (amd64_is_imm32 (ins->inst_imm));
4261 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4264 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4268 g_assert (amd64_is_imm32 (ins->inst_imm));
4269 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4272 g_assert (ins->sreg2 == AMD64_RCX);
4273 amd64_shift_reg (code, X86_SHL, ins->dreg);
4276 g_assert (ins->sreg2 == AMD64_RCX);
4277 amd64_shift_reg (code, X86_SAR, ins->dreg);
4281 g_assert (amd64_is_imm32 (ins->inst_imm));
4282 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4285 g_assert (amd64_is_imm32 (ins->inst_imm));
4286 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4288 case OP_LSHR_UN_IMM:
4289 g_assert (amd64_is_imm32 (ins->inst_imm));
4290 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4293 g_assert (ins->sreg2 == AMD64_RCX);
4294 amd64_shift_reg (code, X86_SHR, ins->dreg);
4298 g_assert (amd64_is_imm32 (ins->inst_imm));
4299 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4304 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4307 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4310 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4313 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4317 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4320 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4323 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4326 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4329 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4332 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4335 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4338 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4341 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4344 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4347 amd64_neg_reg_size (code, ins->sreg1, 4);
4350 amd64_not_reg_size (code, ins->sreg1, 4);
4353 g_assert (ins->sreg2 == AMD64_RCX);
4354 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4357 g_assert (ins->sreg2 == AMD64_RCX);
4358 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4361 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4363 case OP_ISHR_UN_IMM:
4364 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4367 g_assert (ins->sreg2 == AMD64_RCX);
4368 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4371 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4374 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4377 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4378 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4380 case OP_IMUL_OVF_UN:
4381 case OP_LMUL_OVF_UN: {
4382 /* the mul operation and the exception check should most likely be split */
4383 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4384 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4385 /*g_assert (ins->sreg2 == X86_EAX);
4386 g_assert (ins->dreg == X86_EAX);*/
4387 if (ins->sreg2 == X86_EAX) {
4388 non_eax_reg = ins->sreg1;
4389 } else if (ins->sreg1 == X86_EAX) {
4390 non_eax_reg = ins->sreg2;
4392 /* no need to save since we're going to store to it anyway */
4393 if (ins->dreg != X86_EAX) {
4395 amd64_push_reg (code, X86_EAX);
4397 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4398 non_eax_reg = ins->sreg2;
4400 if (ins->dreg == X86_EDX) {
4403 amd64_push_reg (code, X86_EAX);
4407 amd64_push_reg (code, X86_EDX);
4409 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4410 /* save before the check since pop and mov don't change the flags */
4411 if (ins->dreg != X86_EAX)
4412 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4414 amd64_pop_reg (code, X86_EDX);
4416 amd64_pop_reg (code, X86_EAX);
4417 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4421 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4423 case OP_ICOMPARE_IMM:
4424 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4446 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4454 case OP_CMOV_INE_UN:
4455 case OP_CMOV_IGE_UN:
4456 case OP_CMOV_IGT_UN:
4457 case OP_CMOV_ILE_UN:
4458 case OP_CMOV_ILT_UN:
4464 case OP_CMOV_LNE_UN:
4465 case OP_CMOV_LGE_UN:
4466 case OP_CMOV_LGT_UN:
4467 case OP_CMOV_LLE_UN:
4468 case OP_CMOV_LLT_UN:
4469 g_assert (ins->dreg == ins->sreg1);
4470 /* This needs to operate on 64 bit values */
4471 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4475 amd64_not_reg (code, ins->sreg1);
4478 amd64_neg_reg (code, ins->sreg1);
4483 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4484 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4486 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4489 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4490 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4493 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4494 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4497 if (ins->dreg != ins->sreg1)
4498 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4500 case OP_AMD64_SET_XMMREG_R4: {
4502 if (ins->dreg != ins->sreg1)
4503 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4505 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4509 case OP_AMD64_SET_XMMREG_R8: {
4510 if (ins->dreg != ins->sreg1)
4511 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4515 MonoCallInst *call = (MonoCallInst*)ins;
4516 int i, save_area_offset;
4518 g_assert (!cfg->method->save_lmf);
4520 /* Restore callee saved registers */
4521 save_area_offset = cfg->arch.reg_save_area_offset;
4522 for (i = 0; i < AMD64_NREG; ++i)
4523 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4524 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4525 save_area_offset += 8;
4528 if (cfg->arch.omit_fp) {
4529 if (cfg->arch.stack_alloc_size)
4530 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4532 if (call->stack_usage)
4535 /* Copy arguments on the stack to our argument area */
4536 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4537 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4538 amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4542 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4543 amd64_pop_reg (code, AMD64_RBP);
4544 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4550 offset = code - cfg->native_code;
4551 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4552 if (cfg->compile_aot)
4553 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4555 amd64_set_reg_template (code, AMD64_R11);
4556 amd64_jump_reg (code, AMD64_R11);
4557 ins->flags |= MONO_INST_GC_CALLSITE;
4558 ins->backend.pc_offset = code - cfg->native_code;
4562 /* ensure ins->sreg1 is not NULL */
4563 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4566 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4567 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4577 call = (MonoCallInst*)ins;
4579 * The AMD64 ABI forces callers to know about varargs.
4581 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4582 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4583 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4585 * Since the unmanaged calling convention doesn't contain a
4586 * 'vararg' entry, we have to treat every pinvoke call as a
4587 * potential vararg call.
4591 for (i = 0; i < AMD64_XMM_NREG; ++i)
4592 if (call->used_fregs & (1 << i))
4595 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4597 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4600 if (ins->flags & MONO_INST_HAS_METHOD)
4601 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4603 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4604 ins->flags |= MONO_INST_GC_CALLSITE;
4605 ins->backend.pc_offset = code - cfg->native_code;
4606 code = emit_move_return_value (cfg, ins, code);
4613 case OP_VOIDCALL_REG:
4615 call = (MonoCallInst*)ins;
4617 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4618 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4619 ins->sreg1 = AMD64_R11;
4623 * The AMD64 ABI forces callers to know about varargs.
4625 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4626 if (ins->sreg1 == AMD64_RAX) {
4627 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4628 ins->sreg1 = AMD64_R11;
4630 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4631 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4633 * Since the unmanaged calling convention doesn't contain a
4634 * 'vararg' entry, we have to treat every pinvoke call as a
4635 * potential vararg call.
4639 for (i = 0; i < AMD64_XMM_NREG; ++i)
4640 if (call->used_fregs & (1 << i))
4642 if (ins->sreg1 == AMD64_RAX) {
4643 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4644 ins->sreg1 = AMD64_R11;
4647 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4649 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4652 amd64_call_reg (code, ins->sreg1);
4653 ins->flags |= MONO_INST_GC_CALLSITE;
4654 ins->backend.pc_offset = code - cfg->native_code;
4655 code = emit_move_return_value (cfg, ins, code);
4657 case OP_FCALL_MEMBASE:
4658 case OP_RCALL_MEMBASE:
4659 case OP_LCALL_MEMBASE:
4660 case OP_VCALL_MEMBASE:
4661 case OP_VCALL2_MEMBASE:
4662 case OP_VOIDCALL_MEMBASE:
4663 case OP_CALL_MEMBASE:
4664 call = (MonoCallInst*)ins;
4666 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4667 ins->flags |= MONO_INST_GC_CALLSITE;
4668 ins->backend.pc_offset = code - cfg->native_code;
4669 code = emit_move_return_value (cfg, ins, code);
4673 MonoInst *var = cfg->dyn_call_var;
4676 g_assert (var->opcode == OP_REGOFFSET);
4678 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4679 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4681 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4683 /* Save args buffer */
4684 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4686 /* Set fp arg regs */
4687 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4688 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4690 amd64_branch8 (code, X86_CC_Z, -1, 1);
4691 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4692 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4693 amd64_patch (label, code);
4695 /* Set stack args */
4696 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4697 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4698 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4701 /* Set argument registers */
4702 for (i = 0; i < PARAM_REGS; ++i)
4703 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4706 amd64_call_reg (code, AMD64_R10);
4708 ins->flags |= MONO_INST_GC_CALLSITE;
4709 ins->backend.pc_offset = code - cfg->native_code;
4712 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4713 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4714 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4715 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4718 case OP_AMD64_SAVE_SP_TO_LMF: {
4719 MonoInst *lmf_var = cfg->lmf_var;
4720 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4724 g_assert_not_reached ();
4725 amd64_push_reg (code, ins->sreg1);
4727 case OP_X86_PUSH_IMM:
4728 g_assert_not_reached ();
4729 g_assert (amd64_is_imm32 (ins->inst_imm));
4730 amd64_push_imm (code, ins->inst_imm);
4732 case OP_X86_PUSH_MEMBASE:
4733 g_assert_not_reached ();
4734 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4736 case OP_X86_PUSH_OBJ: {
4737 int size = ALIGN_TO (ins->inst_imm, 8);
4739 g_assert_not_reached ();
4741 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4742 amd64_push_reg (code, AMD64_RDI);
4743 amd64_push_reg (code, AMD64_RSI);
4744 amd64_push_reg (code, AMD64_RCX);
4745 if (ins->inst_offset)
4746 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4748 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4749 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4750 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4752 amd64_prefix (code, X86_REP_PREFIX);
4754 amd64_pop_reg (code, AMD64_RCX);
4755 amd64_pop_reg (code, AMD64_RSI);
4756 amd64_pop_reg (code, AMD64_RDI);
4759 case OP_GENERIC_CLASS_INIT: {
4762 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4764 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4766 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4768 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4769 ins->flags |= MONO_INST_GC_CALLSITE;
4770 ins->backend.pc_offset = code - cfg->native_code;
4772 x86_patch (jump, code);
4777 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4779 case OP_X86_LEA_MEMBASE:
4780 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4783 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4786 /* keep alignment */
4787 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4788 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4789 code = mono_emit_stack_alloc (cfg, code, ins);
4790 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4791 if (cfg->param_area)
4792 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4794 case OP_LOCALLOC_IMM: {
4795 guint32 size = ins->inst_imm;
4796 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4798 if (ins->flags & MONO_INST_INIT) {
4802 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4803 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4805 for (i = 0; i < size; i += 8)
4806 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4807 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4809 amd64_mov_reg_imm (code, ins->dreg, size);
4810 ins->sreg1 = ins->dreg;
4812 code = mono_emit_stack_alloc (cfg, code, ins);
4813 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4816 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4817 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4819 if (cfg->param_area)
4820 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4824 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4825 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4826 (gpointer)"mono_arch_throw_exception", FALSE);
4827 ins->flags |= MONO_INST_GC_CALLSITE;
4828 ins->backend.pc_offset = code - cfg->native_code;
4832 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4833 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4834 (gpointer)"mono_arch_rethrow_exception", FALSE);
4835 ins->flags |= MONO_INST_GC_CALLSITE;
4836 ins->backend.pc_offset = code - cfg->native_code;
4839 case OP_CALL_HANDLER:
4841 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4842 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4843 amd64_call_imm (code, 0);
4844 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4845 /* Restore stack alignment */
4846 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4848 case OP_START_HANDLER: {
4849 /* Even though we're saving RSP, use sizeof */
4850 /* gpointer because spvar is of type IntPtr */
4851 /* see: mono_create_spvar_for_region */
4852 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4853 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4855 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4856 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4858 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4862 case OP_ENDFINALLY: {
4863 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4864 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4868 case OP_ENDFILTER: {
4869 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4870 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4871 /* The local allocator will put the result into RAX */
4876 if (ins->dreg != AMD64_RAX)
4877 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4880 ins->inst_c0 = code - cfg->native_code;
4883 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4884 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4886 if (ins->inst_target_bb->native_offset) {
4887 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4889 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4890 if ((cfg->opt & MONO_OPT_BRANCH) &&
4891 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4892 x86_jump8 (code, 0);
4894 x86_jump32 (code, 0);
4898 amd64_jump_reg (code, ins->sreg1);
4921 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4922 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4924 case OP_COND_EXC_EQ:
4925 case OP_COND_EXC_NE_UN:
4926 case OP_COND_EXC_LT:
4927 case OP_COND_EXC_LT_UN:
4928 case OP_COND_EXC_GT:
4929 case OP_COND_EXC_GT_UN:
4930 case OP_COND_EXC_GE:
4931 case OP_COND_EXC_GE_UN:
4932 case OP_COND_EXC_LE:
4933 case OP_COND_EXC_LE_UN:
4934 case OP_COND_EXC_IEQ:
4935 case OP_COND_EXC_INE_UN:
4936 case OP_COND_EXC_ILT:
4937 case OP_COND_EXC_ILT_UN:
4938 case OP_COND_EXC_IGT:
4939 case OP_COND_EXC_IGT_UN:
4940 case OP_COND_EXC_IGE:
4941 case OP_COND_EXC_IGE_UN:
4942 case OP_COND_EXC_ILE:
4943 case OP_COND_EXC_ILE_UN:
4944 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4946 case OP_COND_EXC_OV:
4947 case OP_COND_EXC_NO:
4949 case OP_COND_EXC_NC:
4950 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4951 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4953 case OP_COND_EXC_IOV:
4954 case OP_COND_EXC_INO:
4955 case OP_COND_EXC_IC:
4956 case OP_COND_EXC_INC:
4957 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4958 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4961 /* floating point opcodes */
4963 double d = *(double *)ins->inst_p0;
4965 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4966 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4969 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4970 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4975 float f = *(float *)ins->inst_p0;
4977 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4979 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4981 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4984 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4985 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4987 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4991 case OP_STORER8_MEMBASE_REG:
4992 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4994 case OP_LOADR8_MEMBASE:
4995 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4997 case OP_STORER4_MEMBASE_REG:
4999 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5001 /* This requires a double->single conversion */
5002 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5003 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5006 case OP_LOADR4_MEMBASE:
5008 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5010 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5011 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5014 case OP_ICONV_TO_R4:
5016 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5018 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5019 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5022 case OP_ICONV_TO_R8:
5023 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5025 case OP_LCONV_TO_R4:
5027 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5029 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5030 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5033 case OP_LCONV_TO_R8:
5034 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5036 case OP_FCONV_TO_R4:
5038 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5040 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5041 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5044 case OP_FCONV_TO_I1:
5045 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5047 case OP_FCONV_TO_U1:
5048 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5050 case OP_FCONV_TO_I2:
5051 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5053 case OP_FCONV_TO_U2:
5054 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5056 case OP_FCONV_TO_U4:
5057 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5059 case OP_FCONV_TO_I4:
5061 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5063 case OP_FCONV_TO_I8:
5064 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5067 case OP_RCONV_TO_I1:
5068 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5069 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5071 case OP_RCONV_TO_U1:
5072 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5073 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5075 case OP_RCONV_TO_I2:
5076 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5077 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5079 case OP_RCONV_TO_U2:
5080 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5081 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5083 case OP_RCONV_TO_I4:
5084 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5086 case OP_RCONV_TO_U4:
5087 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5089 case OP_RCONV_TO_I8:
5090 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5092 case OP_RCONV_TO_R8:
5093 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5095 case OP_RCONV_TO_R4:
5096 if (ins->dreg != ins->sreg1)
5097 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5100 case OP_LCONV_TO_R_UN: {
5103 /* Based on gcc code */
5104 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5105 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5108 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5109 br [1] = code; x86_jump8 (code, 0);
5110 amd64_patch (br [0], code);
5113 /* Save to the red zone */
5114 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5115 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5116 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5117 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5118 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5119 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5120 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5121 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5122 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5124 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5125 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5126 amd64_patch (br [1], code);
5129 case OP_LCONV_TO_OVF_U4:
5130 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5131 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5132 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5134 case OP_LCONV_TO_OVF_I4_UN:
5135 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5136 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5137 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5140 if (ins->dreg != ins->sreg1)
5141 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5144 if (ins->dreg != ins->sreg1)
5145 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5147 case OP_MOVE_F_TO_I4:
5149 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5151 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5152 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5155 case OP_MOVE_I4_TO_F:
5156 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5158 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5160 case OP_MOVE_F_TO_I8:
5161 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5163 case OP_MOVE_I8_TO_F:
5164 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5167 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5170 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5173 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5176 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5179 static double r8_0 = -0.0;
5181 g_assert (ins->sreg1 == ins->dreg);
5183 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5184 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5188 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5191 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5194 static guint64 d = 0x7fffffffffffffffUL;
5196 g_assert (ins->sreg1 == ins->dreg);
5198 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5199 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5203 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5207 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5210 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5213 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5216 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5219 static float r4_0 = -0.0;
5221 g_assert (ins->sreg1 == ins->dreg);
5223 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5224 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5225 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5230 g_assert (cfg->opt & MONO_OPT_CMOV);
5231 g_assert (ins->dreg == ins->sreg1);
5232 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5233 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5236 g_assert (cfg->opt & MONO_OPT_CMOV);
5237 g_assert (ins->dreg == ins->sreg1);
5238 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5239 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5242 g_assert (cfg->opt & MONO_OPT_CMOV);
5243 g_assert (ins->dreg == ins->sreg1);
5244 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5245 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5248 g_assert (cfg->opt & MONO_OPT_CMOV);
5249 g_assert (ins->dreg == ins->sreg1);
5250 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5251 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5254 g_assert (cfg->opt & MONO_OPT_CMOV);
5255 g_assert (ins->dreg == ins->sreg1);
5256 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5257 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5260 g_assert (cfg->opt & MONO_OPT_CMOV);
5261 g_assert (ins->dreg == ins->sreg1);
5262 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5263 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5266 g_assert (cfg->opt & MONO_OPT_CMOV);
5267 g_assert (ins->dreg == ins->sreg1);
5268 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5269 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5272 g_assert (cfg->opt & MONO_OPT_CMOV);
5273 g_assert (ins->dreg == ins->sreg1);
5274 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5275 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5281 * The two arguments are swapped because the fbranch instructions
5282 * depend on this for the non-sse case to work.
5284 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5288 * FIXME: Get rid of this.
5289 * The two arguments are swapped because the fbranch instructions
5290 * depend on this for the non-sse case to work.
5292 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5296 /* zeroing the register at the start results in
5297 * shorter and faster code (we can also remove the widening op)
5299 guchar *unordered_check;
5301 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5302 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5303 unordered_check = code;
5304 x86_branch8 (code, X86_CC_P, 0, FALSE);
5306 if (ins->opcode == OP_FCEQ) {
5307 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5308 amd64_patch (unordered_check, code);
5310 guchar *jump_to_end;
5311 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5313 x86_jump8 (code, 0);
5314 amd64_patch (unordered_check, code);
5315 amd64_inc_reg (code, ins->dreg);
5316 amd64_patch (jump_to_end, code);
5322 /* zeroing the register at the start results in
5323 * shorter and faster code (we can also remove the widening op)
5325 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5326 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5327 if (ins->opcode == OP_FCLT_UN) {
5328 guchar *unordered_check = code;
5329 guchar *jump_to_end;
5330 x86_branch8 (code, X86_CC_P, 0, FALSE);
5331 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5333 x86_jump8 (code, 0);
5334 amd64_patch (unordered_check, code);
5335 amd64_inc_reg (code, ins->dreg);
5336 amd64_patch (jump_to_end, code);
5338 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5343 guchar *unordered_check;
5344 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5345 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5346 unordered_check = code;
5347 x86_branch8 (code, X86_CC_P, 0, FALSE);
5348 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5349 amd64_patch (unordered_check, code);
5354 /* zeroing the register at the start results in
5355 * shorter and faster code (we can also remove the widening op)
5357 guchar *unordered_check;
5359 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5360 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5361 if (ins->opcode == OP_FCGT) {
5362 unordered_check = code;
5363 x86_branch8 (code, X86_CC_P, 0, FALSE);
5364 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5365 amd64_patch (unordered_check, code);
5367 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5372 guchar *unordered_check;
5373 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5374 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5375 unordered_check = code;
5376 x86_branch8 (code, X86_CC_P, 0, FALSE);
5377 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5378 amd64_patch (unordered_check, code);
5388 gboolean unordered = FALSE;
5390 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5391 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5393 switch (ins->opcode) {
5395 x86_cond = X86_CC_EQ;
5398 x86_cond = X86_CC_LT;
5401 x86_cond = X86_CC_GT;
5404 x86_cond = X86_CC_GT;
5408 x86_cond = X86_CC_LT;
5412 g_assert_not_reached ();
5417 guchar *unordered_check;
5418 guchar *jump_to_end;
5420 unordered_check = code;
5421 x86_branch8 (code, X86_CC_P, 0, FALSE);
5422 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5424 x86_jump8 (code, 0);
5425 amd64_patch (unordered_check, code);
5426 amd64_inc_reg (code, ins->dreg);
5427 amd64_patch (jump_to_end, code);
5429 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5433 case OP_FCLT_MEMBASE:
5434 case OP_FCGT_MEMBASE:
5435 case OP_FCLT_UN_MEMBASE:
5436 case OP_FCGT_UN_MEMBASE:
5437 case OP_FCEQ_MEMBASE: {
5438 guchar *unordered_check, *jump_to_end;
5441 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5442 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5444 switch (ins->opcode) {
5445 case OP_FCEQ_MEMBASE:
5446 x86_cond = X86_CC_EQ;
5448 case OP_FCLT_MEMBASE:
5449 case OP_FCLT_UN_MEMBASE:
5450 x86_cond = X86_CC_LT;
5452 case OP_FCGT_MEMBASE:
5453 case OP_FCGT_UN_MEMBASE:
5454 x86_cond = X86_CC_GT;
5457 g_assert_not_reached ();
5460 unordered_check = code;
5461 x86_branch8 (code, X86_CC_P, 0, FALSE);
5462 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5464 switch (ins->opcode) {
5465 case OP_FCEQ_MEMBASE:
5466 case OP_FCLT_MEMBASE:
5467 case OP_FCGT_MEMBASE:
5468 amd64_patch (unordered_check, code);
5470 case OP_FCLT_UN_MEMBASE:
5471 case OP_FCGT_UN_MEMBASE:
5473 x86_jump8 (code, 0);
5474 amd64_patch (unordered_check, code);
5475 amd64_inc_reg (code, ins->dreg);
5476 amd64_patch (jump_to_end, code);
5484 guchar *jump = code;
5485 x86_branch8 (code, X86_CC_P, 0, TRUE);
5486 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5487 amd64_patch (jump, code);
5491 /* Branch if C013 != 100 */
5492 /* branch if !ZF or (PF|CF) */
5493 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5494 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5495 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5498 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5501 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5502 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5506 if (ins->opcode == OP_FBGT) {
5509 /* skip branch if C1=1 */
5511 x86_branch8 (code, X86_CC_P, 0, FALSE);
5512 /* branch if (C0 | C3) = 1 */
5513 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5514 amd64_patch (br1, code);
5517 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5521 /* Branch if C013 == 100 or 001 */
5524 /* skip branch if C1=1 */
5526 x86_branch8 (code, X86_CC_P, 0, FALSE);
5527 /* branch if (C0 | C3) = 1 */
5528 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5529 amd64_patch (br1, code);
5533 /* Branch if C013 == 000 */
5534 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5537 /* Branch if C013=000 or 100 */
5540 /* skip branch if C1=1 */
5542 x86_branch8 (code, X86_CC_P, 0, FALSE);
5543 /* branch if C0=0 */
5544 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5545 amd64_patch (br1, code);
5549 /* Branch if C013 != 001 */
5550 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5551 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5554 /* Transfer value to the fp stack */
5555 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5556 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5557 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5559 amd64_push_reg (code, AMD64_RAX);
5561 amd64_fnstsw (code);
5562 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5563 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5564 amd64_pop_reg (code, AMD64_RAX);
5565 amd64_fstp (code, 0);
5566 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5567 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5570 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5574 code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5577 case OP_MEMORY_BARRIER: {
5578 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5582 case OP_ATOMIC_ADD_I4:
5583 case OP_ATOMIC_ADD_I8: {
5584 int dreg = ins->dreg;
5585 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5587 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5590 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5591 amd64_prefix (code, X86_LOCK_PREFIX);
5592 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5593 /* dreg contains the old value, add with sreg2 value */
5594 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5596 if (ins->dreg != dreg)
5597 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5601 case OP_ATOMIC_EXCHANGE_I4:
5602 case OP_ATOMIC_EXCHANGE_I8: {
5603 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5605 /* LOCK prefix is implied. */
5606 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5607 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5608 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5611 case OP_ATOMIC_CAS_I4:
5612 case OP_ATOMIC_CAS_I8: {
5615 if (ins->opcode == OP_ATOMIC_CAS_I8)
5621 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5622 * an explanation of how this works.
5624 g_assert (ins->sreg3 == AMD64_RAX);
5625 g_assert (ins->sreg1 != AMD64_RAX);
5626 g_assert (ins->sreg1 != ins->sreg2);
5628 amd64_prefix (code, X86_LOCK_PREFIX);
5629 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5631 if (ins->dreg != AMD64_RAX)
5632 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5635 case OP_ATOMIC_LOAD_I1: {
5636 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5639 case OP_ATOMIC_LOAD_U1: {
5640 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5643 case OP_ATOMIC_LOAD_I2: {
5644 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5647 case OP_ATOMIC_LOAD_U2: {
5648 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5651 case OP_ATOMIC_LOAD_I4: {
5652 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5655 case OP_ATOMIC_LOAD_U4:
5656 case OP_ATOMIC_LOAD_I8:
5657 case OP_ATOMIC_LOAD_U8: {
5658 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5661 case OP_ATOMIC_LOAD_R4: {
5662 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5663 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5666 case OP_ATOMIC_LOAD_R8: {
5667 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5670 case OP_ATOMIC_STORE_I1:
5671 case OP_ATOMIC_STORE_U1:
5672 case OP_ATOMIC_STORE_I2:
5673 case OP_ATOMIC_STORE_U2:
5674 case OP_ATOMIC_STORE_I4:
5675 case OP_ATOMIC_STORE_U4:
5676 case OP_ATOMIC_STORE_I8:
5677 case OP_ATOMIC_STORE_U8: {
5680 switch (ins->opcode) {
5681 case OP_ATOMIC_STORE_I1:
5682 case OP_ATOMIC_STORE_U1:
5685 case OP_ATOMIC_STORE_I2:
5686 case OP_ATOMIC_STORE_U2:
5689 case OP_ATOMIC_STORE_I4:
5690 case OP_ATOMIC_STORE_U4:
5693 case OP_ATOMIC_STORE_I8:
5694 case OP_ATOMIC_STORE_U8:
5699 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5701 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5705 case OP_ATOMIC_STORE_R4: {
5706 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5707 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5709 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5713 case OP_ATOMIC_STORE_R8: {
5716 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5720 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5724 case OP_CARD_TABLE_WBARRIER: {
5725 int ptr = ins->sreg1;
5726 int value = ins->sreg2;
5728 int nursery_shift, card_table_shift;
5729 gpointer card_table_mask;
5730 size_t nursery_size;
5732 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5733 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5734 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5736 /*If either point to the stack we can simply avoid the WB. This happens due to
5737 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5739 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5743 * We need one register we can clobber, we choose EDX and make sreg1
5744 * fixed EAX to work around limitations in the local register allocator.
5745 * sreg2 might get allocated to EDX, but that is not a problem since
5746 * we use it before clobbering EDX.
5748 g_assert (ins->sreg1 == AMD64_RAX);
5751 * This is the code we produce:
5754 * edx >>= nursery_shift
5755 * cmp edx, (nursery_start >> nursery_shift)
5758 * edx >>= card_table_shift
5764 if (mono_gc_card_table_nursery_check ()) {
5765 if (value != AMD64_RDX)
5766 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5767 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5768 if (shifted_nursery_start >> 31) {
5770 * The value we need to compare against is 64 bits, so we need
5771 * another spare register. We use RBX, which we save and
5774 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5775 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5776 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5777 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5779 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5781 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5783 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5784 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5785 if (card_table_mask)
5786 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5788 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5789 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5791 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5793 if (mono_gc_card_table_nursery_check ())
5794 x86_patch (br, code);
5797 #ifdef MONO_ARCH_SIMD_INTRINSICS
5798 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5800 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5803 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5806 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5809 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5812 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5815 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5818 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5819 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5822 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5825 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5828 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5831 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5834 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5837 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5840 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5843 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5846 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5849 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5852 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5855 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5858 case OP_PSHUFLEW_HIGH:
5859 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5860 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5862 case OP_PSHUFLEW_LOW:
5863 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5864 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5867 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5868 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5871 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5872 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5875 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5876 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5880 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5883 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5886 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5895 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5898 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5899 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5902 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5905 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5908 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5911 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5914 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5917 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5920 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5923 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5926 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5929 case OP_EXTRACT_MASK:
5930 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5934 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5937 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5940 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5944 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5947 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5950 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5953 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5957 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5960 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5963 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5966 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5970 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5973 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5976 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5980 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5983 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5986 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5990 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5993 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5997 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6000 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6003 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6007 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6010 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6013 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6017 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6020 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6023 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6026 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6030 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6033 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6036 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6039 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6042 case OP_PSUM_ABS_DIFF:
6043 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6046 case OP_UNPACK_LOWB:
6047 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6049 case OP_UNPACK_LOWW:
6050 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6052 case OP_UNPACK_LOWD:
6053 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6055 case OP_UNPACK_LOWQ:
6056 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6058 case OP_UNPACK_LOWPS:
6059 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6061 case OP_UNPACK_LOWPD:
6062 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6065 case OP_UNPACK_HIGHB:
6066 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6068 case OP_UNPACK_HIGHW:
6069 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6071 case OP_UNPACK_HIGHD:
6072 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6074 case OP_UNPACK_HIGHQ:
6075 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6077 case OP_UNPACK_HIGHPS:
6078 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6080 case OP_UNPACK_HIGHPD:
6081 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6085 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6088 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6097 case OP_PADDB_SAT_UN:
6098 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6100 case OP_PSUBB_SAT_UN:
6101 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6103 case OP_PADDW_SAT_UN:
6104 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6106 case OP_PSUBW_SAT_UN:
6107 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6111 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6114 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6117 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6120 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6124 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6127 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6130 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6132 case OP_PMULW_HIGH_UN:
6133 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6136 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6140 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6143 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6147 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6150 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6154 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6157 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6161 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6164 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6168 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6171 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6175 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6178 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6182 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6185 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6188 /*TODO: This is appart of the sse spec but not added
6190 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6193 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6198 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6201 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6204 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6207 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6210 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6213 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6216 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6219 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6222 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6225 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6229 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6232 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6236 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6237 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6239 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6244 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6246 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6247 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6251 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6253 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6254 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6255 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6259 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6261 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6264 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6266 case OP_EXTRACTX_U2:
6267 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6269 case OP_INSERTX_U1_SLOW:
6270 /*sreg1 is the extracted ireg (scratch)
6271 /sreg2 is the to be inserted ireg (scratch)
6272 /dreg is the xreg to receive the value*/
6274 /*clear the bits from the extracted word*/
6275 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6276 /*shift the value to insert if needed*/
6277 if (ins->inst_c0 & 1)
6278 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6279 /*join them together*/
6280 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6281 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6283 case OP_INSERTX_I4_SLOW:
6284 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6285 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6286 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6288 case OP_INSERTX_I8_SLOW:
6289 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6291 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6293 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6296 case OP_INSERTX_R4_SLOW:
6297 switch (ins->inst_c0) {
6300 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6302 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6305 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6307 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6309 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6310 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6313 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6315 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6317 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6318 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6321 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6323 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6325 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6326 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6330 case OP_INSERTX_R8_SLOW:
6332 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6334 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6336 case OP_STOREX_MEMBASE_REG:
6337 case OP_STOREX_MEMBASE:
6338 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6340 case OP_LOADX_MEMBASE:
6341 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6343 case OP_LOADX_ALIGNED_MEMBASE:
6344 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6346 case OP_STOREX_ALIGNED_MEMBASE_REG:
6347 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6349 case OP_STOREX_NTA_MEMBASE_REG:
6350 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6352 case OP_PREFETCH_MEMBASE:
6353 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6357 /*FIXME the peephole pass should have killed this*/
6358 if (ins->dreg != ins->sreg1)
6359 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6362 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6365 amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6367 case OP_ICONV_TO_R4_RAW:
6368 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6370 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6373 case OP_FCONV_TO_R8_X:
6374 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6377 case OP_XCONV_R8_TO_I4:
6378 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6379 switch (ins->backend.source_opcode) {
6380 case OP_FCONV_TO_I1:
6381 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6383 case OP_FCONV_TO_U1:
6384 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6386 case OP_FCONV_TO_I2:
6387 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6389 case OP_FCONV_TO_U2:
6390 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6396 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6397 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6398 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6401 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6402 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6405 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6406 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6410 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6412 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6413 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6415 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6418 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6419 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6422 case OP_LIVERANGE_START: {
6423 if (cfg->verbose_level > 1)
6424 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6425 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6428 case OP_LIVERANGE_END: {
6429 if (cfg->verbose_level > 1)
6430 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6431 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6434 case OP_GC_SAFE_POINT: {
6437 g_assert (mono_threads_is_coop_enabled ());
6439 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6440 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6441 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6442 amd64_patch (br[0], code);
6446 case OP_GC_LIVENESS_DEF:
6447 case OP_GC_LIVENESS_USE:
6448 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6449 ins->backend.pc_offset = code - cfg->native_code;
6451 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6452 ins->backend.pc_offset = code - cfg->native_code;
6453 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6455 case OP_GET_LAST_ERROR:
6456 emit_get_last_error(code, ins->dreg);
6459 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6460 g_assert_not_reached ();
6463 if ((code - cfg->native_code - offset) > max_len) {
6464 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6465 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6466 g_assert_not_reached ();
6470 cfg->code_len = code - cfg->native_code;
6473 #endif /* DISABLE_JIT */
6476 mono_arch_register_lowlevel_calls (void)
6478 /* The signature doesn't matter */
6479 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6481 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6483 extern void __chkstk (void);
6484 mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6486 extern void ___chkstk_ms (void);
6487 mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6493 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6495 unsigned char *ip = ji->ip.i + code;
6498 * Debug code to help track down problems where the target of a near call is
6501 if (amd64_is_near_call (ip)) {
6502 gint64 disp = (guint8*)target - (guint8*)ip;
6504 if (!amd64_is_imm32 (disp)) {
6505 printf ("TYPE: %d\n", ji->type);
6507 case MONO_PATCH_INFO_INTERNAL_METHOD:
6508 printf ("V: %s\n", ji->data.name);
6510 case MONO_PATCH_INFO_METHOD_JUMP:
6511 case MONO_PATCH_INFO_METHOD:
6512 printf ("V: %s\n", ji->data.method->name);
6520 amd64_patch (ip, (gpointer)target);
6526 get_max_epilog_size (MonoCompile *cfg)
6528 int max_epilog_size = 16;
6530 if (cfg->method->save_lmf)
6531 max_epilog_size += 256;
6533 if (mono_jit_trace_calls != NULL)
6534 max_epilog_size += 50;
6536 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6537 max_epilog_size += 50;
6539 max_epilog_size += (AMD64_NREG * 2);
6541 return max_epilog_size;
6545 * This macro is used for testing whenever the unwinder works correctly at every point
6546 * where an async exception can happen.
6548 /* This will generate a SIGSEGV at the given point in the code */
6549 #define async_exc_point(code) do { \
6550 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6551 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6552 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6553 cfg->arch.async_point_count ++; \
6559 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6561 int cfa_offset = *cfa_offset_input;
6563 /* Allocate windows stack frame using stack probing method */
6566 if (alloc_size >= 0x1000) {
6567 amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6568 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6571 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6572 if (cfg->arch.omit_fp) {
6573 cfa_offset += alloc_size;
6574 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6575 async_exc_point (code);
6578 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6579 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6580 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6581 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6582 // that will retrieve the expected results.
6583 if (cfg->arch.omit_fp)
6584 mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6587 *cfa_offset_input = cfa_offset;
6590 #endif /* TARGET_WIN32 */
6593 mono_arch_emit_prolog (MonoCompile *cfg)
6595 MonoMethod *method = cfg->method;
6597 MonoMethodSignature *sig;
6599 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6602 MonoInst *lmf_var = cfg->lmf_var;
6603 gboolean args_clobbered = FALSE;
6604 gboolean trace = FALSE;
6606 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6608 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6610 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6613 /* Amount of stack space allocated by register saving code */
6616 /* Offset between RSP and the CFA */
6620 * The prolog consists of the following parts:
6624 * - save callee saved regs using moves
6626 * - save rgctx if needed
6627 * - save lmf if needed
6630 * - save rgctx if needed
6631 * - save lmf if needed
6632 * - save callee saved regs using moves
6637 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6638 // IP saved at CFA - 8
6639 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6640 async_exc_point (code);
6641 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6643 if (!cfg->arch.omit_fp) {
6644 amd64_push_reg (code, AMD64_RBP);
6646 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6647 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6648 async_exc_point (code);
6649 /* These are handled automatically by the stack marking code */
6650 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6652 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6653 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6654 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6655 async_exc_point (code);
6658 /* The param area is always at offset 0 from sp */
6659 /* This needs to be allocated here, since it has to come after the spill area */
6660 if (cfg->param_area) {
6661 if (cfg->arch.omit_fp)
6663 g_assert_not_reached ();
6664 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6667 if (cfg->arch.omit_fp) {
6669 * On enter, the stack is misaligned by the pushing of the return
6670 * address. It is either made aligned by the pushing of %rbp, or by
6673 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6674 if ((alloc_size % 16) == 0) {
6676 /* Mark the padding slot as NOREF */
6677 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6680 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6681 if (cfg->stack_offset != alloc_size) {
6682 /* Mark the padding slot as NOREF */
6683 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6685 cfg->arch.sp_fp_offset = alloc_size;
6689 cfg->arch.stack_alloc_size = alloc_size;
6691 /* Allocate stack frame */
6693 code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6696 /* See mono_emit_stack_alloc */
6697 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6698 guint32 remaining_size = alloc_size;
6699 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6700 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6701 guint32 offset = code - cfg->native_code;
6702 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6703 while (required_code_size >= (cfg->code_size - offset))
6704 cfg->code_size *= 2;
6705 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6706 code = cfg->native_code + offset;
6707 cfg->stat_code_reallocs++;
6710 while (remaining_size >= 0x1000) {
6711 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6712 if (cfg->arch.omit_fp) {
6713 cfa_offset += 0x1000;
6714 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6716 async_exc_point (code);
6718 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6719 remaining_size -= 0x1000;
6721 if (remaining_size) {
6722 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6723 if (cfg->arch.omit_fp) {
6724 cfa_offset += remaining_size;
6725 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6726 async_exc_point (code);
6730 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6731 if (cfg->arch.omit_fp) {
6732 cfa_offset += alloc_size;
6733 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6734 async_exc_point (code);
6740 /* Stack alignment check */
6745 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6746 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6747 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6749 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6750 amd64_breakpoint (code);
6751 amd64_patch (buf, code);
6755 if (mini_get_debug_options ()->init_stacks) {
6756 /* Fill the stack frame with a dummy value to force deterministic behavior */
6758 /* Save registers to the red zone */
6759 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6760 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6762 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6763 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6764 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6767 amd64_prefix (code, X86_REP_PREFIX);
6770 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6771 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6775 if (method->save_lmf)
6776 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6778 /* Save callee saved registers */
6779 if (cfg->arch.omit_fp) {
6780 save_area_offset = cfg->arch.reg_save_area_offset;
6781 /* Save caller saved registers after sp is adjusted */
6782 /* The registers are saved at the bottom of the frame */
6783 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6785 /* The registers are saved just below the saved rbp */
6786 save_area_offset = cfg->arch.reg_save_area_offset;
6789 for (i = 0; i < AMD64_NREG; ++i) {
6790 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6791 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6793 if (cfg->arch.omit_fp) {
6794 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6795 /* These are handled automatically by the stack marking code */
6796 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6798 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6802 save_area_offset += 8;
6803 async_exc_point (code);
6807 /* store runtime generic context */
6808 if (cfg->rgctx_var) {
6809 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6810 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6812 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6814 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6815 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6818 /* compute max_length in order to use short forward jumps */
6819 max_epilog_size = get_max_epilog_size (cfg);
6820 if (cfg->opt & MONO_OPT_BRANCH) {
6821 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6825 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6827 /* max alignment for loops */
6828 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6829 max_length += LOOP_ALIGNMENT;
6831 MONO_BB_FOR_EACH_INS (bb, ins) {
6832 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6835 /* Take prolog and epilog instrumentation into account */
6836 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6837 max_length += max_epilog_size;
6839 bb->max_length = max_length;
6843 sig = mono_method_signature (method);
6846 cinfo = (CallInfo *)cfg->arch.cinfo;
6848 if (sig->ret->type != MONO_TYPE_VOID) {
6849 /* Save volatile arguments to the stack */
6850 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6851 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6854 /* Keep this in sync with emit_load_volatile_arguments */
6855 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6856 ArgInfo *ainfo = cinfo->args + i;
6858 ins = cfg->args [i];
6860 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6861 /* Unused arguments */
6864 /* Save volatile arguments to the stack */
6865 if (ins->opcode != OP_REGVAR) {
6866 switch (ainfo->storage) {
6872 if (stack_offset & 0x1)
6874 else if (stack_offset & 0x2)
6876 else if (stack_offset & 0x4)
6881 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6884 * Save the original location of 'this',
6885 * get_generic_info_from_stack_frame () needs this to properly look up
6886 * the argument value during the handling of async exceptions.
6888 if (ins == cfg->args [0]) {
6889 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6890 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6894 case ArgInFloatSSEReg:
6895 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6897 case ArgInDoubleSSEReg:
6898 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6900 case ArgValuetypeInReg:
6901 for (quad = 0; quad < 2; quad ++) {
6902 switch (ainfo->pair_storage [quad]) {
6904 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6906 case ArgInFloatSSEReg:
6907 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6909 case ArgInDoubleSSEReg:
6910 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6915 g_assert_not_reached ();
6919 case ArgValuetypeAddrInIReg:
6920 if (ainfo->pair_storage [0] == ArgInIReg)
6921 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6923 case ArgValuetypeAddrOnStack:
6925 case ArgGSharedVtInReg:
6926 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6932 /* Argument allocated to (non-volatile) register */
6933 switch (ainfo->storage) {
6935 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6938 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6941 g_assert_not_reached ();
6944 if (ins == cfg->args [0]) {
6945 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6946 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6951 if (cfg->method->save_lmf)
6952 args_clobbered = TRUE;
6955 args_clobbered = TRUE;
6956 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6959 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6960 args_clobbered = TRUE;
6963 * Optimize the common case of the first bblock making a call with the same
6964 * arguments as the method. This works because the arguments are still in their
6965 * original argument registers.
6966 * FIXME: Generalize this
6968 if (!args_clobbered) {
6969 MonoBasicBlock *first_bb = cfg->bb_entry;
6971 int filter = FILTER_IL_SEQ_POINT;
6973 next = mono_bb_first_inst (first_bb, filter);
6974 if (!next && first_bb->next_bb) {
6975 first_bb = first_bb->next_bb;
6976 next = mono_bb_first_inst (first_bb, filter);
6979 if (first_bb->in_count > 1)
6982 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6983 ArgInfo *ainfo = cinfo->args + i;
6984 gboolean match = FALSE;
6986 ins = cfg->args [i];
6987 if (ins->opcode != OP_REGVAR) {
6988 switch (ainfo->storage) {
6990 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6991 if (next->dreg == ainfo->reg) {
6995 next->opcode = OP_MOVE;
6996 next->sreg1 = ainfo->reg;
6997 /* Only continue if the instruction doesn't change argument regs */
6998 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7008 /* Argument allocated to (non-volatile) register */
7009 switch (ainfo->storage) {
7011 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7022 next = mono_inst_next (next, filter);
7023 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7030 if (cfg->gen_sdb_seq_points) {
7031 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7033 /* Initialize seq_point_info_var */
7034 if (cfg->compile_aot) {
7035 /* Initialize the variable from a GOT slot */
7036 /* Same as OP_AOTCONST */
7037 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7038 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7039 g_assert (info_var->opcode == OP_REGOFFSET);
7040 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7043 if (cfg->compile_aot) {
7044 /* Initialize ss_tramp_var */
7045 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7046 g_assert (ins->opcode == OP_REGOFFSET);
7048 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7049 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7050 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7052 /* Initialize ss_tramp_var */
7053 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7054 g_assert (ins->opcode == OP_REGOFFSET);
7056 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7057 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7059 /* Initialize bp_tramp_var */
7060 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7061 g_assert (ins->opcode == OP_REGOFFSET);
7063 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7064 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7068 cfg->code_len = code - cfg->native_code;
7070 g_assert (cfg->code_len < cfg->code_size);
7076 mono_arch_emit_epilog (MonoCompile *cfg)
7078 MonoMethod *method = cfg->method;
7081 int max_epilog_size;
7083 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7084 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7086 max_epilog_size = get_max_epilog_size (cfg);
7088 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7089 cfg->code_size *= 2;
7090 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7091 cfg->stat_code_reallocs++;
7093 code = cfg->native_code + cfg->code_len;
7095 cfg->has_unwind_info_for_epilog = TRUE;
7097 /* Mark the start of the epilog */
7098 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7100 /* Save the uwind state which is needed by the out-of-line code */
7101 mono_emit_unwind_op_remember_state (cfg, code);
7103 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7104 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7106 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7108 if (method->save_lmf) {
7109 /* check if we need to restore protection of the stack after a stack overflow */
7110 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7112 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7113 /* we load the value in a separate instruction: this mechanism may be
7114 * used later as a safer way to do thread interruption
7116 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7117 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7119 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7120 /* note that the call trampoline will preserve eax/edx */
7121 x86_call_reg (code, X86_ECX);
7122 x86_patch (patch, code);
7124 /* FIXME: maybe save the jit tls in the prolog */
7126 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7127 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7131 /* Restore callee saved regs */
7132 for (i = 0; i < AMD64_NREG; ++i) {
7133 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7134 /* Restore only used_int_regs, not arch.saved_iregs */
7135 #if defined(MONO_SUPPORT_TASKLETS)
7138 int restore_reg=(cfg->used_int_regs & (1 << i));
7141 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7142 mono_emit_unwind_op_same_value (cfg, code, i);
7143 async_exc_point (code);
7145 save_area_offset += 8;
7149 /* Load returned vtypes into registers if needed */
7150 cinfo = (CallInfo *)cfg->arch.cinfo;
7151 if (cinfo->ret.storage == ArgValuetypeInReg) {
7152 ArgInfo *ainfo = &cinfo->ret;
7153 MonoInst *inst = cfg->ret;
7155 for (quad = 0; quad < 2; quad ++) {
7156 switch (ainfo->pair_storage [quad]) {
7158 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7160 case ArgInFloatSSEReg:
7161 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7163 case ArgInDoubleSSEReg:
7164 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7169 g_assert_not_reached ();
7174 if (cfg->arch.omit_fp) {
7175 if (cfg->arch.stack_alloc_size) {
7176 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7180 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7181 amd64_pop_reg (code, AMD64_RBP);
7182 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7185 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7188 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7189 async_exc_point (code);
7192 /* Restore the unwind state to be the same as before the epilog */
7193 mono_emit_unwind_op_restore_state (cfg, code);
7195 cfg->code_len = code - cfg->native_code;
7197 g_assert (cfg->code_len < cfg->code_size);
7201 mono_arch_emit_exceptions (MonoCompile *cfg)
7203 MonoJumpInfo *patch_info;
7206 MonoClass *exc_classes [16];
7207 guint8 *exc_throw_start [16], *exc_throw_end [16];
7208 guint32 code_size = 0;
7210 /* Compute needed space */
7211 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7212 if (patch_info->type == MONO_PATCH_INFO_EXC)
7214 if (patch_info->type == MONO_PATCH_INFO_R8)
7215 code_size += 8 + 15; /* sizeof (double) + alignment */
7216 if (patch_info->type == MONO_PATCH_INFO_R4)
7217 code_size += 4 + 15; /* sizeof (float) + alignment */
7218 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7219 code_size += 8 + 7; /*sizeof (void*) + alignment */
7222 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7223 cfg->code_size *= 2;
7224 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7225 cfg->stat_code_reallocs++;
7228 code = cfg->native_code + cfg->code_len;
7230 /* add code to raise exceptions */
7232 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7233 switch (patch_info->type) {
7234 case MONO_PATCH_INFO_EXC: {
7235 MonoClass *exc_class;
7239 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7241 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7242 throw_ip = patch_info->ip.i;
7244 //x86_breakpoint (code);
7245 /* Find a throw sequence for the same exception class */
7246 for (i = 0; i < nthrows; ++i)
7247 if (exc_classes [i] == exc_class)
7250 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7251 x86_jump_code (code, exc_throw_start [i]);
7252 patch_info->type = MONO_PATCH_INFO_NONE;
7256 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7260 exc_classes [nthrows] = exc_class;
7261 exc_throw_start [nthrows] = code;
7263 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7265 patch_info->type = MONO_PATCH_INFO_NONE;
7267 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7269 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7274 exc_throw_end [nthrows] = code;
7284 g_assert(code < cfg->native_code + cfg->code_size);
7287 /* Handle relocations with RIP relative addressing */
7288 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7289 gboolean remove = FALSE;
7290 guint8 *orig_code = code;
7292 switch (patch_info->type) {
7293 case MONO_PATCH_INFO_R8:
7294 case MONO_PATCH_INFO_R4: {
7295 guint8 *pos, *patch_pos;
7298 /* The SSE opcodes require a 16 byte alignment */
7299 code = (guint8*)ALIGN_TO (code, 16);
7301 pos = cfg->native_code + patch_info->ip.i;
7302 if (IS_REX (pos [1])) {
7303 patch_pos = pos + 5;
7304 target_pos = code - pos - 9;
7307 patch_pos = pos + 4;
7308 target_pos = code - pos - 8;
7311 if (patch_info->type == MONO_PATCH_INFO_R8) {
7312 *(double*)code = *(double*)patch_info->data.target;
7313 code += sizeof (double);
7315 *(float*)code = *(float*)patch_info->data.target;
7316 code += sizeof (float);
7319 *(guint32*)(patch_pos) = target_pos;
7324 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7327 if (cfg->compile_aot)
7330 /*loading is faster against aligned addresses.*/
7331 code = (guint8*)ALIGN_TO (code, 8);
7332 memset (orig_code, 0, code - orig_code);
7334 pos = cfg->native_code + patch_info->ip.i;
7336 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7337 if (IS_REX (pos [1]))
7338 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7340 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7342 *(gpointer*)code = (gpointer)patch_info->data.target;
7343 code += sizeof (gpointer);
7353 if (patch_info == cfg->patch_info)
7354 cfg->patch_info = patch_info->next;
7358 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7360 tmp->next = patch_info->next;
7363 g_assert (code < cfg->native_code + cfg->code_size);
7366 cfg->code_len = code - cfg->native_code;
7368 g_assert (cfg->code_len < cfg->code_size);
7372 #endif /* DISABLE_JIT */
7375 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7377 guchar *code = (guchar *)p;
7378 MonoMethodSignature *sig;
7380 int i, n, stack_area = 0;
7382 /* Keep this in sync with mono_arch_get_argument_info */
7384 if (enable_arguments) {
7385 /* Allocate a new area on the stack and save arguments there */
7386 sig = mono_method_signature (cfg->method);
7388 n = sig->param_count + sig->hasthis;
7390 stack_area = ALIGN_TO (n * 8, 16);
7392 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7394 for (i = 0; i < n; ++i) {
7395 inst = cfg->args [i];
7397 if (inst->opcode == OP_REGVAR)
7398 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7400 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7401 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7406 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7407 amd64_set_reg_template (code, AMD64_ARG_REG1);
7408 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7409 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7411 if (enable_arguments)
7412 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7426 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7428 guchar *code = (guchar *)p;
7429 int save_mode = SAVE_NONE;
7430 MonoMethod *method = cfg->method;
7431 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7434 switch (ret_type->type) {
7435 case MONO_TYPE_VOID:
7436 /* special case string .ctor icall */
7437 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7438 save_mode = SAVE_EAX;
7440 save_mode = SAVE_NONE;
7444 save_mode = SAVE_EAX;
7448 save_mode = SAVE_XMM;
7450 case MONO_TYPE_GENERICINST:
7451 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7452 save_mode = SAVE_EAX;
7456 case MONO_TYPE_VALUETYPE:
7457 save_mode = SAVE_STRUCT;
7460 save_mode = SAVE_EAX;
7464 /* Save the result and copy it into the proper argument register */
7465 switch (save_mode) {
7467 amd64_push_reg (code, AMD64_RAX);
7469 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7470 if (enable_arguments)
7471 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7475 if (enable_arguments)
7476 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7479 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7480 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7482 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7484 * The result is already in the proper argument register so no copying
7491 g_assert_not_reached ();
7494 /* Set %al since this is a varargs call */
7495 if (save_mode == SAVE_XMM)
7496 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7498 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7500 if (preserve_argument_registers) {
7501 for (i = 0; i < PARAM_REGS; ++i)
7502 amd64_push_reg (code, param_regs [i]);
7505 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7506 amd64_set_reg_template (code, AMD64_ARG_REG1);
7507 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7509 if (preserve_argument_registers) {
7510 for (i = PARAM_REGS - 1; i >= 0; --i)
7511 amd64_pop_reg (code, param_regs [i]);
7514 /* Restore result */
7515 switch (save_mode) {
7517 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7518 amd64_pop_reg (code, AMD64_RAX);
7524 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7525 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7526 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7531 g_assert_not_reached ();
7538 mono_arch_flush_icache (guint8 *code, gint size)
7544 mono_arch_flush_register_windows (void)
7549 mono_arch_is_inst_imm (gint64 imm)
7551 return amd64_use_imm32 (imm);
7555 * Determine whenever the trap whose info is in SIGINFO is caused by
7559 mono_arch_is_int_overflow (void *sigctx, void *info)
7566 mono_sigctx_to_monoctx (sigctx, &ctx);
7568 rip = (guint8*)ctx.gregs [AMD64_RIP];
7570 if (IS_REX (rip [0])) {
7571 reg = amd64_rex_b (rip [0]);
7577 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7579 reg += x86_modrm_rm (rip [1]);
7581 value = ctx.gregs [reg];
7591 mono_arch_get_patch_offset (guint8 *code)
7597 * \return TRUE if no sw breakpoint was present.
7599 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7600 * breakpoints in the original code, they are removed in the copy.
7603 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7606 * If method_start is non-NULL we need to perform bound checks, since we access memory
7607 * at code - offset we could go before the start of the method and end up in a different
7608 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7611 if (!method_start || code - offset >= method_start) {
7612 memcpy (buf, code - offset, size);
7614 int diff = code - method_start;
7615 memset (buf, 0, size);
7616 memcpy (buf + offset - diff, method_start, diff + size - offset);
7622 mono_arch_get_this_arg_reg (guint8 *code)
7624 return AMD64_ARG_REG1;
7628 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7630 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7633 #define MAX_ARCH_DELEGATE_PARAMS 10
7636 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7638 guint8 *code, *start;
7639 GSList *unwind_ops = NULL;
7642 unwind_ops = mono_arch_get_cie_program ();
7645 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7647 /* Replace the this argument with the target */
7648 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7649 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7650 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7652 g_assert ((code - start) < 64);
7653 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7655 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7657 if (param_count == 0) {
7658 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7660 /* We have to shift the arguments left */
7661 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7662 for (i = 0; i < param_count; ++i) {
7665 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7667 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7669 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7673 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7675 g_assert ((code - start) < 64);
7676 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7679 mono_arch_flush_icache (start, code - start);
7682 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7684 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7685 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7689 if (mono_jit_map_is_enabled ()) {
7692 buff = (char*)"delegate_invoke_has_target";
7694 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7695 mono_emit_jit_tramp (start, code - start, buff);
7699 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7704 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7707 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7709 guint8 *code, *start;
7714 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7717 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7719 unwind_ops = mono_arch_get_cie_program ();
7721 /* Replace the this argument with the target */
7722 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7723 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7726 /* Load the IMT reg */
7727 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7730 /* Load the vtable */
7731 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7732 amd64_jump_membase (code, AMD64_RAX, offset);
7733 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7735 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7736 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7737 g_free (tramp_name);
7743 * mono_arch_get_delegate_invoke_impls:
7745 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7749 mono_arch_get_delegate_invoke_impls (void)
7752 MonoTrampInfo *info;
7755 get_delegate_invoke_impl (&info, TRUE, 0);
7756 res = g_slist_prepend (res, info);
7758 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7759 get_delegate_invoke_impl (&info, FALSE, i);
7760 res = g_slist_prepend (res, info);
7763 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7764 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7765 res = g_slist_prepend (res, info);
7768 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7769 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7770 res = g_slist_prepend (res, info);
7771 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7772 res = g_slist_prepend (res, info);
7779 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7781 guint8 *code, *start;
7784 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7787 /* FIXME: Support more cases */
7788 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7792 static guint8* cached = NULL;
7797 if (mono_aot_only) {
7798 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7800 MonoTrampInfo *info;
7801 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7802 mono_tramp_info_register (info, NULL);
7805 mono_memory_barrier ();
7809 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7810 for (i = 0; i < sig->param_count; ++i)
7811 if (!mono_is_regsize_var (sig->params [i]))
7813 if (sig->param_count > 4)
7816 code = cache [sig->param_count];
7820 if (mono_aot_only) {
7821 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7822 start = (guint8 *)mono_aot_get_trampoline (name);
7825 MonoTrampInfo *info;
7826 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7827 mono_tramp_info_register (info, NULL);
7830 mono_memory_barrier ();
7832 cache [sig->param_count] = start;
7839 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7841 MonoTrampInfo *info;
7844 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7846 mono_tramp_info_register (info, NULL);
7851 mono_arch_finish_init (void)
7853 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7854 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7859 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7863 #define CMP_SIZE (6 + 1)
7864 #define CMP_REG_REG_SIZE (4 + 1)
7865 #define BR_SMALL_SIZE 2
7866 #define BR_LARGE_SIZE 6
7867 #define MOV_REG_IMM_SIZE 10
7868 #define MOV_REG_IMM_32BIT_SIZE 6
7869 #define JUMP_REG_SIZE (2 + 1)
7872 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7874 int i, distance = 0;
7875 for (i = start; i < target; ++i)
7876 distance += imt_entries [i]->chunk_size;
7881 * LOCKING: called with the domain lock held
7884 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7885 gpointer fail_tramp)
7889 guint8 *code, *start;
7890 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7893 for (i = 0; i < count; ++i) {
7894 MonoIMTCheckItem *item = imt_entries [i];
7895 if (item->is_equals) {
7896 if (item->check_target_idx) {
7897 if (!item->compare_done) {
7898 if (amd64_use_imm32 ((gint64)item->key))
7899 item->chunk_size += CMP_SIZE;
7901 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7903 if (item->has_target_code) {
7904 item->chunk_size += MOV_REG_IMM_SIZE;
7906 if (vtable_is_32bit)
7907 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7909 item->chunk_size += MOV_REG_IMM_SIZE;
7911 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7914 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7915 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7917 if (vtable_is_32bit)
7918 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7920 item->chunk_size += MOV_REG_IMM_SIZE;
7921 item->chunk_size += JUMP_REG_SIZE;
7922 /* with assert below:
7923 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7928 if (amd64_use_imm32 ((gint64)item->key))
7929 item->chunk_size += CMP_SIZE;
7931 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7932 item->chunk_size += BR_LARGE_SIZE;
7933 imt_entries [item->check_target_idx]->compare_done = TRUE;
7935 size += item->chunk_size;
7938 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7940 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7943 unwind_ops = mono_arch_get_cie_program ();
7945 for (i = 0; i < count; ++i) {
7946 MonoIMTCheckItem *item = imt_entries [i];
7947 item->code_target = code;
7948 if (item->is_equals) {
7949 gboolean fail_case = !item->check_target_idx && fail_tramp;
7951 if (item->check_target_idx || fail_case) {
7952 if (!item->compare_done || fail_case) {
7953 if (amd64_use_imm32 ((gint64)item->key))
7954 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7956 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7957 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7960 item->jmp_code = code;
7961 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7962 if (item->has_target_code) {
7963 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7964 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7966 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7967 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7971 amd64_patch (item->jmp_code, code);
7972 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7973 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7974 item->jmp_code = NULL;
7977 /* enable the commented code to assert on wrong method */
7979 if (amd64_is_imm32 (item->key))
7980 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7982 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7983 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7985 item->jmp_code = code;
7986 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7987 /* See the comment below about R10 */
7988 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7989 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7990 amd64_patch (item->jmp_code, code);
7991 amd64_breakpoint (code);
7992 item->jmp_code = NULL;
7994 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7995 needs to be preserved. R10 needs
7996 to be preserved for calls which
7997 require a runtime generic context,
7998 but interface calls don't. */
7999 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8000 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8004 if (amd64_use_imm32 ((gint64)item->key))
8005 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8007 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8008 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8010 item->jmp_code = code;
8011 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8012 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8014 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8016 g_assert (code - item->code_target <= item->chunk_size);
8018 /* patch the branches to get to the target items */
8019 for (i = 0; i < count; ++i) {
8020 MonoIMTCheckItem *item = imt_entries [i];
8021 if (item->jmp_code) {
8022 if (item->check_target_idx) {
8023 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8029 mono_stats.imt_trampolines_size += code - start;
8030 g_assert (code - start <= size);
8031 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8033 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8035 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8041 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8043 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8047 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8049 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8053 mono_arch_get_cie_program (void)
8057 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8058 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8066 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8068 MonoInst *ins = NULL;
8071 if (cmethod->klass == mono_defaults.math_class) {
8072 if (strcmp (cmethod->name, "Sin") == 0) {
8074 } else if (strcmp (cmethod->name, "Cos") == 0) {
8076 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8078 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8082 if (opcode && fsig->param_count == 1) {
8083 MONO_INST_NEW (cfg, ins, opcode);
8084 ins->type = STACK_R8;
8085 ins->dreg = mono_alloc_freg (cfg);
8086 ins->sreg1 = args [0]->dreg;
8087 MONO_ADD_INS (cfg->cbb, ins);
8091 if (cfg->opt & MONO_OPT_CMOV) {
8092 if (strcmp (cmethod->name, "Min") == 0) {
8093 if (fsig->params [0]->type == MONO_TYPE_I4)
8095 if (fsig->params [0]->type == MONO_TYPE_U4)
8096 opcode = OP_IMIN_UN;
8097 else if (fsig->params [0]->type == MONO_TYPE_I8)
8099 else if (fsig->params [0]->type == MONO_TYPE_U8)
8100 opcode = OP_LMIN_UN;
8101 } else if (strcmp (cmethod->name, "Max") == 0) {
8102 if (fsig->params [0]->type == MONO_TYPE_I4)
8104 if (fsig->params [0]->type == MONO_TYPE_U4)
8105 opcode = OP_IMAX_UN;
8106 else if (fsig->params [0]->type == MONO_TYPE_I8)
8108 else if (fsig->params [0]->type == MONO_TYPE_U8)
8109 opcode = OP_LMAX_UN;
8113 if (opcode && fsig->param_count == 2) {
8114 MONO_INST_NEW (cfg, ins, opcode);
8115 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8116 ins->dreg = mono_alloc_ireg (cfg);
8117 ins->sreg1 = args [0]->dreg;
8118 ins->sreg2 = args [1]->dreg;
8119 MONO_ADD_INS (cfg->cbb, ins);
8123 /* OP_FREM is not IEEE compatible */
8124 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8125 MONO_INST_NEW (cfg, ins, OP_FREM);
8126 ins->inst_i0 = args [0];
8127 ins->inst_i1 = args [1];
8137 mono_arch_print_tree (MonoInst *tree, int arity)
8143 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8145 return ctx->gregs [reg];
8149 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8151 ctx->gregs [reg] = val;
8155 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8157 gpointer *sp, old_value;
8161 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8162 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8165 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8174 * mono_arch_emit_load_aotconst:
8176 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8177 * TARGET from the mscorlib GOT in full-aot code.
8178 * On AMD64, the result is placed into R11.
8181 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8183 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8184 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8190 * mono_arch_get_trampolines:
8192 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8196 mono_arch_get_trampolines (gboolean aot)
8198 return mono_amd64_get_exception_trampolines (aot);
8201 /* Soft Debug support */
8202 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8205 * mono_arch_set_breakpoint:
8207 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8208 * The location should contain code emitted by OP_SEQ_POINT.
8211 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8216 guint32 native_offset = ip - (guint8*)ji->code_start;
8217 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8219 g_assert (info->bp_addrs [native_offset] == 0);
8220 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8222 /* ip points to a mov r11, 0 */
8223 g_assert (code [0] == 0x41);
8224 g_assert (code [1] == 0xbb);
8225 amd64_mov_reg_imm (code, AMD64_R11, 1);
8230 * mono_arch_clear_breakpoint:
8232 * Clear the breakpoint at IP.
8235 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8240 guint32 native_offset = ip - (guint8*)ji->code_start;
8241 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8243 info->bp_addrs [native_offset] = NULL;
8245 amd64_mov_reg_imm (code, AMD64_R11, 0);
8250 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8252 /* We use soft breakpoints on amd64 */
8257 * mono_arch_skip_breakpoint:
8259 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8260 * we resume, the instruction is not executed again.
8263 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8265 g_assert_not_reached ();
8269 * mono_arch_start_single_stepping:
8271 * Start single stepping.
8274 mono_arch_start_single_stepping (void)
8276 ss_trampoline = mini_get_single_step_trampoline ();
8280 * mono_arch_stop_single_stepping:
8282 * Stop single stepping.
8285 mono_arch_stop_single_stepping (void)
8287 ss_trampoline = NULL;
8291 * mono_arch_is_single_step_event:
8293 * Return whenever the machine state in SIGCTX corresponds to a single
8297 mono_arch_is_single_step_event (void *info, void *sigctx)
8299 /* We use soft breakpoints on amd64 */
8304 * mono_arch_skip_single_step:
8306 * Modify CTX so the ip is placed after the single step trigger instruction,
8307 * we resume, the instruction is not executed again.
8310 mono_arch_skip_single_step (MonoContext *ctx)
8312 g_assert_not_reached ();
8316 * mono_arch_create_seq_point_info:
8318 * Return a pointer to a data structure which is used by the sequence
8319 * point implementation in AOTed code.
8322 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8327 // FIXME: Add a free function
8329 mono_domain_lock (domain);
8330 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8332 mono_domain_unlock (domain);
8335 ji = mono_jit_info_table_find (domain, (char*)code);
8338 // FIXME: Optimize the size
8339 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8341 info->ss_tramp_addr = &ss_trampoline;
8343 mono_domain_lock (domain);
8344 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8346 mono_domain_unlock (domain);
8353 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8355 ext->lmf.previous_lmf = prev_lmf;
8356 /* Mark that this is a MonoLMFExt */
8357 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8358 ext->lmf.rsp = (gssize)ext;
8364 mono_arch_opcode_supported (int opcode)
8367 case OP_ATOMIC_ADD_I4:
8368 case OP_ATOMIC_ADD_I8:
8369 case OP_ATOMIC_EXCHANGE_I4:
8370 case OP_ATOMIC_EXCHANGE_I8:
8371 case OP_ATOMIC_CAS_I4:
8372 case OP_ATOMIC_CAS_I8:
8373 case OP_ATOMIC_LOAD_I1:
8374 case OP_ATOMIC_LOAD_I2:
8375 case OP_ATOMIC_LOAD_I4:
8376 case OP_ATOMIC_LOAD_I8:
8377 case OP_ATOMIC_LOAD_U1:
8378 case OP_ATOMIC_LOAD_U2:
8379 case OP_ATOMIC_LOAD_U4:
8380 case OP_ATOMIC_LOAD_U8:
8381 case OP_ATOMIC_LOAD_R4:
8382 case OP_ATOMIC_LOAD_R8:
8383 case OP_ATOMIC_STORE_I1:
8384 case OP_ATOMIC_STORE_I2:
8385 case OP_ATOMIC_STORE_I4:
8386 case OP_ATOMIC_STORE_I8:
8387 case OP_ATOMIC_STORE_U1:
8388 case OP_ATOMIC_STORE_U2:
8389 case OP_ATOMIC_STORE_U4:
8390 case OP_ATOMIC_STORE_U8:
8391 case OP_ATOMIC_STORE_R4:
8392 case OP_ATOMIC_STORE_R8:
8400 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8402 return get_call_info (mp, sig);