mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  16  */
  17 #include "mini.h"
  18 #include <string.h>
  19 #include <math.h>
  20 #ifdef HAVE_UNISTD_H
  21 #include <unistd.h>
  22 #endif
  23
  24 #include <mono/metadata/abi-details.h>
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/metadata/threads.h>
  28 #include <mono/metadata/profiler-private.h>
  29 #include <mono/metadata/mono-debug.h>
  30 #include <mono/metadata/gc-internals.h>
  31 #include <mono/utils/mono-math.h>
  32 #include <mono/utils/mono-mmap.h>
  33 #include <mono/utils/mono-memory-model.h>
  34 #include <mono/utils/mono-tls.h>
  35 #include <mono/utils/mono-hwcap-x86.h>
  36 #include <mono/utils/mono-threads.h>
  37
  38 #include "trace.h"
  39 #include "ir-emit.h"
  40 #include "mini-amd64.h"
  41 #include "cpu-amd64.h"
  42 #include "debugger-agent.h"
  43 #include "mini-gc.h"
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef TARGET_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  67 static mono_mutex_t mini_arch_mutex;
  68
  69 /* The single step trampoline */
  70 static gpointer ss_trampoline;
  71
  72 /* The breakpoint trampoline */
  73 static gpointer bp_trampoline;
  74
  75 /* Offset between fp and the first argument in the callee */
  76 #define ARGS_OFFSET 16
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return mono_debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline gboolean
 169 amd64_use_imm32 (gint64 val)
 170 {
 171         if (mini_get_debug_options()->single_imm_size)
 172                 return FALSE;
 173
 174         return amd64_is_imm32 (val);
 175 }
 176
 177 #ifdef __native_client_codegen__
 178
 179 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 180 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 181 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 182 /* We only want to force bundle alignment for the top level instruction,    */
 183 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 184 static MonoNativeTlsKey nacl_instruction_depth;
 185
 186 static MonoNativeTlsKey nacl_rex_tag;
 187 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 188
 189 void
 190 amd64_nacl_clear_legacy_prefix_tag ()
 191 {
 192         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 193 }
 194
 195 void
 196 amd64_nacl_tag_legacy_prefix (guint8* code)
 197 {
 198         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 199                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 200 }
 201
 202 void
 203 amd64_nacl_tag_rex (guint8* code)
 204 {
 205         mono_native_tls_set_value (nacl_rex_tag, code);
 206 }
 207
 208 guint8*
 209 amd64_nacl_get_legacy_prefix_tag ()
 210 {
 211         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 212 }
 213
 214 guint8*
 215 amd64_nacl_get_rex_tag ()
 216 {
 217         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 218 }
 219
 220 /* Increment the instruction "depth" described above */
 221 void
 222 amd64_nacl_instruction_pre ()
 223 {
 224         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 225         depth++;
 226         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 227 }
 228
 229 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 230 /* alignment if depth == 0 (top level instruction)                          */
 231 /* IN: start, end    pointers to instruction beginning and end              */
 232 /* OUT: start, end   pointers to beginning and end after possible alignment */
 233 /* GLOBALS: nacl_instruction_depth     defined above                        */
 234 void
 235 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 236 {
 237         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 238         depth--;
 239         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 240
 241         g_assert ( depth >= 0 );
 242         if (depth == 0) {
 243                 uintptr_t space_in_block;
 244                 uintptr_t instlen;
 245                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 246                 /* if legacy prefix is present, and if it was emitted before */
 247                 /* the start of the instruction sequence, adjust the start   */
 248                 if (prefix != NULL && prefix < *start) {
 249                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 250                         *start = prefix;
 251                 }
 252                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 253                 instlen = (uintptr_t)(*end - *start);
 254                 /* Only check for instructions which are less than        */
 255                 /* kNaClAlignment. The only instructions that should ever */
 256                 /* be that long are call sequences, which are already     */
 257                 /* padded out to align the return to the next bundle.     */
 258                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 259                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 260                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 261                         const size_t length = (size_t)((*end)-(*start));
 262                         g_assert (length < MAX_NACL_INST_LENGTH);
 263
 264                         memcpy (copy_of_instruction, *start, length);
 265                         *start = mono_arch_nacl_pad (*start, space_in_block);
 266                         memcpy (*start, copy_of_instruction, length);
 267                         *end = *start + length;
 268                 }
 269                 amd64_nacl_clear_legacy_prefix_tag ();
 270                 amd64_nacl_tag_rex (NULL);
 271         }
 272 }
 273
 274 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 275 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 276 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 277 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 278 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 279 /* IN:      code                                                            */
 280 /*             pointer to current instruction stream (in the                */
 281 /*             middle of an instruction, after opcode is emitted)           */
 282 /*          basereg/offset/dreg                                             */
 283 /*             operands of normal membase address                           */
 284 /* OUT:     code                                                            */
 285 /*             pointer to the end of the membase/memindex emit              */
 286 /* GLOBALS: nacl_rex_tag                                                    */
 287 /*             position in instruction stream that rex prefix was emitted   */
 288 /*          nacl_legacy_prefix_tag                                          */
 289 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 290 void
 291 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 292 {
 293         gint8 true_basereg = basereg;
 294
 295         /* Cache these values, they might change  */
 296         /* as new instructions are emitted below. */
 297         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 298         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 299
 300         /* 'basereg' is given masked to 0x7 at this point, so check */
 301         /* the rex prefix to see if this is an extended register.   */
 302         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 303                 true_basereg |= 0x8;
 304         }
 305
 306 #define X86_LEA_OPCODE (0x8D)
 307
 308         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 309                 guint8* old_instruction_start;
 310
 311                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 312                 /* 32-bits of the old base register (new index register)     */
 313                 guint8 buf[32];
 314                 guint8* buf_ptr = buf;
 315                 size_t insert_len;
 316
 317                 g_assert (rex_tag != NULL);
 318
 319                 if (IS_REX(*rex_tag)) {
 320                         /* The old rex.B should be the new rex.X */
 321                         if (*rex_tag & AMD64_REX_B) {
 322                                 *rex_tag |= AMD64_REX_X;
 323                         }
 324                         /* Since our new base is %r15 set rex.B */
 325                         *rex_tag |= AMD64_REX_B;
 326                 } else {
 327                         /* Shift the instruction by one byte  */
 328                         /* so we can insert a rex prefix      */
 329                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 330                         *code += 1;
 331                         /* New rex prefix only needs rex.B for %r15 base */
 332                         *rex_tag = AMD64_REX(AMD64_REX_B);
 333                 }
 334
 335                 if (legacy_prefix_tag) {
 336                         old_instruction_start = legacy_prefix_tag;
 337                 } else {
 338                         old_instruction_start = rex_tag;
 339                 }
 340
 341                 /* Clears the upper 32-bits of the previous base register */
 342                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 343                 insert_len = buf_ptr - buf;
 344
 345                 /* Move the old instruction forward to make */
 346                 /* room for 'mov' stored in 'buf_ptr'       */
 347                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 348                 *code += insert_len;
 349                 memcpy (old_instruction_start, buf, insert_len);
 350
 351                 /* Sandboxed replacement for the normal membase_emit */
 352                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 353
 354         } else {
 355                 /* Normal default behavior, emit membase memory location */
 356                 x86_membase_emit_body (*code, dreg, basereg, offset);
 357         }
 358 }
 359
 360
 361 static inline unsigned char*
 362 amd64_skip_nops (unsigned char* code)
 363 {
 364         guint8 in_nop;
 365         do {
 366                 in_nop = 0;
 367                 if (   code[0] == 0x90) {
 368                         in_nop = 1;
 369                         code += 1;
 370                 }
 371                 if (   code[0] == 0x66 && code[1] == 0x90) {
 372                         in_nop = 1;
 373                         code += 2;
 374                 }
 375                 if (code[0] == 0x0f && code[1] == 0x1f
 376                  && code[2] == 0x00) {
 377                         in_nop = 1;
 378                         code += 3;
 379                 }
 380                 if (code[0] == 0x0f && code[1] == 0x1f
 381                  && code[2] == 0x40 && code[3] == 0x00) {
 382                         in_nop = 1;
 383                         code += 4;
 384                 }
 385                 if (code[0] == 0x0f && code[1] == 0x1f
 386                  && code[2] == 0x44 && code[3] == 0x00
 387                  && code[4] == 0x00) {
 388                         in_nop = 1;
 389                         code += 5;
 390                 }
 391                 if (code[0] == 0x66 && code[1] == 0x0f
 392                  && code[2] == 0x1f && code[3] == 0x44
 393                  && code[4] == 0x00 && code[5] == 0x00) {
 394                         in_nop = 1;
 395                         code += 6;
 396                 }
 397                 if (code[0] == 0x0f && code[1] == 0x1f
 398                  && code[2] == 0x80 && code[3] == 0x00
 399                  && code[4] == 0x00 && code[5] == 0x00
 400                  && code[6] == 0x00) {
 401                         in_nop = 1;
 402                         code += 7;
 403                 }
 404                 if (code[0] == 0x0f && code[1] == 0x1f
 405                  && code[2] == 0x84 && code[3] == 0x00
 406                  && code[4] == 0x00 && code[5] == 0x00
 407                  && code[6] == 0x00 && code[7] == 0x00) {
 408                         in_nop = 1;
 409                         code += 8;
 410                 }
 411         } while ( in_nop );
 412         return code;
 413 }
 414
 415 guint8*
 416 mono_arch_nacl_skip_nops (guint8* code)
 417 {
 418   return amd64_skip_nops(code);
 419 }
 420
 421 #endif /*__native_client_codegen__*/
 422
 423 static void
 424 amd64_patch (unsigned char* code, gpointer target)
 425 {
 426         guint8 rex = 0;
 427
 428 #ifdef __native_client_codegen__
 429         code = amd64_skip_nops (code);
 430 #endif
 431 #if defined(__native_client_codegen__) && defined(__native_client__)
 432         if (nacl_is_code_address (code)) {
 433                 /* For tail calls, code is patched after being installed */
 434                 /* but not through the normal "patch callsite" method.   */
 435                 unsigned char buf[kNaClAlignment];
 436                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 437                 int ret;
 438                 memcpy (buf, aligned_code, kNaClAlignment);
 439                 /* Patch a temp buffer of bundle size, */
 440                 /* then install to actual location.    */
 441                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 442                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 443                 g_assert (ret == 0);
 444                 return;
 445         }
 446         target = nacl_modify_patch_target (target);
 447 #endif
 448
 449         /* Skip REX */
 450         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 451                 rex = code [0];
 452                 code += 1;
 453         }
 454
 455         if ((code [0] & 0xf8) == 0xb8) {
 456                 /* amd64_set_reg_template */
 457                 *(guint64*)(code + 1) = (guint64)target;
 458         }
 459         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 460                 /* mov 0(%rip), %dreg */
 461                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 462         }
 463         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 464                 /* call *<OFFSET>(%rip) */
 465                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 466         }
 467         else if (code [0] == 0xe8) {
 468                 /* call <DISP> */
 469                 gint64 disp = (guint8*)target - (guint8*)code;
 470                 g_assert (amd64_is_imm32 (disp));
 471                 x86_patch (code, (unsigned char*)target);
 472         }
 473         else
 474                 x86_patch (code, (unsigned char*)target);
 475 }
 476
 477 void
 478 mono_amd64_patch (unsigned char* code, gpointer target)
 479 {
 480         amd64_patch (code, target);
 481 }
 482
 483 #define DEBUG(a) if (cfg->verbose_level > 1) a
 484
 485 static void inline
 486 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 487 {
 488     ainfo->offset = *stack_size;
 489
 490     if (*gr >= PARAM_REGS) {
 491                 ainfo->storage = ArgOnStack;
 492                 ainfo->arg_size = sizeof (mgreg_t);
 493                 /* Since the same stack slot size is used for all arg */
 494                 /*  types, it needs to be big enough to hold them all */
 495                 (*stack_size) += sizeof(mgreg_t);
 496     }
 497     else {
 498                 ainfo->storage = ArgInIReg;
 499                 ainfo->reg = param_regs [*gr];
 500                 (*gr) ++;
 501     }
 502 }
 503
 504 static void inline
 505 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 506 {
 507     ainfo->offset = *stack_size;
 508
 509     if (*gr >= FLOAT_PARAM_REGS) {
 510                 ainfo->storage = ArgOnStack;
 511                 ainfo->arg_size = sizeof (mgreg_t);
 512                 /* Since the same stack slot size is used for both float */
 513                 /*  types, it needs to be big enough to hold them both */
 514                 (*stack_size) += sizeof(mgreg_t);
 515     }
 516     else {
 517                 /* A double register */
 518                 if (is_double)
 519                         ainfo->storage = ArgInDoubleSSEReg;
 520                 else
 521                         ainfo->storage = ArgInFloatSSEReg;
 522                 ainfo->reg = *gr;
 523                 (*gr) += 1;
 524     }
 525 }
 526
 527 typedef enum ArgumentClass {
 528         ARG_CLASS_NO_CLASS,
 529         ARG_CLASS_MEMORY,
 530         ARG_CLASS_INTEGER,
 531         ARG_CLASS_SSE
 532 } ArgumentClass;
 533
 534 static ArgumentClass
 535 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 536 {
 537         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 538         MonoType *ptype;
 539
 540         ptype = mini_get_underlying_type (type);
 541         switch (ptype->type) {
 542         case MONO_TYPE_I1:
 543         case MONO_TYPE_U1:
 544         case MONO_TYPE_I2:
 545         case MONO_TYPE_U2:
 546         case MONO_TYPE_I4:
 547         case MONO_TYPE_U4:
 548         case MONO_TYPE_I:
 549         case MONO_TYPE_U:
 550         case MONO_TYPE_STRING:
 551         case MONO_TYPE_OBJECT:
 552         case MONO_TYPE_CLASS:
 553         case MONO_TYPE_SZARRAY:
 554         case MONO_TYPE_PTR:
 555         case MONO_TYPE_FNPTR:
 556         case MONO_TYPE_ARRAY:
 557         case MONO_TYPE_I8:
 558         case MONO_TYPE_U8:
 559                 class2 = ARG_CLASS_INTEGER;
 560                 break;
 561         case MONO_TYPE_R4:
 562         case MONO_TYPE_R8:
 563 #ifdef TARGET_WIN32
 564                 class2 = ARG_CLASS_INTEGER;
 565 #else
 566                 class2 = ARG_CLASS_SSE;
 567 #endif
 568                 break;
 569
 570         case MONO_TYPE_TYPEDBYREF:
 571                 g_assert_not_reached ();
 572
 573         case MONO_TYPE_GENERICINST:
 574                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 575                         class2 = ARG_CLASS_INTEGER;
 576                         break;
 577                 }
 578                 /* fall through */
 579         case MONO_TYPE_VALUETYPE: {
 580                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 581                 int i;
 582
 583                 for (i = 0; i < info->num_fields; ++i) {
 584                         class2 = class1;
 585                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 586                 }
 587                 break;
 588         }
 589         default:
 590                 g_assert_not_reached ();
 591         }
 592
 593         /* Merge */
 594         if (class1 == class2)
 595                 ;
 596         else if (class1 == ARG_CLASS_NO_CLASS)
 597                 class1 = class2;
 598         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 599                 class1 = ARG_CLASS_MEMORY;
 600         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 601                 class1 = ARG_CLASS_INTEGER;
 602         else
 603                 class1 = ARG_CLASS_SSE;
 604
 605         return class1;
 606 }
 607 #ifdef __native_client_codegen__
 608
 609 /* Default alignment for Native Client is 32-byte. */
 610 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 611
 612 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 613 /* Check that alignment doesn't cross an alignment boundary.             */
 614 guint8*
 615 mono_arch_nacl_pad(guint8 *code, int pad)
 616 {
 617         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 618
 619         if (pad == 0) return code;
 620         /* assertion: alignment cannot cross a block boundary */
 621         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 622                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 623         while (pad >= kMaxPadding) {
 624                 amd64_padding (code, kMaxPadding);
 625                 pad -= kMaxPadding;
 626         }
 627         if (pad != 0) amd64_padding (code, pad);
 628         return code;
 629 }
 630 #endif
 631
 632 static int
 633 count_fields_nested (MonoClass *klass)
 634 {
 635         MonoMarshalType *info;
 636         int i, count;
 637
 638         info = mono_marshal_load_type_info (klass);
 639         g_assert(info);
 640         count = 0;
 641         for (i = 0; i < info->num_fields; ++i) {
 642                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 643                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 644                 else
 645                         count ++;
 646         }
 647         return count;
 648 }
 649
 650 static int
 651 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 652 {
 653         MonoMarshalType *info;
 654         int i;
 655
 656         info = mono_marshal_load_type_info (klass);
 657         g_assert(info);
 658         for (i = 0; i < info->num_fields; ++i) {
 659                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 660                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 661                 } else {
 662                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 663                         fields [index].offset += offset;
 664                         index ++;
 665                 }
 666         }
 667         return index;
 668 }
 669
 670 #ifdef TARGET_WIN32
 671 static void
 672 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 673                                          gboolean is_return,
 674                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 675 {
 676         guint32 size, i, nfields;
 677         guint32 argsize = 8;
 678         ArgumentClass arg_class;
 679         MonoMarshalType *info = NULL;
 680         MonoMarshalField *fields = NULL;
 681         MonoClass *klass;
 682         gboolean pass_on_stack = FALSE;
 683
 684         klass = mono_class_from_mono_type (type);
 685         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 686         if (!sig->pinvoke)
 687                 pass_on_stack = TRUE;
 688
 689         /* If this struct can't be split up naturally into 8-byte */
 690         /* chunks (registers), pass it on the stack.              */
 691         if (sig->pinvoke && !pass_on_stack) {
 692                 guint32 align;
 693                 guint32 field_size;
 694
 695                 info = mono_marshal_load_type_info (klass);
 696                 g_assert (info);
 697
 698                 /*
 699                  * Collect field information recursively to be able to
 700                  * handle nested structures.
 701                  */
 702                 nfields = count_fields_nested (klass);
 703                 fields = g_new0 (MonoMarshalField, nfields);
 704                 collect_field_info_nested (klass, fields, 0, 0);
 705
 706                 for (i = 0; i < nfields; ++i) {
 707                         field_size = mono_marshal_type_size (fields [i].field->type,
 708                                                            fields [i].mspec,
 709                                                            &align, TRUE, klass->unicode);
 710                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 711                                 pass_on_stack = TRUE;
 712                                 break;
 713                         }
 714                 }
 715         }
 716
 717         if (pass_on_stack) {
 718                 /* Allways pass in memory */
 719                 ainfo->offset = *stack_size;
 720                 *stack_size += ALIGN_TO (size, 8);
 721                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 722                 if (!is_return)
 723                         ainfo->arg_size = ALIGN_TO (size, 8);
 724
 725                 g_free (fields);
 726                 return;
 727         }
 728
 729         if (!sig->pinvoke) {
 730                 int n = mono_class_value_size (klass, NULL);
 731
 732                 argsize = n;
 733
 734                 if (n > 8)
 735                         arg_class = ARG_CLASS_MEMORY;
 736                 else
 737                         /* Always pass in 1 integer register */
 738                         arg_class = ARG_CLASS_INTEGER;
 739         } else {
 740                 g_assert (info);
 741
 742                 if (!fields) {
 743                         ainfo->storage = ArgValuetypeInReg;
 744                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 745                         return;
 746                 }
 747
 748                 switch (info->native_size) {
 749                 case 1: case 2: case 4: case 8:
 750                         break;
 751                 default:
 752                         if (is_return) {
 753                                 ainfo->storage = ArgValuetypeAddrInIReg;
 754                                 ainfo->offset = *stack_size;
 755                                 *stack_size += ALIGN_TO (info->native_size, 8);
 756                         }
 757                         else {
 758                                 ainfo->storage = ArgValuetypeAddrInIReg;
 759
 760                                 if (*gr < PARAM_REGS) {
 761                                         ainfo->pair_storage [0] = ArgInIReg;
 762                                         ainfo->pair_regs [0] = param_regs [*gr];
 763                                         (*gr) ++;
 764                                 }
 765                                 else {
 766                                         ainfo->pair_storage [0] = ArgOnStack;
 767                                         ainfo->offset = *stack_size;
 768                                         ainfo->arg_size = sizeof (mgreg_t);
 769                                         *stack_size += 8;
 770                                 }
 771                         }
 772
 773                         g_free (fields);
 774                         return;
 775                 }
 776
 777                 int size;
 778                 guint32 align;
 779                 ArgumentClass class1;
 780
 781                 if (nfields == 0)
 782                         class1 = ARG_CLASS_MEMORY;
 783                 else
 784                         class1 = ARG_CLASS_NO_CLASS;
 785                 for (i = 0; i < nfields; ++i) {
 786                         size = mono_marshal_type_size (fields [i].field->type,
 787                                                                                    fields [i].mspec,
 788                                                                                    &align, TRUE, klass->unicode);
 789                         /* How far into this quad this data extends.*/
 790                         /* (8 is size of quad) */
 791                         argsize = fields [i].offset + size;
 792
 793                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 794                 }
 795                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 796                 arg_class = class1;
 797         }
 798
 799         g_free (fields);
 800
 801         /* Allocate registers */
 802         {
 803                 int orig_gr = *gr;
 804                 int orig_fr = *fr;
 805
 806                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 807                         argsize ++;
 808
 809                 ainfo->storage = ArgValuetypeInReg;
 810                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 811                 ainfo->pair_size [0] = argsize;
 812                 ainfo->pair_size [1] = 0;
 813                 ainfo->nregs = 1;
 814                 switch (arg_class) {
 815                 case ARG_CLASS_INTEGER:
 816                         if (*gr >= PARAM_REGS)
 817                                 arg_class = ARG_CLASS_MEMORY;
 818                         else {
 819                                 ainfo->pair_storage [0] = ArgInIReg;
 820                                 if (is_return)
 821                                         ainfo->pair_regs [0] = return_regs [*gr];
 822                                 else
 823                                         ainfo->pair_regs [0] = param_regs [*gr];
 824                                 (*gr) ++;
 825                         }
 826                         break;
 827                 case ARG_CLASS_SSE:
 828                         if (*fr >= FLOAT_PARAM_REGS)
 829                                 arg_class = ARG_CLASS_MEMORY;
 830                         else {
 831                                 if (argsize <= 4)
 832                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 833                                 else
 834                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 835                                 ainfo->pair_regs [0] = *fr;
 836                                 (*fr) ++;
 837                         }
 838                         break;
 839                 case ARG_CLASS_MEMORY:
 840                         break;
 841                 default:
 842                         g_assert_not_reached ();
 843                 }
 844
 845                 if (arg_class == ARG_CLASS_MEMORY) {
 846                         /* Revert possible register assignments */
 847                         *gr = orig_gr;
 848                         *fr = orig_fr;
 849
 850                         ainfo->offset = *stack_size;
 851                         *stack_size += sizeof (mgreg_t);
 852                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 853                         if (!is_return)
 854                                 ainfo->arg_size = sizeof (mgreg_t);
 855                 }
 856         }
 857 }
 858 #endif /* TARGET_WIN32 */
 859
 860 static void
 861 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 862                            gboolean is_return,
 863                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 864 {
 865 #ifdef TARGET_WIN32
 866         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 867 #else
 868         guint32 size, quad, nquads, i, nfields;
 869         /* Keep track of the size used in each quad so we can */
 870         /* use the right size when copying args/return vars.  */
 871         guint32 quadsize [2] = {8, 8};
 872         ArgumentClass args [2];
 873         MonoMarshalType *info = NULL;
 874         MonoMarshalField *fields = NULL;
 875         MonoClass *klass;
 876         gboolean pass_on_stack = FALSE;
 877
 878         klass = mono_class_from_mono_type (type);
 879         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 880         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 881                 /* We pass and return vtypes of size 8 in a register */
 882         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 883                 pass_on_stack = TRUE;
 884         }
 885
 886         /* If this struct can't be split up naturally into 8-byte */
 887         /* chunks (registers), pass it on the stack.              */
 888         if (sig->pinvoke && !pass_on_stack) {
 889                 guint32 align;
 890                 guint32 field_size;
 891
 892                 info = mono_marshal_load_type_info (klass);
 893                 g_assert (info);
 894
 895                 /*
 896                  * Collect field information recursively to be able to
 897                  * handle nested structures.
 898                  */
 899                 nfields = count_fields_nested (klass);
 900                 fields = g_new0 (MonoMarshalField, nfields);
 901                 collect_field_info_nested (klass, fields, 0, 0);
 902
 903                 for (i = 0; i < nfields; ++i) {
 904                         field_size = mono_marshal_type_size (fields [i].field->type,
 905                                                            fields [i].mspec,
 906                                                            &align, TRUE, klass->unicode);
 907                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 908                                 pass_on_stack = TRUE;
 909                                 break;
 910                         }
 911                 }
 912         }
 913
 914         if (size == 0) {
 915                 ainfo->storage = ArgValuetypeInReg;
 916                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 917                 return;
 918         }
 919
 920         if (pass_on_stack) {
 921                 /* Allways pass in memory */
 922                 ainfo->offset = *stack_size;
 923                 *stack_size += ALIGN_TO (size, 8);
 924                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 925                 if (!is_return)
 926                         ainfo->arg_size = ALIGN_TO (size, 8);
 927
 928                 g_free (fields);
 929                 return;
 930         }
 931
 932         if (size > 8)
 933                 nquads = 2;
 934         else
 935                 nquads = 1;
 936
 937         if (!sig->pinvoke) {
 938                 int n = mono_class_value_size (klass, NULL);
 939
 940                 quadsize [0] = n >= 8 ? 8 : n;
 941                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 942
 943                 /* Always pass in 1 or 2 integer registers */
 944                 args [0] = ARG_CLASS_INTEGER;
 945                 args [1] = ARG_CLASS_INTEGER;
 946                 /* Only the simplest cases are supported */
 947                 if (is_return && nquads != 1) {
 948                         args [0] = ARG_CLASS_MEMORY;
 949                         args [1] = ARG_CLASS_MEMORY;
 950                 }
 951         } else {
 952                 /*
 953                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 954                  * The X87 and SSEUP stuff is left out since there are no such types in
 955                  * the CLR.
 956                  */
 957                 g_assert (info);
 958
 959                 if (!fields) {
 960                         ainfo->storage = ArgValuetypeInReg;
 961                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 962                         return;
 963                 }
 964
 965                 if (info->native_size > 16) {
 966                         ainfo->offset = *stack_size;
 967                         *stack_size += ALIGN_TO (info->native_size, 8);
 968                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 969                         if (!is_return)
 970                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
 971
 972                         g_free (fields);
 973                         return;
 974                 }
 975
 976                 args [0] = ARG_CLASS_NO_CLASS;
 977                 args [1] = ARG_CLASS_NO_CLASS;
 978                 for (quad = 0; quad < nquads; ++quad) {
 979                         int size;
 980                         guint32 align;
 981                         ArgumentClass class1;
 982
 983                         if (nfields == 0)
 984                                 class1 = ARG_CLASS_MEMORY;
 985                         else
 986                                 class1 = ARG_CLASS_NO_CLASS;
 987                         for (i = 0; i < nfields; ++i) {
 988                                 size = mono_marshal_type_size (fields [i].field->type,
 989                                                                                            fields [i].mspec,
 990                                                                                            &align, TRUE, klass->unicode);
 991                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 992                                         /* Unaligned field */
 993                                         NOT_IMPLEMENTED;
 994                                 }
 995
 996                                 /* Skip fields in other quad */
 997                                 if ((quad == 0) && (fields [i].offset >= 8))
 998                                         continue;
 999                                 if ((quad == 1) && (fields [i].offset < 8))
1000                                         continue;
1001
1002                                 /* How far into this quad this data extends.*/
1003                                 /* (8 is size of quad) */
1004                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1005
1006                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1007                         }
1008                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1009                         args [quad] = class1;
1010                 }
1011         }
1012
1013         g_free (fields);
1014
1015         /* Post merger cleanup */
1016         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1017                 args [0] = args [1] = ARG_CLASS_MEMORY;
1018
1019         /* Allocate registers */
1020         {
1021                 int orig_gr = *gr;
1022                 int orig_fr = *fr;
1023
1024                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1025                         quadsize [0] ++;
1026                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1027                         quadsize [1] ++;
1028
1029                 ainfo->storage = ArgValuetypeInReg;
1030                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1031                 g_assert (quadsize [0] <= 8);
1032                 g_assert (quadsize [1] <= 8);
1033                 ainfo->pair_size [0] = quadsize [0];
1034                 ainfo->pair_size [1] = quadsize [1];
1035                 ainfo->nregs = nquads;
1036                 for (quad = 0; quad < nquads; ++quad) {
1037                         switch (args [quad]) {
1038                         case ARG_CLASS_INTEGER:
1039                                 if (*gr >= PARAM_REGS)
1040                                         args [quad] = ARG_CLASS_MEMORY;
1041                                 else {
1042                                         ainfo->pair_storage [quad] = ArgInIReg;
1043                                         if (is_return)
1044                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1045                                         else
1046                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1047                                         (*gr) ++;
1048                                 }
1049                                 break;
1050                         case ARG_CLASS_SSE:
1051                                 if (*fr >= FLOAT_PARAM_REGS)
1052                                         args [quad] = ARG_CLASS_MEMORY;
1053                                 else {
1054                                         if (quadsize[quad] <= 4)
1055                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1056                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1057                                         ainfo->pair_regs [quad] = *fr;
1058                                         (*fr) ++;
1059                                 }
1060                                 break;
1061                         case ARG_CLASS_MEMORY:
1062                                 break;
1063                         default:
1064                                 g_assert_not_reached ();
1065                         }
1066                 }
1067
1068                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1069                         int arg_size;
1070                         /* Revert possible register assignments */
1071                         *gr = orig_gr;
1072                         *fr = orig_fr;
1073
1074                         ainfo->offset = *stack_size;
1075                         if (sig->pinvoke)
1076                                 arg_size = ALIGN_TO (info->native_size, 8);
1077                         else
1078                                 arg_size = nquads * sizeof(mgreg_t);
1079                         *stack_size += arg_size;
1080                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1081                         if (!is_return)
1082                                 ainfo->arg_size = arg_size;
1083                 }
1084         }
1085 #endif /* !TARGET_WIN32 */
1086 }
1087
1088 /*
1089  * get_call_info:
1090  *
1091  *  Obtain information about a call according to the calling convention.
1092  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1093  * Draft Version 0.23" document for more information.
1094  */
1095 static CallInfo*
1096 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1097 {
1098         guint32 i, gr, fr, pstart;
1099         MonoType *ret_type;
1100         int n = sig->hasthis + sig->param_count;
1101         guint32 stack_size = 0;
1102         CallInfo *cinfo;
1103         gboolean is_pinvoke = sig->pinvoke;
1104
1105         if (mp)
1106                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1107         else
1108                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1109
1110         cinfo->nargs = n;
1111
1112         gr = 0;
1113         fr = 0;
1114
1115 #ifdef TARGET_WIN32
1116         /* Reserve space where the callee can save the argument registers */
1117         stack_size = 4 * sizeof (mgreg_t);
1118 #endif
1119
1120         /* return value */
1121         ret_type = mini_get_underlying_type (sig->ret);
1122         switch (ret_type->type) {
1123         case MONO_TYPE_I1:
1124         case MONO_TYPE_U1:
1125         case MONO_TYPE_I2:
1126         case MONO_TYPE_U2:
1127         case MONO_TYPE_I4:
1128         case MONO_TYPE_U4:
1129         case MONO_TYPE_I:
1130         case MONO_TYPE_U:
1131         case MONO_TYPE_PTR:
1132         case MONO_TYPE_FNPTR:
1133         case MONO_TYPE_CLASS:
1134         case MONO_TYPE_OBJECT:
1135         case MONO_TYPE_SZARRAY:
1136         case MONO_TYPE_ARRAY:
1137         case MONO_TYPE_STRING:
1138                 cinfo->ret.storage = ArgInIReg;
1139                 cinfo->ret.reg = AMD64_RAX;
1140                 break;
1141         case MONO_TYPE_U8:
1142         case MONO_TYPE_I8:
1143                 cinfo->ret.storage = ArgInIReg;
1144                 cinfo->ret.reg = AMD64_RAX;
1145                 break;
1146         case MONO_TYPE_R4:
1147                 cinfo->ret.storage = ArgInFloatSSEReg;
1148                 cinfo->ret.reg = AMD64_XMM0;
1149                 break;
1150         case MONO_TYPE_R8:
1151                 cinfo->ret.storage = ArgInDoubleSSEReg;
1152                 cinfo->ret.reg = AMD64_XMM0;
1153                 break;
1154         case MONO_TYPE_GENERICINST:
1155                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1156                         cinfo->ret.storage = ArgInIReg;
1157                         cinfo->ret.reg = AMD64_RAX;
1158                         break;
1159                 }
1160                 if (mini_is_gsharedvt_type (ret_type)) {
1161                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1162                         cinfo->ret.is_gsharedvt_return_value = 1;
1163                         break;
1164                 }
1165                 /* fall through */
1166         case MONO_TYPE_VALUETYPE:
1167         case MONO_TYPE_TYPEDBYREF: {
1168                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1169
1170                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1171                 g_assert (cinfo->ret.storage != ArgInIReg);
1172                 break;
1173         }
1174         case MONO_TYPE_VAR:
1175         case MONO_TYPE_MVAR:
1176                 g_assert (mini_is_gsharedvt_type (ret_type));
1177                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1178                 cinfo->ret.is_gsharedvt_return_value = 1;
1179                 break;
1180         case MONO_TYPE_VOID:
1181                 break;
1182         default:
1183                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1184         }
1185
1186         pstart = 0;
1187         /*
1188          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1189          * the first argument, allowing 'this' to be always passed in the first arg reg.
1190          * Also do this if the first argument is a reference type, since virtual calls
1191          * are sometimes made using calli without sig->hasthis set, like in the delegate
1192          * invoke wrappers.
1193          */
1194         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1195                 if (sig->hasthis) {
1196                         add_general (&gr, &stack_size, cinfo->args + 0);
1197                 } else {
1198                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1199                         pstart = 1;
1200                 }
1201                 add_general (&gr, &stack_size, &cinfo->ret);
1202                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1203                 cinfo->vret_arg_index = 1;
1204         } else {
1205                 /* this */
1206                 if (sig->hasthis)
1207                         add_general (&gr, &stack_size, cinfo->args + 0);
1208
1209                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1210                         add_general (&gr, &stack_size, &cinfo->ret);
1211                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1212                 }
1213         }
1214
1215         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1216                 gr = PARAM_REGS;
1217                 fr = FLOAT_PARAM_REGS;
1218
1219                 /* Emit the signature cookie just before the implicit arguments */
1220                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1221         }
1222
1223         for (i = pstart; i < sig->param_count; ++i) {
1224                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1225                 MonoType *ptype;
1226
1227 #ifdef TARGET_WIN32
1228                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1229                 if (gr > fr)
1230                         fr = gr;
1231                 else if (fr > gr)
1232                         gr = fr;
1233 #endif
1234
1235                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1236                         /* We allways pass the sig cookie on the stack for simplicity */
1237                         /*
1238                          * Prevent implicit arguments + the sig cookie from being passed
1239                          * in registers.
1240                          */
1241                         gr = PARAM_REGS;
1242                         fr = FLOAT_PARAM_REGS;
1243
1244                         /* Emit the signature cookie just before the implicit arguments */
1245                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1246                 }
1247
1248                 ptype = mini_get_underlying_type (sig->params [i]);
1249                 switch (ptype->type) {
1250                 case MONO_TYPE_I1:
1251                 case MONO_TYPE_U1:
1252                         add_general (&gr, &stack_size, ainfo);
1253                         break;
1254                 case MONO_TYPE_I2:
1255                 case MONO_TYPE_U2:
1256                         add_general (&gr, &stack_size, ainfo);
1257                         break;
1258                 case MONO_TYPE_I4:
1259                 case MONO_TYPE_U4:
1260                         add_general (&gr, &stack_size, ainfo);
1261                         break;
1262                 case MONO_TYPE_I:
1263                 case MONO_TYPE_U:
1264                 case MONO_TYPE_PTR:
1265                 case MONO_TYPE_FNPTR:
1266                 case MONO_TYPE_CLASS:
1267                 case MONO_TYPE_OBJECT:
1268                 case MONO_TYPE_STRING:
1269                 case MONO_TYPE_SZARRAY:
1270                 case MONO_TYPE_ARRAY:
1271                         add_general (&gr, &stack_size, ainfo);
1272                         break;
1273                 case MONO_TYPE_GENERICINST:
1274                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1275                                 add_general (&gr, &stack_size, ainfo);
1276                                 break;
1277                         }
1278                         if (mini_is_gsharedvt_variable_type (ptype)) {
1279                                 /* gsharedvt arguments are passed by ref */
1280                                 add_general (&gr, &stack_size, ainfo);
1281                                 if (ainfo->storage == ArgInIReg)
1282                                         ainfo->storage = ArgGSharedVtInReg;
1283                                 else
1284                                         ainfo->storage = ArgGSharedVtOnStack;
1285                                 break;
1286                         }
1287                         /* fall through */
1288                 case MONO_TYPE_VALUETYPE:
1289                 case MONO_TYPE_TYPEDBYREF:
1290                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1291                         break;
1292                 case MONO_TYPE_U8:
1293
1294                 case MONO_TYPE_I8:
1295                         add_general (&gr, &stack_size, ainfo);
1296                         break;
1297                 case MONO_TYPE_R4:
1298                         add_float (&fr, &stack_size, ainfo, FALSE);
1299                         break;
1300                 case MONO_TYPE_R8:
1301                         add_float (&fr, &stack_size, ainfo, TRUE);
1302                         break;
1303                 case MONO_TYPE_VAR:
1304                 case MONO_TYPE_MVAR:
1305                         /* gsharedvt arguments are passed by ref */
1306                         g_assert (mini_is_gsharedvt_type (ptype));
1307                         add_general (&gr, &stack_size, ainfo);
1308                         if (ainfo->storage == ArgInIReg)
1309                                 ainfo->storage = ArgGSharedVtInReg;
1310                         else
1311                                 ainfo->storage = ArgGSharedVtOnStack;
1312                         break;
1313                 default:
1314                         g_assert_not_reached ();
1315                 }
1316         }
1317
1318         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1319                 gr = PARAM_REGS;
1320                 fr = FLOAT_PARAM_REGS;
1321
1322                 /* Emit the signature cookie just before the implicit arguments */
1323                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1324         }
1325
1326         cinfo->stack_usage = stack_size;
1327         cinfo->reg_usage = gr;
1328         cinfo->freg_usage = fr;
1329         return cinfo;
1330 }
1331
1332 /*
1333  * mono_arch_get_argument_info:
1334  * @csig:  a method signature
1335  * @param_count: the number of parameters to consider
1336  * @arg_info: an array to store the result infos
1337  *
1338  * Gathers information on parameters such as size, alignment and
1339  * padding. arg_info should be large enought to hold param_count + 1 entries.
1340  *
1341  * Returns the size of the argument area on the stack.
1342  */
1343 int
1344 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1345 {
1346         int k;
1347         CallInfo *cinfo = get_call_info (NULL, csig);
1348         guint32 args_size = cinfo->stack_usage;
1349
1350         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1351         if (csig->hasthis) {
1352                 arg_info [0].offset = 0;
1353         }
1354
1355         for (k = 0; k < param_count; k++) {
1356                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1357                 /* FIXME: */
1358                 arg_info [k + 1].size = 0;
1359         }
1360
1361         g_free (cinfo);
1362
1363         return args_size;
1364 }
1365
1366 gboolean
1367 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1368 {
1369         CallInfo *c1, *c2;
1370         gboolean res;
1371         MonoType *callee_ret;
1372
1373         c1 = get_call_info (NULL, caller_sig);
1374         c2 = get_call_info (NULL, callee_sig);
1375         res = c1->stack_usage >= c2->stack_usage;
1376         callee_ret = mini_get_underlying_type (callee_sig->ret);
1377         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1378                 /* An address on the callee's stack is passed as the first argument */
1379                 res = FALSE;
1380
1381         g_free (c1);
1382         g_free (c2);
1383
1384         return res;
1385 }
1386
1387 /*
1388  * Initialize the cpu to execute managed code.
1389  */
1390 void
1391 mono_arch_cpu_init (void)
1392 {
1393 #ifndef _MSC_VER
1394         guint16 fpcw;
1395
1396         /* spec compliance requires running with double precision */
1397         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1398         fpcw &= ~X86_FPCW_PRECC_MASK;
1399         fpcw |= X86_FPCW_PREC_DOUBLE;
1400         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1401         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1402 #else
1403         /* TODO: This is crashing on Win64 right now.
1404         * _control87 (_PC_53, MCW_PC);
1405         */
1406 #endif
1407 }
1408
1409 /*
1410  * Initialize architecture specific code.
1411  */
1412 void
1413 mono_arch_init (void)
1414 {
1415         mono_os_mutex_init_recursive (&mini_arch_mutex);
1416 #if defined(__native_client_codegen__)
1417         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1418         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1419         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1420         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1421 #endif
1422
1423         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1424         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1425         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1426         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1427 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1428         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1429 #endif
1430
1431         if (!mono_aot_only)
1432                 bp_trampoline = mini_get_breakpoint_trampoline ();
1433 }
1434
1435 /*
1436  * Cleanup architecture specific code.
1437  */
1438 void
1439 mono_arch_cleanup (void)
1440 {
1441         mono_os_mutex_destroy (&mini_arch_mutex);
1442 #if defined(__native_client_codegen__)
1443         mono_native_tls_free (nacl_instruction_depth);
1444         mono_native_tls_free (nacl_rex_tag);
1445         mono_native_tls_free (nacl_legacy_prefix_tag);
1446 #endif
1447 }
1448
1449 /*
1450  * This function returns the optimizations supported on this cpu.
1451  */
1452 guint32
1453 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1454 {
1455         guint32 opts = 0;
1456
1457         *exclude_mask = 0;
1458
1459         if (mono_hwcap_x86_has_cmov) {
1460                 opts |= MONO_OPT_CMOV;
1461
1462                 if (mono_hwcap_x86_has_fcmov)
1463                         opts |= MONO_OPT_FCMOV;
1464                 else
1465                         *exclude_mask |= MONO_OPT_FCMOV;
1466         } else {
1467                 *exclude_mask |= MONO_OPT_CMOV;
1468         }
1469
1470         return opts;
1471 }
1472
1473 /*
1474  * This function test for all SSE functions supported.
1475  *
1476  * Returns a bitmask corresponding to all supported versions.
1477  *
1478  */
1479 guint32
1480 mono_arch_cpu_enumerate_simd_versions (void)
1481 {
1482         guint32 sse_opts = 0;
1483
1484         if (mono_hwcap_x86_has_sse1)
1485                 sse_opts |= SIMD_VERSION_SSE1;
1486
1487         if (mono_hwcap_x86_has_sse2)
1488                 sse_opts |= SIMD_VERSION_SSE2;
1489
1490         if (mono_hwcap_x86_has_sse3)
1491                 sse_opts |= SIMD_VERSION_SSE3;
1492
1493         if (mono_hwcap_x86_has_ssse3)
1494                 sse_opts |= SIMD_VERSION_SSSE3;
1495
1496         if (mono_hwcap_x86_has_sse41)
1497                 sse_opts |= SIMD_VERSION_SSE41;
1498
1499         if (mono_hwcap_x86_has_sse42)
1500                 sse_opts |= SIMD_VERSION_SSE42;
1501
1502         if (mono_hwcap_x86_has_sse4a)
1503                 sse_opts |= SIMD_VERSION_SSE4a;
1504
1505         return sse_opts;
1506 }
1507
1508 #ifndef DISABLE_JIT
1509
1510 GList *
1511 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1512 {
1513         GList *vars = NULL;
1514         int i;
1515
1516         for (i = 0; i < cfg->num_varinfo; i++) {
1517                 MonoInst *ins = cfg->varinfo [i];
1518                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1519
1520                 /* unused vars */
1521                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1522                         continue;
1523
1524                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1525                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1526                         continue;
1527
1528                 if (mono_is_regsize_var (ins->inst_vtype)) {
1529                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1530                         g_assert (i == vmv->idx);
1531                         vars = g_list_prepend (vars, vmv);
1532                 }
1533         }
1534
1535         vars = mono_varlist_sort (cfg, vars, 0);
1536
1537         return vars;
1538 }
1539
1540 /**
1541  * mono_arch_compute_omit_fp:
1542  *
1543  *   Determine whenever the frame pointer can be eliminated.
1544  */
1545 static void
1546 mono_arch_compute_omit_fp (MonoCompile *cfg)
1547 {
1548         MonoMethodSignature *sig;
1549         MonoMethodHeader *header;
1550         int i, locals_size;
1551         CallInfo *cinfo;
1552
1553         if (cfg->arch.omit_fp_computed)
1554                 return;
1555
1556         header = cfg->header;
1557
1558         sig = mono_method_signature (cfg->method);
1559
1560         if (!cfg->arch.cinfo)
1561                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1562         cinfo = (CallInfo *)cfg->arch.cinfo;
1563
1564         /*
1565          * FIXME: Remove some of the restrictions.
1566          */
1567         cfg->arch.omit_fp = TRUE;
1568         cfg->arch.omit_fp_computed = TRUE;
1569
1570 #ifdef __native_client_codegen__
1571         /* NaCl modules may not change the value of RBP, so it cannot be */
1572         /* used as a normal register, but it can be used as a frame pointer*/
1573         cfg->disable_omit_fp = TRUE;
1574         cfg->arch.omit_fp = FALSE;
1575 #endif
1576
1577         if (cfg->disable_omit_fp)
1578                 cfg->arch.omit_fp = FALSE;
1579
1580         if (!debug_omit_fp ())
1581                 cfg->arch.omit_fp = FALSE;
1582         /*
1583         if (cfg->method->save_lmf)
1584                 cfg->arch.omit_fp = FALSE;
1585         */
1586         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1587                 cfg->arch.omit_fp = FALSE;
1588         if (header->num_clauses)
1589                 cfg->arch.omit_fp = FALSE;
1590         if (cfg->param_area)
1591                 cfg->arch.omit_fp = FALSE;
1592         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1593                 cfg->arch.omit_fp = FALSE;
1594         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1595                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1596                 cfg->arch.omit_fp = FALSE;
1597         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1598                 ArgInfo *ainfo = &cinfo->args [i];
1599
1600                 if (ainfo->storage == ArgOnStack) {
1601                         /*
1602                          * The stack offset can only be determined when the frame
1603                          * size is known.
1604                          */
1605                         cfg->arch.omit_fp = FALSE;
1606                 }
1607         }
1608
1609         locals_size = 0;
1610         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1611                 MonoInst *ins = cfg->varinfo [i];
1612                 int ialign;
1613
1614                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1615         }
1616 }
1617
1618 GList *
1619 mono_arch_get_global_int_regs (MonoCompile *cfg)
1620 {
1621         GList *regs = NULL;
1622
1623         mono_arch_compute_omit_fp (cfg);
1624
1625         if (cfg->arch.omit_fp)
1626                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1627
1628         /* We use the callee saved registers for global allocation */
1629         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1630         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1631         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1632         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1633 #ifndef __native_client_codegen__
1634         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1635 #endif
1636 #ifdef TARGET_WIN32
1637         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1638         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1639 #endif
1640
1641         return regs;
1642 }
1643
1644 GList*
1645 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1646 {
1647         GList *regs = NULL;
1648         int i;
1649
1650         /* All XMM registers */
1651         for (i = 0; i < 16; ++i)
1652                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1653
1654         return regs;
1655 }
1656
1657 GList*
1658 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1659 {
1660         static GList *r = NULL;
1661
1662         if (r == NULL) {
1663                 GList *regs = NULL;
1664
1665                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1666                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1667                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1668                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1669                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1670 #ifndef __native_client_codegen__
1671                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1672 #endif
1673
1674                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1675                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1676                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1677                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1678                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1679                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1680                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1681                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1682
1683                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1684         }
1685
1686         return r;
1687 }
1688
1689 GList*
1690 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1691 {
1692         int i;
1693         static GList *r = NULL;
1694
1695         if (r == NULL) {
1696                 GList *regs = NULL;
1697
1698                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1699                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1700
1701                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1702         }
1703
1704         return r;
1705 }
1706
1707 /*
1708  * mono_arch_regalloc_cost:
1709  *
1710  *  Return the cost, in number of memory references, of the action of
1711  * allocating the variable VMV into a register during global register
1712  * allocation.
1713  */
1714 guint32
1715 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1716 {
1717         MonoInst *ins = cfg->varinfo [vmv->idx];
1718
1719         if (cfg->method->save_lmf)
1720                 /* The register is already saved */
1721                 /* substract 1 for the invisible store in the prolog */
1722                 return (ins->opcode == OP_ARG) ? 0 : 1;
1723         else
1724                 /* push+pop */
1725                 return (ins->opcode == OP_ARG) ? 1 : 2;
1726 }
1727
1728 /*
1729  * mono_arch_fill_argument_info:
1730  *
1731  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1732  * of the method.
1733  */
1734 void
1735 mono_arch_fill_argument_info (MonoCompile *cfg)
1736 {
1737         MonoType *sig_ret;
1738         MonoMethodSignature *sig;
1739         MonoInst *ins;
1740         int i;
1741         CallInfo *cinfo;
1742
1743         sig = mono_method_signature (cfg->method);
1744
1745         cinfo = (CallInfo *)cfg->arch.cinfo;
1746         sig_ret = mini_get_underlying_type (sig->ret);
1747
1748         /*
1749          * Contrary to mono_arch_allocate_vars (), the information should describe
1750          * where the arguments are at the beginning of the method, not where they can be
1751          * accessed during the execution of the method. The later makes no sense for the
1752          * global register allocator, since a variable can be in more than one location.
1753          */
1754         switch (cinfo->ret.storage) {
1755         case ArgInIReg:
1756         case ArgInFloatSSEReg:
1757         case ArgInDoubleSSEReg:
1758                 cfg->ret->opcode = OP_REGVAR;
1759                 cfg->ret->inst_c0 = cinfo->ret.reg;
1760                 break;
1761         case ArgValuetypeInReg:
1762                 cfg->ret->opcode = OP_REGOFFSET;
1763                 cfg->ret->inst_basereg = -1;
1764                 cfg->ret->inst_offset = -1;
1765                 break;
1766         case ArgNone:
1767                 break;
1768         default:
1769                 g_assert_not_reached ();
1770         }
1771
1772         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1773                 ArgInfo *ainfo = &cinfo->args [i];
1774
1775                 ins = cfg->args [i];
1776
1777                 switch (ainfo->storage) {
1778                 case ArgInIReg:
1779                 case ArgInFloatSSEReg:
1780                 case ArgInDoubleSSEReg:
1781                         ins->opcode = OP_REGVAR;
1782                         ins->inst_c0 = ainfo->reg;
1783                         break;
1784                 case ArgOnStack:
1785                         ins->opcode = OP_REGOFFSET;
1786                         ins->inst_basereg = -1;
1787                         ins->inst_offset = -1;
1788                         break;
1789                 case ArgValuetypeInReg:
1790                         /* Dummy */
1791                         ins->opcode = OP_NOP;
1792                         break;
1793                 default:
1794                         g_assert_not_reached ();
1795                 }
1796         }
1797 }
1798
1799 void
1800 mono_arch_allocate_vars (MonoCompile *cfg)
1801 {
1802         MonoType *sig_ret;
1803         MonoMethodSignature *sig;
1804         MonoInst *ins;
1805         int i, offset;
1806         guint32 locals_stack_size, locals_stack_align;
1807         gint32 *offsets;
1808         CallInfo *cinfo;
1809
1810         sig = mono_method_signature (cfg->method);
1811
1812         cinfo = (CallInfo *)cfg->arch.cinfo;
1813         sig_ret = mini_get_underlying_type (sig->ret);
1814
1815         mono_arch_compute_omit_fp (cfg);
1816
1817         /*
1818          * We use the ABI calling conventions for managed code as well.
1819          * Exception: valuetypes are only sometimes passed or returned in registers.
1820          */
1821
1822         /*
1823          * The stack looks like this:
1824          * <incoming arguments passed on the stack>
1825          * <return value>
1826          * <lmf/caller saved registers>
1827          * <locals>
1828          * <spill area>
1829          * <localloc area>  -> grows dynamically
1830          * <params area>
1831          */
1832
1833         if (cfg->arch.omit_fp) {
1834                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1835                 cfg->frame_reg = AMD64_RSP;
1836                 offset = 0;
1837         } else {
1838                 /* Locals are allocated backwards from %fp */
1839                 cfg->frame_reg = AMD64_RBP;
1840                 offset = 0;
1841         }
1842
1843         cfg->arch.saved_iregs = cfg->used_int_regs;
1844         if (cfg->method->save_lmf)
1845                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1846                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1847
1848         if (cfg->arch.omit_fp)
1849                 cfg->arch.reg_save_area_offset = offset;
1850         /* Reserve space for callee saved registers */
1851         for (i = 0; i < AMD64_NREG; ++i)
1852                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1853                         offset += sizeof(mgreg_t);
1854                 }
1855         if (!cfg->arch.omit_fp)
1856                 cfg->arch.reg_save_area_offset = -offset;
1857
1858         if (sig_ret->type != MONO_TYPE_VOID) {
1859                 switch (cinfo->ret.storage) {
1860                 case ArgInIReg:
1861                 case ArgInFloatSSEReg:
1862                 case ArgInDoubleSSEReg:
1863                         cfg->ret->opcode = OP_REGVAR;
1864                         cfg->ret->inst_c0 = cinfo->ret.reg;
1865                         cfg->ret->dreg = cinfo->ret.reg;
1866                         break;
1867                 case ArgValuetypeAddrInIReg:
1868                         /* The register is volatile */
1869                         cfg->vret_addr->opcode = OP_REGOFFSET;
1870                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1871                         if (cfg->arch.omit_fp) {
1872                                 cfg->vret_addr->inst_offset = offset;
1873                                 offset += 8;
1874                         } else {
1875                                 offset += 8;
1876                                 cfg->vret_addr->inst_offset = -offset;
1877                         }
1878                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1879                                 printf ("vret_addr =");
1880                                 mono_print_ins (cfg->vret_addr);
1881                         }
1882                         break;
1883                 case ArgValuetypeInReg:
1884                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1885                         cfg->ret->opcode = OP_REGOFFSET;
1886                         cfg->ret->inst_basereg = cfg->frame_reg;
1887                         if (cfg->arch.omit_fp) {
1888                                 cfg->ret->inst_offset = offset;
1889                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1890                         } else {
1891                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1892                                 cfg->ret->inst_offset = - offset;
1893                         }
1894                         break;
1895                 default:
1896                         g_assert_not_reached ();
1897                 }
1898         }
1899
1900         /* Allocate locals */
1901         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1902         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1903                 char *mname = mono_method_full_name (cfg->method, TRUE);
1904                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1905                 g_free (mname);
1906                 return;
1907         }
1908
1909         if (locals_stack_align) {
1910                 offset += (locals_stack_align - 1);
1911                 offset &= ~(locals_stack_align - 1);
1912         }
1913         if (cfg->arch.omit_fp) {
1914                 cfg->locals_min_stack_offset = offset;
1915                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1916         } else {
1917                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1918                 cfg->locals_max_stack_offset = - offset;
1919         }
1920
1921         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1922                 if (offsets [i] != -1) {
1923                         MonoInst *ins = cfg->varinfo [i];
1924                         ins->opcode = OP_REGOFFSET;
1925                         ins->inst_basereg = cfg->frame_reg;
1926                         if (cfg->arch.omit_fp)
1927                                 ins->inst_offset = (offset + offsets [i]);
1928                         else
1929                                 ins->inst_offset = - (offset + offsets [i]);
1930                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1931                 }
1932         }
1933         offset += locals_stack_size;
1934
1935         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1936                 g_assert (!cfg->arch.omit_fp);
1937                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1938                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1939         }
1940
1941         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1942                 ins = cfg->args [i];
1943                 if (ins->opcode != OP_REGVAR) {
1944                         ArgInfo *ainfo = &cinfo->args [i];
1945                         gboolean inreg = TRUE;
1946
1947                         /* FIXME: Allocate volatile arguments to registers */
1948                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1949                                 inreg = FALSE;
1950
1951                         /*
1952                          * Under AMD64, all registers used to pass arguments to functions
1953                          * are volatile across calls.
1954                          * FIXME: Optimize this.
1955                          */
1956                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1957                                 inreg = FALSE;
1958
1959                         ins->opcode = OP_REGOFFSET;
1960
1961                         switch (ainfo->storage) {
1962                         case ArgInIReg:
1963                         case ArgInFloatSSEReg:
1964                         case ArgInDoubleSSEReg:
1965                         case ArgGSharedVtInReg:
1966                                 if (inreg) {
1967                                         ins->opcode = OP_REGVAR;
1968                                         ins->dreg = ainfo->reg;
1969                                 }
1970                                 break;
1971                         case ArgOnStack:
1972                         case ArgGSharedVtOnStack:
1973                                 g_assert (!cfg->arch.omit_fp);
1974                                 ins->opcode = OP_REGOFFSET;
1975                                 ins->inst_basereg = cfg->frame_reg;
1976                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1977                                 break;
1978                         case ArgValuetypeInReg:
1979                                 break;
1980                         case ArgValuetypeAddrInIReg: {
1981                                 MonoInst *indir;
1982                                 g_assert (!cfg->arch.omit_fp);
1983
1984                                 MONO_INST_NEW (cfg, indir, 0);
1985                                 indir->opcode = OP_REGOFFSET;
1986                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1987                                         indir->inst_basereg = cfg->frame_reg;
1988                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1989                                         offset += (sizeof (gpointer));
1990                                         indir->inst_offset = - offset;
1991                                 }
1992                                 else {
1993                                         indir->inst_basereg = cfg->frame_reg;
1994                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1995                                 }
1996
1997                                 ins->opcode = OP_VTARG_ADDR;
1998                                 ins->inst_left = indir;
1999
2000                                 break;
2001                         }
2002                         default:
2003                                 NOT_IMPLEMENTED;
2004                         }
2005
2006                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
2007                                 ins->opcode = OP_REGOFFSET;
2008                                 ins->inst_basereg = cfg->frame_reg;
2009                                 /* These arguments are saved to the stack in the prolog */
2010                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2011                                 if (cfg->arch.omit_fp) {
2012                                         ins->inst_offset = offset;
2013                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2014                                         // Arguments are yet supported by the stack map creation code
2015                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2016                                 } else {
2017                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2018                                         ins->inst_offset = - offset;
2019                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2020                                 }
2021                         }
2022                 }
2023         }
2024
2025         cfg->stack_offset = offset;
2026 }
2027
2028 void
2029 mono_arch_create_vars (MonoCompile *cfg)
2030 {
2031         MonoMethodSignature *sig;
2032         CallInfo *cinfo;
2033         MonoType *sig_ret;
2034
2035         sig = mono_method_signature (cfg->method);
2036
2037         if (!cfg->arch.cinfo)
2038                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2039         cinfo = (CallInfo *)cfg->arch.cinfo;
2040
2041         if (cinfo->ret.storage == ArgValuetypeInReg)
2042                 cfg->ret_var_is_local = TRUE;
2043
2044         sig_ret = mini_get_underlying_type (sig->ret);
2045         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2046                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2047                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2048                         printf ("vret_addr = ");
2049                         mono_print_ins (cfg->vret_addr);
2050                 }
2051         }
2052
2053         if (cfg->gen_sdb_seq_points) {
2054                 MonoInst *ins;
2055
2056                 if (cfg->compile_aot) {
2057                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2058                         ins->flags |= MONO_INST_VOLATILE;
2059                         cfg->arch.seq_point_info_var = ins;
2060                 }
2061                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2062                 ins->flags |= MONO_INST_VOLATILE;
2063                 cfg->arch.ss_tramp_var = ins;
2064
2065                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2066                 ins->flags |= MONO_INST_VOLATILE;
2067                 cfg->arch.bp_tramp_var = ins;
2068         }
2069
2070         if (cfg->method->save_lmf)
2071                 cfg->create_lmf_var = TRUE;
2072
2073         if (cfg->method->save_lmf) {
2074                 cfg->lmf_ir = TRUE;
2075 #if !defined(TARGET_WIN32)
2076                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2077                         cfg->lmf_ir_mono_lmf = TRUE;
2078 #endif
2079         }
2080 }
2081
2082 static void
2083 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2084 {
2085         MonoInst *ins;
2086
2087         switch (storage) {
2088         case ArgInIReg:
2089                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2090                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2091                 ins->sreg1 = tree->dreg;
2092                 MONO_ADD_INS (cfg->cbb, ins);
2093                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2094                 break;
2095         case ArgInFloatSSEReg:
2096                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2097                 ins->dreg = mono_alloc_freg (cfg);
2098                 ins->sreg1 = tree->dreg;
2099                 MONO_ADD_INS (cfg->cbb, ins);
2100
2101                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2102                 break;
2103         case ArgInDoubleSSEReg:
2104                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2105                 ins->dreg = mono_alloc_freg (cfg);
2106                 ins->sreg1 = tree->dreg;
2107                 MONO_ADD_INS (cfg->cbb, ins);
2108
2109                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2110
2111                 break;
2112         default:
2113                 g_assert_not_reached ();
2114         }
2115 }
2116
2117 static int
2118 arg_storage_to_load_membase (ArgStorage storage)
2119 {
2120         switch (storage) {
2121         case ArgInIReg:
2122 #if defined(__mono_ilp32__)
2123                 return OP_LOADI8_MEMBASE;
2124 #else
2125                 return OP_LOAD_MEMBASE;
2126 #endif
2127         case ArgInDoubleSSEReg:
2128                 return OP_LOADR8_MEMBASE;
2129         case ArgInFloatSSEReg:
2130                 return OP_LOADR4_MEMBASE;
2131         default:
2132                 g_assert_not_reached ();
2133         }
2134
2135         return -1;
2136 }
2137
2138 static void
2139 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2140 {
2141         MonoMethodSignature *tmp_sig;
2142         int sig_reg;
2143
2144         if (call->tail_call)
2145                 NOT_IMPLEMENTED;
2146
2147         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2148
2149         /*
2150          * mono_ArgIterator_Setup assumes the signature cookie is
2151          * passed first and all the arguments which were before it are
2152          * passed on the stack after the signature. So compensate by
2153          * passing a different signature.
2154          */
2155         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2156         tmp_sig->param_count -= call->signature->sentinelpos;
2157         tmp_sig->sentinelpos = 0;
2158         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2159
2160         sig_reg = mono_alloc_ireg (cfg);
2161         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2162
2163         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2164 }
2165
2166 #ifdef ENABLE_LLVM
2167 static inline LLVMArgStorage
2168 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2169 {
2170         switch (storage) {
2171         case ArgInIReg:
2172                 return LLVMArgInIReg;
2173         case ArgNone:
2174                 return LLVMArgNone;
2175         case ArgGSharedVtInReg:
2176         case ArgGSharedVtOnStack:
2177                 return LLVMArgGSharedVt;
2178         default:
2179                 g_assert_not_reached ();
2180                 return LLVMArgNone;
2181         }
2182 }
2183
2184 LLVMCallInfo*
2185 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2186 {
2187         int i, n;
2188         CallInfo *cinfo;
2189         ArgInfo *ainfo;
2190         int j;
2191         LLVMCallInfo *linfo;
2192         MonoType *t, *sig_ret;
2193
2194         n = sig->param_count + sig->hasthis;
2195         sig_ret = mini_get_underlying_type (sig->ret);
2196
2197         cinfo = get_call_info (cfg->mempool, sig);
2198
2199         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2200
2201         /*
2202          * LLVM always uses the native ABI while we use our own ABI, the
2203          * only difference is the handling of vtypes:
2204          * - we only pass/receive them in registers in some cases, and only
2205          *   in 1 or 2 integer registers.
2206          */
2207         switch (cinfo->ret.storage) {
2208         case ArgNone:
2209                 linfo->ret.storage = LLVMArgNone;
2210                 break;
2211         case ArgInIReg:
2212         case ArgInFloatSSEReg:
2213         case ArgInDoubleSSEReg:
2214                 linfo->ret.storage = LLVMArgNormal;
2215                 break;
2216         case ArgValuetypeInReg: {
2217                 ainfo = &cinfo->ret;
2218
2219                 if (sig->pinvoke &&
2220                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2221                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2222                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
2223                         cfg->disable_llvm = TRUE;
2224                         return linfo;
2225                 }
2226
2227                 linfo->ret.storage = LLVMArgVtypeInReg;
2228                 for (j = 0; j < 2; ++j)
2229                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2230                 break;
2231         }
2232         case ArgValuetypeAddrInIReg:
2233                 /* Vtype returned using a hidden argument */
2234                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2235                 linfo->vret_arg_index = cinfo->vret_arg_index;
2236                 break;
2237         default:
2238                 g_assert_not_reached ();
2239                 break;
2240         }
2241
2242         for (i = 0; i < n; ++i) {
2243                 ainfo = cinfo->args + i;
2244
2245                 if (i >= sig->hasthis)
2246                         t = sig->params [i - sig->hasthis];
2247                 else
2248                         t = &mono_defaults.int_class->byval_arg;
2249
2250                 linfo->args [i].storage = LLVMArgNone;
2251
2252                 switch (ainfo->storage) {
2253                 case ArgInIReg:
2254                         linfo->args [i].storage = LLVMArgNormal;
2255                         break;
2256                 case ArgInDoubleSSEReg:
2257                 case ArgInFloatSSEReg:
2258                         linfo->args [i].storage = LLVMArgNormal;
2259                         break;
2260                 case ArgOnStack:
2261                         if (MONO_TYPE_ISSTRUCT (t))
2262                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2263                         else
2264                                 linfo->args [i].storage = LLVMArgNormal;
2265                         break;
2266                 case ArgValuetypeInReg:
2267                         if (sig->pinvoke &&
2268                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2269                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2270                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2271                                 cfg->disable_llvm = TRUE;
2272                                 return linfo;
2273                         }
2274
2275                         linfo->args [i].storage = LLVMArgVtypeInReg;
2276                         for (j = 0; j < 2; ++j)
2277                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2278                         break;
2279                 case ArgGSharedVtInReg:
2280                 case ArgGSharedVtOnStack:
2281                         linfo->args [i].storage = LLVMArgGSharedVt;
2282                         break;
2283                 default:
2284                         cfg->exception_message = g_strdup ("ainfo->storage");
2285                         cfg->disable_llvm = TRUE;
2286                         break;
2287                 }
2288         }
2289
2290         return linfo;
2291 }
2292 #endif
2293
2294 void
2295 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2296 {
2297         MonoInst *arg, *in;
2298         MonoMethodSignature *sig;
2299         MonoType *sig_ret;
2300         int i, n;
2301         CallInfo *cinfo;
2302         ArgInfo *ainfo;
2303
2304         sig = call->signature;
2305         n = sig->param_count + sig->hasthis;
2306
2307         cinfo = get_call_info (cfg->mempool, sig);
2308
2309         sig_ret = sig->ret;
2310
2311         if (COMPILE_LLVM (cfg)) {
2312                 /* We shouldn't be called in the llvm case */
2313                 cfg->disable_llvm = TRUE;
2314                 return;
2315         }
2316
2317         /*
2318          * Emit all arguments which are passed on the stack to prevent register
2319          * allocation problems.
2320          */
2321         for (i = 0; i < n; ++i) {
2322                 MonoType *t;
2323                 ainfo = cinfo->args + i;
2324
2325                 in = call->args [i];
2326
2327                 if (sig->hasthis && i == 0)
2328                         t = &mono_defaults.object_class->byval_arg;
2329                 else
2330                         t = sig->params [i - sig->hasthis];
2331
2332                 t = mini_get_underlying_type (t);
2333                 //XXX what about ArgGSharedVtOnStack here?
2334                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2335                         if (!t->byref) {
2336                                 if (t->type == MONO_TYPE_R4)
2337                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2338                                 else if (t->type == MONO_TYPE_R8)
2339                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2340                                 else
2341                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2342                         } else {
2343                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2344                         }
2345                         if (cfg->compute_gc_maps) {
2346                                 MonoInst *def;
2347
2348                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2349                         }
2350                 }
2351         }
2352
2353         /*
2354          * Emit all parameters passed in registers in non-reverse order for better readability
2355          * and to help the optimization in emit_prolog ().
2356          */
2357         for (i = 0; i < n; ++i) {
2358                 ainfo = cinfo->args + i;
2359
2360                 in = call->args [i];
2361
2362                 if (ainfo->storage == ArgInIReg)
2363                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2364         }
2365
2366         for (i = n - 1; i >= 0; --i) {
2367                 MonoType *t;
2368
2369                 ainfo = cinfo->args + i;
2370
2371                 in = call->args [i];
2372
2373                 if (sig->hasthis && i == 0)
2374                         t = &mono_defaults.object_class->byval_arg;
2375                 else
2376                         t = sig->params [i - sig->hasthis];
2377                 t = mini_get_underlying_type (t);
2378
2379                 switch (ainfo->storage) {
2380                 case ArgInIReg:
2381                         /* Already done */
2382                         break;
2383                 case ArgInFloatSSEReg:
2384                 case ArgInDoubleSSEReg:
2385                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2386                         break;
2387                 case ArgOnStack:
2388                 case ArgValuetypeInReg:
2389                 case ArgValuetypeAddrInIReg:
2390                 case ArgGSharedVtInReg:
2391                 case ArgGSharedVtOnStack: {
2392                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2393                                 /* Already emitted above */
2394                                 break;
2395                         //FIXME what about ArgGSharedVtOnStack ?
2396                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2397                                 MonoInst *call_inst = (MonoInst*)call;
2398                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2399                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2400                                 break;
2401                         }
2402
2403                         guint32 align;
2404                         guint32 size;
2405
2406                         if (sig->pinvoke)
2407                                 size = mono_type_native_stack_size (t, &align);
2408                         else {
2409                                 /*
2410                                  * Other backends use mono_type_stack_size (), but that
2411                                  * aligns the size to 8, which is larger than the size of
2412                                  * the source, leading to reads of invalid memory if the
2413                                  * source is at the end of address space.
2414                                  */
2415                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2416                         }
2417
2418                         if (size >= 10000) {
2419                                 /* Avoid asserts in emit_memcpy () */
2420                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2421                                 /* Continue normally */
2422                         }
2423
2424                         if (size > 0) {
2425                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2426                                 arg->sreg1 = in->dreg;
2427                                 arg->klass = mono_class_from_mono_type (t);
2428                                 arg->backend.size = size;
2429                                 arg->inst_p0 = call;
2430                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2431                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2432
2433                                 MONO_ADD_INS (cfg->cbb, arg);
2434                         }
2435                         break;
2436                 }
2437                 default:
2438                         g_assert_not_reached ();
2439                 }
2440
2441                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2442                         /* Emit the signature cookie just before the implicit arguments */
2443                         emit_sig_cookie (cfg, call, cinfo);
2444         }
2445
2446         /* Handle the case where there are no implicit arguments */
2447         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2448                 emit_sig_cookie (cfg, call, cinfo);
2449
2450         switch (cinfo->ret.storage) {
2451         case ArgValuetypeInReg:
2452                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2453                         /*
2454                          * Tell the JIT to use a more efficient calling convention: call using
2455                          * OP_CALL, compute the result location after the call, and save the
2456                          * result there.
2457                          */
2458                         call->vret_in_reg = TRUE;
2459                         /*
2460                          * Nullify the instruction computing the vret addr to enable
2461                          * future optimizations.
2462                          */
2463                         if (call->vret_var)
2464                                 NULLIFY_INS (call->vret_var);
2465                 } else {
2466                         if (call->tail_call)
2467                                 NOT_IMPLEMENTED;
2468                         /*
2469                          * The valuetype is in RAX:RDX after the call, need to be copied to
2470                          * the stack. Push the address here, so the call instruction can
2471                          * access it.
2472                          */
2473                         if (!cfg->arch.vret_addr_loc) {
2474                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2475                                 /* Prevent it from being register allocated or optimized away */
2476                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2477                         }
2478
2479                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2480                 }
2481                 break;
2482         case ArgValuetypeAddrInIReg: {
2483                 MonoInst *vtarg;
2484                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2485                 vtarg->sreg1 = call->vret_var->dreg;
2486                 vtarg->dreg = mono_alloc_preg (cfg);
2487                 MONO_ADD_INS (cfg->cbb, vtarg);
2488
2489                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2490                 break;
2491         }
2492         default:
2493                 break;
2494         }
2495
2496         if (cfg->method->save_lmf) {
2497                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2498                 MONO_ADD_INS (cfg->cbb, arg);
2499         }
2500
2501         call->stack_usage = cinfo->stack_usage;
2502 }
2503
2504 void
2505 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2506 {
2507         MonoInst *arg;
2508         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2509         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2510         int size = ins->backend.size;
2511
2512         switch (ainfo->storage) {
2513         case ArgValuetypeInReg: {
2514                 MonoInst *load;
2515                 int part;
2516
2517                 for (part = 0; part < 2; ++part) {
2518                         if (ainfo->pair_storage [part] == ArgNone)
2519                                 continue;
2520
2521                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2522                         load->inst_basereg = src->dreg;
2523                         load->inst_offset = part * sizeof(mgreg_t);
2524
2525                         switch (ainfo->pair_storage [part]) {
2526                         case ArgInIReg:
2527                                 load->dreg = mono_alloc_ireg (cfg);
2528                                 break;
2529                         case ArgInDoubleSSEReg:
2530                         case ArgInFloatSSEReg:
2531                                 load->dreg = mono_alloc_freg (cfg);
2532                                 break;
2533                         default:
2534                                 g_assert_not_reached ();
2535                         }
2536                         MONO_ADD_INS (cfg->cbb, load);
2537
2538                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2539                 }
2540                 break;
2541         }
2542         case ArgValuetypeAddrInIReg: {
2543                 MonoInst *vtaddr, *load;
2544                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2545
2546                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2547                 cfg->has_indirection = TRUE;
2548                 load->inst_p0 = vtaddr;
2549                 vtaddr->flags |= MONO_INST_INDIRECT;
2550                 load->type = STACK_MP;
2551                 load->klass = vtaddr->klass;
2552                 load->dreg = mono_alloc_ireg (cfg);
2553                 MONO_ADD_INS (cfg->cbb, load);
2554                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2555
2556                 if (ainfo->pair_storage [0] == ArgInIReg) {
2557                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2558                         arg->dreg = mono_alloc_ireg (cfg);
2559                         arg->sreg1 = load->dreg;
2560                         arg->inst_imm = 0;
2561                         MONO_ADD_INS (cfg->cbb, arg);
2562                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2563                 } else {
2564                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2565                 }
2566                 break;
2567         }
2568         case ArgGSharedVtInReg:
2569                 /* Pass by addr */
2570                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2571                 break;
2572         case ArgGSharedVtOnStack:
2573                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2574                 break;
2575         default:
2576                 if (size == 8) {
2577                         int dreg = mono_alloc_ireg (cfg);
2578
2579                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2580                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2581                 } else if (size <= 40) {
2582                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2583                 } else {
2584                         // FIXME: Code growth
2585                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2586                 }
2587
2588                 if (cfg->compute_gc_maps) {
2589                         MonoInst *def;
2590                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2591                 }
2592         }
2593 }
2594
2595 void
2596 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2597 {
2598         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2599
2600         if (ret->type == MONO_TYPE_R4) {
2601                 if (COMPILE_LLVM (cfg))
2602                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2603                 else
2604                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2605                 return;
2606         } else if (ret->type == MONO_TYPE_R8) {
2607                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2608                 return;
2609         }
2610
2611         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2612 }
2613
2614 #endif /* DISABLE_JIT */
2615
2616 #define EMIT_COND_BRANCH(ins,cond,sign) \
2617         if (ins->inst_true_bb->native_offset) { \
2618                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2619         } else { \
2620                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2621                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2622             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2623                         x86_branch8 (code, cond, 0, sign); \
2624                 else \
2625                         x86_branch32 (code, cond, 0, sign); \
2626 }
2627
2628 typedef struct {
2629         MonoMethodSignature *sig;
2630         CallInfo *cinfo;
2631 } ArchDynCallInfo;
2632
2633 static gboolean
2634 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2635 {
2636         int i;
2637
2638 #ifdef HOST_WIN32
2639         return FALSE;
2640 #endif
2641
2642         switch (cinfo->ret.storage) {
2643         case ArgNone:
2644         case ArgInIReg:
2645         case ArgInFloatSSEReg:
2646         case ArgInDoubleSSEReg:
2647                 break;
2648         case ArgValuetypeInReg: {
2649                 ArgInfo *ainfo = &cinfo->ret;
2650
2651                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2652                         return FALSE;
2653                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2654                         return FALSE;
2655                 break;
2656         }
2657         default:
2658                 return FALSE;
2659         }
2660
2661         for (i = 0; i < cinfo->nargs; ++i) {
2662                 ArgInfo *ainfo = &cinfo->args [i];
2663                 switch (ainfo->storage) {
2664                 case ArgInIReg:
2665                 case ArgInFloatSSEReg:
2666                 case ArgInDoubleSSEReg:
2667                         break;
2668                 case ArgValuetypeInReg:
2669                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2670                                 return FALSE;
2671                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2672                                 return FALSE;
2673                         break;
2674                 default:
2675                         return FALSE;
2676                 }
2677         }
2678
2679         return TRUE;
2680 }
2681
2682 /*
2683  * mono_arch_dyn_call_prepare:
2684  *
2685  *   Return a pointer to an arch-specific structure which contains information
2686  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2687  * supported for SIG.
2688  * This function is equivalent to ffi_prep_cif in libffi.
2689  */
2690 MonoDynCallInfo*
2691 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2692 {
2693         ArchDynCallInfo *info;
2694         CallInfo *cinfo;
2695
2696         cinfo = get_call_info (NULL, sig);
2697
2698         if (!dyn_call_supported (sig, cinfo)) {
2699                 g_free (cinfo);
2700                 return NULL;
2701         }
2702
2703         info = g_new0 (ArchDynCallInfo, 1);
2704         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2705         info->sig = sig;
2706         info->cinfo = cinfo;
2707
2708         return (MonoDynCallInfo*)info;
2709 }
2710
2711 /*
2712  * mono_arch_dyn_call_free:
2713  *
2714  *   Free a MonoDynCallInfo structure.
2715  */
2716 void
2717 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2718 {
2719         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2720
2721         g_free (ainfo->cinfo);
2722         g_free (ainfo);
2723 }
2724
2725 #if !defined(__native_client__)
2726 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2727 #define GREG_TO_PTR(greg) (gpointer)(greg)
2728 #else
2729 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2730 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2731 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2732 #endif
2733
2734 /*
2735  * mono_arch_get_start_dyn_call:
2736  *
2737  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2738  * store the result into BUF.
2739  * ARGS should be an array of pointers pointing to the arguments.
2740  * RET should point to a memory buffer large enought to hold the result of the
2741  * call.
2742  * This function should be as fast as possible, any work which does not depend
2743  * on the actual values of the arguments should be done in
2744  * mono_arch_dyn_call_prepare ().
2745  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2746  * libffi.
2747  */
2748 void
2749 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2750 {
2751         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2752         DynCallArgs *p = (DynCallArgs*)buf;
2753         int arg_index, greg, freg, i, pindex;
2754         MonoMethodSignature *sig = dinfo->sig;
2755         int buffer_offset = 0;
2756
2757         g_assert (buf_len >= sizeof (DynCallArgs));
2758
2759         p->res = 0;
2760         p->ret = ret;
2761
2762         arg_index = 0;
2763         greg = 0;
2764         freg = 0;
2765         pindex = 0;
2766
2767         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2768                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2769                 if (!sig->hasthis)
2770                         pindex = 1;
2771         }
2772
2773         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2774                 p->regs [greg ++] = PTR_TO_GREG(ret);
2775
2776         for (i = pindex; i < sig->param_count; i++) {
2777                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2778                 gpointer *arg = args [arg_index ++];
2779
2780                 if (t->byref) {
2781                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2782                         continue;
2783                 }
2784
2785                 switch (t->type) {
2786                 case MONO_TYPE_STRING:
2787                 case MONO_TYPE_CLASS:
2788                 case MONO_TYPE_ARRAY:
2789                 case MONO_TYPE_SZARRAY:
2790                 case MONO_TYPE_OBJECT:
2791                 case MONO_TYPE_PTR:
2792                 case MONO_TYPE_I:
2793                 case MONO_TYPE_U:
2794 #if !defined(__mono_ilp32__)
2795                 case MONO_TYPE_I8:
2796                 case MONO_TYPE_U8:
2797 #endif
2798                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2799                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2800                         break;
2801 #if defined(__mono_ilp32__)
2802                 case MONO_TYPE_I8:
2803                 case MONO_TYPE_U8:
2804                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2805                         p->regs [greg ++] = *(guint64*)(arg);
2806                         break;
2807 #endif
2808                 case MONO_TYPE_U1:
2809                         p->regs [greg ++] = *(guint8*)(arg);
2810                         break;
2811                 case MONO_TYPE_I1:
2812                         p->regs [greg ++] = *(gint8*)(arg);
2813                         break;
2814                 case MONO_TYPE_I2:
2815                         p->regs [greg ++] = *(gint16*)(arg);
2816                         break;
2817                 case MONO_TYPE_U2:
2818                         p->regs [greg ++] = *(guint16*)(arg);
2819                         break;
2820                 case MONO_TYPE_I4:
2821                         p->regs [greg ++] = *(gint32*)(arg);
2822                         break;
2823                 case MONO_TYPE_U4:
2824                         p->regs [greg ++] = *(guint32*)(arg);
2825                         break;
2826                 case MONO_TYPE_R4: {
2827                         double d;
2828
2829                         *(float*)&d = *(float*)(arg);
2830                         p->has_fp = 1;
2831                         p->fregs [freg ++] = d;
2832                         break;
2833                 }
2834                 case MONO_TYPE_R8:
2835                         p->has_fp = 1;
2836                         p->fregs [freg ++] = *(double*)(arg);
2837                         break;
2838                 case MONO_TYPE_GENERICINST:
2839                     if (MONO_TYPE_IS_REFERENCE (t)) {
2840                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2841                                 break;
2842                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2843                                         MonoClass *klass = mono_class_from_mono_type (t);
2844                                         guint8 *nullable_buf;
2845                                         int size;
2846
2847                                         size = mono_class_value_size (klass, NULL);
2848                                         nullable_buf = p->buffer + buffer_offset;
2849                                         buffer_offset += size;
2850                                         g_assert (buffer_offset <= 256);
2851
2852                                         /* The argument pointed to by arg is either a boxed vtype or null */
2853                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2854
2855                                         arg = (gpointer*)nullable_buf;
2856                                         /* Fall though */
2857
2858                         } else {
2859                                 /* Fall through */
2860                         }
2861                 case MONO_TYPE_VALUETYPE: {
2862                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2863
2864                         g_assert (ainfo->storage == ArgValuetypeInReg);
2865                         if (ainfo->pair_storage [0] != ArgNone) {
2866                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2867                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2868                         }
2869                         if (ainfo->pair_storage [1] != ArgNone) {
2870                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2871                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2872                         }
2873                         break;
2874                 }
2875                 default:
2876                         g_assert_not_reached ();
2877                 }
2878         }
2879
2880         g_assert (greg <= PARAM_REGS);
2881 }
2882
2883 /*
2884  * mono_arch_finish_dyn_call:
2885  *
2886  *   Store the result of a dyn call into the return value buffer passed to
2887  * start_dyn_call ().
2888  * This function should be as fast as possible, any work which does not depend
2889  * on the actual values of the arguments should be done in
2890  * mono_arch_dyn_call_prepare ().
2891  */
2892 void
2893 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2894 {
2895         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2896         MonoMethodSignature *sig = dinfo->sig;
2897         DynCallArgs *dargs = (DynCallArgs*)buf;
2898         guint8 *ret = dargs->ret;
2899         mgreg_t res = dargs->res;
2900         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2901
2902         switch (sig_ret->type) {
2903         case MONO_TYPE_VOID:
2904                 *(gpointer*)ret = NULL;
2905                 break;
2906         case MONO_TYPE_STRING:
2907         case MONO_TYPE_CLASS:
2908         case MONO_TYPE_ARRAY:
2909         case MONO_TYPE_SZARRAY:
2910         case MONO_TYPE_OBJECT:
2911         case MONO_TYPE_I:
2912         case MONO_TYPE_U:
2913         case MONO_TYPE_PTR:
2914                 *(gpointer*)ret = GREG_TO_PTR(res);
2915                 break;
2916         case MONO_TYPE_I1:
2917                 *(gint8*)ret = res;
2918                 break;
2919         case MONO_TYPE_U1:
2920                 *(guint8*)ret = res;
2921                 break;
2922         case MONO_TYPE_I2:
2923                 *(gint16*)ret = res;
2924                 break;
2925         case MONO_TYPE_U2:
2926                 *(guint16*)ret = res;
2927                 break;
2928         case MONO_TYPE_I4:
2929                 *(gint32*)ret = res;
2930                 break;
2931         case MONO_TYPE_U4:
2932                 *(guint32*)ret = res;
2933                 break;
2934         case MONO_TYPE_I8:
2935                 *(gint64*)ret = res;
2936                 break;
2937         case MONO_TYPE_U8:
2938                 *(guint64*)ret = res;
2939                 break;
2940         case MONO_TYPE_R4:
2941                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2942                 break;
2943         case MONO_TYPE_R8:
2944                 *(double*)ret = dargs->fregs [0];
2945                 break;
2946         case MONO_TYPE_GENERICINST:
2947                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2948                         *(gpointer*)ret = GREG_TO_PTR(res);
2949                         break;
2950                 } else {
2951                         /* Fall through */
2952                 }
2953         case MONO_TYPE_VALUETYPE:
2954                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2955                         /* Nothing to do */
2956                 } else {
2957                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2958
2959                         g_assert (ainfo->storage == ArgValuetypeInReg);
2960
2961                         if (ainfo->pair_storage [0] != ArgNone) {
2962                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2963                                 ((mgreg_t*)ret)[0] = res;
2964                         }
2965
2966                         g_assert (ainfo->pair_storage [1] == ArgNone);
2967                 }
2968                 break;
2969         default:
2970                 g_assert_not_reached ();
2971         }
2972 }
2973
2974 /* emit an exception if condition is fail */
2975 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2976         do {                                                        \
2977                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2978                 if (tins == NULL) {                                                                             \
2979                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2980                                         MONO_PATCH_INFO_EXC, exc_name);  \
2981                         x86_branch32 (code, cond, 0, signed);               \
2982                 } else {        \
2983                         EMIT_COND_BRANCH (tins, cond, signed);  \
2984                 }                       \
2985         } while (0);
2986
2987 #define EMIT_FPCOMPARE(code) do { \
2988         amd64_fcompp (code); \
2989         amd64_fnstsw (code); \
2990 } while (0);
2991
2992 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2993     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2994         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2995         amd64_ ##op (code); \
2996         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2997         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2998 } while (0);
2999
3000 static guint8*
3001 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3002 {
3003         gboolean no_patch = FALSE;
3004
3005         /*
3006          * FIXME: Add support for thunks
3007          */
3008         {
3009                 gboolean near_call = FALSE;
3010
3011                 /*
3012                  * Indirect calls are expensive so try to make a near call if possible.
3013                  * The caller memory is allocated by the code manager so it is
3014                  * guaranteed to be at a 32 bit offset.
3015                  */
3016
3017                 if (patch_type != MONO_PATCH_INFO_ABS) {
3018                         /* The target is in memory allocated using the code manager */
3019                         near_call = TRUE;
3020
3021                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3022                                 if (((MonoMethod*)data)->klass->image->aot_module)
3023                                         /* The callee might be an AOT method */
3024                                         near_call = FALSE;
3025                                 if (((MonoMethod*)data)->dynamic)
3026                                         /* The target is in malloc-ed memory */
3027                                         near_call = FALSE;
3028                         }
3029
3030                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3031                                 /*
3032                                  * The call might go directly to a native function without
3033                                  * the wrapper.
3034                                  */
3035                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3036                                 if (mi) {
3037                                         gconstpointer target = mono_icall_get_wrapper (mi);
3038                                         if ((((guint64)target) >> 32) != 0)
3039                                                 near_call = FALSE;
3040                                 }
3041                         }
3042                 }
3043                 else {
3044                         MonoJumpInfo *jinfo = NULL;
3045
3046                         if (cfg->abs_patches)
3047                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3048                         if (jinfo) {
3049                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3050                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3051                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3052                                                 near_call = TRUE;
3053                                         no_patch = TRUE;
3054                                 } else {
3055                                         /*
3056                                          * This is not really an optimization, but required because the
3057                                          * generic class init trampolines use R11 to pass the vtable.
3058                                          */
3059                                         near_call = TRUE;
3060                                 }
3061                         } else {
3062                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3063                                 if (info) {
3064                                         if (info->func == info->wrapper) {
3065                                                 /* No wrapper */
3066                                                 if ((((guint64)info->func) >> 32) == 0)
3067                                                         near_call = TRUE;
3068                                         }
3069                                         else {
3070                                                 /* See the comment in mono_codegen () */
3071                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3072                                                         near_call = TRUE;
3073                                         }
3074                                 }
3075                                 else if ((((guint64)data) >> 32) == 0) {
3076                                         near_call = TRUE;
3077                                         no_patch = TRUE;
3078                                 }
3079                         }
3080                 }
3081
3082                 if (cfg->method->dynamic)
3083                         /* These methods are allocated using malloc */
3084                         near_call = FALSE;
3085
3086 #ifdef MONO_ARCH_NOMAP32BIT
3087                 near_call = FALSE;
3088 #endif
3089 #if defined(__native_client__)
3090                 /* Always use near_call == TRUE for Native Client */
3091                 near_call = TRUE;
3092 #endif
3093                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3094                 if (optimize_for_xen)
3095                         near_call = FALSE;
3096
3097                 if (cfg->compile_aot) {
3098                         near_call = TRUE;
3099                         no_patch = TRUE;
3100                 }
3101
3102                 if (near_call) {
3103                         /*
3104                          * Align the call displacement to an address divisible by 4 so it does
3105                          * not span cache lines. This is required for code patching to work on SMP
3106                          * systems.
3107                          */
3108                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3109                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3110                                 amd64_padding (code, pad_size);
3111                         }
3112                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3113                         amd64_call_code (code, 0);
3114                 }
3115                 else {
3116                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3117                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3118                         amd64_call_reg (code, GP_SCRATCH_REG);
3119                 }
3120         }
3121
3122         return code;
3123 }
3124
3125 static inline guint8*
3126 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3127 {
3128 #ifdef TARGET_WIN32
3129         if (win64_adjust_stack)
3130                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3131 #endif
3132         code = emit_call_body (cfg, code, patch_type, data);
3133 #ifdef TARGET_WIN32
3134         if (win64_adjust_stack)
3135                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3136 #endif
3137
3138         return code;
3139 }
3140
3141 static inline int
3142 store_membase_imm_to_store_membase_reg (int opcode)
3143 {
3144         switch (opcode) {
3145         case OP_STORE_MEMBASE_IMM:
3146                 return OP_STORE_MEMBASE_REG;
3147         case OP_STOREI4_MEMBASE_IMM:
3148                 return OP_STOREI4_MEMBASE_REG;
3149         case OP_STOREI8_MEMBASE_IMM:
3150                 return OP_STOREI8_MEMBASE_REG;
3151         }
3152
3153         return -1;
3154 }
3155
3156 #ifndef DISABLE_JIT
3157
3158 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3159
3160 /*
3161  * mono_arch_peephole_pass_1:
3162  *
3163  *   Perform peephole opts which should/can be performed before local regalloc
3164  */
3165 void
3166 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3167 {
3168         MonoInst *ins, *n;
3169
3170         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3171                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3172
3173                 switch (ins->opcode) {
3174                 case OP_ADD_IMM:
3175                 case OP_IADD_IMM:
3176                 case OP_LADD_IMM:
3177                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3178                                 /*
3179                                  * X86_LEA is like ADD, but doesn't have the
3180                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3181                                  * its operand to 64 bit.
3182                                  */
3183                                 ins->opcode = OP_X86_LEA_MEMBASE;
3184                                 ins->inst_basereg = ins->sreg1;
3185                         }
3186                         break;
3187                 case OP_LXOR:
3188                 case OP_IXOR:
3189                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3190                                 MonoInst *ins2;
3191
3192                                 /*
3193                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3194                                  * the latter has length 2-3 instead of 6 (reverse constant
3195                                  * propagation). These instruction sequences are very common
3196                                  * in the initlocals bblock.
3197                                  */
3198                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3199                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3200                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3201                                                 ins2->sreg1 = ins->dreg;
3202                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3203                                                 /* Continue */
3204                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3205                                                 NULLIFY_INS (ins2);
3206                                                 /* Continue */
3207                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3208                                                 /* Continue */
3209                                         } else {
3210                                                 break;
3211                                         }
3212                                 }
3213                         }
3214                         break;
3215                 case OP_COMPARE_IMM:
3216                 case OP_LCOMPARE_IMM:
3217                         /* OP_COMPARE_IMM (reg, 0)
3218                          * -->
3219                          * OP_AMD64_TEST_NULL (reg)
3220                          */
3221                         if (!ins->inst_imm)
3222                                 ins->opcode = OP_AMD64_TEST_NULL;
3223                         break;
3224                 case OP_ICOMPARE_IMM:
3225                         if (!ins->inst_imm)
3226                                 ins->opcode = OP_X86_TEST_NULL;
3227                         break;
3228                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3229                         /*
3230                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3231                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3232                          * -->
3233                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3234                          * OP_COMPARE_IMM reg, imm
3235                          *
3236                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3237                          */
3238                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3239                             ins->inst_basereg == last_ins->inst_destbasereg &&
3240                             ins->inst_offset == last_ins->inst_offset) {
3241                                         ins->opcode = OP_ICOMPARE_IMM;
3242                                         ins->sreg1 = last_ins->sreg1;
3243
3244                                         /* check if we can remove cmp reg,0 with test null */
3245                                         if (!ins->inst_imm)
3246                                                 ins->opcode = OP_X86_TEST_NULL;
3247                                 }
3248
3249                         break;
3250                 }
3251
3252                 mono_peephole_ins (bb, ins);
3253         }
3254 }
3255
3256 void
3257 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3258 {
3259         MonoInst *ins, *n;
3260
3261         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3262                 switch (ins->opcode) {
3263                 case OP_ICONST:
3264                 case OP_I8CONST: {
3265                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3266                         /* reg = 0 -> XOR (reg, reg) */
3267                         /* XOR sets cflags on x86, so we cant do it always */
3268                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3269                                 ins->opcode = OP_LXOR;
3270                                 ins->sreg1 = ins->dreg;
3271                                 ins->sreg2 = ins->dreg;
3272                                 /* Fall through */
3273                         } else {
3274                                 break;
3275                         }
3276                 }
3277                 case OP_LXOR:
3278                         /*
3279                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3280                          * 0 result into 64 bits.
3281                          */
3282                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3283                                 ins->opcode = OP_IXOR;
3284                         }
3285                         /* Fall through */
3286                 case OP_IXOR:
3287                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3288                                 MonoInst *ins2;
3289
3290                                 /*
3291                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3292                                  * the latter has length 2-3 instead of 6 (reverse constant
3293                                  * propagation). These instruction sequences are very common
3294                                  * in the initlocals bblock.
3295                                  */
3296                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3297                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3298                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3299                                                 ins2->sreg1 = ins->dreg;
3300                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3301                                                 /* Continue */
3302                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3303                                                 NULLIFY_INS (ins2);
3304                                                 /* Continue */
3305                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3306                                                 /* Continue */
3307                                         } else {
3308                                                 break;
3309                                         }
3310                                 }
3311                         }
3312                         break;
3313                 case OP_IADD_IMM:
3314                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3315                                 ins->opcode = OP_X86_INC_REG;
3316                         break;
3317                 case OP_ISUB_IMM:
3318                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3319                                 ins->opcode = OP_X86_DEC_REG;
3320                         break;
3321                 }
3322
3323                 mono_peephole_ins (bb, ins);
3324         }
3325 }
3326
3327 #define NEW_INS(cfg,ins,dest,op) do {   \
3328                 MONO_INST_NEW ((cfg), (dest), (op)); \
3329         (dest)->cil_code = (ins)->cil_code; \
3330         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3331         } while (0)
3332
3333 /*
3334  * mono_arch_lowering_pass:
3335  *
3336  *  Converts complex opcodes into simpler ones so that each IR instruction
3337  * corresponds to one machine instruction.
3338  */
3339 void
3340 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3341 {
3342         MonoInst *ins, *n, *temp;
3343
3344         /*
3345          * FIXME: Need to add more instructions, but the current machine
3346          * description can't model some parts of the composite instructions like
3347          * cdq.
3348          */
3349         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3350                 switch (ins->opcode) {
3351                 case OP_DIV_IMM:
3352                 case OP_REM_IMM:
3353                 case OP_IDIV_IMM:
3354                 case OP_IDIV_UN_IMM:
3355                 case OP_IREM_UN_IMM:
3356                 case OP_LREM_IMM:
3357                 case OP_IREM_IMM:
3358                         mono_decompose_op_imm (cfg, bb, ins);
3359                         break;
3360                 case OP_COMPARE_IMM:
3361                 case OP_LCOMPARE_IMM:
3362                         if (!amd64_use_imm32 (ins->inst_imm)) {
3363                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3364                                 temp->inst_c0 = ins->inst_imm;
3365                                 temp->dreg = mono_alloc_ireg (cfg);
3366                                 ins->opcode = OP_COMPARE;
3367                                 ins->sreg2 = temp->dreg;
3368                         }
3369                         break;
3370 #ifndef __mono_ilp32__
3371                 case OP_LOAD_MEMBASE:
3372 #endif
3373                 case OP_LOADI8_MEMBASE:
3374 #ifndef __native_client_codegen__
3375                 /*  Don't generate memindex opcodes (to simplify */
3376                 /*  read sandboxing) */
3377                         if (!amd64_use_imm32 (ins->inst_offset)) {
3378                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3379                                 temp->inst_c0 = ins->inst_offset;
3380                                 temp->dreg = mono_alloc_ireg (cfg);
3381                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3382                                 ins->inst_indexreg = temp->dreg;
3383                         }
3384 #endif
3385                         break;
3386 #ifndef __mono_ilp32__
3387                 case OP_STORE_MEMBASE_IMM:
3388 #endif
3389                 case OP_STOREI8_MEMBASE_IMM:
3390                         if (!amd64_use_imm32 (ins->inst_imm)) {
3391                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3392                                 temp->inst_c0 = ins->inst_imm;
3393                                 temp->dreg = mono_alloc_ireg (cfg);
3394                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3395                                 ins->sreg1 = temp->dreg;
3396                         }
3397                         break;
3398 #ifdef MONO_ARCH_SIMD_INTRINSICS
3399                 case OP_EXPAND_I1: {
3400                                 int temp_reg1 = mono_alloc_ireg (cfg);
3401                                 int temp_reg2 = mono_alloc_ireg (cfg);
3402                                 int original_reg = ins->sreg1;
3403
3404                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3405                                 temp->sreg1 = original_reg;
3406                                 temp->dreg = temp_reg1;
3407
3408                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3409                                 temp->sreg1 = temp_reg1;
3410                                 temp->dreg = temp_reg2;
3411                                 temp->inst_imm = 8;
3412
3413                                 NEW_INS (cfg, ins, temp, OP_LOR);
3414                                 temp->sreg1 = temp->dreg = temp_reg2;
3415                                 temp->sreg2 = temp_reg1;
3416
3417                                 ins->opcode = OP_EXPAND_I2;
3418                                 ins->sreg1 = temp_reg2;
3419                         }
3420                         break;
3421 #endif
3422                 default:
3423                         break;
3424                 }
3425         }
3426
3427         bb->max_vreg = cfg->next_vreg;
3428 }
3429
3430 static const int
3431 branch_cc_table [] = {
3432         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3433         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3434         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3435 };
3436
3437 /* Maps CMP_... constants to X86_CC_... constants */
3438 static const int
3439 cc_table [] = {
3440         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3441         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3442 };
3443
3444 static const int
3445 cc_signed_table [] = {
3446         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3447         FALSE, FALSE, FALSE, FALSE
3448 };
3449
3450 /*#include "cprop.c"*/
3451
3452 static unsigned char*
3453 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3454 {
3455         if (size == 8)
3456                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3457         else
3458                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3459
3460         if (size == 1)
3461                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3462         else if (size == 2)
3463                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3464         return code;
3465 }
3466
3467 static unsigned char*
3468 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3469 {
3470         int sreg = tree->sreg1;
3471         int need_touch = FALSE;
3472
3473 #if defined(TARGET_WIN32)
3474         need_touch = TRUE;
3475 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3476         if (!tree->flags & MONO_INST_INIT)
3477                 need_touch = TRUE;
3478 #endif
3479
3480         if (need_touch) {
3481                 guint8* br[5];
3482
3483                 /*
3484                  * Under Windows:
3485                  * If requested stack size is larger than one page,
3486                  * perform stack-touch operation
3487                  */
3488                 /*
3489                  * Generate stack probe code.
3490                  * Under Windows, it is necessary to allocate one page at a time,
3491                  * "touching" stack after each successful sub-allocation. This is
3492                  * because of the way stack growth is implemented - there is a
3493                  * guard page before the lowest stack page that is currently commited.
3494                  * Stack normally grows sequentially so OS traps access to the
3495                  * guard page and commits more pages when needed.
3496                  */
3497                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3498                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3499
3500                 br[2] = code; /* loop */
3501                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3502                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3503                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3504                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3505                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3506                 amd64_patch (br[3], br[2]);
3507                 amd64_test_reg_reg (code, sreg, sreg);
3508                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3509                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3510
3511                 br[1] = code; x86_jump8 (code, 0);
3512
3513                 amd64_patch (br[0], code);
3514                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3515                 amd64_patch (br[1], code);
3516                 amd64_patch (br[4], code);
3517         }
3518         else
3519                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3520
3521         if (tree->flags & MONO_INST_INIT) {
3522                 int offset = 0;
3523                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3524                         amd64_push_reg (code, AMD64_RAX);
3525                         offset += 8;
3526                 }
3527                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3528                         amd64_push_reg (code, AMD64_RCX);
3529                         offset += 8;
3530                 }
3531                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3532                         amd64_push_reg (code, AMD64_RDI);
3533                         offset += 8;
3534                 }
3535
3536                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3537                 if (sreg != AMD64_RCX)
3538                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3539                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3540
3541                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3542                 if (cfg->param_area)
3543                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3544                 amd64_cld (code);
3545 #if defined(__default_codegen__)
3546                 amd64_prefix (code, X86_REP_PREFIX);
3547                 amd64_stosl (code);
3548 #elif defined(__native_client_codegen__)
3549                 /* NaCl stos pseudo-instruction */
3550                 amd64_codegen_pre(code);
3551                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3552                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3553                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3554                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3555                 amd64_prefix (code, X86_REP_PREFIX);
3556                 amd64_stosl (code);
3557                 amd64_codegen_post(code);
3558 #endif /* __native_client_codegen__ */
3559
3560                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3561                         amd64_pop_reg (code, AMD64_RDI);
3562                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3563                         amd64_pop_reg (code, AMD64_RCX);
3564                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3565                         amd64_pop_reg (code, AMD64_RAX);
3566         }
3567         return code;
3568 }
3569
3570 static guint8*
3571 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3572 {
3573         CallInfo *cinfo;
3574         guint32 quad;
3575
3576         /* Move return value to the target register */
3577         /* FIXME: do this in the local reg allocator */
3578         switch (ins->opcode) {
3579         case OP_CALL:
3580         case OP_CALL_REG:
3581         case OP_CALL_MEMBASE:
3582         case OP_LCALL:
3583         case OP_LCALL_REG:
3584         case OP_LCALL_MEMBASE:
3585                 g_assert (ins->dreg == AMD64_RAX);
3586                 break;
3587         case OP_FCALL:
3588         case OP_FCALL_REG:
3589         case OP_FCALL_MEMBASE: {
3590                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3591                 if (rtype->type == MONO_TYPE_R4) {
3592                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3593                 }
3594                 else {
3595                         if (ins->dreg != AMD64_XMM0)
3596                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3597                 }
3598                 break;
3599         }
3600         case OP_RCALL:
3601         case OP_RCALL_REG:
3602         case OP_RCALL_MEMBASE:
3603                 if (ins->dreg != AMD64_XMM0)
3604                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3605                 break;
3606         case OP_VCALL:
3607         case OP_VCALL_REG:
3608         case OP_VCALL_MEMBASE:
3609         case OP_VCALL2:
3610         case OP_VCALL2_REG:
3611         case OP_VCALL2_MEMBASE:
3612                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3613                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3614                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3615
3616                         /* Load the destination address */
3617                         g_assert (loc->opcode == OP_REGOFFSET);
3618                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3619
3620                         for (quad = 0; quad < 2; quad ++) {
3621                                 switch (cinfo->ret.pair_storage [quad]) {
3622                                 case ArgInIReg:
3623                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3624                                         break;
3625                                 case ArgInFloatSSEReg:
3626                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3627                                         break;
3628                                 case ArgInDoubleSSEReg:
3629                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3630                                         break;
3631                                 case ArgNone:
3632                                         break;
3633                                 default:
3634                                         NOT_IMPLEMENTED;
3635                                 }
3636                         }
3637                 }
3638                 break;
3639         }
3640
3641         return code;
3642 }
3643
3644 #endif /* DISABLE_JIT */
3645
3646 #ifdef __APPLE__
3647 static int tls_gs_offset;
3648 #endif
3649
3650 gboolean
3651 mono_amd64_have_tls_get (void)
3652 {
3653 #ifdef TARGET_MACH
3654         static gboolean have_tls_get = FALSE;
3655         static gboolean inited = FALSE;
3656
3657         if (inited)
3658                 return have_tls_get;
3659
3660 #if MONO_HAVE_FAST_TLS
3661         guint8 *ins = (guint8*)pthread_getspecific;
3662
3663         /*
3664          * We're looking for these two instructions:
3665          *
3666          * mov    %gs:[offset](,%rdi,8),%rax
3667          * retq
3668          */
3669         have_tls_get = ins [0] == 0x65 &&
3670                        ins [1] == 0x48 &&
3671                        ins [2] == 0x8b &&
3672                        ins [3] == 0x04 &&
3673                        ins [4] == 0xfd &&
3674                        ins [6] == 0x00 &&
3675                        ins [7] == 0x00 &&
3676                        ins [8] == 0x00 &&
3677                        ins [9] == 0xc3;
3678
3679         tls_gs_offset = ins[5];
3680
3681         /*
3682          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3683          * For that version we're looking for these instructions:
3684          *
3685          * pushq  %rbp
3686          * movq   %rsp, %rbp
3687          * mov    %gs:[offset](,%rdi,8),%rax
3688          * popq   %rbp
3689          * retq
3690          */
3691         if (!have_tls_get) {
3692                 have_tls_get = ins [0] == 0x55 &&
3693                                ins [1] == 0x48 &&
3694                                ins [2] == 0x89 &&
3695                                ins [3] == 0xe5 &&
3696                                ins [4] == 0x65 &&
3697                                ins [5] == 0x48 &&
3698                                ins [6] == 0x8b &&
3699                                ins [7] == 0x04 &&
3700                                ins [8] == 0xfd &&
3701                                ins [10] == 0x00 &&
3702                                ins [11] == 0x00 &&
3703                                ins [12] == 0x00 &&
3704                                ins [13] == 0x5d &&
3705                                ins [14] == 0xc3;
3706
3707                 tls_gs_offset = ins[9];
3708         }
3709 #endif
3710
3711         inited = TRUE;
3712
3713         return have_tls_get;
3714 #elif defined(TARGET_ANDROID)
3715         return FALSE;
3716 #else
3717         return TRUE;
3718 #endif
3719 }
3720
3721 int
3722 mono_amd64_get_tls_gs_offset (void)
3723 {
3724 #ifdef TARGET_OSX
3725         return tls_gs_offset;
3726 #else
3727         g_assert_not_reached ();
3728         return -1;
3729 #endif
3730 }
3731
3732 /*
3733  * mono_amd64_emit_tls_get:
3734  * @code: buffer to store code to
3735  * @dreg: hard register where to place the result
3736  * @tls_offset: offset info
3737  *
3738  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3739  * the dreg register the item in the thread local storage identified
3740  * by tls_offset.
3741  *
3742  * Returns: a pointer to the end of the stored code
3743  */
3744 guint8*
3745 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3746 {
3747 #ifdef TARGET_WIN32
3748         if (tls_offset < 64) {
3749                 x86_prefix (code, X86_GS_PREFIX);
3750                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3751         } else {
3752                 guint8 *buf [16];
3753
3754                 g_assert (tls_offset < 0x440);
3755                 /* Load TEB->TlsExpansionSlots */
3756                 x86_prefix (code, X86_GS_PREFIX);
3757                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3758                 amd64_test_reg_reg (code, dreg, dreg);
3759                 buf [0] = code;
3760                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3761                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3762                 amd64_patch (buf [0], code);
3763         }
3764 #elif defined(__APPLE__)
3765         x86_prefix (code, X86_GS_PREFIX);
3766         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3767 #else
3768         if (optimize_for_xen) {
3769                 x86_prefix (code, X86_FS_PREFIX);
3770                 amd64_mov_reg_mem (code, dreg, 0, 8);
3771                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3772         } else {
3773                 x86_prefix (code, X86_FS_PREFIX);
3774                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3775         }
3776 #endif
3777         return code;
3778 }
3779
3780 static guint8*
3781 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3782 {
3783         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3784 #ifdef TARGET_OSX
3785         if (dreg != offset_reg)
3786                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3787         amd64_prefix (code, X86_GS_PREFIX);
3788         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3789 #elif defined(__linux__)
3790         int tmpreg = -1;
3791
3792         if (dreg == offset_reg) {
3793                 /* Use a temporary reg by saving it to the redzone */
3794                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3795                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3796                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3797                 offset_reg = tmpreg;
3798         }
3799         x86_prefix (code, X86_FS_PREFIX);
3800         amd64_mov_reg_mem (code, dreg, 0, 8);
3801         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3802         if (tmpreg != -1)
3803                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3804 #else
3805         g_assert_not_reached ();
3806 #endif
3807         return code;
3808 }
3809
3810 static guint8*
3811 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3812 {
3813 #ifdef TARGET_WIN32
3814         g_assert_not_reached ();
3815 #elif defined(__APPLE__)
3816         x86_prefix (code, X86_GS_PREFIX);
3817         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3818 #else
3819         g_assert (!optimize_for_xen);
3820         x86_prefix (code, X86_FS_PREFIX);
3821         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3822 #endif
3823         return code;
3824 }
3825
3826 static guint8*
3827 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3828 {
3829         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3830 #ifdef TARGET_WIN32
3831         g_assert_not_reached ();
3832 #elif defined(__APPLE__)
3833         x86_prefix (code, X86_GS_PREFIX);
3834         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3835 #else
3836         x86_prefix (code, X86_FS_PREFIX);
3837         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3838 #endif
3839         return code;
3840 }
3841
3842  /*
3843  * mono_arch_translate_tls_offset:
3844  *
3845  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3846  */
3847 int
3848 mono_arch_translate_tls_offset (int offset)
3849 {
3850 #ifdef __APPLE__
3851         return tls_gs_offset + (offset * 8);
3852 #else
3853         return offset;
3854 #endif
3855 }
3856
3857 /*
3858  * emit_setup_lmf:
3859  *
3860  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3861  */
3862 static guint8*
3863 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3864 {
3865         /*
3866          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3867          */
3868         /*
3869          * sp is saved right before calls but we need to save it here too so
3870          * async stack walks would work.
3871          */
3872         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3873         /* Save rbp */
3874         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3875         if (cfg->arch.omit_fp && cfa_offset != -1)
3876                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3877
3878         /* These can't contain refs */
3879         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3880         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3881         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3882         /* These are handled automatically by the stack marking code */
3883         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3884
3885         return code;
3886 }
3887
3888 /* benchmark and set based on cpu */
3889 #define LOOP_ALIGNMENT 8
3890 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3891
3892 #ifndef DISABLE_JIT
3893 void
3894 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3895 {
3896         MonoInst *ins;
3897         MonoCallInst *call;
3898         guint offset;
3899         guint8 *code = cfg->native_code + cfg->code_len;
3900         int max_len;
3901
3902         /* Fix max_offset estimate for each successor bb */
3903         if (cfg->opt & MONO_OPT_BRANCH) {
3904                 int current_offset = cfg->code_len;
3905                 MonoBasicBlock *current_bb;
3906                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3907                         current_bb->max_offset = current_offset;
3908                         current_offset += current_bb->max_length;
3909                 }
3910         }
3911
3912         if (cfg->opt & MONO_OPT_LOOP) {
3913                 int pad, align = LOOP_ALIGNMENT;
3914                 /* set alignment depending on cpu */
3915                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3916                         pad = align - pad;
3917                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3918                         amd64_padding (code, pad);
3919                         cfg->code_len += pad;
3920                         bb->native_offset = cfg->code_len;
3921                 }
3922         }
3923
3924 #if defined(__native_client_codegen__)
3925         /* For Native Client, all indirect call/jump targets must be */
3926         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3927         /* indirectly as well.                                       */
3928         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3929                                       (bb->flags & BB_EXCEPTION_HANDLER);
3930
3931         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3932                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3933                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3934                 cfg->code_len += pad;
3935                 bb->native_offset = cfg->code_len;
3936         }
3937 #endif  /*__native_client_codegen__*/
3938
3939         if (cfg->verbose_level > 2)
3940                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3941
3942         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3943                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3944                 g_assert (!cfg->compile_aot);
3945
3946                 cov->data [bb->dfn].cil_code = bb->cil_code;
3947                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3948                 /* this is not thread save, but good enough */
3949                 amd64_inc_membase (code, AMD64_R11, 0);
3950         }
3951
3952         offset = code - cfg->native_code;
3953
3954         mono_debug_open_block (cfg, bb, offset);
3955
3956     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3957                 x86_breakpoint (code);
3958
3959         MONO_BB_FOR_EACH_INS (bb, ins) {
3960                 offset = code - cfg->native_code;
3961
3962                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3963
3964 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3965
3966                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3967                         cfg->code_size *= 2;
3968                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3969                         code = cfg->native_code + offset;
3970                         cfg->stat_code_reallocs++;
3971                 }
3972
3973                 if (cfg->debug_info)
3974                         mono_debug_record_line_number (cfg, ins, offset);
3975
3976                 switch (ins->opcode) {
3977                 case OP_BIGMUL:
3978                         amd64_mul_reg (code, ins->sreg2, TRUE);
3979                         break;
3980                 case OP_BIGMUL_UN:
3981                         amd64_mul_reg (code, ins->sreg2, FALSE);
3982                         break;
3983                 case OP_X86_SETEQ_MEMBASE:
3984                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3985                         break;
3986                 case OP_STOREI1_MEMBASE_IMM:
3987                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3988                         break;
3989                 case OP_STOREI2_MEMBASE_IMM:
3990                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3991                         break;
3992                 case OP_STOREI4_MEMBASE_IMM:
3993                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3994                         break;
3995                 case OP_STOREI1_MEMBASE_REG:
3996                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3997                         break;
3998                 case OP_STOREI2_MEMBASE_REG:
3999                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4000                         break;
4001                 /* In AMD64 NaCl, pointers are 4 bytes, */
4002                 /*  so STORE_* != STOREI8_*. Likewise below. */
4003                 case OP_STORE_MEMBASE_REG:
4004                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4005                         break;
4006                 case OP_STOREI8_MEMBASE_REG:
4007                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4008                         break;
4009                 case OP_STOREI4_MEMBASE_REG:
4010                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4011                         break;
4012                 case OP_STORE_MEMBASE_IMM:
4013 #ifndef __native_client_codegen__
4014                         /* In NaCl, this could be a PCONST type, which could */
4015                         /* mean a pointer type was copied directly into the  */
4016                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4017                         /* the value would be 0x00000000FFFFFFFF which is    */
4018                         /* not proper for an imm32 unless you cast it.       */
4019                         g_assert (amd64_is_imm32 (ins->inst_imm));
4020 #endif
4021                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4022                         break;
4023                 case OP_STOREI8_MEMBASE_IMM:
4024                         g_assert (amd64_is_imm32 (ins->inst_imm));
4025                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4026                         break;
4027                 case OP_LOAD_MEM:
4028 #ifdef __mono_ilp32__
4029                         /* In ILP32, pointers are 4 bytes, so separate these */
4030                         /* cases, use literal 8 below where we really want 8 */
4031                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4032                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4033                         break;
4034 #endif
4035                 case OP_LOADI8_MEM:
4036                         // FIXME: Decompose this earlier
4037                         if (amd64_use_imm32 (ins->inst_imm))
4038                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4039                         else {
4040                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4041                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4042                         }
4043                         break;
4044                 case OP_LOADI4_MEM:
4045                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4046                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4047                         break;
4048                 case OP_LOADU4_MEM:
4049                         // FIXME: Decompose this earlier
4050                         if (amd64_use_imm32 (ins->inst_imm))
4051                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4052                         else {
4053                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4054                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4055                         }
4056                         break;
4057                 case OP_LOADU1_MEM:
4058                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4059                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4060                         break;
4061                 case OP_LOADU2_MEM:
4062                         /* For NaCl, pointers are 4 bytes, so separate these */
4063                         /* cases, use literal 8 below where we really want 8 */
4064                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4065                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4066                         break;
4067                 case OP_LOAD_MEMBASE:
4068                         g_assert (amd64_is_imm32 (ins->inst_offset));
4069                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4070                         break;
4071                 case OP_LOADI8_MEMBASE:
4072                         /* Use literal 8 instead of sizeof pointer or */
4073                         /* register, we really want 8 for this opcode */
4074                         g_assert (amd64_is_imm32 (ins->inst_offset));
4075                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4076                         break;
4077                 case OP_LOADI4_MEMBASE:
4078                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4079                         break;
4080                 case OP_LOADU4_MEMBASE:
4081                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4082                         break;
4083                 case OP_LOADU1_MEMBASE:
4084                         /* The cpu zero extends the result into 64 bits */
4085                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4086                         break;
4087                 case OP_LOADI1_MEMBASE:
4088                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4089                         break;
4090                 case OP_LOADU2_MEMBASE:
4091                         /* The cpu zero extends the result into 64 bits */
4092                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4093                         break;
4094                 case OP_LOADI2_MEMBASE:
4095                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4096                         break;
4097                 case OP_AMD64_LOADI8_MEMINDEX:
4098                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4099                         break;
4100                 case OP_LCONV_TO_I1:
4101                 case OP_ICONV_TO_I1:
4102                 case OP_SEXT_I1:
4103                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4104                         break;
4105                 case OP_LCONV_TO_I2:
4106                 case OP_ICONV_TO_I2:
4107                 case OP_SEXT_I2:
4108                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4109                         break;
4110                 case OP_LCONV_TO_U1:
4111                 case OP_ICONV_TO_U1:
4112                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4113                         break;
4114                 case OP_LCONV_TO_U2:
4115                 case OP_ICONV_TO_U2:
4116                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4117                         break;
4118                 case OP_ZEXT_I4:
4119                         /* Clean out the upper word */
4120                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4121                         break;
4122                 case OP_SEXT_I4:
4123                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4124                         break;
4125                 case OP_COMPARE:
4126                 case OP_LCOMPARE:
4127                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4128                         break;
4129                 case OP_COMPARE_IMM:
4130 #if defined(__mono_ilp32__)
4131                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4132                         g_assert (amd64_is_imm32 (ins->inst_imm));
4133                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4134                         break;
4135 #endif
4136                 case OP_LCOMPARE_IMM:
4137                         g_assert (amd64_is_imm32 (ins->inst_imm));
4138                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4139                         break;
4140                 case OP_X86_COMPARE_REG_MEMBASE:
4141                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4142                         break;
4143                 case OP_X86_TEST_NULL:
4144                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4145                         break;
4146                 case OP_AMD64_TEST_NULL:
4147                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4148                         break;
4149
4150                 case OP_X86_ADD_REG_MEMBASE:
4151                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4152                         break;
4153                 case OP_X86_SUB_REG_MEMBASE:
4154                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4155                         break;
4156                 case OP_X86_AND_REG_MEMBASE:
4157                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4158                         break;
4159                 case OP_X86_OR_REG_MEMBASE:
4160                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4161                         break;
4162                 case OP_X86_XOR_REG_MEMBASE:
4163                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4164                         break;
4165
4166                 case OP_X86_ADD_MEMBASE_IMM:
4167                         /* FIXME: Make a 64 version too */
4168                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4169                         break;
4170                 case OP_X86_SUB_MEMBASE_IMM:
4171                         g_assert (amd64_is_imm32 (ins->inst_imm));
4172                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4173                         break;
4174                 case OP_X86_AND_MEMBASE_IMM:
4175                         g_assert (amd64_is_imm32 (ins->inst_imm));
4176                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4177                         break;
4178                 case OP_X86_OR_MEMBASE_IMM:
4179                         g_assert (amd64_is_imm32 (ins->inst_imm));
4180                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4181                         break;
4182                 case OP_X86_XOR_MEMBASE_IMM:
4183                         g_assert (amd64_is_imm32 (ins->inst_imm));
4184                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4185                         break;
4186                 case OP_X86_ADD_MEMBASE_REG:
4187                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4188                         break;
4189                 case OP_X86_SUB_MEMBASE_REG:
4190                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4191                         break;
4192                 case OP_X86_AND_MEMBASE_REG:
4193                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4194                         break;
4195                 case OP_X86_OR_MEMBASE_REG:
4196                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4197                         break;
4198                 case OP_X86_XOR_MEMBASE_REG:
4199                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4200                         break;
4201                 case OP_X86_INC_MEMBASE:
4202                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4203                         break;
4204                 case OP_X86_INC_REG:
4205                         amd64_inc_reg_size (code, ins->dreg, 4);
4206                         break;
4207                 case OP_X86_DEC_MEMBASE:
4208                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4209                         break;
4210                 case OP_X86_DEC_REG:
4211                         amd64_dec_reg_size (code, ins->dreg, 4);
4212                         break;
4213                 case OP_X86_MUL_REG_MEMBASE:
4214                 case OP_X86_MUL_MEMBASE_REG:
4215                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4216                         break;
4217                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4218                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4219                         break;
4220                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4221                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4222                         break;
4223                 case OP_AMD64_COMPARE_MEMBASE_REG:
4224                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4225                         break;
4226                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4227                         g_assert (amd64_is_imm32 (ins->inst_imm));
4228                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4229                         break;
4230                 case OP_X86_COMPARE_MEMBASE8_IMM:
4231                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4232                         break;
4233                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4234                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4235                         break;
4236                 case OP_AMD64_COMPARE_REG_MEMBASE:
4237                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4238                         break;
4239
4240                 case OP_AMD64_ADD_REG_MEMBASE:
4241                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4242                         break;
4243                 case OP_AMD64_SUB_REG_MEMBASE:
4244                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4245                         break;
4246                 case OP_AMD64_AND_REG_MEMBASE:
4247                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4248                         break;
4249                 case OP_AMD64_OR_REG_MEMBASE:
4250                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4251                         break;
4252                 case OP_AMD64_XOR_REG_MEMBASE:
4253                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4254                         break;
4255
4256                 case OP_AMD64_ADD_MEMBASE_REG:
4257                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4258                         break;
4259                 case OP_AMD64_SUB_MEMBASE_REG:
4260                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4261                         break;
4262                 case OP_AMD64_AND_MEMBASE_REG:
4263                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4264                         break;
4265                 case OP_AMD64_OR_MEMBASE_REG:
4266                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4267                         break;
4268                 case OP_AMD64_XOR_MEMBASE_REG:
4269                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4270                         break;
4271
4272                 case OP_AMD64_ADD_MEMBASE_IMM:
4273                         g_assert (amd64_is_imm32 (ins->inst_imm));
4274                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4275                         break;
4276                 case OP_AMD64_SUB_MEMBASE_IMM:
4277                         g_assert (amd64_is_imm32 (ins->inst_imm));
4278                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4279                         break;
4280                 case OP_AMD64_AND_MEMBASE_IMM:
4281                         g_assert (amd64_is_imm32 (ins->inst_imm));
4282                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4283                         break;
4284                 case OP_AMD64_OR_MEMBASE_IMM:
4285                         g_assert (amd64_is_imm32 (ins->inst_imm));
4286                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4287                         break;
4288                 case OP_AMD64_XOR_MEMBASE_IMM:
4289                         g_assert (amd64_is_imm32 (ins->inst_imm));
4290                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4291                         break;
4292
4293                 case OP_BREAK:
4294                         amd64_breakpoint (code);
4295                         break;
4296                 case OP_RELAXED_NOP:
4297                         x86_prefix (code, X86_REP_PREFIX);
4298                         x86_nop (code);
4299                         break;
4300                 case OP_HARD_NOP:
4301                         x86_nop (code);
4302                         break;
4303                 case OP_NOP:
4304                 case OP_DUMMY_USE:
4305                 case OP_DUMMY_STORE:
4306                 case OP_DUMMY_ICONST:
4307                 case OP_DUMMY_R8CONST:
4308                 case OP_NOT_REACHED:
4309                 case OP_NOT_NULL:
4310                         break;
4311                 case OP_IL_SEQ_POINT:
4312                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4313                         break;
4314                 case OP_SEQ_POINT: {
4315                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4316                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4317                                 guint8 *label;
4318
4319                                 /* Load ss_tramp_var */
4320                                 /* This is equal to &ss_trampoline */
4321                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4322                                 /* Load the trampoline address */
4323                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4324                                 /* Call it if it is non-null */
4325                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4326                                 label = code;
4327                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4328                                 amd64_call_reg (code, AMD64_R11);
4329                                 amd64_patch (label, code);
4330                         }
4331
4332                         /*
4333                          * This is the address which is saved in seq points,
4334                          */
4335                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4336
4337                         if (cfg->compile_aot) {
4338                                 guint32 offset = code - cfg->native_code;
4339                                 guint32 val;
4340                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4341                                 guint8 *label;
4342
4343                                 /* Load info var */
4344                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4345                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4346                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4347                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4348                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4349                                 label = code;
4350                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4351                                 /* Call the trampoline */
4352                                 amd64_call_reg (code, AMD64_R11);
4353                                 amd64_patch (label, code);
4354                         } else {
4355                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4356                                 guint8 *label;
4357
4358                                 /*
4359                                  * Emit a test+branch against a constant, the constant will be overwritten
4360                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4361                                  */
4362                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4363                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4364                                 label = code;
4365                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4366
4367                                 g_assert (var);
4368                                 g_assert (var->opcode == OP_REGOFFSET);
4369                                 /* Load bp_tramp_var */
4370                                 /* This is equal to &bp_trampoline */
4371                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4372                                 /* Call the trampoline */
4373                                 amd64_call_membase (code, AMD64_R11, 0);
4374                                 amd64_patch (label, code);
4375                         }
4376                         /*
4377                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4378                          * to another IL offset.
4379                          */
4380                         x86_nop (code);
4381                         break;
4382                 }
4383                 case OP_ADDCC:
4384                 case OP_LADDCC:
4385                 case OP_LADD:
4386                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4387                         break;
4388                 case OP_ADC:
4389                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4390                         break;
4391                 case OP_ADD_IMM:
4392                 case OP_LADD_IMM:
4393                         g_assert (amd64_is_imm32 (ins->inst_imm));
4394                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4395                         break;
4396                 case OP_ADC_IMM:
4397                         g_assert (amd64_is_imm32 (ins->inst_imm));
4398                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4399                         break;
4400                 case OP_SUBCC:
4401                 case OP_LSUBCC:
4402                 case OP_LSUB:
4403                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4404                         break;
4405                 case OP_SBB:
4406                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4407                         break;
4408                 case OP_SUB_IMM:
4409                 case OP_LSUB_IMM:
4410                         g_assert (amd64_is_imm32 (ins->inst_imm));
4411                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4412                         break;
4413                 case OP_SBB_IMM:
4414                         g_assert (amd64_is_imm32 (ins->inst_imm));
4415                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4416                         break;
4417                 case OP_LAND:
4418                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4419                         break;
4420                 case OP_AND_IMM:
4421                 case OP_LAND_IMM:
4422                         g_assert (amd64_is_imm32 (ins->inst_imm));
4423                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4424                         break;
4425                 case OP_LMUL:
4426                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4427                         break;
4428                 case OP_MUL_IMM:
4429                 case OP_LMUL_IMM:
4430                 case OP_IMUL_IMM: {
4431                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4432
4433                         switch (ins->inst_imm) {
4434                         case 2:
4435                                 /* MOV r1, r2 */
4436                                 /* ADD r1, r1 */
4437                                 if (ins->dreg != ins->sreg1)
4438                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4439                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4440                                 break;
4441                         case 3:
4442                                 /* LEA r1, [r2 + r2*2] */
4443                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4444                                 break;
4445                         case 5:
4446                                 /* LEA r1, [r2 + r2*4] */
4447                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4448                                 break;
4449                         case 6:
4450                                 /* LEA r1, [r2 + r2*2] */
4451                                 /* ADD r1, r1          */
4452                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4453                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4454                                 break;
4455                         case 9:
4456                                 /* LEA r1, [r2 + r2*8] */
4457                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4458                                 break;
4459                         case 10:
4460                                 /* LEA r1, [r2 + r2*4] */
4461                                 /* ADD r1, r1          */
4462                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4463                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4464                                 break;
4465                         case 12:
4466                                 /* LEA r1, [r2 + r2*2] */
4467                                 /* SHL r1, 2           */
4468                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4469                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4470                                 break;
4471                         case 25:
4472                                 /* LEA r1, [r2 + r2*4] */
4473                                 /* LEA r1, [r1 + r1*4] */
4474                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4475                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4476                                 break;
4477                         case 100:
4478                                 /* LEA r1, [r2 + r2*4] */
4479                                 /* SHL r1, 2           */
4480                                 /* LEA r1, [r1 + r1*4] */
4481                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4482                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4483                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4484                                 break;
4485                         default:
4486                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4487                                 break;
4488                         }
4489                         break;
4490                 }
4491                 case OP_LDIV:
4492                 case OP_LREM:
4493 #if defined( __native_client_codegen__ )
4494                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4495                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4496 #endif
4497                         /* Regalloc magic makes the div/rem cases the same */
4498                         if (ins->sreg2 == AMD64_RDX) {
4499                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4500                                 amd64_cdq (code);
4501                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4502                         } else {
4503                                 amd64_cdq (code);
4504                                 amd64_div_reg (code, ins->sreg2, TRUE);
4505                         }
4506                         break;
4507                 case OP_LDIV_UN:
4508                 case OP_LREM_UN:
4509 #if defined( __native_client_codegen__ )
4510                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4511                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4512 #endif
4513                         if (ins->sreg2 == AMD64_RDX) {
4514                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4515                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4516                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4517                         } else {
4518                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4519                                 amd64_div_reg (code, ins->sreg2, FALSE);
4520                         }
4521                         break;
4522                 case OP_IDIV:
4523                 case OP_IREM:
4524 #if defined( __native_client_codegen__ )
4525                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4526                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4527 #endif
4528                         if (ins->sreg2 == AMD64_RDX) {
4529                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4530                                 amd64_cdq_size (code, 4);
4531                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4532                         } else {
4533                                 amd64_cdq_size (code, 4);
4534                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4535                         }
4536                         break;
4537                 case OP_IDIV_UN:
4538                 case OP_IREM_UN:
4539 #if defined( __native_client_codegen__ )
4540                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4541                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4542 #endif
4543                         if (ins->sreg2 == AMD64_RDX) {
4544                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4545                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4546                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4547                         } else {
4548                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4549                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4550                         }
4551                         break;
4552                 case OP_LMUL_OVF:
4553                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4554                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4555                         break;
4556                 case OP_LOR:
4557                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4558                         break;
4559                 case OP_OR_IMM:
4560                 case OP_LOR_IMM:
4561                         g_assert (amd64_is_imm32 (ins->inst_imm));
4562                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4563                         break;
4564                 case OP_LXOR:
4565                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4566                         break;
4567                 case OP_XOR_IMM:
4568                 case OP_LXOR_IMM:
4569                         g_assert (amd64_is_imm32 (ins->inst_imm));
4570                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4571                         break;
4572                 case OP_LSHL:
4573                         g_assert (ins->sreg2 == AMD64_RCX);
4574                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4575                         break;
4576                 case OP_LSHR:
4577                         g_assert (ins->sreg2 == AMD64_RCX);
4578                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4579                         break;
4580                 case OP_SHR_IMM:
4581                 case OP_LSHR_IMM:
4582                         g_assert (amd64_is_imm32 (ins->inst_imm));
4583                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4584                         break;
4585                 case OP_SHR_UN_IMM:
4586                         g_assert (amd64_is_imm32 (ins->inst_imm));
4587                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4588                         break;
4589                 case OP_LSHR_UN_IMM:
4590                         g_assert (amd64_is_imm32 (ins->inst_imm));
4591                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4592                         break;
4593                 case OP_LSHR_UN:
4594                         g_assert (ins->sreg2 == AMD64_RCX);
4595                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4596                         break;
4597                 case OP_SHL_IMM:
4598                 case OP_LSHL_IMM:
4599                         g_assert (amd64_is_imm32 (ins->inst_imm));
4600                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4601                         break;
4602
4603                 case OP_IADDCC:
4604                 case OP_IADD:
4605                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4606                         break;
4607                 case OP_IADC:
4608                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4609                         break;
4610                 case OP_IADD_IMM:
4611                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4612                         break;
4613                 case OP_IADC_IMM:
4614                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4615                         break;
4616                 case OP_ISUBCC:
4617                 case OP_ISUB:
4618                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4619                         break;
4620                 case OP_ISBB:
4621                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4622                         break;
4623                 case OP_ISUB_IMM:
4624                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4625                         break;
4626                 case OP_ISBB_IMM:
4627                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4628                         break;
4629                 case OP_IAND:
4630                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4631                         break;
4632                 case OP_IAND_IMM:
4633                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4634                         break;
4635                 case OP_IOR:
4636                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4637                         break;
4638                 case OP_IOR_IMM:
4639                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4640                         break;
4641                 case OP_IXOR:
4642                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4643                         break;
4644                 case OP_IXOR_IMM:
4645                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4646                         break;
4647                 case OP_INEG:
4648                         amd64_neg_reg_size (code, ins->sreg1, 4);
4649                         break;
4650                 case OP_INOT:
4651                         amd64_not_reg_size (code, ins->sreg1, 4);
4652                         break;
4653                 case OP_ISHL:
4654                         g_assert (ins->sreg2 == AMD64_RCX);
4655                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4656                         break;
4657                 case OP_ISHR:
4658                         g_assert (ins->sreg2 == AMD64_RCX);
4659                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4660                         break;
4661                 case OP_ISHR_IMM:
4662                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4663                         break;
4664                 case OP_ISHR_UN_IMM:
4665                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4666                         break;
4667                 case OP_ISHR_UN:
4668                         g_assert (ins->sreg2 == AMD64_RCX);
4669                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4670                         break;
4671                 case OP_ISHL_IMM:
4672                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4673                         break;
4674                 case OP_IMUL:
4675                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4676                         break;
4677                 case OP_IMUL_OVF:
4678                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4679                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4680                         break;
4681                 case OP_IMUL_OVF_UN:
4682                 case OP_LMUL_OVF_UN: {
4683                         /* the mul operation and the exception check should most likely be split */
4684                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4685                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4686                         /*g_assert (ins->sreg2 == X86_EAX);
4687                         g_assert (ins->dreg == X86_EAX);*/
4688                         if (ins->sreg2 == X86_EAX) {
4689                                 non_eax_reg = ins->sreg1;
4690                         } else if (ins->sreg1 == X86_EAX) {
4691                                 non_eax_reg = ins->sreg2;
4692                         } else {
4693                                 /* no need to save since we're going to store to it anyway */
4694                                 if (ins->dreg != X86_EAX) {
4695                                         saved_eax = TRUE;
4696                                         amd64_push_reg (code, X86_EAX);
4697                                 }
4698                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4699                                 non_eax_reg = ins->sreg2;
4700                         }
4701                         if (ins->dreg == X86_EDX) {
4702                                 if (!saved_eax) {
4703                                         saved_eax = TRUE;
4704                                         amd64_push_reg (code, X86_EAX);
4705                                 }
4706                         } else {
4707                                 saved_edx = TRUE;
4708                                 amd64_push_reg (code, X86_EDX);
4709                         }
4710                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4711                         /* save before the check since pop and mov don't change the flags */
4712                         if (ins->dreg != X86_EAX)
4713                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4714                         if (saved_edx)
4715                                 amd64_pop_reg (code, X86_EDX);
4716                         if (saved_eax)
4717                                 amd64_pop_reg (code, X86_EAX);
4718                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4719                         break;
4720                 }
4721                 case OP_ICOMPARE:
4722                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4723                         break;
4724                 case OP_ICOMPARE_IMM:
4725                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4726                         break;
4727                 case OP_IBEQ:
4728                 case OP_IBLT:
4729                 case OP_IBGT:
4730                 case OP_IBGE:
4731                 case OP_IBLE:
4732                 case OP_LBEQ:
4733                 case OP_LBLT:
4734                 case OP_LBGT:
4735                 case OP_LBGE:
4736                 case OP_LBLE:
4737                 case OP_IBNE_UN:
4738                 case OP_IBLT_UN:
4739                 case OP_IBGT_UN:
4740                 case OP_IBGE_UN:
4741                 case OP_IBLE_UN:
4742                 case OP_LBNE_UN:
4743                 case OP_LBLT_UN:
4744                 case OP_LBGT_UN:
4745                 case OP_LBGE_UN:
4746                 case OP_LBLE_UN:
4747                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4748                         break;
4749
4750                 case OP_CMOV_IEQ:
4751                 case OP_CMOV_IGE:
4752                 case OP_CMOV_IGT:
4753                 case OP_CMOV_ILE:
4754                 case OP_CMOV_ILT:
4755                 case OP_CMOV_INE_UN:
4756                 case OP_CMOV_IGE_UN:
4757                 case OP_CMOV_IGT_UN:
4758                 case OP_CMOV_ILE_UN:
4759                 case OP_CMOV_ILT_UN:
4760                 case OP_CMOV_LEQ:
4761                 case OP_CMOV_LGE:
4762                 case OP_CMOV_LGT:
4763                 case OP_CMOV_LLE:
4764                 case OP_CMOV_LLT:
4765                 case OP_CMOV_LNE_UN:
4766                 case OP_CMOV_LGE_UN:
4767                 case OP_CMOV_LGT_UN:
4768                 case OP_CMOV_LLE_UN:
4769                 case OP_CMOV_LLT_UN:
4770                         g_assert (ins->dreg == ins->sreg1);
4771                         /* This needs to operate on 64 bit values */
4772                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4773                         break;
4774
4775                 case OP_LNOT:
4776                         amd64_not_reg (code, ins->sreg1);
4777                         break;
4778                 case OP_LNEG:
4779                         amd64_neg_reg (code, ins->sreg1);
4780                         break;
4781
4782                 case OP_ICONST:
4783                 case OP_I8CONST:
4784                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4785                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4786                         else
4787                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4788                         break;
4789                 case OP_AOTCONST:
4790                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4791                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4792                         break;
4793                 case OP_JUMP_TABLE:
4794                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4795                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4796                         break;
4797                 case OP_MOVE:
4798                         if (ins->dreg != ins->sreg1)
4799                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4800                         break;
4801                 case OP_AMD64_SET_XMMREG_R4: {
4802                         if (cfg->r4fp) {
4803                                 if (ins->dreg != ins->sreg1)
4804                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4805                         } else {
4806                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4807                         }
4808                         break;
4809                 }
4810                 case OP_AMD64_SET_XMMREG_R8: {
4811                         if (ins->dreg != ins->sreg1)
4812                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4813                         break;
4814                 }
4815                 case OP_TAILCALL: {
4816                         MonoCallInst *call = (MonoCallInst*)ins;
4817                         int i, save_area_offset;
4818
4819                         g_assert (!cfg->method->save_lmf);
4820
4821                         /* Restore callee saved registers */
4822                         save_area_offset = cfg->arch.reg_save_area_offset;
4823                         for (i = 0; i < AMD64_NREG; ++i)
4824                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4825                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4826                                         save_area_offset += 8;
4827                                 }
4828
4829                         if (cfg->arch.omit_fp) {
4830                                 if (cfg->arch.stack_alloc_size)
4831                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4832                                 // FIXME:
4833                                 if (call->stack_usage)
4834                                         NOT_IMPLEMENTED;
4835                         } else {
4836                                 /* Copy arguments on the stack to our argument area */
4837                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4838                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4839                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4840                                 }
4841
4842                                 amd64_leave (code);
4843                         }
4844
4845                         offset = code - cfg->native_code;
4846                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4847                         if (cfg->compile_aot)
4848                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4849                         else
4850                                 amd64_set_reg_template (code, AMD64_R11);
4851                         amd64_jump_reg (code, AMD64_R11);
4852                         ins->flags |= MONO_INST_GC_CALLSITE;
4853                         ins->backend.pc_offset = code - cfg->native_code;
4854                         break;
4855                 }
4856                 case OP_CHECK_THIS:
4857                         /* ensure ins->sreg1 is not NULL */
4858                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4859                         break;
4860                 case OP_ARGLIST: {
4861                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4862                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4863                         break;
4864                 }
4865                 case OP_CALL:
4866                 case OP_FCALL:
4867                 case OP_RCALL:
4868                 case OP_LCALL:
4869                 case OP_VCALL:
4870                 case OP_VCALL2:
4871                 case OP_VOIDCALL:
4872                         call = (MonoCallInst*)ins;
4873                         /*
4874                          * The AMD64 ABI forces callers to know about varargs.
4875                          */
4876                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4877                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4878                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4879                                 /*
4880                                  * Since the unmanaged calling convention doesn't contain a
4881                                  * 'vararg' entry, we have to treat every pinvoke call as a
4882                                  * potential vararg call.
4883                                  */
4884                                 guint32 nregs, i;
4885                                 nregs = 0;
4886                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4887                                         if (call->used_fregs & (1 << i))
4888                                                 nregs ++;
4889                                 if (!nregs)
4890                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4891                                 else
4892                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4893                         }
4894
4895                         if (ins->flags & MONO_INST_HAS_METHOD)
4896                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4897                         else
4898                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4899                         ins->flags |= MONO_INST_GC_CALLSITE;
4900                         ins->backend.pc_offset = code - cfg->native_code;
4901                         code = emit_move_return_value (cfg, ins, code);
4902                         break;
4903                 case OP_FCALL_REG:
4904                 case OP_RCALL_REG:
4905                 case OP_LCALL_REG:
4906                 case OP_VCALL_REG:
4907                 case OP_VCALL2_REG:
4908                 case OP_VOIDCALL_REG:
4909                 case OP_CALL_REG:
4910                         call = (MonoCallInst*)ins;
4911
4912                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4913                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4914                                 ins->sreg1 = AMD64_R11;
4915                         }
4916
4917                         /*
4918                          * The AMD64 ABI forces callers to know about varargs.
4919                          */
4920                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4921                                 if (ins->sreg1 == AMD64_RAX) {
4922                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4923                                         ins->sreg1 = AMD64_R11;
4924                                 }
4925                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4926                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4927                                 /*
4928                                  * Since the unmanaged calling convention doesn't contain a
4929                                  * 'vararg' entry, we have to treat every pinvoke call as a
4930                                  * potential vararg call.
4931                                  */
4932                                 guint32 nregs, i;
4933                                 nregs = 0;
4934                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4935                                         if (call->used_fregs & (1 << i))
4936                                                 nregs ++;
4937                                 if (ins->sreg1 == AMD64_RAX) {
4938                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4939                                         ins->sreg1 = AMD64_R11;
4940                                 }
4941                                 if (!nregs)
4942                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4943                                 else
4944                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4945                         }
4946
4947                         amd64_call_reg (code, ins->sreg1);
4948                         ins->flags |= MONO_INST_GC_CALLSITE;
4949                         ins->backend.pc_offset = code - cfg->native_code;
4950                         code = emit_move_return_value (cfg, ins, code);
4951                         break;
4952                 case OP_FCALL_MEMBASE:
4953                 case OP_RCALL_MEMBASE:
4954                 case OP_LCALL_MEMBASE:
4955                 case OP_VCALL_MEMBASE:
4956                 case OP_VCALL2_MEMBASE:
4957                 case OP_VOIDCALL_MEMBASE:
4958                 case OP_CALL_MEMBASE:
4959                         call = (MonoCallInst*)ins;
4960
4961                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4962                         ins->flags |= MONO_INST_GC_CALLSITE;
4963                         ins->backend.pc_offset = code - cfg->native_code;
4964                         code = emit_move_return_value (cfg, ins, code);
4965                         break;
4966                 case OP_DYN_CALL: {
4967                         int i;
4968                         MonoInst *var = cfg->dyn_call_var;
4969                         guint8 *label;
4970
4971                         g_assert (var->opcode == OP_REGOFFSET);
4972
4973                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4974                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4975                         /* r10 = ftn */
4976                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4977
4978                         /* Save args buffer */
4979                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4980
4981                         /* Set fp arg regs */
4982                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4983                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4984                         label = code;
4985                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4986                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4987                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4988                         amd64_patch (label, code);
4989
4990                         /* Set argument registers */
4991                         for (i = 0; i < PARAM_REGS; ++i)
4992                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4993
4994                         /* Make the call */
4995                         amd64_call_reg (code, AMD64_R10);
4996
4997                         ins->flags |= MONO_INST_GC_CALLSITE;
4998                         ins->backend.pc_offset = code - cfg->native_code;
4999
5000                         /* Save result */
5001                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5002                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5003                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
5004                         break;
5005                 }
5006                 case OP_AMD64_SAVE_SP_TO_LMF: {
5007                         MonoInst *lmf_var = cfg->lmf_var;
5008                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5009                         break;
5010                 }
5011                 case OP_X86_PUSH:
5012                         g_assert_not_reached ();
5013                         amd64_push_reg (code, ins->sreg1);
5014                         break;
5015                 case OP_X86_PUSH_IMM:
5016                         g_assert_not_reached ();
5017                         g_assert (amd64_is_imm32 (ins->inst_imm));
5018                         amd64_push_imm (code, ins->inst_imm);
5019                         break;
5020                 case OP_X86_PUSH_MEMBASE:
5021                         g_assert_not_reached ();
5022                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5023                         break;
5024                 case OP_X86_PUSH_OBJ: {
5025                         int size = ALIGN_TO (ins->inst_imm, 8);
5026
5027                         g_assert_not_reached ();
5028
5029                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5030                         amd64_push_reg (code, AMD64_RDI);
5031                         amd64_push_reg (code, AMD64_RSI);
5032                         amd64_push_reg (code, AMD64_RCX);
5033                         if (ins->inst_offset)
5034                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5035                         else
5036                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5037                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5038                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5039                         amd64_cld (code);
5040                         amd64_prefix (code, X86_REP_PREFIX);
5041                         amd64_movsd (code);
5042                         amd64_pop_reg (code, AMD64_RCX);
5043                         amd64_pop_reg (code, AMD64_RSI);
5044                         amd64_pop_reg (code, AMD64_RDI);
5045                         break;
5046                 }
5047                 case OP_GENERIC_CLASS_INIT: {
5048                         static int byte_offset = -1;
5049                         static guint8 bitmask;
5050                         guint8 *jump;
5051
5052                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5053
5054                         if (byte_offset < 0)
5055                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5056
5057                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5058                         jump = code;
5059                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5060
5061                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5062                         ins->flags |= MONO_INST_GC_CALLSITE;
5063                         ins->backend.pc_offset = code - cfg->native_code;
5064
5065                         x86_patch (jump, code);
5066                         break;
5067                 }
5068
5069                 case OP_X86_LEA:
5070                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5071                         break;
5072                 case OP_X86_LEA_MEMBASE:
5073                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5074                         break;
5075                 case OP_X86_XCHG:
5076                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5077                         break;
5078                 case OP_LOCALLOC:
5079                         /* keep alignment */
5080                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5081                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5082                         code = mono_emit_stack_alloc (cfg, code, ins);
5083                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5084                         if (cfg->param_area)
5085                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5086                         break;
5087                 case OP_LOCALLOC_IMM: {
5088                         guint32 size = ins->inst_imm;
5089                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5090
5091                         if (ins->flags & MONO_INST_INIT) {
5092                                 if (size < 64) {
5093                                         int i;
5094
5095                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5096                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5097
5098                                         for (i = 0; i < size; i += 8)
5099                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5100                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5101                                 } else {
5102                                         amd64_mov_reg_imm (code, ins->dreg, size);
5103                                         ins->sreg1 = ins->dreg;
5104
5105                                         code = mono_emit_stack_alloc (cfg, code, ins);
5106                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5107                                 }
5108                         } else {
5109                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5110                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5111                         }
5112                         if (cfg->param_area)
5113                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5114                         break;
5115                 }
5116                 case OP_THROW: {
5117                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5118                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5119                                              (gpointer)"mono_arch_throw_exception", FALSE);
5120                         ins->flags |= MONO_INST_GC_CALLSITE;
5121                         ins->backend.pc_offset = code - cfg->native_code;
5122                         break;
5123                 }
5124                 case OP_RETHROW: {
5125                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5126                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5127                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5128                         ins->flags |= MONO_INST_GC_CALLSITE;
5129                         ins->backend.pc_offset = code - cfg->native_code;
5130                         break;
5131                 }
5132                 case OP_CALL_HANDLER:
5133                         /* Align stack */
5134                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5135                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5136                         amd64_call_imm (code, 0);
5137                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5138                         /* Restore stack alignment */
5139                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5140                         break;
5141                 case OP_START_HANDLER: {
5142                         /* Even though we're saving RSP, use sizeof */
5143                         /* gpointer because spvar is of type IntPtr */
5144                         /* see: mono_create_spvar_for_region */
5145                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5146                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5147
5148                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5149                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5150                                 cfg->param_area) {
5151                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5152                         }
5153                         break;
5154                 }
5155                 case OP_ENDFINALLY: {
5156                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5157                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5158                         amd64_ret (code);
5159                         break;
5160                 }
5161                 case OP_ENDFILTER: {
5162                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5163                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5164                         /* The local allocator will put the result into RAX */
5165                         amd64_ret (code);
5166                         break;
5167                 }
5168                 case OP_GET_EX_OBJ:
5169                         if (ins->dreg != AMD64_RAX)
5170                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5171                         break;
5172                 case OP_LABEL:
5173                         ins->inst_c0 = code - cfg->native_code;
5174                         break;
5175                 case OP_BR:
5176                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5177                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5178                         //break;
5179                                 if (ins->inst_target_bb->native_offset) {
5180                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5181                                 } else {
5182                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5183                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5184                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5185                                                 x86_jump8 (code, 0);
5186                                         else
5187                                                 x86_jump32 (code, 0);
5188                         }
5189                         break;
5190                 case OP_BR_REG:
5191                         amd64_jump_reg (code, ins->sreg1);
5192                         break;
5193                 case OP_ICNEQ:
5194                 case OP_ICGE:
5195                 case OP_ICLE:
5196                 case OP_ICGE_UN:
5197                 case OP_ICLE_UN:
5198
5199                 case OP_CEQ:
5200                 case OP_LCEQ:
5201                 case OP_ICEQ:
5202                 case OP_CLT:
5203                 case OP_LCLT:
5204                 case OP_ICLT:
5205                 case OP_CGT:
5206                 case OP_ICGT:
5207                 case OP_LCGT:
5208                 case OP_CLT_UN:
5209                 case OP_LCLT_UN:
5210                 case OP_ICLT_UN:
5211                 case OP_CGT_UN:
5212                 case OP_LCGT_UN:
5213                 case OP_ICGT_UN:
5214                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5215                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5216                         break;
5217                 case OP_COND_EXC_EQ:
5218                 case OP_COND_EXC_NE_UN:
5219                 case OP_COND_EXC_LT:
5220                 case OP_COND_EXC_LT_UN:
5221                 case OP_COND_EXC_GT:
5222                 case OP_COND_EXC_GT_UN:
5223                 case OP_COND_EXC_GE:
5224                 case OP_COND_EXC_GE_UN:
5225                 case OP_COND_EXC_LE:
5226                 case OP_COND_EXC_LE_UN:
5227                 case OP_COND_EXC_IEQ:
5228                 case OP_COND_EXC_INE_UN:
5229                 case OP_COND_EXC_ILT:
5230                 case OP_COND_EXC_ILT_UN:
5231                 case OP_COND_EXC_IGT:
5232                 case OP_COND_EXC_IGT_UN:
5233                 case OP_COND_EXC_IGE:
5234                 case OP_COND_EXC_IGE_UN:
5235                 case OP_COND_EXC_ILE:
5236                 case OP_COND_EXC_ILE_UN:
5237                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5238                         break;
5239                 case OP_COND_EXC_OV:
5240                 case OP_COND_EXC_NO:
5241                 case OP_COND_EXC_C:
5242                 case OP_COND_EXC_NC:
5243                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5244                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5245                         break;
5246                 case OP_COND_EXC_IOV:
5247                 case OP_COND_EXC_INO:
5248                 case OP_COND_EXC_IC:
5249                 case OP_COND_EXC_INC:
5250                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5251                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5252                         break;
5253
5254                 /* floating point opcodes */
5255                 case OP_R8CONST: {
5256                         double d = *(double *)ins->inst_p0;
5257
5258                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5259                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5260                         }
5261                         else {
5262                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5263                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5264                         }
5265                         break;
5266                 }
5267                 case OP_R4CONST: {
5268                         float f = *(float *)ins->inst_p0;
5269
5270                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5271                                 if (cfg->r4fp)
5272                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5273                                 else
5274                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5275                         }
5276                         else {
5277                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5278                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5279                                 if (!cfg->r4fp)
5280                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5281                         }
5282                         break;
5283                 }
5284                 case OP_STORER8_MEMBASE_REG:
5285                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5286                         break;
5287                 case OP_LOADR8_MEMBASE:
5288                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5289                         break;
5290                 case OP_STORER4_MEMBASE_REG:
5291                         if (cfg->r4fp) {
5292                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5293                         } else {
5294                                 /* This requires a double->single conversion */
5295                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5296                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5297                         }
5298                         break;
5299                 case OP_LOADR4_MEMBASE:
5300                         if (cfg->r4fp) {
5301                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5302                         } else {
5303                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5304                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5305                         }
5306                         break;
5307                 case OP_ICONV_TO_R4:
5308                         if (cfg->r4fp) {
5309                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5310                         } else {
5311                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5312                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5313                         }
5314                         break;
5315                 case OP_ICONV_TO_R8:
5316                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5317                         break;
5318                 case OP_LCONV_TO_R4:
5319                         if (cfg->r4fp) {
5320                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5321                         } else {
5322                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5323                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5324                         }
5325                         break;
5326                 case OP_LCONV_TO_R8:
5327                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5328                         break;
5329                 case OP_FCONV_TO_R4:
5330                         if (cfg->r4fp) {
5331                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5332                         } else {
5333                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5334                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5335                         }
5336                         break;
5337                 case OP_FCONV_TO_I1:
5338                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5339                         break;
5340                 case OP_FCONV_TO_U1:
5341                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5342                         break;
5343                 case OP_FCONV_TO_I2:
5344                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5345                         break;
5346                 case OP_FCONV_TO_U2:
5347                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5348                         break;
5349                 case OP_FCONV_TO_U4:
5350                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5351                         break;
5352                 case OP_FCONV_TO_I4:
5353                 case OP_FCONV_TO_I:
5354                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5355                         break;
5356                 case OP_FCONV_TO_I8:
5357                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5358                         break;
5359
5360                 case OP_RCONV_TO_I1:
5361                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5362                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5363                         break;
5364                 case OP_RCONV_TO_U1:
5365                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5366                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5367                         break;
5368                 case OP_RCONV_TO_I2:
5369                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5370                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5371                         break;
5372                 case OP_RCONV_TO_U2:
5373                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5374                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5375                         break;
5376                 case OP_RCONV_TO_I4:
5377                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5378                         break;
5379                 case OP_RCONV_TO_U4:
5380                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5381                         break;
5382                 case OP_RCONV_TO_I8:
5383                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5384                         break;
5385                 case OP_RCONV_TO_R8:
5386                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5387                         break;
5388                 case OP_RCONV_TO_R4:
5389                         if (ins->dreg != ins->sreg1)
5390                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5391                         break;
5392
5393                 case OP_LCONV_TO_R_UN: {
5394                         guint8 *br [2];
5395
5396                         /* Based on gcc code */
5397                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5398                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5399
5400                         /* Positive case */
5401                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5402                         br [1] = code; x86_jump8 (code, 0);
5403                         amd64_patch (br [0], code);
5404
5405                         /* Negative case */
5406                         /* Save to the red zone */
5407                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5408                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5409                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5410                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5411                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5412                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5413                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5414                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5415                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5416                         /* Restore */
5417                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5418                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5419                         amd64_patch (br [1], code);
5420                         break;
5421                 }
5422                 case OP_LCONV_TO_OVF_U4:
5423                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5424                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5425                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5426                         break;
5427                 case OP_LCONV_TO_OVF_I4_UN:
5428                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5429                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5430                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5431                         break;
5432                 case OP_FMOVE:
5433                         if (ins->dreg != ins->sreg1)
5434                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5435                         break;
5436                 case OP_RMOVE:
5437                         if (ins->dreg != ins->sreg1)
5438                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5439                         break;
5440                 case OP_MOVE_F_TO_I4:
5441                         if (cfg->r4fp) {
5442                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5443                         } else {
5444                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5445                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5446                         }
5447                         break;
5448                 case OP_MOVE_I4_TO_F:
5449                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5450                         if (!cfg->r4fp)
5451                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5452                         break;
5453                 case OP_MOVE_F_TO_I8:
5454                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5455                         break;
5456                 case OP_MOVE_I8_TO_F:
5457                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5458                         break;
5459                 case OP_FADD:
5460                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5461                         break;
5462                 case OP_FSUB:
5463                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5464                         break;
5465                 case OP_FMUL:
5466                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5467                         break;
5468                 case OP_FDIV:
5469                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5470                         break;
5471                 case OP_FNEG: {
5472                         static double r8_0 = -0.0;
5473
5474                         g_assert (ins->sreg1 == ins->dreg);
5475
5476                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5477                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5478                         break;
5479                 }
5480                 case OP_SIN:
5481                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5482                         break;
5483                 case OP_COS:
5484                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5485                         break;
5486                 case OP_ABS: {
5487                         static guint64 d = 0x7fffffffffffffffUL;
5488
5489                         g_assert (ins->sreg1 == ins->dreg);
5490
5491                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5492                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5493                         break;
5494                 }
5495                 case OP_SQRT:
5496                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5497                         break;
5498
5499                 case OP_RADD:
5500                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5501                         break;
5502                 case OP_RSUB:
5503                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5504                         break;
5505                 case OP_RMUL:
5506                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5507                         break;
5508                 case OP_RDIV:
5509                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5510                         break;
5511                 case OP_RNEG: {
5512                         static float r4_0 = -0.0;
5513
5514                         g_assert (ins->sreg1 == ins->dreg);
5515
5516                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5517                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5518                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5519                         break;
5520                 }
5521
5522                 case OP_IMIN:
5523                         g_assert (cfg->opt & MONO_OPT_CMOV);
5524                         g_assert (ins->dreg == ins->sreg1);
5525                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5526                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5527                         break;
5528                 case OP_IMIN_UN:
5529                         g_assert (cfg->opt & MONO_OPT_CMOV);
5530                         g_assert (ins->dreg == ins->sreg1);
5531                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5532                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5533                         break;
5534                 case OP_IMAX:
5535                         g_assert (cfg->opt & MONO_OPT_CMOV);
5536                         g_assert (ins->dreg == ins->sreg1);
5537                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5538                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5539                         break;
5540                 case OP_IMAX_UN:
5541                         g_assert (cfg->opt & MONO_OPT_CMOV);
5542                         g_assert (ins->dreg == ins->sreg1);
5543                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5544                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5545                         break;
5546                 case OP_LMIN:
5547                         g_assert (cfg->opt & MONO_OPT_CMOV);
5548                         g_assert (ins->dreg == ins->sreg1);
5549                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5550                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5551                         break;
5552                 case OP_LMIN_UN:
5553                         g_assert (cfg->opt & MONO_OPT_CMOV);
5554                         g_assert (ins->dreg == ins->sreg1);
5555                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5556                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5557                         break;
5558                 case OP_LMAX:
5559                         g_assert (cfg->opt & MONO_OPT_CMOV);
5560                         g_assert (ins->dreg == ins->sreg1);
5561                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5562                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5563                         break;
5564                 case OP_LMAX_UN:
5565                         g_assert (cfg->opt & MONO_OPT_CMOV);
5566                         g_assert (ins->dreg == ins->sreg1);
5567                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5568                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5569                         break;
5570                 case OP_X86_FPOP:
5571                         break;
5572                 case OP_FCOMPARE:
5573                         /*
5574                          * The two arguments are swapped because the fbranch instructions
5575                          * depend on this for the non-sse case to work.
5576                          */
5577                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5578                         break;
5579                 case OP_RCOMPARE:
5580                         /*
5581                          * FIXME: Get rid of this.
5582                          * The two arguments are swapped because the fbranch instructions
5583                          * depend on this for the non-sse case to work.
5584                          */
5585                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5586                         break;
5587                 case OP_FCNEQ:
5588                 case OP_FCEQ: {
5589                         /* zeroing the register at the start results in
5590                          * shorter and faster code (we can also remove the widening op)
5591                          */
5592                         guchar *unordered_check;
5593
5594                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5595                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5596                         unordered_check = code;
5597                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5598
5599                         if (ins->opcode == OP_FCEQ) {
5600                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5601                                 amd64_patch (unordered_check, code);
5602                         } else {
5603                                 guchar *jump_to_end;
5604                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5605                                 jump_to_end = code;
5606                                 x86_jump8 (code, 0);
5607                                 amd64_patch (unordered_check, code);
5608                                 amd64_inc_reg (code, ins->dreg);
5609                                 amd64_patch (jump_to_end, code);
5610                         }
5611                         break;
5612                 }
5613                 case OP_FCLT:
5614                 case OP_FCLT_UN: {
5615                         /* zeroing the register at the start results in
5616                          * shorter and faster code (we can also remove the widening op)
5617                          */
5618                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5619                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5620                         if (ins->opcode == OP_FCLT_UN) {
5621                                 guchar *unordered_check = code;
5622                                 guchar *jump_to_end;
5623                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5624                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5625                                 jump_to_end = code;
5626                                 x86_jump8 (code, 0);
5627                                 amd64_patch (unordered_check, code);
5628                                 amd64_inc_reg (code, ins->dreg);
5629                                 amd64_patch (jump_to_end, code);
5630                         } else {
5631                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5632                         }
5633                         break;
5634                 }
5635                 case OP_FCLE: {
5636                         guchar *unordered_check;
5637                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5638                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5639                         unordered_check = code;
5640                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5641                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5642                         amd64_patch (unordered_check, code);
5643                         break;
5644                 }
5645                 case OP_FCGT:
5646                 case OP_FCGT_UN: {
5647                         /* zeroing the register at the start results in
5648                          * shorter and faster code (we can also remove the widening op)
5649                          */
5650                         guchar *unordered_check;
5651
5652                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5653                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5654                         if (ins->opcode == OP_FCGT) {
5655                                 unordered_check = code;
5656                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5657                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5658                                 amd64_patch (unordered_check, code);
5659                         } else {
5660                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5661                         }
5662                         break;
5663                 }
5664                 case OP_FCGE: {
5665                         guchar *unordered_check;
5666                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5667                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5668                         unordered_check = code;
5669                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5670                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5671                         amd64_patch (unordered_check, code);
5672                         break;
5673                 }
5674
5675                 case OP_RCEQ:
5676                 case OP_RCGT:
5677                 case OP_RCLT:
5678                 case OP_RCLT_UN:
5679                 case OP_RCGT_UN: {
5680                         int x86_cond;
5681                         gboolean unordered = FALSE;
5682
5683                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5684                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5685
5686                         switch (ins->opcode) {
5687                         case OP_RCEQ:
5688                                 x86_cond = X86_CC_EQ;
5689                                 break;
5690                         case OP_RCGT:
5691                                 x86_cond = X86_CC_LT;
5692                                 break;
5693                         case OP_RCLT:
5694                                 x86_cond = X86_CC_GT;
5695                                 break;
5696                         case OP_RCLT_UN:
5697                                 x86_cond = X86_CC_GT;
5698                                 unordered = TRUE;
5699                                 break;
5700                         case OP_RCGT_UN:
5701                                 x86_cond = X86_CC_LT;
5702                                 unordered = TRUE;
5703                                 break;
5704                         default:
5705                                 g_assert_not_reached ();
5706                                 break;
5707                         }
5708
5709                         if (unordered) {
5710                                 guchar *unordered_check;
5711                                 guchar *jump_to_end;
5712
5713                                 unordered_check = code;
5714                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5715                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5716                                 jump_to_end = code;
5717                                 x86_jump8 (code, 0);
5718                                 amd64_patch (unordered_check, code);
5719                                 amd64_inc_reg (code, ins->dreg);
5720                                 amd64_patch (jump_to_end, code);
5721                         } else {
5722                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5723                         }
5724                         break;
5725                 }
5726                 case OP_FCLT_MEMBASE:
5727                 case OP_FCGT_MEMBASE:
5728                 case OP_FCLT_UN_MEMBASE:
5729                 case OP_FCGT_UN_MEMBASE:
5730                 case OP_FCEQ_MEMBASE: {
5731                         guchar *unordered_check, *jump_to_end;
5732                         int x86_cond;
5733
5734                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5735                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5736
5737                         switch (ins->opcode) {
5738                         case OP_FCEQ_MEMBASE:
5739                                 x86_cond = X86_CC_EQ;
5740                                 break;
5741                         case OP_FCLT_MEMBASE:
5742                         case OP_FCLT_UN_MEMBASE:
5743                                 x86_cond = X86_CC_LT;
5744                                 break;
5745                         case OP_FCGT_MEMBASE:
5746                         case OP_FCGT_UN_MEMBASE:
5747                                 x86_cond = X86_CC_GT;
5748                                 break;
5749                         default:
5750                                 g_assert_not_reached ();
5751                         }
5752
5753                         unordered_check = code;
5754                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5755                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5756
5757                         switch (ins->opcode) {
5758                         case OP_FCEQ_MEMBASE:
5759                         case OP_FCLT_MEMBASE:
5760                         case OP_FCGT_MEMBASE:
5761                                 amd64_patch (unordered_check, code);
5762                                 break;
5763                         case OP_FCLT_UN_MEMBASE:
5764                         case OP_FCGT_UN_MEMBASE:
5765                                 jump_to_end = code;
5766                                 x86_jump8 (code, 0);
5767                                 amd64_patch (unordered_check, code);
5768                                 amd64_inc_reg (code, ins->dreg);
5769                                 amd64_patch (jump_to_end, code);
5770                                 break;
5771                         default:
5772                                 break;
5773                         }
5774                         break;
5775                 }
5776                 case OP_FBEQ: {
5777                         guchar *jump = code;
5778                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5779                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5780                         amd64_patch (jump, code);
5781                         break;
5782                 }
5783                 case OP_FBNE_UN:
5784                         /* Branch if C013 != 100 */
5785                         /* branch if !ZF or (PF|CF) */
5786                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5787                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5788                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5789                         break;
5790                 case OP_FBLT:
5791                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5792                         break;
5793                 case OP_FBLT_UN:
5794                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5795                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5796                         break;
5797                 case OP_FBGT:
5798                 case OP_FBGT_UN:
5799                         if (ins->opcode == OP_FBGT) {
5800                                 guchar *br1;
5801
5802                                 /* skip branch if C1=1 */
5803                                 br1 = code;
5804                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5805                                 /* branch if (C0 | C3) = 1 */
5806                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5807                                 amd64_patch (br1, code);
5808                                 break;
5809                         } else {
5810                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5811                         }
5812                         break;
5813                 case OP_FBGE: {
5814                         /* Branch if C013 == 100 or 001 */
5815                         guchar *br1;
5816
5817                         /* skip branch if C1=1 */
5818                         br1 = code;
5819                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5820                         /* branch if (C0 | C3) = 1 */
5821                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5822                         amd64_patch (br1, code);
5823                         break;
5824                 }
5825                 case OP_FBGE_UN:
5826                         /* Branch if C013 == 000 */
5827                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5828                         break;
5829                 case OP_FBLE: {
5830                         /* Branch if C013=000 or 100 */
5831                         guchar *br1;
5832
5833                         /* skip branch if C1=1 */
5834                         br1 = code;
5835                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5836                         /* branch if C0=0 */
5837                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5838                         amd64_patch (br1, code);
5839                         break;
5840                 }
5841                 case OP_FBLE_UN:
5842                         /* Branch if C013 != 001 */
5843                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5844                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5845                         break;
5846                 case OP_CKFINITE:
5847                         /* Transfer value to the fp stack */
5848                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5849                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5850                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5851
5852                         amd64_push_reg (code, AMD64_RAX);
5853                         amd64_fxam (code);
5854                         amd64_fnstsw (code);
5855                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5856                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5857                         amd64_pop_reg (code, AMD64_RAX);
5858                         amd64_fstp (code, 0);
5859                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5860                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5861                         break;
5862                 case OP_TLS_GET: {
5863                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5864                         break;
5865                 }
5866                 case OP_TLS_GET_REG:
5867                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5868                         break;
5869                 case OP_TLS_SET: {
5870                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5871                         break;
5872                 }
5873                 case OP_TLS_SET_REG: {
5874                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5875                         break;
5876                 }
5877                 case OP_MEMORY_BARRIER: {
5878                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5879                                 x86_mfence (code);
5880                         break;
5881                 }
5882                 case OP_ATOMIC_ADD_I4:
5883                 case OP_ATOMIC_ADD_I8: {
5884                         int dreg = ins->dreg;
5885                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5886
5887                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5888                                 dreg = AMD64_R11;
5889
5890                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5891                         amd64_prefix (code, X86_LOCK_PREFIX);
5892                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5893                         /* dreg contains the old value, add with sreg2 value */
5894                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5895
5896                         if (ins->dreg != dreg)
5897                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5898
5899                         break;
5900                 }
5901                 case OP_ATOMIC_EXCHANGE_I4:
5902                 case OP_ATOMIC_EXCHANGE_I8: {
5903                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5904
5905                         /* LOCK prefix is implied. */
5906                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5907                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5908                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5909                         break;
5910                 }
5911                 case OP_ATOMIC_CAS_I4:
5912                 case OP_ATOMIC_CAS_I8: {
5913                         guint32 size;
5914
5915                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5916                                 size = 8;
5917                         else
5918                                 size = 4;
5919
5920                         /*
5921                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5922                          * an explanation of how this works.
5923                          */
5924                         g_assert (ins->sreg3 == AMD64_RAX);
5925                         g_assert (ins->sreg1 != AMD64_RAX);
5926                         g_assert (ins->sreg1 != ins->sreg2);
5927
5928                         amd64_prefix (code, X86_LOCK_PREFIX);
5929                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5930
5931                         if (ins->dreg != AMD64_RAX)
5932                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5933                         break;
5934                 }
5935                 case OP_ATOMIC_LOAD_I1: {
5936                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5937                         break;
5938                 }
5939                 case OP_ATOMIC_LOAD_U1: {
5940                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5941                         break;
5942                 }
5943                 case OP_ATOMIC_LOAD_I2: {
5944                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5945                         break;
5946                 }
5947                 case OP_ATOMIC_LOAD_U2: {
5948                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5949                         break;
5950                 }
5951                 case OP_ATOMIC_LOAD_I4: {
5952                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5953                         break;
5954                 }
5955                 case OP_ATOMIC_LOAD_U4:
5956                 case OP_ATOMIC_LOAD_I8:
5957                 case OP_ATOMIC_LOAD_U8: {
5958                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5959                         break;
5960                 }
5961                 case OP_ATOMIC_LOAD_R4: {
5962                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5963                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5964                         break;
5965                 }
5966                 case OP_ATOMIC_LOAD_R8: {
5967                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5968                         break;
5969                 }
5970                 case OP_ATOMIC_STORE_I1:
5971                 case OP_ATOMIC_STORE_U1:
5972                 case OP_ATOMIC_STORE_I2:
5973                 case OP_ATOMIC_STORE_U2:
5974                 case OP_ATOMIC_STORE_I4:
5975                 case OP_ATOMIC_STORE_U4:
5976                 case OP_ATOMIC_STORE_I8:
5977                 case OP_ATOMIC_STORE_U8: {
5978                         int size;
5979
5980                         switch (ins->opcode) {
5981                         case OP_ATOMIC_STORE_I1:
5982                         case OP_ATOMIC_STORE_U1:
5983                                 size = 1;
5984                                 break;
5985                         case OP_ATOMIC_STORE_I2:
5986                         case OP_ATOMIC_STORE_U2:
5987                                 size = 2;
5988                                 break;
5989                         case OP_ATOMIC_STORE_I4:
5990                         case OP_ATOMIC_STORE_U4:
5991                                 size = 4;
5992                                 break;
5993                         case OP_ATOMIC_STORE_I8:
5994                         case OP_ATOMIC_STORE_U8:
5995                                 size = 8;
5996                                 break;
5997                         }
5998
5999                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6000
6001                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6002                                 x86_mfence (code);
6003                         break;
6004                 }
6005                 case OP_ATOMIC_STORE_R4: {
6006                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6007                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6008
6009                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6010                                 x86_mfence (code);
6011                         break;
6012                 }
6013                 case OP_ATOMIC_STORE_R8: {
6014                         x86_nop (code);
6015                         x86_nop (code);
6016                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6017                         x86_nop (code);
6018                         x86_nop (code);
6019
6020                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6021                                 x86_mfence (code);
6022                         break;
6023                 }
6024                 case OP_CARD_TABLE_WBARRIER: {
6025                         int ptr = ins->sreg1;
6026                         int value = ins->sreg2;
6027                         guchar *br = 0;
6028                         int nursery_shift, card_table_shift;
6029                         gpointer card_table_mask;
6030                         size_t nursery_size;
6031
6032                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6033                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6034                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6035
6036                         /*If either point to the stack we can simply avoid the WB. This happens due to
6037                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6038                          */
6039                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6040                                 continue;
6041
6042                         /*
6043                          * We need one register we can clobber, we choose EDX and make sreg1
6044                          * fixed EAX to work around limitations in the local register allocator.
6045                          * sreg2 might get allocated to EDX, but that is not a problem since
6046                          * we use it before clobbering EDX.
6047                          */
6048                         g_assert (ins->sreg1 == AMD64_RAX);
6049
6050                         /*
6051                          * This is the code we produce:
6052                          *
6053                          *   edx = value
6054                          *   edx >>= nursery_shift
6055                          *   cmp edx, (nursery_start >> nursery_shift)
6056                          *   jne done
6057                          *   edx = ptr
6058                          *   edx >>= card_table_shift
6059                          *   edx += cardtable
6060                          *   [edx] = 1
6061                          * done:
6062                          */
6063
6064                         if (mono_gc_card_table_nursery_check ()) {
6065                                 if (value != AMD64_RDX)
6066                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6067                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6068                                 if (shifted_nursery_start >> 31) {
6069                                         /*
6070                                          * The value we need to compare against is 64 bits, so we need
6071                                          * another spare register.  We use RBX, which we save and
6072                                          * restore.
6073                                          */
6074                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6075                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6076                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6077                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6078                                 } else {
6079                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6080                                 }
6081                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6082                         }
6083                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6084                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6085                         if (card_table_mask)
6086                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6087
6088                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6089                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6090
6091                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6092
6093                         if (mono_gc_card_table_nursery_check ())
6094                                 x86_patch (br, code);
6095                         break;
6096                 }
6097 #ifdef MONO_ARCH_SIMD_INTRINSICS
6098                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6099                 case OP_ADDPS:
6100                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_DIVPS:
6103                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_MULPS:
6106                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_SUBPS:
6109                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111                 case OP_MAXPS:
6112                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_MINPS:
6115                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_COMPPS:
6118                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6119                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6120                         break;
6121                 case OP_ANDPS:
6122                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124                 case OP_ANDNPS:
6125                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6126                         break;
6127                 case OP_ORPS:
6128                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6129                         break;
6130                 case OP_XORPS:
6131                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133                 case OP_SQRTPS:
6134                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6135                         break;
6136                 case OP_RSQRTPS:
6137                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6138                         break;
6139                 case OP_RCPPS:
6140                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6141                         break;
6142                 case OP_ADDSUBPS:
6143                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_HADDPS:
6146                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_HSUBPS:
6149                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151                 case OP_DUPPS_HIGH:
6152                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6153                         break;
6154                 case OP_DUPPS_LOW:
6155                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6156                         break;
6157
6158                 case OP_PSHUFLEW_HIGH:
6159                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6160                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6161                         break;
6162                 case OP_PSHUFLEW_LOW:
6163                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6164                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6165                         break;
6166                 case OP_PSHUFLED:
6167                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6168                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6169                         break;
6170                 case OP_SHUFPS:
6171                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6172                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6173                         break;
6174                 case OP_SHUFPD:
6175                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6176                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6177                         break;
6178
6179                 case OP_ADDPD:
6180                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6181                         break;
6182                 case OP_DIVPD:
6183                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6184                         break;
6185                 case OP_MULPD:
6186                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_SUBPD:
6189                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_MAXPD:
6192                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_MINPD:
6195                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197                 case OP_COMPPD:
6198                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6199                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6200                         break;
6201                 case OP_ANDPD:
6202                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_ANDNPD:
6205                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_ORPD:
6208                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210                 case OP_XORPD:
6211                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6212                         break;
6213                 case OP_SQRTPD:
6214                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6215                         break;
6216                 case OP_ADDSUBPD:
6217                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6218                         break;
6219                 case OP_HADDPD:
6220                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6221                         break;
6222                 case OP_HSUBPD:
6223                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6224                         break;
6225                 case OP_DUPPD:
6226                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6227                         break;
6228
6229                 case OP_EXTRACT_MASK:
6230                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6231                         break;
6232
6233                 case OP_PAND:
6234                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_POR:
6237                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239                 case OP_PXOR:
6240                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6241                         break;
6242
6243                 case OP_PADDB:
6244                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6245                         break;
6246                 case OP_PADDW:
6247                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6248                         break;
6249                 case OP_PADDD:
6250                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6251                         break;
6252                 case OP_PADDQ:
6253                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6254                         break;
6255
6256                 case OP_PSUBB:
6257                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6258                         break;
6259                 case OP_PSUBW:
6260                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6261                         break;
6262                 case OP_PSUBD:
6263                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6264                         break;
6265                 case OP_PSUBQ:
6266                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6267                         break;
6268
6269                 case OP_PMAXB_UN:
6270                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6271                         break;
6272                 case OP_PMAXW_UN:
6273                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6274                         break;
6275                 case OP_PMAXD_UN:
6276                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6277                         break;
6278
6279                 case OP_PMAXB:
6280                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6281                         break;
6282                 case OP_PMAXW:
6283                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6284                         break;
6285                 case OP_PMAXD:
6286                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6287                         break;
6288
6289                 case OP_PAVGB_UN:
6290                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6291                         break;
6292                 case OP_PAVGW_UN:
6293                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6294                         break;
6295
6296                 case OP_PMINB_UN:
6297                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6298                         break;
6299                 case OP_PMINW_UN:
6300                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6301                         break;
6302                 case OP_PMIND_UN:
6303                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6304                         break;
6305
6306                 case OP_PMINB:
6307                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6308                         break;
6309                 case OP_PMINW:
6310                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6311                         break;
6312                 case OP_PMIND:
6313                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6314                         break;
6315
6316                 case OP_PCMPEQB:
6317                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6318                         break;
6319                 case OP_PCMPEQW:
6320                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6321                         break;
6322                 case OP_PCMPEQD:
6323                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6324                         break;
6325                 case OP_PCMPEQQ:
6326                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6327                         break;
6328
6329                 case OP_PCMPGTB:
6330                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6331                         break;
6332                 case OP_PCMPGTW:
6333                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6334                         break;
6335                 case OP_PCMPGTD:
6336                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6337                         break;
6338                 case OP_PCMPGTQ:
6339                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6340                         break;
6341
6342                 case OP_PSUM_ABS_DIFF:
6343                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6344                         break;
6345
6346                 case OP_UNPACK_LOWB:
6347                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6348                         break;
6349                 case OP_UNPACK_LOWW:
6350                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6351                         break;
6352                 case OP_UNPACK_LOWD:
6353                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6354                         break;
6355                 case OP_UNPACK_LOWQ:
6356                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6357                         break;
6358                 case OP_UNPACK_LOWPS:
6359                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6360                         break;
6361                 case OP_UNPACK_LOWPD:
6362                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6363                         break;
6364
6365                 case OP_UNPACK_HIGHB:
6366                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6367                         break;
6368                 case OP_UNPACK_HIGHW:
6369                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6370                         break;
6371                 case OP_UNPACK_HIGHD:
6372                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6373                         break;
6374                 case OP_UNPACK_HIGHQ:
6375                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6376                         break;
6377                 case OP_UNPACK_HIGHPS:
6378                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6379                         break;
6380                 case OP_UNPACK_HIGHPD:
6381                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6382                         break;
6383
6384                 case OP_PACKW:
6385                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6386                         break;
6387                 case OP_PACKD:
6388                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6389                         break;
6390                 case OP_PACKW_UN:
6391                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6392                         break;
6393                 case OP_PACKD_UN:
6394                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6395                         break;
6396
6397                 case OP_PADDB_SAT_UN:
6398                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6399                         break;
6400                 case OP_PSUBB_SAT_UN:
6401                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6402                         break;
6403                 case OP_PADDW_SAT_UN:
6404                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6405                         break;
6406                 case OP_PSUBW_SAT_UN:
6407                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6408                         break;
6409
6410                 case OP_PADDB_SAT:
6411                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6412                         break;
6413                 case OP_PSUBB_SAT:
6414                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6415                         break;
6416                 case OP_PADDW_SAT:
6417                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6418                         break;
6419                 case OP_PSUBW_SAT:
6420                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6421                         break;
6422
6423                 case OP_PMULW:
6424                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6425                         break;
6426                 case OP_PMULD:
6427                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6428                         break;
6429                 case OP_PMULQ:
6430                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6431                         break;
6432                 case OP_PMULW_HIGH_UN:
6433                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6434                         break;
6435                 case OP_PMULW_HIGH:
6436                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6437                         break;
6438
6439                 case OP_PSHRW:
6440                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6441                         break;
6442                 case OP_PSHRW_REG:
6443                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6444                         break;
6445
6446                 case OP_PSARW:
6447                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6448                         break;
6449                 case OP_PSARW_REG:
6450                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6451                         break;
6452
6453                 case OP_PSHLW:
6454                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6455                         break;
6456                 case OP_PSHLW_REG:
6457                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6458                         break;
6459
6460                 case OP_PSHRD:
6461                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6462                         break;
6463                 case OP_PSHRD_REG:
6464                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6465                         break;
6466
6467                 case OP_PSARD:
6468                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6469                         break;
6470                 case OP_PSARD_REG:
6471                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6472                         break;
6473
6474                 case OP_PSHLD:
6475                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6476                         break;
6477                 case OP_PSHLD_REG:
6478                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6479                         break;
6480
6481                 case OP_PSHRQ:
6482                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6483                         break;
6484                 case OP_PSHRQ_REG:
6485                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6486                         break;
6487
6488                 /*TODO: This is appart of the sse spec but not added
6489                 case OP_PSARQ:
6490                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6491                         break;
6492                 case OP_PSARQ_REG:
6493                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6494                         break;
6495                 */
6496
6497                 case OP_PSHLQ:
6498                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6499                         break;
6500                 case OP_PSHLQ_REG:
6501                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6502                         break;
6503                 case OP_CVTDQ2PD:
6504                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6505                         break;
6506                 case OP_CVTDQ2PS:
6507                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6508                         break;
6509                 case OP_CVTPD2DQ:
6510                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6511                         break;
6512                 case OP_CVTPD2PS:
6513                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6514                         break;
6515                 case OP_CVTPS2DQ:
6516                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6517                         break;
6518                 case OP_CVTPS2PD:
6519                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6520                         break;
6521                 case OP_CVTTPD2DQ:
6522                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6523                         break;
6524                 case OP_CVTTPS2DQ:
6525                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6526                         break;
6527
6528                 case OP_ICONV_TO_X:
6529                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6530                         break;
6531                 case OP_EXTRACT_I4:
6532                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6533                         break;
6534                 case OP_EXTRACT_I8:
6535                         if (ins->inst_c0) {
6536                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6537                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6538                         } else {
6539                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6540                         }
6541                         break;
6542                 case OP_EXTRACT_I1:
6543                 case OP_EXTRACT_U1:
6544                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6545                         if (ins->inst_c0)
6546                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6547                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6548                         break;
6549                 case OP_EXTRACT_I2:
6550                 case OP_EXTRACT_U2:
6551                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6552                         if (ins->inst_c0)
6553                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6554                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6555                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6556                         break;
6557                 case OP_EXTRACT_R8:
6558                         if (ins->inst_c0)
6559                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6560                         else
6561                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6562                         break;
6563                 case OP_INSERT_I2:
6564                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6565                         break;
6566                 case OP_EXTRACTX_U2:
6567                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6568                         break;
6569                 case OP_INSERTX_U1_SLOW:
6570                         /*sreg1 is the extracted ireg (scratch)
6571                         /sreg2 is the to be inserted ireg (scratch)
6572                         /dreg is the xreg to receive the value*/
6573
6574                         /*clear the bits from the extracted word*/
6575                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6576                         /*shift the value to insert if needed*/
6577                         if (ins->inst_c0 & 1)
6578                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6579                         /*join them together*/
6580                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6581                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6582                         break;
6583                 case OP_INSERTX_I4_SLOW:
6584                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6585                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6586                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6587                         break;
6588                 case OP_INSERTX_I8_SLOW:
6589                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6590                         if (ins->inst_c0)
6591                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6592                         else
6593                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6594                         break;
6595
6596                 case OP_INSERTX_R4_SLOW:
6597                         switch (ins->inst_c0) {
6598                         case 0:
6599                                 if (cfg->r4fp)
6600                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6601                                 else
6602                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6603                                 break;
6604                         case 1:
6605                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6606                                 if (cfg->r4fp)
6607                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6608                                 else
6609                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6610                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6611                                 break;
6612                         case 2:
6613                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6614                                 if (cfg->r4fp)
6615                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6616                                 else
6617                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6618                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6619                                 break;
6620                         case 3:
6621                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6622                                 if (cfg->r4fp)
6623                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6624                                 else
6625                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6626                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6627                                 break;
6628                         }
6629                         break;
6630                 case OP_INSERTX_R8_SLOW:
6631                         if (ins->inst_c0)
6632                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6633                         else
6634                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6635                         break;
6636                 case OP_STOREX_MEMBASE_REG:
6637                 case OP_STOREX_MEMBASE:
6638                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6639                         break;
6640                 case OP_LOADX_MEMBASE:
6641                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6642                         break;
6643                 case OP_LOADX_ALIGNED_MEMBASE:
6644                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6645                         break;
6646                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6647                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6648                         break;
6649                 case OP_STOREX_NTA_MEMBASE_REG:
6650                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6651                         break;
6652                 case OP_PREFETCH_MEMBASE:
6653                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6654                         break;
6655
6656                 case OP_XMOVE:
6657                         /*FIXME the peephole pass should have killed this*/
6658                         if (ins->dreg != ins->sreg1)
6659                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6660                         break;
6661                 case OP_XZERO:
6662                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6663                         break;
6664                 case OP_ICONV_TO_R4_RAW:
6665                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6666                         break;
6667
6668                 case OP_FCONV_TO_R8_X:
6669                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6670                         break;
6671
6672                 case OP_XCONV_R8_TO_I4:
6673                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6674                         switch (ins->backend.source_opcode) {
6675                         case OP_FCONV_TO_I1:
6676                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6677                                 break;
6678                         case OP_FCONV_TO_U1:
6679                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6680                                 break;
6681                         case OP_FCONV_TO_I2:
6682                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6683                                 break;
6684                         case OP_FCONV_TO_U2:
6685                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6686                                 break;
6687                         }
6688                         break;
6689
6690                 case OP_EXPAND_I2:
6691                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6692                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6693                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6694                         break;
6695                 case OP_EXPAND_I4:
6696                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6697                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6698                         break;
6699                 case OP_EXPAND_I8:
6700                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6701                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6702                         break;
6703                 case OP_EXPAND_R4:
6704                         if (cfg->r4fp) {
6705                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6706                         } else {
6707                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6708                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6709                         }
6710                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6711                         break;
6712                 case OP_EXPAND_R8:
6713                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6714                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6715                         break;
6716 #endif
6717                 case OP_LIVERANGE_START: {
6718                         if (cfg->verbose_level > 1)
6719                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6720                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6721                         break;
6722                 }
6723                 case OP_LIVERANGE_END: {
6724                         if (cfg->verbose_level > 1)
6725                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6726                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6727                         break;
6728                 }
6729                 case OP_GC_SAFE_POINT: {
6730                         const char *polling_func = NULL;
6731                         int compare_val = 0;
6732                         guint8 *br [1];
6733
6734 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6735                         polling_func = "mono_nacl_gc";
6736                         compare_val = 0xFFFFFFFF;
6737 #else
6738                         g_assert (mono_threads_is_coop_enabled ());
6739                         polling_func = "mono_threads_state_poll";
6740                         compare_val = 1;
6741 #endif
6742
6743                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6744                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6745                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6746                         amd64_patch (br[0], code);
6747                         break;
6748                 }
6749
6750                 case OP_GC_LIVENESS_DEF:
6751                 case OP_GC_LIVENESS_USE:
6752                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6753                         ins->backend.pc_offset = code - cfg->native_code;
6754                         break;
6755                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6756                         ins->backend.pc_offset = code - cfg->native_code;
6757                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6758                         break;
6759                 default:
6760                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6761                         g_assert_not_reached ();
6762                 }
6763
6764                 if ((code - cfg->native_code - offset) > max_len) {
6765 #if !defined(__native_client_codegen__)
6766                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6767                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6768                         g_assert_not_reached ();
6769 #endif
6770                 }
6771         }
6772
6773         cfg->code_len = code - cfg->native_code;
6774 }
6775
6776 #endif /* DISABLE_JIT */
6777
6778 void
6779 mono_arch_register_lowlevel_calls (void)
6780 {
6781         /* The signature doesn't matter */
6782         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6783 }
6784
6785 void
6786 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6787 {
6788         unsigned char *ip = ji->ip.i + code;
6789
6790         /*
6791          * Debug code to help track down problems where the target of a near call is
6792          * is not valid.
6793          */
6794         if (amd64_is_near_call (ip)) {
6795                 gint64 disp = (guint8*)target - (guint8*)ip;
6796
6797                 if (!amd64_is_imm32 (disp)) {
6798                         printf ("TYPE: %d\n", ji->type);
6799                         switch (ji->type) {
6800                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6801                                 printf ("V: %s\n", ji->data.name);
6802                                 break;
6803                         case MONO_PATCH_INFO_METHOD_JUMP:
6804                         case MONO_PATCH_INFO_METHOD:
6805                                 printf ("V: %s\n", ji->data.method->name);
6806                                 break;
6807                         default:
6808                                 break;
6809                         }
6810                 }
6811         }
6812
6813         amd64_patch (ip, (gpointer)target);
6814 }
6815
6816 #ifndef DISABLE_JIT
6817
6818 static int
6819 get_max_epilog_size (MonoCompile *cfg)
6820 {
6821         int max_epilog_size = 16;
6822
6823         if (cfg->method->save_lmf)
6824                 max_epilog_size += 256;
6825
6826         if (mono_jit_trace_calls != NULL)
6827                 max_epilog_size += 50;
6828
6829         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6830                 max_epilog_size += 50;
6831
6832         max_epilog_size += (AMD64_NREG * 2);
6833
6834         return max_epilog_size;
6835 }
6836
6837 /*
6838  * This macro is used for testing whenever the unwinder works correctly at every point
6839  * where an async exception can happen.
6840  */
6841 /* This will generate a SIGSEGV at the given point in the code */
6842 #define async_exc_point(code) do { \
6843     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6844          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6845              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6846          cfg->arch.async_point_count ++; \
6847     } \
6848 } while (0)
6849
6850 guint8 *
6851 mono_arch_emit_prolog (MonoCompile *cfg)
6852 {
6853         MonoMethod *method = cfg->method;
6854         MonoBasicBlock *bb;
6855         MonoMethodSignature *sig;
6856         MonoInst *ins;
6857         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6858         guint8 *code;
6859         CallInfo *cinfo;
6860         MonoInst *lmf_var = cfg->lmf_var;
6861         gboolean args_clobbered = FALSE;
6862         gboolean trace = FALSE;
6863 #ifdef __native_client_codegen__
6864         guint alignment_check;
6865 #endif
6866
6867         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6868
6869 #if defined(__default_codegen__)
6870         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6871 #elif defined(__native_client_codegen__)
6872         /* native_code_alloc is not 32-byte aligned, native_code is. */
6873         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6874
6875         /* Align native_code to next nearest kNaclAlignment byte. */
6876         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6877         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6878
6879         code = cfg->native_code;
6880
6881         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6882         g_assert (alignment_check == 0);
6883 #endif
6884
6885         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6886                 trace = TRUE;
6887
6888         /* Amount of stack space allocated by register saving code */
6889         pos = 0;
6890
6891         /* Offset between RSP and the CFA */
6892         cfa_offset = 0;
6893
6894         /*
6895          * The prolog consists of the following parts:
6896          * FP present:
6897          * - push rbp, mov rbp, rsp
6898          * - save callee saved regs using pushes
6899          * - allocate frame
6900          * - save rgctx if needed
6901          * - save lmf if needed
6902          * FP not present:
6903          * - allocate frame
6904          * - save rgctx if needed
6905          * - save lmf if needed
6906          * - save callee saved regs using moves
6907          */
6908
6909         // CFA = sp + 8
6910         cfa_offset = 8;
6911         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6912         // IP saved at CFA - 8
6913         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6914         async_exc_point (code);
6915         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6916
6917         if (!cfg->arch.omit_fp) {
6918                 amd64_push_reg (code, AMD64_RBP);
6919                 cfa_offset += 8;
6920                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6921                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6922                 async_exc_point (code);
6923 #ifdef TARGET_WIN32
6924                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6925 #endif
6926                 /* These are handled automatically by the stack marking code */
6927                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6928
6929                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6930                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6931                 async_exc_point (code);
6932 #ifdef TARGET_WIN32
6933                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6934 #endif
6935         }
6936
6937         /* The param area is always at offset 0 from sp */
6938         /* This needs to be allocated here, since it has to come after the spill area */
6939         if (cfg->param_area) {
6940                 if (cfg->arch.omit_fp)
6941                         // FIXME:
6942                         g_assert_not_reached ();
6943                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6944         }
6945
6946         if (cfg->arch.omit_fp) {
6947                 /*
6948                  * On enter, the stack is misaligned by the pushing of the return
6949                  * address. It is either made aligned by the pushing of %rbp, or by
6950                  * this.
6951                  */
6952                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6953                 if ((alloc_size % 16) == 0) {
6954                         alloc_size += 8;
6955                         /* Mark the padding slot as NOREF */
6956                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6957                 }
6958         } else {
6959                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6960                 if (cfg->stack_offset != alloc_size) {
6961                         /* Mark the padding slot as NOREF */
6962                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6963                 }
6964                 cfg->arch.sp_fp_offset = alloc_size;
6965                 alloc_size -= pos;
6966         }
6967
6968         cfg->arch.stack_alloc_size = alloc_size;
6969
6970         /* Allocate stack frame */
6971         if (alloc_size) {
6972                 /* See mono_emit_stack_alloc */
6973 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6974                 guint32 remaining_size = alloc_size;
6975                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6976                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6977                 guint32 offset = code - cfg->native_code;
6978                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6979                         while (required_code_size >= (cfg->code_size - offset))
6980                                 cfg->code_size *= 2;
6981                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6982                         code = cfg->native_code + offset;
6983                         cfg->stat_code_reallocs++;
6984                 }
6985
6986                 while (remaining_size >= 0x1000) {
6987                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6988                         if (cfg->arch.omit_fp) {
6989                                 cfa_offset += 0x1000;
6990                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6991                         }
6992                         async_exc_point (code);
6993 #ifdef TARGET_WIN32
6994                         if (cfg->arch.omit_fp)
6995                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6996 #endif
6997
6998                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6999                         remaining_size -= 0x1000;
7000                 }
7001                 if (remaining_size) {
7002                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7003                         if (cfg->arch.omit_fp) {
7004                                 cfa_offset += remaining_size;
7005                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7006                                 async_exc_point (code);
7007                         }
7008 #ifdef TARGET_WIN32
7009                         if (cfg->arch.omit_fp)
7010                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7011 #endif
7012                 }
7013 #else
7014                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7015                 if (cfg->arch.omit_fp) {
7016                         cfa_offset += alloc_size;
7017                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7018                         async_exc_point (code);
7019                 }
7020 #endif
7021         }
7022
7023         /* Stack alignment check */
7024 #if 0
7025         {
7026                 guint8 *buf;
7027
7028                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7029                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7030                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7031                 buf = code;
7032                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
7033                 amd64_breakpoint (code);
7034                 amd64_patch (buf, code);
7035         }
7036 #endif
7037
7038         if (mini_get_debug_options ()->init_stacks) {
7039                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7040
7041                 /* Save registers to the red zone */
7042                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7043                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7044
7045                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7046                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7047                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7048
7049                 amd64_cld (code);
7050 #if defined(__default_codegen__)
7051                 amd64_prefix (code, X86_REP_PREFIX);
7052                 amd64_stosl (code);
7053 #elif defined(__native_client_codegen__)
7054                 /* NaCl stos pseudo-instruction */
7055                 amd64_codegen_pre (code);
7056                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7057                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7058                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7059                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7060                 amd64_prefix (code, X86_REP_PREFIX);
7061                 amd64_stosl (code);
7062                 amd64_codegen_post (code);
7063 #endif /* __native_client_codegen__ */
7064
7065                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7066                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7067         }
7068
7069         /* Save LMF */
7070         if (method->save_lmf)
7071                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7072
7073         /* Save callee saved registers */
7074         if (cfg->arch.omit_fp) {
7075                 save_area_offset = cfg->arch.reg_save_area_offset;
7076                 /* Save caller saved registers after sp is adjusted */
7077                 /* The registers are saved at the bottom of the frame */
7078                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7079         } else {
7080                 /* The registers are saved just below the saved rbp */
7081                 save_area_offset = cfg->arch.reg_save_area_offset;
7082         }
7083
7084         for (i = 0; i < AMD64_NREG; ++i) {
7085                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7086                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7087
7088                         if (cfg->arch.omit_fp) {
7089                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7090                                 /* These are handled automatically by the stack marking code */
7091                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7092                         } else {
7093                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7094                                 // FIXME: GC
7095                         }
7096
7097                         save_area_offset += 8;
7098                         async_exc_point (code);
7099                 }
7100         }
7101
7102         /* store runtime generic context */
7103         if (cfg->rgctx_var) {
7104                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7105                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7106
7107                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7108
7109                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7110                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7111         }
7112
7113         /* compute max_length in order to use short forward jumps */
7114         max_epilog_size = get_max_epilog_size (cfg);
7115         if (cfg->opt & MONO_OPT_BRANCH) {
7116                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7117                         MonoInst *ins;
7118                         int max_length = 0;
7119
7120                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7121                                 max_length += 6;
7122                         /* max alignment for loops */
7123                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7124                                 max_length += LOOP_ALIGNMENT;
7125 #ifdef __native_client_codegen__
7126                         /* max alignment for native client */
7127                         max_length += kNaClAlignment;
7128 #endif
7129
7130                         MONO_BB_FOR_EACH_INS (bb, ins) {
7131 #ifdef __native_client_codegen__
7132                                 {
7133                                         int space_in_block = kNaClAlignment -
7134                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7135                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7136                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7137                                                 max_length += space_in_block;
7138                                         }
7139                                 }
7140 #endif  /*__native_client_codegen__*/
7141                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7142                         }
7143
7144                         /* Take prolog and epilog instrumentation into account */
7145                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7146                                 max_length += max_epilog_size;
7147
7148                         bb->max_length = max_length;
7149                 }
7150         }
7151
7152         sig = mono_method_signature (method);
7153         pos = 0;
7154
7155         cinfo = (CallInfo *)cfg->arch.cinfo;
7156
7157         if (sig->ret->type != MONO_TYPE_VOID) {
7158                 /* Save volatile arguments to the stack */
7159                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7160                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7161         }
7162
7163         /* Keep this in sync with emit_load_volatile_arguments */
7164         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7165                 ArgInfo *ainfo = cinfo->args + i;
7166
7167                 ins = cfg->args [i];
7168
7169                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7170                         /* Unused arguments */
7171                         continue;
7172
7173                 /* Save volatile arguments to the stack */
7174                 if (ins->opcode != OP_REGVAR) {
7175                         switch (ainfo->storage) {
7176                         case ArgInIReg: {
7177                                 guint32 size = 8;
7178
7179                                 /* FIXME: I1 etc */
7180                                 /*
7181                                 if (stack_offset & 0x1)
7182                                         size = 1;
7183                                 else if (stack_offset & 0x2)
7184                                         size = 2;
7185                                 else if (stack_offset & 0x4)
7186                                         size = 4;
7187                                 else
7188                                         size = 8;
7189                                 */
7190                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7191
7192                                 /*
7193                                  * Save the original location of 'this',
7194                                  * get_generic_info_from_stack_frame () needs this to properly look up
7195                                  * the argument value during the handling of async exceptions.
7196                                  */
7197                                 if (ins == cfg->args [0]) {
7198                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7199                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7200                                 }
7201                                 break;
7202                         }
7203                         case ArgInFloatSSEReg:
7204                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7205                                 break;
7206                         case ArgInDoubleSSEReg:
7207                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7208                                 break;
7209                         case ArgValuetypeInReg:
7210                                 for (quad = 0; quad < 2; quad ++) {
7211                                         switch (ainfo->pair_storage [quad]) {
7212                                         case ArgInIReg:
7213                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7214                                                 break;
7215                                         case ArgInFloatSSEReg:
7216                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7217                                                 break;
7218                                         case ArgInDoubleSSEReg:
7219                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7220                                                 break;
7221                                         case ArgNone:
7222                                                 break;
7223                                         default:
7224                                                 g_assert_not_reached ();
7225                                         }
7226                                 }
7227                                 break;
7228                         case ArgValuetypeAddrInIReg:
7229                                 if (ainfo->pair_storage [0] == ArgInIReg)
7230                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7231                                 break;
7232                         case ArgGSharedVtInReg:
7233                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7234                                 break;
7235                         default:
7236                                 break;
7237                         }
7238                 } else {
7239                         /* Argument allocated to (non-volatile) register */
7240                         switch (ainfo->storage) {
7241                         case ArgInIReg:
7242                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7243                                 break;
7244                         case ArgOnStack:
7245                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7246                                 break;
7247                         default:
7248                                 g_assert_not_reached ();
7249                         }
7250
7251                         if (ins == cfg->args [0]) {
7252                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7253                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7254                         }
7255                 }
7256         }
7257
7258         if (cfg->method->save_lmf)
7259                 args_clobbered = TRUE;
7260
7261         if (trace) {
7262                 args_clobbered = TRUE;
7263                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7264         }
7265
7266         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7267                 args_clobbered = TRUE;
7268
7269         /*
7270          * Optimize the common case of the first bblock making a call with the same
7271          * arguments as the method. This works because the arguments are still in their
7272          * original argument registers.
7273          * FIXME: Generalize this
7274          */
7275         if (!args_clobbered) {
7276                 MonoBasicBlock *first_bb = cfg->bb_entry;
7277                 MonoInst *next;
7278                 int filter = FILTER_IL_SEQ_POINT;
7279
7280                 next = mono_bb_first_inst (first_bb, filter);
7281                 if (!next && first_bb->next_bb) {
7282                         first_bb = first_bb->next_bb;
7283                         next = mono_bb_first_inst (first_bb, filter);
7284                 }
7285
7286                 if (first_bb->in_count > 1)
7287                         next = NULL;
7288
7289                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7290                         ArgInfo *ainfo = cinfo->args + i;
7291                         gboolean match = FALSE;
7292
7293                         ins = cfg->args [i];
7294                         if (ins->opcode != OP_REGVAR) {
7295                                 switch (ainfo->storage) {
7296                                 case ArgInIReg: {
7297                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7298                                                 if (next->dreg == ainfo->reg) {
7299                                                         NULLIFY_INS (next);
7300                                                         match = TRUE;
7301                                                 } else {
7302                                                         next->opcode = OP_MOVE;
7303                                                         next->sreg1 = ainfo->reg;
7304                                                         /* Only continue if the instruction doesn't change argument regs */
7305                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7306                                                                 match = TRUE;
7307                                                 }
7308                                         }
7309                                         break;
7310                                 }
7311                                 default:
7312                                         break;
7313                                 }
7314                         } else {
7315                                 /* Argument allocated to (non-volatile) register */
7316                                 switch (ainfo->storage) {
7317                                 case ArgInIReg:
7318                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7319                                                 NULLIFY_INS (next);
7320                                                 match = TRUE;
7321                                         }
7322                                         break;
7323                                 default:
7324                                         break;
7325                                 }
7326                         }
7327
7328                         if (match) {
7329                                 next = mono_inst_next (next, filter);
7330                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7331                                 if (!next)
7332                                         break;
7333                         }
7334                 }
7335         }
7336
7337         if (cfg->gen_sdb_seq_points) {
7338                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7339
7340                 /* Initialize seq_point_info_var */
7341                 if (cfg->compile_aot) {
7342                         /* Initialize the variable from a GOT slot */
7343                         /* Same as OP_AOTCONST */
7344                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7345                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7346                         g_assert (info_var->opcode == OP_REGOFFSET);
7347                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7348                 }
7349
7350                 if (cfg->compile_aot) {
7351                         /* Initialize ss_tramp_var */
7352                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7353                         g_assert (ins->opcode == OP_REGOFFSET);
7354
7355                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7356                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7357                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7358                 } else {
7359                         /* Initialize ss_tramp_var */
7360                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7361                         g_assert (ins->opcode == OP_REGOFFSET);
7362
7363                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7364                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7365
7366                         /* Initialize bp_tramp_var */
7367                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7368                         g_assert (ins->opcode == OP_REGOFFSET);
7369
7370                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7371                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7372                 }
7373         }
7374
7375         cfg->code_len = code - cfg->native_code;
7376
7377         g_assert (cfg->code_len < cfg->code_size);
7378
7379         return code;
7380 }
7381
7382 void
7383 mono_arch_emit_epilog (MonoCompile *cfg)
7384 {
7385         MonoMethod *method = cfg->method;
7386         int quad, i;
7387         guint8 *code;
7388         int max_epilog_size;
7389         CallInfo *cinfo;
7390         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7391         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7392
7393         max_epilog_size = get_max_epilog_size (cfg);
7394
7395         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7396                 cfg->code_size *= 2;
7397                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7398                 cfg->stat_code_reallocs++;
7399         }
7400         code = cfg->native_code + cfg->code_len;
7401
7402         cfg->has_unwind_info_for_epilog = TRUE;
7403
7404         /* Mark the start of the epilog */
7405         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7406
7407         /* Save the uwind state which is needed by the out-of-line code */
7408         mono_emit_unwind_op_remember_state (cfg, code);
7409
7410         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7411                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7412
7413         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7414
7415         if (method->save_lmf) {
7416                 /* check if we need to restore protection of the stack after a stack overflow */
7417                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7418                         guint8 *patch;
7419                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7420                         /* we load the value in a separate instruction: this mechanism may be
7421                          * used later as a safer way to do thread interruption
7422                          */
7423                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7424                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7425                         patch = code;
7426                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7427                         /* note that the call trampoline will preserve eax/edx */
7428                         x86_call_reg (code, X86_ECX);
7429                         x86_patch (patch, code);
7430                 } else {
7431                         /* FIXME: maybe save the jit tls in the prolog */
7432                 }
7433                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7434                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7435                 }
7436         }
7437
7438         /* Restore callee saved regs */
7439         for (i = 0; i < AMD64_NREG; ++i) {
7440                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7441                         /* Restore only used_int_regs, not arch.saved_iregs */
7442                         if (cfg->used_int_regs & (1 << i)) {
7443                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7444                                 mono_emit_unwind_op_same_value (cfg, code, i);
7445                                 async_exc_point (code);
7446                         }
7447                         save_area_offset += 8;
7448                 }
7449         }
7450
7451         /* Load returned vtypes into registers if needed */
7452         cinfo = (CallInfo *)cfg->arch.cinfo;
7453         if (cinfo->ret.storage == ArgValuetypeInReg) {
7454                 ArgInfo *ainfo = &cinfo->ret;
7455                 MonoInst *inst = cfg->ret;
7456
7457                 for (quad = 0; quad < 2; quad ++) {
7458                         switch (ainfo->pair_storage [quad]) {
7459                         case ArgInIReg:
7460                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7461                                 break;
7462                         case ArgInFloatSSEReg:
7463                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7464                                 break;
7465                         case ArgInDoubleSSEReg:
7466                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7467                                 break;
7468                         case ArgNone:
7469                                 break;
7470                         default:
7471                                 g_assert_not_reached ();
7472                         }
7473                 }
7474         }
7475
7476         if (cfg->arch.omit_fp) {
7477                 if (cfg->arch.stack_alloc_size) {
7478                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7479                 }
7480         } else {
7481                 amd64_leave (code);
7482                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7483         }
7484         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7485         async_exc_point (code);
7486         amd64_ret (code);
7487
7488         /* Restore the unwind state to be the same as before the epilog */
7489         mono_emit_unwind_op_restore_state (cfg, code);
7490
7491         cfg->code_len = code - cfg->native_code;
7492
7493         g_assert (cfg->code_len < cfg->code_size);
7494 }
7495
7496 void
7497 mono_arch_emit_exceptions (MonoCompile *cfg)
7498 {
7499         MonoJumpInfo *patch_info;
7500         int nthrows, i;
7501         guint8 *code;
7502         MonoClass *exc_classes [16];
7503         guint8 *exc_throw_start [16], *exc_throw_end [16];
7504         guint32 code_size = 0;
7505
7506         /* Compute needed space */
7507         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7508                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7509                         code_size += 40;
7510                 if (patch_info->type == MONO_PATCH_INFO_R8)
7511                         code_size += 8 + 15; /* sizeof (double) + alignment */
7512                 if (patch_info->type == MONO_PATCH_INFO_R4)
7513                         code_size += 4 + 15; /* sizeof (float) + alignment */
7514                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7515                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7516         }
7517
7518 #ifdef __native_client_codegen__
7519         /* Give us extra room on Native Client.  This could be   */
7520         /* more carefully calculated, but bundle alignment makes */
7521         /* it much trickier, so *2 like other places is good.    */
7522         code_size *= 2;
7523 #endif
7524
7525         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7526                 cfg->code_size *= 2;
7527                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7528                 cfg->stat_code_reallocs++;
7529         }
7530
7531         code = cfg->native_code + cfg->code_len;
7532
7533         /* add code to raise exceptions */
7534         nthrows = 0;
7535         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7536                 switch (patch_info->type) {
7537                 case MONO_PATCH_INFO_EXC: {
7538                         MonoClass *exc_class;
7539                         guint8 *buf, *buf2;
7540                         guint32 throw_ip;
7541
7542                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7543
7544                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7545                         throw_ip = patch_info->ip.i;
7546
7547                         //x86_breakpoint (code);
7548                         /* Find a throw sequence for the same exception class */
7549                         for (i = 0; i < nthrows; ++i)
7550                                 if (exc_classes [i] == exc_class)
7551                                         break;
7552                         if (i < nthrows) {
7553                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7554                                 x86_jump_code (code, exc_throw_start [i]);
7555                                 patch_info->type = MONO_PATCH_INFO_NONE;
7556                         }
7557                         else {
7558                                 buf = code;
7559                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7560                                 buf2 = code;
7561
7562                                 if (nthrows < 16) {
7563                                         exc_classes [nthrows] = exc_class;
7564                                         exc_throw_start [nthrows] = code;
7565                                 }
7566                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7567
7568                                 patch_info->type = MONO_PATCH_INFO_NONE;
7569
7570                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7571
7572                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7573                                 while (buf < buf2)
7574                                         x86_nop (buf);
7575
7576                                 if (nthrows < 16) {
7577                                         exc_throw_end [nthrows] = code;
7578                                         nthrows ++;
7579                                 }
7580                         }
7581                         break;
7582                 }
7583                 default:
7584                         /* do nothing */
7585                         break;
7586                 }
7587                 g_assert(code < cfg->native_code + cfg->code_size);
7588         }
7589
7590         /* Handle relocations with RIP relative addressing */
7591         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7592                 gboolean remove = FALSE;
7593                 guint8 *orig_code = code;
7594
7595                 switch (patch_info->type) {
7596                 case MONO_PATCH_INFO_R8:
7597                 case MONO_PATCH_INFO_R4: {
7598                         guint8 *pos, *patch_pos;
7599                         guint32 target_pos;
7600
7601                         /* The SSE opcodes require a 16 byte alignment */
7602 #if defined(__default_codegen__)
7603                         code = (guint8*)ALIGN_TO (code, 16);
7604 #elif defined(__native_client_codegen__)
7605                         {
7606                                 /* Pad this out with HLT instructions  */
7607                                 /* or we can get garbage bytes emitted */
7608                                 /* which will fail validation          */
7609                                 guint8 *aligned_code;
7610                                 /* extra align to make room for  */
7611                                 /* mov/push below                      */
7612                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7613                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7614                                 /* The technique of hiding data in an  */
7615                                 /* instruction has a problem here: we  */
7616                                 /* need the data aligned to a 16-byte  */
7617                                 /* boundary but the instruction cannot */
7618                                 /* cross the bundle boundary. so only  */
7619                                 /* odd multiples of 16 can be used     */
7620                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7621                                         aligned_code += 16;
7622                                 }
7623                                 while (code < aligned_code) {
7624                                         *(code++) = 0xf4; /* hlt */
7625                                 }
7626                         }
7627 #endif
7628
7629                         pos = cfg->native_code + patch_info->ip.i;
7630                         if (IS_REX (pos [1])) {
7631                                 patch_pos = pos + 5;
7632                                 target_pos = code - pos - 9;
7633                         }
7634                         else {
7635                                 patch_pos = pos + 4;
7636                                 target_pos = code - pos - 8;
7637                         }
7638
7639                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7640 #ifdef __native_client_codegen__
7641                                 /* Hide 64-bit data in a         */
7642                                 /* "mov imm64, r11" instruction. */
7643                                 /* write it before the start of  */
7644                                 /* the data*/
7645                                 *(code-2) = 0x49; /* prefix      */
7646                                 *(code-1) = 0xbb; /* mov X, %r11 */
7647 #endif
7648                                 *(double*)code = *(double*)patch_info->data.target;
7649                                 code += sizeof (double);
7650                         } else {
7651 #ifdef __native_client_codegen__
7652                                 /* Hide 32-bit data in a        */
7653                                 /* "push imm32" instruction.    */
7654                                 *(code-1) = 0x68; /* push */
7655 #endif
7656                                 *(float*)code = *(float*)patch_info->data.target;
7657                                 code += sizeof (float);
7658                         }
7659
7660                         *(guint32*)(patch_pos) = target_pos;
7661
7662                         remove = TRUE;
7663                         break;
7664                 }
7665                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7666                         guint8 *pos;
7667
7668                         if (cfg->compile_aot)
7669                                 continue;
7670
7671                         /*loading is faster against aligned addresses.*/
7672                         code = (guint8*)ALIGN_TO (code, 8);
7673                         memset (orig_code, 0, code - orig_code);
7674
7675                         pos = cfg->native_code + patch_info->ip.i;
7676
7677                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7678                         if (IS_REX (pos [1]))
7679                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7680                         else
7681                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7682
7683                         *(gpointer*)code = (gpointer)patch_info->data.target;
7684                         code += sizeof (gpointer);
7685
7686                         remove = TRUE;
7687                         break;
7688                 }
7689                 default:
7690                         break;
7691                 }
7692
7693                 if (remove) {
7694                         if (patch_info == cfg->patch_info)
7695                                 cfg->patch_info = patch_info->next;
7696                         else {
7697                                 MonoJumpInfo *tmp;
7698
7699                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7700                                         ;
7701                                 tmp->next = patch_info->next;
7702                         }
7703                 }
7704                 g_assert (code < cfg->native_code + cfg->code_size);
7705         }
7706
7707         cfg->code_len = code - cfg->native_code;
7708
7709         g_assert (cfg->code_len < cfg->code_size);
7710
7711 }
7712
7713 #endif /* DISABLE_JIT */
7714
7715 void*
7716 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7717 {
7718         guchar *code = (guchar *)p;
7719         MonoMethodSignature *sig;
7720         MonoInst *inst;
7721         int i, n, stack_area = 0;
7722
7723         /* Keep this in sync with mono_arch_get_argument_info */
7724
7725         if (enable_arguments) {
7726                 /* Allocate a new area on the stack and save arguments there */
7727                 sig = mono_method_signature (cfg->method);
7728
7729                 n = sig->param_count + sig->hasthis;
7730
7731                 stack_area = ALIGN_TO (n * 8, 16);
7732
7733                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7734
7735                 for (i = 0; i < n; ++i) {
7736                         inst = cfg->args [i];
7737
7738                         if (inst->opcode == OP_REGVAR)
7739                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7740                         else {
7741                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7742                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7743                         }
7744                 }
7745         }
7746
7747         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7748         amd64_set_reg_template (code, AMD64_ARG_REG1);
7749         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7750         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7751
7752         if (enable_arguments)
7753                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7754
7755         return code;
7756 }
7757
7758 enum {
7759         SAVE_NONE,
7760         SAVE_STRUCT,
7761         SAVE_EAX,
7762         SAVE_EAX_EDX,
7763         SAVE_XMM
7764 };
7765
7766 void*
7767 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7768 {
7769         guchar *code = (guchar *)p;
7770         int save_mode = SAVE_NONE;
7771         MonoMethod *method = cfg->method;
7772         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7773         int i;
7774
7775         switch (ret_type->type) {
7776         case MONO_TYPE_VOID:
7777                 /* special case string .ctor icall */
7778                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7779                         save_mode = SAVE_EAX;
7780                 else
7781                         save_mode = SAVE_NONE;
7782                 break;
7783         case MONO_TYPE_I8:
7784         case MONO_TYPE_U8:
7785                 save_mode = SAVE_EAX;
7786                 break;
7787         case MONO_TYPE_R4:
7788         case MONO_TYPE_R8:
7789                 save_mode = SAVE_XMM;
7790                 break;
7791         case MONO_TYPE_GENERICINST:
7792                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7793                         save_mode = SAVE_EAX;
7794                         break;
7795                 }
7796                 /* Fall through */
7797         case MONO_TYPE_VALUETYPE:
7798                 save_mode = SAVE_STRUCT;
7799                 break;
7800         default:
7801                 save_mode = SAVE_EAX;
7802                 break;
7803         }
7804
7805         /* Save the result and copy it into the proper argument register */
7806         switch (save_mode) {
7807         case SAVE_EAX:
7808                 amd64_push_reg (code, AMD64_RAX);
7809                 /* Align stack */
7810                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7811                 if (enable_arguments)
7812                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7813                 break;
7814         case SAVE_STRUCT:
7815                 /* FIXME: */
7816                 if (enable_arguments)
7817                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7818                 break;
7819         case SAVE_XMM:
7820                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7821                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7822                 /* Align stack */
7823                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7824                 /*
7825                  * The result is already in the proper argument register so no copying
7826                  * needed.
7827                  */
7828                 break;
7829         case SAVE_NONE:
7830                 break;
7831         default:
7832                 g_assert_not_reached ();
7833         }
7834
7835         /* Set %al since this is a varargs call */
7836         if (save_mode == SAVE_XMM)
7837                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7838         else
7839                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7840
7841         if (preserve_argument_registers) {
7842                 for (i = 0; i < PARAM_REGS; ++i)
7843                         amd64_push_reg (code, param_regs [i]);
7844         }
7845
7846         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7847         amd64_set_reg_template (code, AMD64_ARG_REG1);
7848         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7849
7850         if (preserve_argument_registers) {
7851                 for (i = PARAM_REGS - 1; i >= 0; --i)
7852                         amd64_pop_reg (code, param_regs [i]);
7853         }
7854
7855         /* Restore result */
7856         switch (save_mode) {
7857         case SAVE_EAX:
7858                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7859                 amd64_pop_reg (code, AMD64_RAX);
7860                 break;
7861         case SAVE_STRUCT:
7862                 /* FIXME: */
7863                 break;
7864         case SAVE_XMM:
7865                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7866                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7867                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7868                 break;
7869         case SAVE_NONE:
7870                 break;
7871         default:
7872                 g_assert_not_reached ();
7873         }
7874
7875         return code;
7876 }
7877
7878 void
7879 mono_arch_flush_icache (guint8 *code, gint size)
7880 {
7881         /* Not needed */
7882 }
7883
7884 void
7885 mono_arch_flush_register_windows (void)
7886 {
7887 }
7888
7889 gboolean
7890 mono_arch_is_inst_imm (gint64 imm)
7891 {
7892         return amd64_use_imm32 (imm);
7893 }
7894
7895 /*
7896  * Determine whenever the trap whose info is in SIGINFO is caused by
7897  * integer overflow.
7898  */
7899 gboolean
7900 mono_arch_is_int_overflow (void *sigctx, void *info)
7901 {
7902         MonoContext ctx;
7903         guint8* rip;
7904         int reg;
7905         gint64 value;
7906
7907         mono_sigctx_to_monoctx (sigctx, &ctx);
7908
7909         rip = (guint8*)ctx.gregs [AMD64_RIP];
7910
7911         if (IS_REX (rip [0])) {
7912                 reg = amd64_rex_b (rip [0]);
7913                 rip ++;
7914         }
7915         else
7916                 reg = 0;
7917
7918         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7919                 /* idiv REG */
7920                 reg += x86_modrm_rm (rip [1]);
7921
7922                 value = ctx.gregs [reg];
7923
7924                 if (value == -1)
7925                         return TRUE;
7926         }
7927
7928         return FALSE;
7929 }
7930
7931 guint32
7932 mono_arch_get_patch_offset (guint8 *code)
7933 {
7934         return 3;
7935 }
7936
7937 /**
7938  * mono_breakpoint_clean_code:
7939  *
7940  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7941  * breakpoints in the original code, they are removed in the copy.
7942  *
7943  * Returns TRUE if no sw breakpoint was present.
7944  */
7945 gboolean
7946 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7947 {
7948         /*
7949          * If method_start is non-NULL we need to perform bound checks, since we access memory
7950          * at code - offset we could go before the start of the method and end up in a different
7951          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7952          * instead.
7953          */
7954         if (!method_start || code - offset >= method_start) {
7955                 memcpy (buf, code - offset, size);
7956         } else {
7957                 int diff = code - method_start;
7958                 memset (buf, 0, size);
7959                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7960         }
7961         return TRUE;
7962 }
7963
7964 #if defined(__native_client_codegen__)
7965 /* For membase calls, we want the base register. for Native Client,  */
7966 /* all indirect calls have the following sequence with the given sizes: */
7967 /* mov %eXX,%eXX                                [2-3]   */
7968 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7969 /* and $0xffffffffffffffe0,%r11d                [4]     */
7970 /* add %r15,%r11                                [3]     */
7971 /* callq *%r11                                  [3]     */
7972
7973
7974 /* Determine if code points to a NaCl call-through-register sequence, */
7975 /* (i.e., the last 3 instructions listed above) */
7976 int
7977 is_nacl_call_reg_sequence(guint8* code)
7978 {
7979         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7980                                "\x4d\x03\xdf"     /* add */
7981                                "\x41\xff\xd3";   /* call */
7982         return memcmp(code, sequence, 10) == 0;
7983 }
7984
7985 /* Determine if code points to the first opcode of the mov membase component */
7986 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7987 /* (there could be a REX prefix before the opcode but it is ignored) */
7988 static int
7989 is_nacl_indirect_call_membase_sequence(guint8* code)
7990 {
7991                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7992         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7993                /* and that src reg = dest reg */
7994                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7995                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7996                IS_REX(code[2]) &&
7997                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7998                /* and has dst of r11 and base of r15 */
7999                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8000                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8001 }
8002 #endif /* __native_client_codegen__ */
8003
8004 int
8005 mono_arch_get_this_arg_reg (guint8 *code)
8006 {
8007         return AMD64_ARG_REG1;
8008 }
8009
8010 gpointer
8011 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8012 {
8013         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8014 }
8015
8016 #define MAX_ARCH_DELEGATE_PARAMS 10
8017
8018 static gpointer
8019 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8020 {
8021         guint8 *code, *start;
8022         GSList *unwind_ops = NULL;
8023         int i;
8024
8025         unwind_ops = mono_arch_get_cie_program ();
8026
8027         if (has_target) {
8028                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8029
8030                 /* Replace the this argument with the target */
8031                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8032                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8033                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8034
8035                 g_assert ((code - start) < 64);
8036         } else {
8037                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8038
8039                 if (param_count == 0) {
8040                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8041                 } else {
8042                         /* We have to shift the arguments left */
8043                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8044                         for (i = 0; i < param_count; ++i) {
8045 #ifdef TARGET_WIN32
8046                                 if (i < 3)
8047                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8048                                 else
8049                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8050 #else
8051                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8052 #endif
8053                         }
8054
8055                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8056                 }
8057                 g_assert ((code - start) < 64);
8058         }
8059
8060         nacl_global_codeman_validate (&start, 64, &code);
8061         mono_arch_flush_icache (start, code - start);
8062
8063         if (has_target) {
8064                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8065         } else {
8066                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8067                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8068                 g_free (name);
8069         }
8070
8071         if (mono_jit_map_is_enabled ()) {
8072                 char *buff;
8073                 if (has_target)
8074                         buff = (char*)"delegate_invoke_has_target";
8075                 else
8076                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8077                 mono_emit_jit_tramp (start, code - start, buff);
8078                 if (!has_target)
8079                         g_free (buff);
8080         }
8081         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8082
8083         return start;
8084 }
8085
8086 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8087
8088 static gpointer
8089 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8090 {
8091         guint8 *code, *start;
8092         int size = 20;
8093         char *tramp_name;
8094         GSList *unwind_ops;
8095
8096         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8097                 return NULL;
8098
8099         start = code = (guint8 *)mono_global_codeman_reserve (size);
8100
8101         unwind_ops = mono_arch_get_cie_program ();
8102
8103         /* Replace the this argument with the target */
8104         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8105         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8106
8107         if (load_imt_reg) {
8108                 /* Load the IMT reg */
8109                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8110         }
8111
8112         /* Load the vtable */
8113         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8114         amd64_jump_membase (code, AMD64_RAX, offset);
8115         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8116
8117         if (load_imt_reg)
8118                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8119         else
8120                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8121         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8122         g_free (tramp_name);
8123
8124         return start;
8125 }
8126
8127 /*
8128  * mono_arch_get_delegate_invoke_impls:
8129  *
8130  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8131  * trampolines.
8132  */
8133 GSList*
8134 mono_arch_get_delegate_invoke_impls (void)
8135 {
8136         GSList *res = NULL;
8137         MonoTrampInfo *info;
8138         int i;
8139
8140         get_delegate_invoke_impl (&info, TRUE, 0);
8141         res = g_slist_prepend (res, info);
8142
8143         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8144                 get_delegate_invoke_impl (&info, FALSE, i);
8145                 res = g_slist_prepend (res, info);
8146         }
8147
8148         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8149                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8150                 res = g_slist_prepend (res, info);
8151
8152                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8153                 res = g_slist_prepend (res, info);
8154         }
8155
8156         return res;
8157 }
8158
8159 gpointer
8160 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8161 {
8162         guint8 *code, *start;
8163         int i;
8164
8165         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8166                 return NULL;
8167
8168         /* FIXME: Support more cases */
8169         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8170                 return NULL;
8171
8172         if (has_target) {
8173                 static guint8* cached = NULL;
8174
8175                 if (cached)
8176                         return cached;
8177
8178                 if (mono_aot_only) {
8179                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8180                 } else {
8181                         MonoTrampInfo *info;
8182                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8183                         mono_tramp_info_register (info, NULL);
8184                 }
8185
8186                 mono_memory_barrier ();
8187
8188                 cached = start;
8189         } else {
8190                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8191                 for (i = 0; i < sig->param_count; ++i)
8192                         if (!mono_is_regsize_var (sig->params [i]))
8193                                 return NULL;
8194                 if (sig->param_count > 4)
8195                         return NULL;
8196
8197                 code = cache [sig->param_count];
8198                 if (code)
8199                         return code;
8200
8201                 if (mono_aot_only) {
8202                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8203                         start = (guint8 *)mono_aot_get_trampoline (name);
8204                         g_free (name);
8205                 } else {
8206                         MonoTrampInfo *info;
8207                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8208                         mono_tramp_info_register (info, NULL);
8209                 }
8210
8211                 mono_memory_barrier ();
8212
8213                 cache [sig->param_count] = start;
8214         }
8215
8216         return start;
8217 }
8218
8219 gpointer
8220 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8221 {
8222         MonoTrampInfo *info;
8223         gpointer code;
8224
8225         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8226         if (code)
8227                 mono_tramp_info_register (info, NULL);
8228         return code;
8229 }
8230
8231 void
8232 mono_arch_finish_init (void)
8233 {
8234 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8235         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8236 #endif
8237 }
8238
8239 void
8240 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8241 {
8242 }
8243
8244 #if defined(__default_codegen__)
8245 #define CMP_SIZE (6 + 1)
8246 #define CMP_REG_REG_SIZE (4 + 1)
8247 #define BR_SMALL_SIZE 2
8248 #define BR_LARGE_SIZE 6
8249 #define MOV_REG_IMM_SIZE 10
8250 #define MOV_REG_IMM_32BIT_SIZE 6
8251 #define JUMP_REG_SIZE (2 + 1)
8252 #elif defined(__native_client_codegen__)
8253 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8254 #define CMP_SIZE ((6 + 1) * 2 - 1)
8255 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8256 #define BR_SMALL_SIZE (2 * 2 - 1)
8257 #define BR_LARGE_SIZE (6 * 2 - 1)
8258 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8259 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8260 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8261 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8262 /* Jump membase's size is large and unpredictable    */
8263 /* in native client, just pad it out a whole bundle. */
8264 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8265 #endif
8266
8267 static int
8268 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8269 {
8270         int i, distance = 0;
8271         for (i = start; i < target; ++i)
8272                 distance += imt_entries [i]->chunk_size;
8273         return distance;
8274 }
8275
8276 /*
8277  * LOCKING: called with the domain lock held
8278  */
8279 gpointer
8280 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8281         gpointer fail_tramp)
8282 {
8283         int i;
8284         int size = 0;
8285         guint8 *code, *start;
8286         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8287         GSList *unwind_ops;
8288
8289         for (i = 0; i < count; ++i) {
8290                 MonoIMTCheckItem *item = imt_entries [i];
8291                 if (item->is_equals) {
8292                         if (item->check_target_idx) {
8293                                 if (!item->compare_done) {
8294                                         if (amd64_use_imm32 ((gint64)item->key))
8295                                                 item->chunk_size += CMP_SIZE;
8296                                         else
8297                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8298                                 }
8299                                 if (item->has_target_code) {
8300                                         item->chunk_size += MOV_REG_IMM_SIZE;
8301                                 } else {
8302                                         if (vtable_is_32bit)
8303                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8304                                         else
8305                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8306 #ifdef __native_client_codegen__
8307                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8308 #endif
8309                                 }
8310                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8311                         } else {
8312                                 if (fail_tramp) {
8313                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8314                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8315                                 } else {
8316                                         if (vtable_is_32bit)
8317                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8318                                         else
8319                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8320                                         item->chunk_size += JUMP_REG_SIZE;
8321                                         /* with assert below:
8322                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8323                                          */
8324 #ifdef __native_client_codegen__
8325                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8326 #endif
8327                                 }
8328                         }
8329                 } else {
8330                         if (amd64_use_imm32 ((gint64)item->key))
8331                                 item->chunk_size += CMP_SIZE;
8332                         else
8333                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8334                         item->chunk_size += BR_LARGE_SIZE;
8335                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8336                 }
8337                 size += item->chunk_size;
8338         }
8339 #if defined(__native_client__) && defined(__native_client_codegen__)
8340         /* In Native Client, we don't re-use thunks, allocate from the */
8341         /* normal code manager paths. */
8342         code = mono_domain_code_reserve (domain, size);
8343 #else
8344         if (fail_tramp)
8345                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8346         else
8347                 code = (guint8 *)mono_domain_code_reserve (domain, size);
8348 #endif
8349         start = code;
8350
8351         unwind_ops = mono_arch_get_cie_program ();
8352
8353         for (i = 0; i < count; ++i) {
8354                 MonoIMTCheckItem *item = imt_entries [i];
8355                 item->code_target = code;
8356                 if (item->is_equals) {
8357                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8358
8359                         if (item->check_target_idx || fail_case) {
8360                                 if (!item->compare_done || fail_case) {
8361                                         if (amd64_use_imm32 ((gint64)item->key))
8362                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8363                                         else {
8364                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8365                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8366                                         }
8367                                 }
8368                                 item->jmp_code = code;
8369                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8370                                 if (item->has_target_code) {
8371                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8372                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8373                                 } else {
8374                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8375                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8376                                 }
8377
8378                                 if (fail_case) {
8379                                         amd64_patch (item->jmp_code, code);
8380                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8381                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8382                                         item->jmp_code = NULL;
8383                                 }
8384                         } else {
8385                                 /* enable the commented code to assert on wrong method */
8386 #if 0
8387                                 if (amd64_is_imm32 (item->key))
8388                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8389                                 else {
8390                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8391                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8392                                 }
8393                                 item->jmp_code = code;
8394                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8395                                 /* See the comment below about R10 */
8396                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8397                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8398                                 amd64_patch (item->jmp_code, code);
8399                                 amd64_breakpoint (code);
8400                                 item->jmp_code = NULL;
8401 #else
8402                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8403                                    needs to be preserved.  R10 needs
8404                                    to be preserved for calls which
8405                                    require a runtime generic context,
8406                                    but interface calls don't. */
8407                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8408                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8409 #endif
8410                         }
8411                 } else {
8412                         if (amd64_use_imm32 ((gint64)item->key))
8413                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8414                         else {
8415                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8416                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8417                         }
8418                         item->jmp_code = code;
8419                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8420                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8421                         else
8422                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8423                 }
8424                 g_assert (code - item->code_target <= item->chunk_size);
8425         }
8426         /* patch the branches to get to the target items */
8427         for (i = 0; i < count; ++i) {
8428                 MonoIMTCheckItem *item = imt_entries [i];
8429                 if (item->jmp_code) {
8430                         if (item->check_target_idx) {
8431                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8432                         }
8433                 }
8434         }
8435
8436         if (!fail_tramp)
8437                 mono_stats.imt_thunks_size += code - start;
8438         g_assert (code - start <= size);
8439
8440         nacl_domain_code_validate(domain, &start, size, &code);
8441         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8442
8443         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8444
8445         return start;
8446 }
8447
8448 MonoMethod*
8449 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8450 {
8451         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8452 }
8453
8454 MonoVTable*
8455 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8456 {
8457         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8458 }
8459
8460 GSList*
8461 mono_arch_get_cie_program (void)
8462 {
8463         GSList *l = NULL;
8464
8465         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8466         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8467
8468         return l;
8469 }
8470
8471 #ifndef DISABLE_JIT
8472
8473 MonoInst*
8474 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8475 {
8476         MonoInst *ins = NULL;
8477         int opcode = 0;
8478
8479         if (cmethod->klass == mono_defaults.math_class) {
8480                 if (strcmp (cmethod->name, "Sin") == 0) {
8481                         opcode = OP_SIN;
8482                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8483                         opcode = OP_COS;
8484                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8485                         opcode = OP_SQRT;
8486                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8487                         opcode = OP_ABS;
8488                 }
8489
8490                 if (opcode && fsig->param_count == 1) {
8491                         MONO_INST_NEW (cfg, ins, opcode);
8492                         ins->type = STACK_R8;
8493                         ins->dreg = mono_alloc_freg (cfg);
8494                         ins->sreg1 = args [0]->dreg;
8495                         MONO_ADD_INS (cfg->cbb, ins);
8496                 }
8497
8498                 opcode = 0;
8499                 if (cfg->opt & MONO_OPT_CMOV) {
8500                         if (strcmp (cmethod->name, "Min") == 0) {
8501                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8502                                         opcode = OP_IMIN;
8503                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8504                                         opcode = OP_IMIN_UN;
8505                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8506                                         opcode = OP_LMIN;
8507                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8508                                         opcode = OP_LMIN_UN;
8509                         } else if (strcmp (cmethod->name, "Max") == 0) {
8510                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8511                                         opcode = OP_IMAX;
8512                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8513                                         opcode = OP_IMAX_UN;
8514                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8515                                         opcode = OP_LMAX;
8516                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8517                                         opcode = OP_LMAX_UN;
8518                         }
8519                 }
8520
8521                 if (opcode && fsig->param_count == 2) {
8522                         MONO_INST_NEW (cfg, ins, opcode);
8523                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8524                         ins->dreg = mono_alloc_ireg (cfg);
8525                         ins->sreg1 = args [0]->dreg;
8526                         ins->sreg2 = args [1]->dreg;
8527                         MONO_ADD_INS (cfg->cbb, ins);
8528                 }
8529
8530 #if 0
8531                 /* OP_FREM is not IEEE compatible */
8532                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8533                         MONO_INST_NEW (cfg, ins, OP_FREM);
8534                         ins->inst_i0 = args [0];
8535                         ins->inst_i1 = args [1];
8536                 }
8537 #endif
8538         }
8539
8540         return ins;
8541 }
8542 #endif
8543
8544 gboolean
8545 mono_arch_print_tree (MonoInst *tree, int arity)
8546 {
8547         return 0;
8548 }
8549
8550 mgreg_t
8551 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8552 {
8553         return ctx->gregs [reg];
8554 }
8555
8556 void
8557 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8558 {
8559         ctx->gregs [reg] = val;
8560 }
8561
8562 gpointer
8563 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8564 {
8565         gpointer *sp, old_value;
8566         char *bp;
8567
8568         /*Load the spvar*/
8569         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8570         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8571
8572         old_value = *sp;
8573         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8574                 return old_value;
8575
8576         *sp = new_value;
8577
8578         return old_value;
8579 }
8580
8581 /*
8582  * mono_arch_emit_load_aotconst:
8583  *
8584  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8585  * TARGET from the mscorlib GOT in full-aot code.
8586  * On AMD64, the result is placed into R11.
8587  */
8588 guint8*
8589 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8590 {
8591         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8592         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8593
8594         return code;
8595 }
8596
8597 /*
8598  * mono_arch_get_trampolines:
8599  *
8600  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8601  * for AOT.
8602  */
8603 GSList *
8604 mono_arch_get_trampolines (gboolean aot)
8605 {
8606         return mono_amd64_get_exception_trampolines (aot);
8607 }
8608
8609 /* Soft Debug support */
8610 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8611
8612 /*
8613  * mono_arch_set_breakpoint:
8614  *
8615  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8616  * The location should contain code emitted by OP_SEQ_POINT.
8617  */
8618 void
8619 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8620 {
8621         guint8 *code = ip;
8622
8623         if (ji->from_aot) {
8624                 guint32 native_offset = ip - (guint8*)ji->code_start;
8625                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8626
8627                 g_assert (info->bp_addrs [native_offset] == 0);
8628                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8629         } else {
8630                 /* ip points to a mov r11, 0 */
8631                 g_assert (code [0] == 0x41);
8632                 g_assert (code [1] == 0xbb);
8633                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8634         }
8635 }
8636
8637 /*
8638  * mono_arch_clear_breakpoint:
8639  *
8640  *   Clear the breakpoint at IP.
8641  */
8642 void
8643 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8644 {
8645         guint8 *code = ip;
8646
8647         if (ji->from_aot) {
8648                 guint32 native_offset = ip - (guint8*)ji->code_start;
8649                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8650
8651                 info->bp_addrs [native_offset] = NULL;
8652         } else {
8653                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8654         }
8655 }
8656
8657 gboolean
8658 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8659 {
8660         /* We use soft breakpoints on amd64 */
8661         return FALSE;
8662 }
8663
8664 /*
8665  * mono_arch_skip_breakpoint:
8666  *
8667  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8668  * we resume, the instruction is not executed again.
8669  */
8670 void
8671 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8672 {
8673         g_assert_not_reached ();
8674 }
8675
8676 /*
8677  * mono_arch_start_single_stepping:
8678  *
8679  *   Start single stepping.
8680  */
8681 void
8682 mono_arch_start_single_stepping (void)
8683 {
8684         ss_trampoline = mini_get_single_step_trampoline ();
8685 }
8686
8687 /*
8688  * mono_arch_stop_single_stepping:
8689  *
8690  *   Stop single stepping.
8691  */
8692 void
8693 mono_arch_stop_single_stepping (void)
8694 {
8695         ss_trampoline = NULL;
8696 }
8697
8698 /*
8699  * mono_arch_is_single_step_event:
8700  *
8701  *   Return whenever the machine state in SIGCTX corresponds to a single
8702  * step event.
8703  */
8704 gboolean
8705 mono_arch_is_single_step_event (void *info, void *sigctx)
8706 {
8707         /* We use soft breakpoints on amd64 */
8708         return FALSE;
8709 }
8710
8711 /*
8712  * mono_arch_skip_single_step:
8713  *
8714  *   Modify CTX so the ip is placed after the single step trigger instruction,
8715  * we resume, the instruction is not executed again.
8716  */
8717 void
8718 mono_arch_skip_single_step (MonoContext *ctx)
8719 {
8720         g_assert_not_reached ();
8721 }
8722
8723 /*
8724  * mono_arch_create_seq_point_info:
8725  *
8726  *   Return a pointer to a data structure which is used by the sequence
8727  * point implementation in AOTed code.
8728  */
8729 gpointer
8730 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8731 {
8732         SeqPointInfo *info;
8733         MonoJitInfo *ji;
8734
8735         // FIXME: Add a free function
8736
8737         mono_domain_lock (domain);
8738         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8739                                                                 code);
8740         mono_domain_unlock (domain);
8741
8742         if (!info) {
8743                 ji = mono_jit_info_table_find (domain, (char*)code);
8744                 g_assert (ji);
8745
8746                 // FIXME: Optimize the size
8747                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8748
8749                 info->ss_tramp_addr = &ss_trampoline;
8750
8751                 mono_domain_lock (domain);
8752                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8753                                                          code, info);
8754                 mono_domain_unlock (domain);
8755         }
8756
8757         return info;
8758 }
8759
8760 void
8761 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8762 {
8763         ext->lmf.previous_lmf = prev_lmf;
8764         /* Mark that this is a MonoLMFExt */
8765         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8766         ext->lmf.rsp = (gssize)ext;
8767 }
8768
8769 #endif
8770
8771 gboolean
8772 mono_arch_opcode_supported (int opcode)
8773 {
8774         switch (opcode) {
8775         case OP_ATOMIC_ADD_I4:
8776         case OP_ATOMIC_ADD_I8:
8777         case OP_ATOMIC_EXCHANGE_I4:
8778         case OP_ATOMIC_EXCHANGE_I8:
8779         case OP_ATOMIC_CAS_I4:
8780         case OP_ATOMIC_CAS_I8:
8781         case OP_ATOMIC_LOAD_I1:
8782         case OP_ATOMIC_LOAD_I2:
8783         case OP_ATOMIC_LOAD_I4:
8784         case OP_ATOMIC_LOAD_I8:
8785         case OP_ATOMIC_LOAD_U1:
8786         case OP_ATOMIC_LOAD_U2:
8787         case OP_ATOMIC_LOAD_U4:
8788         case OP_ATOMIC_LOAD_U8:
8789         case OP_ATOMIC_LOAD_R4:
8790         case OP_ATOMIC_LOAD_R8:
8791         case OP_ATOMIC_STORE_I1:
8792         case OP_ATOMIC_STORE_I2:
8793         case OP_ATOMIC_STORE_I4:
8794         case OP_ATOMIC_STORE_I8:
8795         case OP_ATOMIC_STORE_U1:
8796         case OP_ATOMIC_STORE_U2:
8797         case OP_ATOMIC_STORE_U4:
8798         case OP_ATOMIC_STORE_U8:
8799         case OP_ATOMIC_STORE_R4:
8800         case OP_ATOMIC_STORE_R8:
8801                 return TRUE;
8802         default:
8803                 return FALSE;
8804         }
8805 }
8806
8807 CallInfo*
8808 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8809 {
8810         return get_call_info (mp, sig);
8811 }