mono/mini/local-propagation.c

   1 /**
   2  * \file
   3  * Local constant, copy and tree propagation.
   4  *
   5  * To make some sense of the tree mover, read mono/docs/tree-mover.txt
   6  *
   7  * Author:
   8  *   Paolo Molaro (lupus@ximian.com)
   9  *   Dietmar Maurer (dietmar@ximian.com)
  10  *   Massimiliano Mantione (massi@ximian.com)
  11  *
  12  * (C) 2006 Novell, Inc.  http://www.novell.com
  13  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  14  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  15  */
  16
  17 #include <config.h>
  18 #include <mono/utils/mono-compiler.h>
  19
  20 #ifndef DISABLE_JIT
  21
  22 #include <string.h>
  23 #include <stdio.h>
  24 #ifdef HAVE_ALLOCA_H
  25 #include <alloca.h>
  26 #endif
  27
  28 #include <mono/metadata/debug-helpers.h>
  29 #include <mono/metadata/mempool.h>
  30 #include <mono/metadata/opcodes.h>
  31 #include <mono/utils/unlocked.h>
  32 #include "mini.h"
  33 #include "ir-emit.h"
  34
  35 #ifndef MONO_ARCH_IS_OP_MEMBASE
  36 #define MONO_ARCH_IS_OP_MEMBASE(opcode) FALSE
  37 #endif
  38
  39 static inline MonoBitSet*
  40 mono_bitset_mp_new_noinit (MonoMemPool *mp,  guint32 max_size)
  41 {
  42         int size = mono_bitset_alloc_size (max_size, 0);
  43         gpointer mem;
  44
  45         mem = mono_mempool_alloc (mp, size);
  46         return mono_bitset_mem_new (mem, max_size, MONO_BITSET_DONT_FREE);
  47 }
  48
  49 struct magic_unsigned {
  50         guint32 magic_number;
  51         gboolean addition;
  52         int shift;
  53 };
  54
  55 struct magic_signed {
  56         gint32 magic_number;
  57         int shift;
  58 };
  59
  60 /* http://www.hackersdelight.org/hdcodetxt/magicu.c.txt */
  61 static struct magic_unsigned
  62 compute_magic_unsigned (guint32 divisor) {
  63         guint32 nc, delta, q1, r1, q2, r2;
  64         struct magic_unsigned magu;
  65         gboolean gt = FALSE;
  66         int p;
  67
  68         magu.addition = 0;
  69         nc = -1 - (-divisor) % divisor;
  70         p = 31;
  71         q1 = 0x80000000 / nc;
  72         r1 = 0x80000000 - q1 * nc;
  73         q2 = 0x7FFFFFFF / divisor;
  74         r2 = 0x7FFFFFFF - q2 * divisor;
  75         do {
  76                 p = p + 1;
  77                 if (q1 >= 0x80000000)
  78                         gt = TRUE;
  79                 if (r1 >= nc - r1) {
  80                         q1 = 2 * q1 + 1;
  81                         r1 = 2 * r1 - nc;
  82                 } else {
  83                         q1 = 2 * q1;
  84                         r1 = 2 * r1;
  85                 }
  86                 if (r2 + 1 >= divisor - r2) {
  87                         if (q2 >= 0x7FFFFFFF)
  88                                 magu.addition = 1;
  89                         q2 = 2 * q2 + 1;
  90                         r2 = 2 * r2 + 1 - divisor;
  91                 } else {
  92                         if (q2 >= 0x80000000)
  93                                 magu.addition = 1;
  94                         q2 = 2 * q2;
  95                         r2 = 2 * r2 + 1;
  96                 }
  97                 delta = divisor - 1 - r2;
  98         } while (!gt && (q1 < delta || (q1 == delta && r1 == 0)));
  99
 100         magu.magic_number = q2 + 1;
 101         magu.shift = p - 32;
 102         return magu;
 103 }
 104
 105 /* http://www.hackersdelight.org/hdcodetxt/magic.c.txt */
 106 static struct magic_signed
 107 compute_magic_signed (gint32 divisor) {
 108         int p;
 109         guint32 ad, anc, delta, q1, r1, q2, r2, t;
 110         const guint32 two31 = 0x80000000;
 111         struct magic_signed mag;
 112
 113         ad = abs (divisor);
 114         t = two31 + ((unsigned)divisor >> 31);
 115         anc = t - 1 - t % ad;
 116         p = 31;
 117         q1 = two31 / anc;
 118         r1 = two31 - q1 * anc;
 119         q2 = two31 / ad;
 120         r2 = two31 - q2 * ad;
 121         do {
 122                 p++;
 123                 q1 *= 2;
 124                 r1 *= 2;
 125                 if (r1 >= anc) {
 126                         q1++;
 127                         r1 -= anc;
 128                 }
 129
 130                 q2 *= 2;
 131                 r2 *= 2;
 132
 133                 if (r2 >= ad) {
 134                         q2++;
 135                         r2 -= ad;
 136                 }
 137
 138                 delta = ad - r2;
 139         } while (q1 < delta || (q1 == delta && r1 == 0));
 140
 141         mag.magic_number = q2 + 1;
 142         if (divisor < 0)
 143                 mag.magic_number = -mag.magic_number;
 144         mag.shift = p - 32;
 145         return mag;
 146 }
 147
 148 static gboolean
 149 mono_strength_reduction_division (MonoCompile *cfg, MonoInst *ins)
 150 {
 151         gboolean allocated_vregs = FALSE;
 152         /*
 153          * We don't use it on 32bit systems because on those
 154          * platforms we emulate long multiplication, driving the
 155          * performance back down.
 156          */
 157         switch (ins->opcode) {
 158                 case OP_IDIV_UN_IMM: {
 159                         guint32 tmp_regl;
 160 #if SIZEOF_REGISTER == 8
 161                         guint32 dividend_reg;
 162 #else
 163                         guint32 tmp_regi;
 164 #endif
 165                         struct magic_unsigned mag;
 166                         int power2 = mono_is_power_of_two (ins->inst_imm);
 167
 168                         /* The decomposition doesn't handle exception throwing */
 169                         if (ins->inst_imm == 0)
 170                                 break;
 171
 172                         if (power2 >= 0) {
 173                                 ins->opcode = OP_ISHR_UN_IMM;
 174                                 ins->sreg2 = -1;
 175                                 ins->inst_imm = power2;
 176                                 break;
 177                         }
 178                         if (cfg->backend->disable_div_with_mul)
 179                                 break;
 180                         allocated_vregs = TRUE;
 181                         /*
 182                          * Replacement of unsigned division with multiplication,
 183                          * shifts and additions Hacker's Delight, chapter 10-10.
 184                          */
 185                         mag = compute_magic_unsigned (ins->inst_imm);
 186                         tmp_regl = alloc_lreg (cfg);
 187 #if SIZEOF_REGISTER == 8
 188                         dividend_reg = alloc_lreg (cfg);
 189                         MONO_EMIT_NEW_I8CONST (cfg, tmp_regl, mag.magic_number);
 190                         MONO_EMIT_NEW_UNALU (cfg, OP_ZEXT_I4, dividend_reg, ins->sreg1);
 191                         MONO_EMIT_NEW_BIALU (cfg, OP_LMUL, tmp_regl, dividend_reg, tmp_regl);
 192                         if (mag.addition) {
 193                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32);
 194                                 MONO_EMIT_NEW_BIALU (cfg, OP_LADD, tmp_regl, tmp_regl, dividend_reg);
 195                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, mag.shift);
 196                         } else {
 197                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, 32 + mag.shift);
 198                         }
 199 #else
 200                         tmp_regi = alloc_ireg (cfg);
 201                         MONO_EMIT_NEW_ICONST (cfg, tmp_regi, mag.magic_number);
 202                         MONO_EMIT_NEW_BIALU (cfg, OP_BIGMUL_UN, tmp_regl, ins->sreg1, tmp_regi);
 203                         /* Long shifts below will be decomposed during cprop */
 204                         if (mag.addition) {
 205                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32);
 206                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADDCC, MONO_LVREG_LS (tmp_regl), MONO_LVREG_LS (tmp_regl), ins->sreg1);
 207                                 /* MONO_LVREG_MS (tmp_reg) is 0, save in it the carry */
 208                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADC, MONO_LVREG_MS (tmp_regl), MONO_LVREG_MS (tmp_regl), MONO_LVREG_MS (tmp_regl));
 209                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, mag.shift);
 210                         } else {
 211                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, tmp_regl, tmp_regl, 32 + mag.shift);
 212                         }
 213                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ins->dreg, MONO_LVREG_LS (tmp_regl));
 214 #endif
 215                         UnlockedIncrement (&mono_jit_stats.optimized_divisions);
 216                         break;
 217                 }
 218                 case OP_IDIV_IMM: {
 219                         guint32 tmp_regl;
 220 #if SIZEOF_REGISTER == 8
 221                         guint32 dividend_reg;
 222 #else
 223                         guint32 tmp_regi;
 224 #endif
 225                         struct magic_signed mag;
 226                         int power2 = mono_is_power_of_two (ins->inst_imm);
 227                         /* The decomposition doesn't handle exception throwing */
 228                         /* Optimization with MUL does not apply for -1, 0 and 1 divisors */
 229                         if (ins->inst_imm == 0 || ins->inst_imm == -1) {
 230                                 break;
 231                         } else if (ins->inst_imm == 1) {
 232                                 ins->opcode = OP_MOVE;
 233                                 ins->inst_imm = 0;
 234                                 break;
 235                         }
 236                         allocated_vregs = TRUE;
 237                         if (power2 == 1) {
 238                                 guint32 r1 = alloc_ireg (cfg);
 239                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, r1, ins->sreg1, 31);
 240                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, r1, r1, ins->sreg1);
 241                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, ins->dreg, r1, 1);
 242                                 break;
 243                         } else if (power2 > 0 && power2 < 31) {
 244                                 guint32 r1 = alloc_ireg (cfg);
 245                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, r1, ins->sreg1, 31);
 246                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, r1, r1, (32 - power2));
 247                                 MONO_EMIT_NEW_BIALU (cfg, OP_IADD, r1, r1, ins->sreg1);
 248                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, ins->dreg, r1, power2);
 249                                 break;
 250                         }
 251
 252                         if (cfg->backend->disable_div_with_mul)
 253                                 break;
 254                         /*
 255                          * Replacement of signed division with multiplication,
 256                          * shifts and additions Hacker's Delight, chapter 10-6.
 257                          */
 258                         mag = compute_magic_signed (ins->inst_imm);
 259                         tmp_regl = alloc_lreg (cfg);
 260 #if SIZEOF_REGISTER == 8
 261                         dividend_reg = alloc_lreg (cfg);
 262                         MONO_EMIT_NEW_I8CONST (cfg, tmp_regl, mag.magic_number);
 263                         MONO_EMIT_NEW_UNALU (cfg, OP_SEXT_I4, dividend_reg, ins->sreg1);
 264                         MONO_EMIT_NEW_BIALU (cfg, OP_LMUL, tmp_regl, dividend_reg, tmp_regl);
 265                         if ((ins->inst_imm > 0 && mag.magic_number < 0) || (ins->inst_imm < 0 && mag.magic_number > 0)) {
 266                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, 32);
 267                                 if (ins->inst_imm > 0 && mag.magic_number < 0) {
 268                                         MONO_EMIT_NEW_BIALU (cfg, OP_LADD, tmp_regl, tmp_regl, dividend_reg);
 269                                 } else if (ins->inst_imm < 0 && mag.magic_number > 0) {
 270                                         MONO_EMIT_NEW_BIALU (cfg, OP_LSUB, tmp_regl, tmp_regl, dividend_reg);
 271                                 }
 272                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, mag.shift);
 273                         } else {
 274                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_IMM, tmp_regl, tmp_regl, 32 + mag.shift);
 275                         }
 276                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_LSHR_UN_IMM, ins->dreg, tmp_regl, SIZEOF_REGISTER * 8 - 1);
 277                         MONO_EMIT_NEW_BIALU (cfg, OP_LADD, ins->dreg, ins->dreg, tmp_regl);
 278 #else
 279                         tmp_regi = alloc_ireg (cfg);
 280                         MONO_EMIT_NEW_ICONST (cfg, tmp_regi, mag.magic_number);
 281                         MONO_EMIT_NEW_BIALU (cfg, OP_BIGMUL, tmp_regl, ins->sreg1, tmp_regi);
 282                         if ((ins->inst_imm > 0 && mag.magic_number < 0) || (ins->inst_imm < 0 && mag.magic_number > 0)) {
 283                                 if (ins->inst_imm > 0 && mag.magic_number < 0) {
 284                                         /* Opposite sign, cannot overflow */
 285                                         MONO_EMIT_NEW_BIALU (cfg, OP_IADD, tmp_regi, MONO_LVREG_MS (tmp_regl), ins->sreg1);
 286                                 } else if (ins->inst_imm < 0 && mag.magic_number > 0) {
 287                                         /* Same sign, cannot overflow */
 288                                         MONO_EMIT_NEW_BIALU (cfg, OP_ISUB, tmp_regi, MONO_LVREG_MS (tmp_regl), ins->sreg1);
 289                                 }
 290                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, tmp_regi, tmp_regi, mag.shift);
 291                         } else {
 292                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, tmp_regi, MONO_LVREG_MS (tmp_regl), mag.shift);
 293                         }
 294                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, ins->dreg, tmp_regi, SIZEOF_REGISTER * 8 - 1);
 295                         MONO_EMIT_NEW_BIALU (cfg, OP_IADD, ins->dreg, ins->dreg, tmp_regi);
 296 #endif
 297                         UnlockedIncrement (&mono_jit_stats.optimized_divisions);
 298                         break;
 299                 }
 300         }
 301         return allocated_vregs;
 302 }
 303
 304 /*
 305  * Replaces ins with optimized opcodes.
 306  *
 307  * We can emit to cbb the equivalent instructions which will be used as
 308  * replacement for ins, or simply change the fields of ins. Spec needs to
 309  * be updated if we silently change the opcode of ins.
 310  *
 311  * Returns TRUE if additional vregs were allocated.
 312  */
 313 static gboolean
 314 mono_strength_reduction_ins (MonoCompile *cfg, MonoInst *ins, const char **spec)
 315 {
 316         gboolean allocated_vregs = FALSE;
 317
 318         /* FIXME: Add long/float */
 319         switch (ins->opcode) {
 320         case OP_MOVE:
 321         case OP_XMOVE:
 322                 if (ins->dreg == ins->sreg1) {
 323                         NULLIFY_INS (ins);
 324                 }
 325                 break;
 326         case OP_ADD_IMM:
 327         case OP_IADD_IMM:
 328         case OP_SUB_IMM:
 329         case OP_ISUB_IMM:
 330 #if SIZEOF_REGISTER == 8
 331         case OP_LADD_IMM:
 332         case OP_LSUB_IMM:
 333 #endif
 334                 if (ins->inst_imm == 0) {
 335                         ins->opcode = OP_MOVE;
 336                 }
 337                 break;
 338         case OP_MUL_IMM:
 339         case OP_IMUL_IMM:
 340 #if SIZEOF_REGISTER == 8
 341         case OP_LMUL_IMM:
 342 #endif
 343                 if (ins->inst_imm == 0) {
 344                         ins->opcode = (ins->opcode == OP_LMUL_IMM) ? OP_I8CONST : OP_ICONST;
 345                         ins->inst_c0 = 0;
 346                         ins->sreg1 = -1;
 347                 } else if (ins->inst_imm == 1) {
 348                         ins->opcode = OP_MOVE;
 349                 } else if ((ins->opcode == OP_IMUL_IMM) && (ins->inst_imm == -1)) {
 350                         ins->opcode = OP_INEG;
 351                 } else if ((ins->opcode == OP_LMUL_IMM) && (ins->inst_imm == -1)) {
 352                         ins->opcode = OP_LNEG;
 353                 } else {
 354                         int power2 = mono_is_power_of_two (ins->inst_imm);
 355                         if (power2 >= 0) {
 356                                 ins->opcode = (ins->opcode == OP_MUL_IMM) ? OP_SHL_IMM : ((ins->opcode == OP_LMUL_IMM) ? OP_LSHL_IMM : OP_ISHL_IMM);
 357                                 ins->inst_imm = power2;
 358                         }
 359                 }
 360                 break;
 361         case OP_IREM_UN_IMM: {
 362                 int power2 = mono_is_power_of_two (ins->inst_imm);
 363
 364                 if (power2 >= 0) {
 365                         ins->opcode = OP_IAND_IMM;
 366                         ins->sreg2 = -1;
 367                         ins->inst_imm = (1 << power2) - 1;
 368                 }
 369                 break;
 370         }
 371         case OP_IDIV_UN_IMM:
 372         case OP_IDIV_IMM: {
 373                 if (!COMPILE_LLVM (cfg))
 374                         allocated_vregs = mono_strength_reduction_division (cfg, ins);
 375                 break;
 376         }
 377 #if SIZEOF_REGISTER == 8
 378         case OP_LREM_IMM:
 379 #endif
 380         case OP_IREM_IMM: {
 381                 int power = mono_is_power_of_two (ins->inst_imm);
 382                 if (ins->inst_imm == 1) {
 383                         ins->opcode = OP_ICONST;
 384                         MONO_INST_NULLIFY_SREGS (ins);
 385                         ins->inst_c0 = 0;
 386 #if __s390__
 387                 }
 388 #else
 389                 } else if ((ins->inst_imm > 0) && (ins->inst_imm < (1LL << 32)) && (power != -1)) {
 390                         gboolean is_long = ins->opcode == OP_LREM_IMM;
 391                         int compensator_reg = alloc_ireg (cfg);
 392                         int intermediate_reg;
 393
 394                         /* Based on gcc code */
 395
 396                         /* Add compensation for negative numerators */
 397
 398                         if (power > 1) {
 399                                 intermediate_reg = compensator_reg;
 400                                 MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LSHR_IMM : OP_ISHR_IMM, intermediate_reg, ins->sreg1, is_long ? 63 : 31);
 401                         } else {
 402                                 intermediate_reg = ins->sreg1;
 403                         }
 404
 405                         MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LSHR_UN_IMM : OP_ISHR_UN_IMM, compensator_reg, intermediate_reg, (is_long ? 64 : 32) - power);
 406                         MONO_EMIT_NEW_BIALU (cfg, is_long ? OP_LADD : OP_IADD, ins->dreg, ins->sreg1, compensator_reg);
 407                         /* Compute remainder */
 408                         MONO_EMIT_NEW_BIALU_IMM (cfg, is_long ? OP_LAND_IMM : OP_AND_IMM, ins->dreg, ins->dreg, (1 << power) - 1);
 409                         /* Remove compensation */
 410                         MONO_EMIT_NEW_BIALU (cfg, is_long ? OP_LSUB : OP_ISUB, ins->dreg, ins->dreg, compensator_reg);
 411
 412                         allocated_vregs = TRUE;
 413                 }
 414 #endif
 415                 break;
 416         }
 417 #if SIZEOF_REGISTER == 4
 418         case OP_LSHR_IMM: {
 419                 if (COMPILE_LLVM (cfg))
 420                         break;
 421                 if (ins->inst_c1 == 32) {
 422                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 423                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 31);
 424                 } else if (ins->inst_c1 == 0) {
 425                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 426                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 427                 } else if (ins->inst_c1 > 32) {
 428                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1 - 32);
 429                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 31);
 430                 } else {
 431                         guint32 tmpreg = alloc_ireg (cfg);
 432                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, tmpreg, MONO_LVREG_MS (ins->sreg1), 32 - ins->inst_c1);
 433                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
 434                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
 435                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->dreg), tmpreg);
 436                         allocated_vregs = TRUE;
 437                 }
 438                 break;
 439         }
 440         case OP_LSHR_UN_IMM: {
 441                 if (COMPILE_LLVM (cfg))
 442                         break;
 443                 if (ins->inst_c1 == 32) {
 444                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 445                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_MS (ins->dreg), 0);
 446                 } else if (ins->inst_c1 == 0) {
 447                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 448                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 449                 } else if (ins->inst_c1 > 32) {
 450                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1 - 32);
 451                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_MS (ins->dreg), 0);
 452                 } else {
 453                         guint32 tmpreg = alloc_ireg (cfg);
 454                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, tmpreg, MONO_LVREG_MS (ins->sreg1), 32 - ins->inst_c1);
 455                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
 456                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
 457                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->dreg), tmpreg);
 458                         allocated_vregs = TRUE;
 459                 }
 460                 break;
 461         }
 462         case OP_LSHL_IMM: {
 463                 if (COMPILE_LLVM (cfg))
 464                         break;
 465                 if (ins->inst_c1 == 32) {
 466                         /* just move the lower half to the upper and zero the lower word */
 467                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 468                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_LS (ins->dreg), 0);
 469                 } else if (ins->inst_c1 == 0) {
 470                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
 471                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1));
 472                 } else if (ins->inst_c1 > 32) {
 473                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1 - 32);
 474                         MONO_EMIT_NEW_ICONST (cfg, MONO_LVREG_LS (ins->dreg), 0);
 475                 } else {
 476                         guint32 tmpreg = alloc_ireg (cfg);
 477                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHR_UN_IMM, tmpreg, MONO_LVREG_LS (ins->sreg1), 32 - ins->inst_c1);
 478                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), ins->inst_c1);
 479                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ISHL_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), ins->inst_c1);
 480                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg), tmpreg);
 481                         allocated_vregs = TRUE;
 482                 }
 483                 break;
 484         }
 485 #endif
 486
 487         default:
 488                 break;
 489         }
 490
 491         *spec = INS_INFO (ins->opcode);
 492         return allocated_vregs;
 493 }
 494
 495 /*
 496  * mono_local_cprop:
 497  *
 498  *  A combined local copy and constant propagation pass.
 499  */
 500 void
 501 mono_local_cprop (MonoCompile *cfg)
 502 {
 503         MonoBasicBlock *bb, *bb_opt;
 504         MonoInst **defs;
 505         gint32 *def_index;
 506         int max;
 507         int filter = FILTER_IL_SEQ_POINT;
 508         int initial_max_vregs = cfg->next_vreg;
 509
 510         max = cfg->next_vreg;
 511         defs = (MonoInst **)mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * cfg->next_vreg);
 512         def_index = (gint32 *)mono_mempool_alloc (cfg->mempool, sizeof (guint32) * cfg->next_vreg);
 513         cfg->cbb = bb_opt = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoBasicBlock));
 514
 515         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
 516                 MonoInst *ins;
 517                 int ins_index;
 518                 int last_call_index;
 519
 520                 /* Manually init the defs entries used by the bblock */
 521                 MONO_BB_FOR_EACH_INS (bb, ins) {
 522                         int sregs [MONO_MAX_SRC_REGS];
 523                         int num_sregs, i;
 524
 525                         if (ins->dreg != -1) {
 526 #if SIZEOF_REGISTER == 4
 527                                 const char *spec = INS_INFO (ins->opcode);
 528                                 if (spec [MONO_INST_DEST] == 'l') {
 529                                         defs [ins->dreg + 1] = NULL;
 530                                         defs [ins->dreg + 2] = NULL;
 531                                 }
 532 #endif
 533                                 defs [ins->dreg] = NULL;
 534                         }
 535
 536                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 537                         for (i = 0; i < num_sregs; ++i) {
 538                                 int sreg = sregs [i];
 539 #if SIZEOF_REGISTER == 4
 540                                 const char *spec = INS_INFO (ins->opcode);
 541                                 if (spec [MONO_INST_SRC1 + i] == 'l') {
 542                                         defs [sreg + 1] = NULL;
 543                                         defs [sreg + 2] = NULL;
 544                                 }
 545 #endif
 546                                 defs [sreg] = NULL;
 547                         }
 548                 }
 549
 550                 ins_index = 0;
 551                 last_call_index = -1;
 552                 MONO_BB_FOR_EACH_INS (bb, ins) {
 553                         const char *spec = INS_INFO (ins->opcode);
 554                         int regtype, srcindex, sreg;
 555                         int num_sregs;
 556                         int sregs [MONO_MAX_SRC_REGS];
 557
 558                         if (ins->opcode == OP_NOP) {
 559                                 MONO_DELETE_INS (bb, ins);
 560                                 continue;
 561                         }
 562
 563                         g_assert (ins->opcode > MONO_CEE_LAST);
 564
 565                         /* FIXME: Optimize this */
 566                         if (ins->opcode == OP_LDADDR) {
 567                                 MonoInst *var = (MonoInst *)ins->inst_p0;
 568
 569                                 defs [var->dreg] = NULL;
 570                                 /*
 571                                 if (!MONO_TYPE_ISSTRUCT (var->inst_vtype))
 572                                         break;
 573                                 */
 574                         }
 575
 576                         if (MONO_IS_STORE_MEMBASE (ins)) {
 577                                 sreg = ins->dreg;
 578                                 regtype = 'i';
 579
 580                                 if ((regtype == 'i') && (sreg != -1) && defs [sreg]) {
 581                                         MonoInst *def = defs [sreg];
 582
 583                                         if ((def->opcode == OP_MOVE) && (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg])) && !vreg_is_volatile (cfg, def->sreg1)) {
 584                                                 int vreg = def->sreg1;
 585                                                 if (cfg->verbose_level > 2) printf ("CCOPY: R%d -> R%d\n", sreg, vreg);
 586                                                 ins->dreg = vreg;
 587                                         }
 588                                 }
 589                         }
 590
 591                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 592                         for (srcindex = 0; srcindex < num_sregs; ++srcindex) {
 593                                 MonoInst *def;
 594
 595                                 mono_inst_get_src_registers (ins, sregs);
 596
 597                                 regtype = spec [MONO_INST_SRC1 + srcindex];
 598                                 sreg = sregs [srcindex];
 599
 600                                 if ((regtype == ' ') || (sreg == -1) || (!defs [sreg]))
 601                                         continue;
 602
 603                                 def = defs [sreg];
 604
 605                                 /* Copy propagation */
 606                                 /*
 607                                  * The first check makes sure the source of the copy did not change since
 608                                  * the copy was made.
 609                                  * The second check avoids volatile variables.
 610                                  * The third check avoids copy propagating local vregs through a call,
 611                                  * since the lvreg will be spilled
 612                                  * The fourth check avoids copy propagating a vreg in cases where
 613                                  * it would be eliminated anyway by reverse copy propagation later,
 614                                  * because propagating it would create another use for it, thus making
 615                                  * it impossible to use reverse copy propagation.
 616                                  */
 617                                 /* Enabling this for floats trips up the fp stack */
 618                                 /*
 619                                  * Enabling this for floats on amd64 seems to cause a failure in
 620                                  * basic-math.cs, most likely because it gets rid of some r8->r4
 621                                  * conversions.
 622                                  */
 623                                 if (MONO_IS_MOVE (def) &&
 624                                         (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg])) &&
 625                                         !vreg_is_volatile (cfg, def->sreg1) &&
 626                                         /* This avoids propagating local vregs across calls */
 627                                         ((get_vreg_to_inst (cfg, def->sreg1) || !defs [def->sreg1] || (def_index [def->sreg1] >= last_call_index) || (def->opcode == OP_VMOVE))) &&
 628                                         !(defs [def->sreg1] && mono_inst_next (defs [def->sreg1], filter) == def) &&
 629                                         (!MONO_ARCH_USE_FPSTACK || (def->opcode != OP_FMOVE)) &&
 630                                         (def->opcode != OP_FMOVE)) {
 631                                         int vreg = def->sreg1;
 632
 633                                         if (cfg->verbose_level > 2) printf ("CCOPY/2: R%d -> R%d\n", sreg, vreg);
 634                                         sregs [srcindex] = vreg;
 635                                         mono_inst_set_src_registers (ins, sregs);
 636
 637                                         /* Allow further iterations */
 638                                         srcindex = -1;
 639                                         continue;
 640                                 }
 641
 642                                 /* Constant propagation */
 643                                 /* FIXME: Make is_inst_imm a macro */
 644                                 /* FIXME: Make is_inst_imm take an opcode argument */
 645                                 /* is_inst_imm is only needed for binops */
 646                                 if ((((def->opcode == OP_ICONST) || ((sizeof (gpointer) == 8) && (def->opcode == OP_I8CONST)) || (def->opcode == OP_PCONST)) &&
 647                                          (((srcindex == 0) && (ins->sreg2 == -1)) || mono_arch_is_inst_imm (def->inst_c0))) ||
 648                                         (!MONO_ARCH_USE_FPSTACK && (def->opcode == OP_R8CONST))) {
 649                                         guint32 opcode2;
 650
 651                                         /* srcindex == 1 -> binop, ins->sreg2 == -1 -> unop */
 652                                         if ((srcindex == 1) && (ins->sreg1 != -1) && defs [ins->sreg1] &&
 653                                                 ((defs [ins->sreg1]->opcode == OP_ICONST) || defs [ins->sreg1]->opcode == OP_PCONST) &&
 654                                                 defs [ins->sreg2]) {
 655                                                 /* Both arguments are constants, perform cfold */
 656                                                 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], defs [ins->sreg2], TRUE);
 657                                         } else if ((srcindex == 0) && (ins->sreg2 != -1) && defs [ins->sreg2]) {
 658                                                 /* Arg 1 is constant, swap arguments if possible */
 659                                                 int opcode = ins->opcode;
 660                                                 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], defs [ins->sreg2], TRUE);
 661                                                 if (ins->opcode != opcode) {
 662                                                         /* Allow further iterations */
 663                                                         srcindex = -1;
 664                                                         continue;
 665                                                 }
 666                                         } else if ((srcindex == 0) && (ins->sreg2 == -1)) {
 667                                                 /* Constant unop, perform cfold */
 668                                                 mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], NULL, TRUE);
 669                                         }
 670
 671                                         opcode2 = mono_op_to_op_imm (ins->opcode);
 672                                         if ((opcode2 != -1) && mono_arch_is_inst_imm (def->inst_c0) && ((srcindex == 1) || (ins->sreg2 == -1))) {
 673                                                 ins->opcode = opcode2;
 674                                                 if ((def->opcode == OP_I8CONST) && (sizeof (gpointer) == 4)) {
 675                                                         ins->inst_ls_word = def->inst_ls_word;
 676                                                         ins->inst_ms_word = def->inst_ms_word;
 677                                                 } else {
 678                                                         ins->inst_imm = def->inst_c0;
 679                                                 }
 680                                                 sregs [srcindex] = -1;
 681                                                 mono_inst_set_src_registers (ins, sregs);
 682
 683                                                 if ((opcode2 == OP_VOIDCALL) || (opcode2 == OP_CALL) || (opcode2 == OP_LCALL) || (opcode2 == OP_FCALL))
 684                                                         ((MonoCallInst*)ins)->fptr = (gpointer)ins->inst_imm;
 685
 686                                                 /* Allow further iterations */
 687                                                 srcindex = -1;
 688                                                 continue;
 689                                         }
 690                                         else {
 691                                                 /* Special cases */
 692 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 693                                                 if ((ins->opcode == OP_X86_LEA) && (srcindex == 1)) {
 694 #if SIZEOF_REGISTER == 8
 695                                                         /* FIXME: Use OP_PADD_IMM when the new JIT is done */
 696                                                         ins->opcode = OP_LADD_IMM;
 697 #else
 698                                                         ins->opcode = OP_ADD_IMM;
 699 #endif
 700                                                         ins->inst_imm += def->inst_c0 << ins->backend.shift_amount;
 701                                                         ins->sreg2 = -1;
 702                                                 }
 703 #endif
 704                                                 opcode2 = mono_load_membase_to_load_mem (ins->opcode);
 705                                                 if ((srcindex == 0) && (opcode2 != -1) && mono_arch_is_inst_imm (def->inst_c0)) {
 706                                                         ins->opcode = opcode2;
 707                                                         ins->inst_imm = def->inst_c0 + ins->inst_offset;
 708                                                         ins->sreg1 = -1;
 709                                                 }
 710                                         }
 711                                 }
 712                                 else if (((def->opcode == OP_ADD_IMM) || (def->opcode == OP_LADD_IMM)) && (MONO_IS_LOAD_MEMBASE (ins) || MONO_ARCH_IS_OP_MEMBASE (ins->opcode))) {
 713                                         /* ADD_IMM is created by spill_global_vars */
 714                                         /*
 715                                          * We have to guarantee that def->sreg1 haven't changed since def->dreg
 716                                          * was defined. cfg->frame_reg is assumed to remain constant.
 717                                          */
 718                                         if ((def->sreg1 == cfg->frame_reg) || ((mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1))) {
 719                                                 ins->inst_basereg = def->sreg1;
 720                                                 ins->inst_offset += def->inst_imm;
 721                                         }
 722                                 } else if ((ins->opcode == OP_ISUB_IMM) && (def->opcode == OP_IADD_IMM) && (mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1)) {
 723                                         ins->sreg1 = def->sreg1;
 724                                         ins->inst_imm -= def->inst_imm;
 725                                 } else if ((ins->opcode == OP_IADD_IMM) && (def->opcode == OP_ISUB_IMM) && (mono_inst_next (def, filter) == ins) && (def->dreg != def->sreg1)) {
 726                                         ins->sreg1 = def->sreg1;
 727                                         ins->inst_imm -= def->inst_imm;
 728                                 } else if (ins->opcode == OP_STOREI1_MEMBASE_REG &&
 729                                                    (def->opcode == OP_ICONV_TO_U1 || def->opcode == OP_ICONV_TO_I1 || def->opcode == OP_SEXT_I4 || (SIZEOF_REGISTER == 8 && def->opcode == OP_LCONV_TO_U1)) &&
 730                                                    (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg]))) {
 731                                         /* Avoid needless sign extension */
 732                                         ins->sreg1 = def->sreg1;
 733                                 } else if (ins->opcode == OP_STOREI2_MEMBASE_REG &&
 734                                                    (def->opcode == OP_ICONV_TO_U2 || def->opcode == OP_ICONV_TO_I2 || def->opcode == OP_SEXT_I4 || (SIZEOF_REGISTER == 8 && def->opcode == OP_LCONV_TO_I2)) &&
 735                                                    (!defs [def->sreg1] || (def_index [def->sreg1] < def_index [sreg]))) {
 736                                         /* Avoid needless sign extension */
 737                                         ins->sreg1 = def->sreg1;
 738                                 } else if (ins->opcode == OP_COMPARE_IMM && def->opcode == OP_LDADDR && ins->inst_imm == 0) {
 739                                         MonoInst dummy_arg1;
 740
 741                                         memset (&dummy_arg1, 0, sizeof (MonoInst));
 742                                         dummy_arg1.opcode = OP_ICONST;
 743                                         dummy_arg1.inst_c0 = 1;
 744
 745                                         mono_constant_fold_ins (cfg, ins, &dummy_arg1, NULL, TRUE);
 746                                 } else if (srcindex == 0 && ins->opcode == OP_COMPARE && defs [ins->sreg1]->opcode == OP_PCONST && defs [ins->sreg2] && defs [ins->sreg2]->opcode == OP_PCONST) {
 747                                         /* typeof(T) == typeof(..) */
 748                                         mono_constant_fold_ins (cfg, ins, defs [ins->sreg1], defs [ins->sreg2], TRUE);
 749                                 }
 750                         }
 751
 752                         g_assert (cfg->cbb == bb_opt);
 753                         g_assert (!bb_opt->code);
 754                         /* Do strength reduction here */
 755                         if (mono_strength_reduction_ins (cfg, ins, &spec) && max < cfg->next_vreg) {
 756                                 MonoInst **defs_prev = defs;
 757                                 gint32 *def_index_prev = def_index;
 758                                 guint32 prev_max = max;
 759                                 guint32 additional_vregs = cfg->next_vreg - initial_max_vregs;
 760
 761                                 /* We have more vregs so we need to reallocate defs and def_index arrays */
 762                                 max  = initial_max_vregs + additional_vregs * 2;
 763                                 defs = (MonoInst **)mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * max);
 764                                 def_index = (gint32 *)mono_mempool_alloc (cfg->mempool, sizeof (guint32) * max);
 765
 766                                 /* Keep the entries for the previous vregs, zero the rest */
 767                                 memcpy (defs, defs_prev, sizeof (MonoInst*) * prev_max);
 768                                 memset (defs + prev_max, 0, sizeof (MonoInst*) * (max - prev_max));
 769                                 memcpy (def_index, def_index_prev, sizeof (guint32) * prev_max);
 770                                 memset (def_index + prev_max, 0, sizeof (guint32) * (max - prev_max));
 771                         }
 772
 773                         if (cfg->cbb->code || (cfg->cbb != bb_opt)) {
 774                                 MonoInst *saved_prev = ins->prev;
 775
 776                                 /* If we have code in cbb, we need to replace ins with the decomposition */
 777                                 mono_replace_ins (cfg, bb, ins, &ins->prev, bb_opt, cfg->cbb);
 778                                 bb_opt->code = bb_opt->last_ins = NULL;
 779                                 bb_opt->in_count = bb_opt->out_count = 0;
 780                                 cfg->cbb = bb_opt;
 781
 782                                 /* ins is hanging, continue scanning the emitted code */
 783                                 ins = saved_prev;
 784                                 continue;
 785                         }
 786
 787                         if (spec [MONO_INST_DEST] != ' ') {
 788                                 MonoInst *def = defs [ins->dreg];
 789
 790                                 if (def && (def->opcode == OP_ADD_IMM) && (def->sreg1 == cfg->frame_reg) && (MONO_IS_STORE_MEMBASE (ins))) {
 791                                         /* ADD_IMM is created by spill_global_vars */
 792                                         /* cfg->frame_reg is assumed to remain constant */
 793                                         ins->inst_destbasereg = def->sreg1;
 794                                         ins->inst_offset += def->inst_imm;
 795                                 }
 796
 797                                 if (!MONO_IS_STORE_MEMBASE (ins) && !vreg_is_volatile (cfg, ins->dreg)) {
 798                                         defs [ins->dreg] = ins;
 799                                         def_index [ins->dreg] = ins_index;
 800                                 }
 801                         }
 802
 803                         if (MONO_IS_CALL (ins))
 804                                 last_call_index = ins_index;
 805
 806                         ins_index ++;
 807                 }
 808         }
 809 }
 810
 811 static inline gboolean
 812 reg_is_softreg_no_fpstack (int reg, const char spec)
 813 {
 814         return (spec == 'i' && reg >= MONO_MAX_IREGS)
 815                 || ((spec == 'f' && reg >= MONO_MAX_FREGS) && !MONO_ARCH_USE_FPSTACK)
 816 #ifdef MONO_ARCH_SIMD_INTRINSICS
 817                 || (spec == 'x' && reg >= MONO_MAX_XREGS)
 818 #endif
 819                 || (spec == 'v');
 820 }
 821
 822 static inline gboolean
 823 reg_is_softreg (int reg, const char spec)
 824 {
 825         return (spec == 'i' && reg >= MONO_MAX_IREGS)
 826                 || (spec == 'f' && reg >= MONO_MAX_FREGS)
 827 #ifdef MONO_ARCH_SIMD_INTRINSICS
 828                 || (spec == 'x' && reg >= MONO_MAX_XREGS)
 829 #endif
 830                 || (spec == 'v');
 831 }
 832
 833 static inline gboolean
 834 mono_is_simd_accessor (MonoInst *ins)
 835 {
 836         switch (ins->opcode) {
 837 #ifdef MONO_ARCH_SIMD_INTRINSICS
 838         case OP_INSERT_I1:
 839         case OP_INSERT_I2:
 840         case OP_INSERT_I4:
 841         case OP_INSERT_I8:
 842         case OP_INSERT_R4:
 843         case OP_INSERT_R8:
 844
 845         case OP_INSERTX_U1_SLOW:
 846         case OP_INSERTX_I4_SLOW:
 847         case OP_INSERTX_R4_SLOW:
 848         case OP_INSERTX_R8_SLOW:
 849         case OP_INSERTX_I8_SLOW:
 850                 return TRUE;
 851 #endif
 852         default:
 853                 return FALSE;
 854         }
 855 }
 856
 857 /**
 858  * mono_local_deadce:
 859  *
 860  *   Get rid of the dead assignments to local vregs like the ones created by the
 861  * copyprop pass.
 862  */
 863 void
 864 mono_local_deadce (MonoCompile *cfg)
 865 {
 866         MonoBasicBlock *bb;
 867         MonoInst *ins, *prev;
 868         MonoBitSet *used, *defined;
 869
 870         //mono_print_code (cfg, "BEFORE LOCAL-DEADCE");
 871
 872         /*
 873          * Assignments to global vregs can't be eliminated so this pass must come
 874          * after the handle_global_vregs () pass.
 875          */
 876
 877         used = mono_bitset_mp_new_noinit (cfg->mempool, cfg->next_vreg + 1);
 878         defined = mono_bitset_mp_new_noinit (cfg->mempool, cfg->next_vreg + 1);
 879
 880         /* First pass: collect liveness info */
 881         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
 882                 /* Manually init the defs entries used by the bblock */
 883                 MONO_BB_FOR_EACH_INS (bb, ins) {
 884                         const char *spec = INS_INFO (ins->opcode);
 885                         int sregs [MONO_MAX_SRC_REGS];
 886                         int num_sregs, i;
 887
 888                         if (spec [MONO_INST_DEST] != ' ') {
 889                                 mono_bitset_clear_fast (used, ins->dreg);
 890                                 mono_bitset_clear_fast (defined, ins->dreg);
 891 #if SIZEOF_REGISTER == 4
 892                                 /* Regpairs */
 893                                 mono_bitset_clear_fast (used, ins->dreg + 1);
 894                                 mono_bitset_clear_fast (defined, ins->dreg + 1);
 895 #endif
 896                         }
 897                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 898                         for (i = 0; i < num_sregs; ++i) {
 899                                 mono_bitset_clear_fast (used, sregs [i]);
 900 #if SIZEOF_REGISTER == 4
 901                                 mono_bitset_clear_fast (used, sregs [i] + 1);
 902 #endif
 903                         }
 904                 }
 905
 906                 /*
 907                  * Make a reverse pass over the instruction list
 908                  */
 909                 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
 910                         const char *spec = INS_INFO (ins->opcode);
 911                         int sregs [MONO_MAX_SRC_REGS];
 912                         int num_sregs, i;
 913                         MonoInst *prev_f = mono_inst_prev (ins, FILTER_NOP | FILTER_IL_SEQ_POINT);
 914
 915                         if (ins->opcode == OP_NOP) {
 916                                 MONO_DELETE_INS (bb, ins);
 917                                 continue;
 918                         }
 919
 920                         g_assert (ins->opcode > MONO_CEE_LAST);
 921
 922                         if (MONO_IS_NON_FP_MOVE (ins) && prev_f) {
 923                                 MonoInst *def;
 924                                 const char *spec2;
 925
 926                                 def = prev_f;
 927                                 spec2 = INS_INFO (def->opcode);
 928
 929                                 /*
 930                                  * Perform a limited kind of reverse copy propagation, i.e.
 931                                  * transform B <- FOO; A <- B into A <- FOO
 932                                  * This isn't copyprop, not deadce, but it can only be performed
 933                                  * after handle_global_vregs () has run.
 934                                  */
 935                                 if (!get_vreg_to_inst (cfg, ins->sreg1) && (spec2 [MONO_INST_DEST] != ' ') && (def->dreg == ins->sreg1) && !mono_bitset_test_fast (used, ins->sreg1) && !MONO_IS_STORE_MEMBASE (def) && reg_is_softreg (ins->sreg1, spec [MONO_INST_DEST]) && !mono_is_simd_accessor (def)) {
 936                                         if (cfg->verbose_level > 2) {
 937                                                 printf ("\tReverse copyprop in BB%d on ", bb->block_num);
 938                                                 mono_print_ins (ins);
 939                                         }
 940
 941                                         def->dreg = ins->dreg;
 942                                         MONO_DELETE_INS (bb, ins);
 943                                         spec = INS_INFO (ins->opcode);
 944                                 }
 945                         }
 946
 947                         /* Enabling this on x86 could screw up the fp stack */
 948                         if (reg_is_softreg_no_fpstack (ins->dreg, spec [MONO_INST_DEST])) {
 949                                 /*
 950                                  * Assignments to global vregs can only be eliminated if there is another
 951                                  * assignment to the same vreg later in the same bblock.
 952                                  */
 953                                 if (!mono_bitset_test_fast (used, ins->dreg) &&
 954                                         (!get_vreg_to_inst (cfg, ins->dreg) || (!bb->extended && !vreg_is_volatile (cfg, ins->dreg) && mono_bitset_test_fast (defined, ins->dreg))) &&
 955                                         MONO_INS_HAS_NO_SIDE_EFFECT (ins)) {
 956                                         /* Happens with CMOV instructions */
 957                                         if (prev_f && prev_f->opcode == OP_ICOMPARE_IMM) {
 958                                                 MonoInst *prev = prev_f;
 959                                                 /*
 960                                                  * Can't use DELETE_INS since that would interfere with the
 961                                                  * FOR_EACH_INS loop.
 962                                                  */
 963                                                 NULLIFY_INS (prev);
 964                                         }
 965                                         //printf ("DEADCE: "); mono_print_ins (ins);
 966                                         MONO_DELETE_INS (bb, ins);
 967                                         spec = INS_INFO (ins->opcode);
 968                                 }
 969
 970                                 if (spec [MONO_INST_DEST] != ' ')
 971                                         mono_bitset_clear_fast (used, ins->dreg);
 972                         }
 973
 974                         if (spec [MONO_INST_DEST] != ' ')
 975                                 mono_bitset_set_fast (defined, ins->dreg);
 976                         num_sregs = mono_inst_get_src_registers (ins, sregs);
 977                         for (i = 0; i < num_sregs; ++i)
 978                                 mono_bitset_set_fast (used, sregs [i]);
 979                         if (MONO_IS_STORE_MEMBASE (ins))
 980                                 mono_bitset_set_fast (used, ins->dreg);
 981
 982                         if (MONO_IS_CALL (ins)) {
 983                                 MonoCallInst *call = (MonoCallInst*)ins;
 984                                 GSList *l;
 985
 986                                 if (call->out_ireg_args) {
 987                                         for (l = call->out_ireg_args; l; l = l->next) {
 988                                                 guint32 regpair, reg;
 989
 990                                                 regpair = (guint32)(gssize)(l->data);
 991                                                 reg = regpair & 0xffffff;
 992
 993                                                 mono_bitset_set_fast (used, reg);
 994                                         }
 995                                 }
 996
 997                                 if (call->out_freg_args) {
 998                                         for (l = call->out_freg_args; l; l = l->next) {
 999                                                 guint32 regpair, reg;
1000
1001                                                 regpair = (guint32)(gssize)(l->data);
1002                                                 reg = regpair & 0xffffff;
1003
1004                                                 mono_bitset_set_fast (used, reg);
1005                                         }
1006                                 }
1007                         }
1008                 }
1009         }
1010
1011         //mono_print_code (cfg, "AFTER LOCAL-DEADCE");
1012 }
1013
1014 #else /* !DISABLE_JIT */
1015
1016 MONO_EMPTY_SOURCE_FILE (local_propagation);
1017
1018 #endif /* !DISABLE_JIT */