2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
19 #ifdef __native_client_codegen__
20 extern gint8 nacl_align_byte;
21 #endif /* __native_client_codegen__ */
24 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
25 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do { mono_nacl_align_inst(inst_ptr_ptr, inst_len); } while (0)
26 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
27 #define x86_call_sequence_post_val(inst) \
28 (mono_nacl_align_call(&_code_start, &(inst)), _code_start);
29 #define x86_call_sequence_pre(inst) x86_call_sequence_pre_val((inst))
30 #define x86_call_sequence_post(inst) x86_call_sequence_post_val((inst))
32 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do {} while (0)
33 /* Two variants are needed to avoid warnings */
34 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
35 #define x86_call_sequence_post_val(inst) _code_start
36 #define x86_call_sequence_pre(inst)
37 #define x86_call_sequence_post(inst)
38 #endif /* __native_client_codegen__ */
42 // x86 register numbers
69 // opcodes for alu instructions
83 // opcodes for shift instructions
98 // opcodes for floating-point instructions
112 // integer conditions codes
115 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
116 X86_CC_NE = 1, X86_CC_NZ = 1,
117 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
118 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
119 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
120 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
121 X86_CC_LZ = 6, X86_CC_S = 6,
122 X86_CC_GEZ = 7, X86_CC_NS = 7,
123 X86_CC_P = 8, X86_CC_PE = 8,
124 X86_CC_NP = 9, X86_CC_PO = 9,
136 X86_FP_CC_MASK = 0x4500
139 /* FP control word */
141 X86_FPCW_INVOPEX_MASK = 0x1,
142 X86_FPCW_DENOPEX_MASK = 0x2,
143 X86_FPCW_ZERODIV_MASK = 0x4,
144 X86_FPCW_OVFEX_MASK = 0x8,
145 X86_FPCW_UNDFEX_MASK = 0x10,
146 X86_FPCW_PRECEX_MASK = 0x20,
147 X86_FPCW_PRECC_MASK = 0x300,
148 X86_FPCW_ROUNDC_MASK = 0xc00,
150 /* values for precision control */
151 X86_FPCW_PREC_SINGLE = 0,
152 X86_FPCW_PREC_DOUBLE = 0x200,
153 X86_FPCW_PREC_EXTENDED = 0x300,
155 /* values for rounding control */
156 X86_FPCW_ROUND_NEAREST = 0,
157 X86_FPCW_ROUND_DOWN = 0x400,
158 X86_FPCW_ROUND_UP = 0x800,
159 X86_FPCW_ROUND_TOZERO = 0xc00
166 X86_LOCK_PREFIX = 0xF0,
167 X86_REPNZ_PREFIX = 0xF2,
168 X86_REPZ_PREFIX = 0xF3,
169 X86_REP_PREFIX = 0xF3,
170 X86_CS_PREFIX = 0x2E,
171 X86_SS_PREFIX = 0x36,
172 X86_DS_PREFIX = 0x3E,
173 X86_ES_PREFIX = 0x26,
174 X86_FS_PREFIX = 0x64,
175 X86_GS_PREFIX = 0x65,
176 X86_UNLIKELY_PREFIX = 0x2E,
177 X86_LIKELY_PREFIX = 0x3E,
178 X86_OPERAND_PREFIX = 0x66,
179 X86_ADDRESS_PREFIX = 0x67
182 static const unsigned char
183 x86_cc_unsigned_map [X86_NCC] = {
198 static const unsigned char
199 x86_cc_signed_map [X86_NCC] = {
219 #define X86_NOBASEREG (-1)
222 // bitvector mask for callee-saved registers
224 #define X86_ESI_MASK (1<<X86_ESI)
225 #define X86_EDI_MASK (1<<X86_EDI)
226 #define X86_EBX_MASK (1<<X86_EBX)
227 #define X86_EBP_MASK (1<<X86_EBP)
229 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
230 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
231 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
233 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
234 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
236 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
241 // +--------------------------------+
242 // | in_arg[0] = var[0] |
243 // | in_arg[1] = var[1] |
245 // | in_arg[n_arg-1] = var[n_arg-1] |
246 // +--------------------------------+
248 // +--------------------------------+
249 // | saved EBP | <-- frame pointer (EBP)
250 // +--------------------------------+
252 // +--------------------------------+
254 // | var[n_arg+1] | local variables area
257 // +--------------------------------+
260 // | spill area | area for spilling mimic stack
262 // +--------------------------------|
264 // | ebp [ESP_Frame only] |
265 // | esi | 0..3 callee-saved regs
266 // | edi | <-- stack pointer (ESP)
267 // +--------------------------------+
269 // | stk1 | operand stack area/
270 // | . . . | out args
272 // +--------------------------------|
279 * useful building blocks
281 #define x86_modrm_mod(modrm) ((modrm) >> 6)
282 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
283 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
285 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
286 #define x86_imm_emit32(inst,imm) \
288 x86_imm_buf imb; imb.val = (int) (imm); \
289 *(inst)++ = imb.b [0]; \
290 *(inst)++ = imb.b [1]; \
291 *(inst)++ = imb.b [2]; \
292 *(inst)++ = imb.b [3]; \
294 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
295 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
296 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
297 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
299 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
300 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
301 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
302 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
304 #define kMaxMembaseEmitPadding 6
306 #define x86_membase_emit_body(inst,r,basereg,disp) do {\
307 if ((basereg) == X86_ESP) { \
309 x86_address_byte ((inst), 0, (r), X86_ESP); \
310 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
311 } else if (x86_is_imm8((disp))) { \
312 x86_address_byte ((inst), 1, (r), X86_ESP); \
313 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
314 x86_imm_emit8 ((inst), (disp)); \
316 x86_address_byte ((inst), 2, (r), X86_ESP); \
317 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
318 x86_imm_emit32 ((inst), (disp)); \
322 if ((disp) == 0 && (basereg) != X86_EBP) { \
323 x86_address_byte ((inst), 0, (r), (basereg)); \
326 if (x86_is_imm8((disp))) { \
327 x86_address_byte ((inst), 1, (r), (basereg)); \
328 x86_imm_emit8 ((inst), (disp)); \
330 x86_address_byte ((inst), 2, (r), (basereg)); \
331 x86_imm_emit32 ((inst), (disp)); \
335 #if defined(__native_client_codegen__) && defined(TARGET_AMD64)
336 #define x86_membase_emit(inst,r,basereg,disp) \
338 amd64_nacl_membase_handler(&(inst), (basereg), (disp), (r)) ; \
340 #else /* __default_codegen__ || 32-bit NaCl codegen */
341 #define x86_membase_emit(inst,r,basereg,disp) \
343 x86_membase_emit_body((inst),(r),(basereg),(disp)); \
347 #define kMaxMemindexEmitPadding 6
349 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
351 if ((basereg) == X86_NOBASEREG) { \
352 x86_address_byte ((inst), 0, (r), 4); \
353 x86_address_byte ((inst), (shift), (indexreg), 5); \
354 x86_imm_emit32 ((inst), (disp)); \
355 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
356 x86_address_byte ((inst), 0, (r), 4); \
357 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
358 } else if (x86_is_imm8((disp))) { \
359 x86_address_byte ((inst), 1, (r), 4); \
360 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
361 x86_imm_emit8 ((inst), (disp)); \
363 x86_address_byte ((inst), 2, (r), 4); \
364 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
365 x86_imm_emit32 ((inst), (disp)); \
370 * target is the position in the code where to jump to:
372 * .. output loop code...
373 * x86_mov_reg_imm (code, X86_EAX, 0);
375 * x86_loop (code, -1);
379 * x86_patch (loop, target);
381 * ins should point at the start of the instruction that encodes a target.
382 * the instruction is inspected for validity and the correct displacement
385 #define x86_do_patch(ins,target) \
387 unsigned char* pos = (ins) + 1; \
388 int disp, size = 0; \
389 switch (*(unsigned char*)(ins)) { \
390 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
391 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
392 ++size; ++pos; break; /* prefix for 32-bit disp */ \
393 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
394 case 0xeb: /* jump8 */ \
395 /* conditional jump opcodes */ \
396 case 0x70: case 0x71: case 0x72: case 0x73: \
397 case 0x74: case 0x75: case 0x76: case 0x77: \
398 case 0x78: case 0x79: case 0x7a: case 0x7b: \
399 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
401 default: assert (0); \
403 disp = (target) - pos; \
404 if (size) x86_imm_emit32 (pos, disp - 4); \
405 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
409 #if defined( __native_client_codegen__ ) && defined(TARGET_X86)
411 #define x86_skip_nops(inst) \
416 if (inst[0] == 0x90) { \
420 if (inst[0] == 0x8b && inst[1] == 0xc0) { \
424 if (inst[0] == 0x8d && inst[1] == 0x6d \
425 && inst[2] == 0x00) { \
429 if (inst[0] == 0x8d && inst[1] == 0x64 \
430 && inst[2] == 0x24 && inst[3] == 0x00) { \
434 /* skip inst+=5 case because it's the 4-byte + 1-byte case */ \
435 if (inst[0] == 0x8d && inst[1] == 0xad \
436 && inst[2] == 0x00 && inst[3] == 0x00 \
437 && inst[4] == 0x00 && inst[5] == 0x00) { \
441 if (inst[0] == 0x8d && inst[1] == 0xa4 \
442 && inst[2] == 0x24 && inst[3] == 0x00 \
443 && inst[4] == 0x00 && inst[5] == 0x00 \
444 && inst[6] == 0x00 ) { \
448 } while ( in_nop ); \
451 #if defined(__native_client__)
452 #define x86_patch(ins,target) \
454 unsigned char* inst = (ins); \
455 guint8* new_target = nacl_modify_patch_target((target)); \
456 x86_skip_nops((inst)); \
457 x86_do_patch((inst), new_target); \
459 #else /* __native_client__ */
460 #define x86_patch(ins,target) \
462 unsigned char* inst = (ins); \
463 guint8* new_target = (target); \
464 x86_skip_nops((inst)); \
465 x86_do_patch((inst), new_target); \
467 #endif /* __native_client__ */
470 #define x86_patch(ins,target) do { x86_do_patch((ins), (target)); } while (0)
471 #endif /* __native_client_codegen__ */
473 #ifdef __native_client_codegen__
474 /* The breakpoint instruction is illegal in Native Client, although the HALT */
475 /* instruction is allowed. The breakpoint is used several places in mini-x86.c */
476 /* and exceptions-x86.c. */
477 #define x86_breakpoint(inst) \
482 #define x86_breakpoint(inst) \
488 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
489 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
490 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
491 #define x86_stosd(inst) x86_stosl((inst))
492 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
493 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
494 #define x86_movsd(inst) x86_movsl((inst))
496 #if defined(__default_codegen__)
497 #define x86_prefix(inst,p) \
499 *(inst)++ =(unsigned char) (p); \
501 #elif defined(__native_client_codegen__)
502 #if defined(TARGET_X86)
503 /* kNaClAlignment - 1 is the max value we can pass into x86_codegen_pre. */
504 /* This keeps us from having to call x86_codegen_pre with specific */
505 /* knowledge of the size of the instruction that follows it, and */
506 /* localizes the alignment requirement to this spot. */
507 #define x86_prefix(inst,p) \
509 x86_codegen_pre(&(inst), kNaClAlignment - 1); \
510 *(inst)++ =(unsigned char) (p); \
512 #elif defined(TARGET_AMD64)
513 /* We need to tag any prefixes so we can perform proper membase sandboxing */
514 /* See: mini-amd64.c:amd64_nacl_membase_handler for verbose details */
515 #define x86_prefix(inst,p) \
517 amd64_nacl_tag_legacy_prefix((inst)); \
518 *(inst)++ =(unsigned char) (p); \
521 #endif /* TARGET_AMD64 */
523 #endif /* __native_client_codegen__ */
525 #define x86_mfence(inst) \
527 x86_codegen_pre(&(inst), 3); \
533 #define x86_rdtsc(inst) \
535 x86_codegen_pre(&(inst), 2); \
540 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
542 x86_codegen_pre(&(inst), 3); \
543 *(inst)++ = (unsigned char)0x0f; \
544 *(inst)++ = (unsigned char)0xb1; \
545 x86_reg_emit ((inst), (reg), (dreg)); \
548 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
550 x86_codegen_pre(&(inst), 7); \
551 *(inst)++ = (unsigned char)0x0f; \
552 *(inst)++ = (unsigned char)0xb1; \
553 x86_mem_emit ((inst), (reg), (mem)); \
556 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
558 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
559 *(inst)++ = (unsigned char)0x0f; \
560 *(inst)++ = (unsigned char)0xb1; \
561 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
564 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
566 x86_codegen_pre(&(inst), 2); \
568 *(inst)++ = (unsigned char)0x86; \
570 *(inst)++ = (unsigned char)0x87; \
571 x86_reg_emit ((inst), (reg), (dreg)); \
574 #define x86_xchg_mem_reg(inst,mem,reg,size) \
576 x86_codegen_pre(&(inst), 6); \
578 *(inst)++ = (unsigned char)0x86; \
580 *(inst)++ = (unsigned char)0x87; \
581 x86_mem_emit ((inst), (reg), (mem)); \
584 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
586 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
588 *(inst)++ = (unsigned char)0x86; \
590 *(inst)++ = (unsigned char)0x87; \
591 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
594 #define x86_xadd_reg_reg(inst,dreg,reg,size) \
596 x86_codegen_pre(&(inst), 3); \
597 *(inst)++ = (unsigned char)0x0F; \
599 *(inst)++ = (unsigned char)0xC0; \
601 *(inst)++ = (unsigned char)0xC1; \
602 x86_reg_emit ((inst), (reg), (dreg)); \
605 #define x86_xadd_mem_reg(inst,mem,reg,size) \
607 x86_codegen_pre(&(inst), 7); \
608 *(inst)++ = (unsigned char)0x0F; \
610 *(inst)++ = (unsigned char)0xC0; \
612 *(inst)++ = (unsigned char)0xC1; \
613 x86_mem_emit ((inst), (reg), (mem)); \
616 #define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \
618 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
619 *(inst)++ = (unsigned char)0x0F; \
621 *(inst)++ = (unsigned char)0xC0; \
623 *(inst)++ = (unsigned char)0xC1; \
624 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
627 #define x86_inc_mem(inst,mem) \
629 x86_codegen_pre(&(inst), 6); \
630 *(inst)++ = (unsigned char)0xff; \
631 x86_mem_emit ((inst), 0, (mem)); \
634 #define x86_inc_membase(inst,basereg,disp) \
636 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
637 *(inst)++ = (unsigned char)0xff; \
638 x86_membase_emit ((inst), 0, (basereg), (disp)); \
641 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
643 #define x86_dec_mem(inst,mem) \
645 x86_codegen_pre(&(inst), 6); \
646 *(inst)++ = (unsigned char)0xff; \
647 x86_mem_emit ((inst), 1, (mem)); \
650 #define x86_dec_membase(inst,basereg,disp) \
652 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
653 *(inst)++ = (unsigned char)0xff; \
654 x86_membase_emit ((inst), 1, (basereg), (disp)); \
657 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
659 #define x86_not_mem(inst,mem) \
661 x86_codegen_pre(&(inst), 6); \
662 *(inst)++ = (unsigned char)0xf7; \
663 x86_mem_emit ((inst), 2, (mem)); \
666 #define x86_not_membase(inst,basereg,disp) \
668 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
669 *(inst)++ = (unsigned char)0xf7; \
670 x86_membase_emit ((inst), 2, (basereg), (disp)); \
673 #define x86_not_reg(inst,reg) \
675 x86_codegen_pre(&(inst), 2); \
676 *(inst)++ = (unsigned char)0xf7; \
677 x86_reg_emit ((inst), 2, (reg)); \
680 #define x86_neg_mem(inst,mem) \
682 x86_codegen_pre(&(inst), 6); \
683 *(inst)++ = (unsigned char)0xf7; \
684 x86_mem_emit ((inst), 3, (mem)); \
687 #define x86_neg_membase(inst,basereg,disp) \
689 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
690 *(inst)++ = (unsigned char)0xf7; \
691 x86_membase_emit ((inst), 3, (basereg), (disp)); \
694 #define x86_neg_reg(inst,reg) \
696 x86_codegen_pre(&(inst), 2); \
697 *(inst)++ = (unsigned char)0xf7; \
698 x86_reg_emit ((inst), 3, (reg)); \
701 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
703 #define x86_alu_reg_imm(inst,opc,reg,imm) \
705 if ((reg) == X86_EAX) { \
706 x86_codegen_pre(&(inst), 5); \
707 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
708 x86_imm_emit32 ((inst), (imm)); \
711 if (x86_is_imm8((imm))) { \
712 x86_codegen_pre(&(inst), 3); \
713 *(inst)++ = (unsigned char)0x83; \
714 x86_reg_emit ((inst), (opc), (reg)); \
715 x86_imm_emit8 ((inst), (imm)); \
717 x86_codegen_pre(&(inst), 6); \
718 *(inst)++ = (unsigned char)0x81; \
719 x86_reg_emit ((inst), (opc), (reg)); \
720 x86_imm_emit32 ((inst), (imm)); \
724 #define x86_alu_mem_imm(inst,opc,mem,imm) \
726 if (x86_is_imm8((imm))) { \
727 x86_codegen_pre(&(inst), 7); \
728 *(inst)++ = (unsigned char)0x83; \
729 x86_mem_emit ((inst), (opc), (mem)); \
730 x86_imm_emit8 ((inst), (imm)); \
732 x86_codegen_pre(&(inst), 10); \
733 *(inst)++ = (unsigned char)0x81; \
734 x86_mem_emit ((inst), (opc), (mem)); \
735 x86_imm_emit32 ((inst), (imm)); \
739 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
741 if (x86_is_imm8((imm))) { \
742 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
743 *(inst)++ = (unsigned char)0x83; \
744 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
745 x86_imm_emit8 ((inst), (imm)); \
747 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
748 *(inst)++ = (unsigned char)0x81; \
749 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
750 x86_imm_emit32 ((inst), (imm)); \
754 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
756 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
757 *(inst)++ = (unsigned char)0x80; \
758 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
759 x86_imm_emit8 ((inst), (imm)); \
762 #define x86_alu_mem_reg(inst,opc,mem,reg) \
764 x86_codegen_pre(&(inst), 6); \
765 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
766 x86_mem_emit ((inst), (reg), (mem)); \
769 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
771 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
772 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
773 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
776 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
778 x86_codegen_pre(&(inst), 2); \
779 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
780 x86_reg_emit ((inst), (dreg), (reg)); \
784 * @x86_alu_reg8_reg8:
785 * Supports ALU operations between two 8-bit registers.
786 * dreg := dreg opc reg
787 * X86_Reg_No enum is used to specify the registers.
788 * Additionally is_*_h flags are used to specify what part
789 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
790 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
792 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
794 x86_codegen_pre(&(inst), 2); \
795 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
796 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
799 #define x86_alu_reg_mem(inst,opc,reg,mem) \
801 x86_codegen_pre(&(inst), 6); \
802 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
803 x86_mem_emit ((inst), (reg), (mem)); \
806 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
808 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
809 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
810 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
813 #define x86_test_reg_imm(inst,reg,imm) \
815 x86_codegen_pre(&(inst), 6); \
816 if ((reg) == X86_EAX) { \
817 *(inst)++ = (unsigned char)0xa9; \
819 *(inst)++ = (unsigned char)0xf7; \
820 x86_reg_emit ((inst), 0, (reg)); \
822 x86_imm_emit32 ((inst), (imm)); \
825 #define x86_test_mem_imm8(inst,mem,imm) \
827 x86_codegen_pre(&(inst), 7); \
828 *(inst)++ = (unsigned char)0xf6; \
829 x86_mem_emit ((inst), 0, (mem)); \
830 x86_imm_emit8 ((inst), (imm)); \
833 #define x86_test_mem_imm(inst,mem,imm) \
835 x86_codegen_pre(&(inst), 10); \
836 *(inst)++ = (unsigned char)0xf7; \
837 x86_mem_emit ((inst), 0, (mem)); \
838 x86_imm_emit32 ((inst), (imm)); \
841 #define x86_test_membase_imm(inst,basereg,disp,imm) \
843 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
844 *(inst)++ = (unsigned char)0xf7; \
845 x86_membase_emit ((inst), 0, (basereg), (disp)); \
846 x86_imm_emit32 ((inst), (imm)); \
849 #define x86_test_reg_reg(inst,dreg,reg) \
851 x86_codegen_pre(&(inst), 2); \
852 *(inst)++ = (unsigned char)0x85; \
853 x86_reg_emit ((inst), (reg), (dreg)); \
856 #define x86_test_mem_reg(inst,mem,reg) \
858 x86_codegen_pre(&(inst), 6); \
859 *(inst)++ = (unsigned char)0x85; \
860 x86_mem_emit ((inst), (reg), (mem)); \
863 #define x86_test_membase_reg(inst,basereg,disp,reg) \
865 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
866 *(inst)++ = (unsigned char)0x85; \
867 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
870 #define x86_shift_reg_imm(inst,opc,reg,imm) \
873 x86_codegen_pre(&(inst), 2); \
874 *(inst)++ = (unsigned char)0xd1; \
875 x86_reg_emit ((inst), (opc), (reg)); \
877 x86_codegen_pre(&(inst), 3); \
878 *(inst)++ = (unsigned char)0xc1; \
879 x86_reg_emit ((inst), (opc), (reg)); \
880 x86_imm_emit8 ((inst), (imm)); \
884 #define x86_shift_mem_imm(inst,opc,mem,imm) \
887 x86_codegen_pre(&(inst), 6); \
888 *(inst)++ = (unsigned char)0xd1; \
889 x86_mem_emit ((inst), (opc), (mem)); \
891 x86_codegen_pre(&(inst), 7); \
892 *(inst)++ = (unsigned char)0xc1; \
893 x86_mem_emit ((inst), (opc), (mem)); \
894 x86_imm_emit8 ((inst), (imm)); \
898 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
901 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
902 *(inst)++ = (unsigned char)0xd1; \
903 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
905 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
906 *(inst)++ = (unsigned char)0xc1; \
907 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
908 x86_imm_emit8 ((inst), (imm)); \
912 #define x86_shift_reg(inst,opc,reg) \
914 x86_codegen_pre(&(inst), 2); \
915 *(inst)++ = (unsigned char)0xd3; \
916 x86_reg_emit ((inst), (opc), (reg)); \
919 #define x86_shift_mem(inst,opc,mem) \
921 x86_codegen_pre(&(inst), 6); \
922 *(inst)++ = (unsigned char)0xd3; \
923 x86_mem_emit ((inst), (opc), (mem)); \
926 #define x86_shift_membase(inst,opc,basereg,disp) \
928 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
929 *(inst)++ = (unsigned char)0xd3; \
930 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
934 * Multi op shift missing.
937 #define x86_shrd_reg(inst,dreg,reg) \
939 x86_codegen_pre(&(inst), 3); \
940 *(inst)++ = (unsigned char)0x0f; \
941 *(inst)++ = (unsigned char)0xad; \
942 x86_reg_emit ((inst), (reg), (dreg)); \
945 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
947 x86_codegen_pre(&(inst), 4); \
948 *(inst)++ = (unsigned char)0x0f; \
949 *(inst)++ = (unsigned char)0xac; \
950 x86_reg_emit ((inst), (reg), (dreg)); \
951 x86_imm_emit8 ((inst), (shamt)); \
954 #define x86_shld_reg(inst,dreg,reg) \
956 x86_codegen_pre(&(inst), 3); \
957 *(inst)++ = (unsigned char)0x0f; \
958 *(inst)++ = (unsigned char)0xa5; \
959 x86_reg_emit ((inst), (reg), (dreg)); \
962 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
964 x86_codegen_pre(&(inst), 4); \
965 *(inst)++ = (unsigned char)0x0f; \
966 *(inst)++ = (unsigned char)0xa4; \
967 x86_reg_emit ((inst), (reg), (dreg)); \
968 x86_imm_emit8 ((inst), (shamt)); \
974 #define x86_mul_reg(inst,reg,is_signed) \
976 x86_codegen_pre(&(inst), 2); \
977 *(inst)++ = (unsigned char)0xf7; \
978 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
981 #define x86_mul_mem(inst,mem,is_signed) \
983 x86_codegen_pre(&(inst), 6); \
984 *(inst)++ = (unsigned char)0xf7; \
985 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
988 #define x86_mul_membase(inst,basereg,disp,is_signed) \
990 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
991 *(inst)++ = (unsigned char)0xf7; \
992 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
998 #define x86_imul_reg_reg(inst,dreg,reg) \
1000 x86_codegen_pre(&(inst), 3); \
1001 *(inst)++ = (unsigned char)0x0f; \
1002 *(inst)++ = (unsigned char)0xaf; \
1003 x86_reg_emit ((inst), (dreg), (reg)); \
1006 #define x86_imul_reg_mem(inst,reg,mem) \
1008 x86_codegen_pre(&(inst), 7); \
1009 *(inst)++ = (unsigned char)0x0f; \
1010 *(inst)++ = (unsigned char)0xaf; \
1011 x86_mem_emit ((inst), (reg), (mem)); \
1014 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
1016 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1017 *(inst)++ = (unsigned char)0x0f; \
1018 *(inst)++ = (unsigned char)0xaf; \
1019 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1025 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
1027 if (x86_is_imm8 ((imm))) { \
1028 x86_codegen_pre(&(inst), 3); \
1029 *(inst)++ = (unsigned char)0x6b; \
1030 x86_reg_emit ((inst), (dreg), (reg)); \
1031 x86_imm_emit8 ((inst), (imm)); \
1033 x86_codegen_pre(&(inst), 6); \
1034 *(inst)++ = (unsigned char)0x69; \
1035 x86_reg_emit ((inst), (dreg), (reg)); \
1036 x86_imm_emit32 ((inst), (imm)); \
1040 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
1042 if (x86_is_imm8 ((imm))) { \
1043 x86_codegen_pre(&(inst), 7); \
1044 *(inst)++ = (unsigned char)0x6b; \
1045 x86_mem_emit ((inst), (reg), (mem)); \
1046 x86_imm_emit8 ((inst), (imm)); \
1048 x86_codegen_pre(&(inst), 6); \
1049 *(inst)++ = (unsigned char)0x69; \
1050 x86_mem_emit ((inst), (reg), (mem)); \
1051 x86_imm_emit32 ((inst), (imm)); \
1055 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
1057 if (x86_is_imm8 ((imm))) { \
1058 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1059 *(inst)++ = (unsigned char)0x6b; \
1060 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1061 x86_imm_emit8 ((inst), (imm)); \
1063 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1064 *(inst)++ = (unsigned char)0x69; \
1065 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1066 x86_imm_emit32 ((inst), (imm)); \
1071 * divide EDX:EAX by rm;
1072 * eax = quotient, edx = remainder
1075 #define x86_div_reg(inst,reg,is_signed) \
1077 x86_codegen_pre(&(inst), 2); \
1078 *(inst)++ = (unsigned char)0xf7; \
1079 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
1082 #define x86_div_mem(inst,mem,is_signed) \
1084 x86_codegen_pre(&(inst), 6); \
1085 *(inst)++ = (unsigned char)0xf7; \
1086 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
1089 #define x86_div_membase(inst,basereg,disp,is_signed) \
1091 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1092 *(inst)++ = (unsigned char)0xf7; \
1093 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
1096 #define x86_mov_mem_reg(inst,mem,reg,size) \
1098 x86_codegen_pre(&(inst), 7); \
1100 case 1: *(inst)++ = (unsigned char)0x88; break; \
1101 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1102 case 4: *(inst)++ = (unsigned char)0x89; break; \
1103 default: assert (0); \
1105 x86_mem_emit ((inst), (reg), (mem)); \
1108 #define x86_mov_regp_reg(inst,regp,reg,size) \
1110 x86_codegen_pre(&(inst), 3); \
1112 case 1: *(inst)++ = (unsigned char)0x88; break; \
1113 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1114 case 4: *(inst)++ = (unsigned char)0x89; break; \
1115 default: assert (0); \
1117 x86_regp_emit ((inst), (reg), (regp)); \
1120 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
1122 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1124 case 1: *(inst)++ = (unsigned char)0x88; break; \
1125 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1126 case 4: *(inst)++ = (unsigned char)0x89; break; \
1127 default: assert (0); \
1129 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1132 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
1134 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1136 case 1: *(inst)++ = (unsigned char)0x88; break; \
1137 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1138 case 4: *(inst)++ = (unsigned char)0x89; break; \
1139 default: assert (0); \
1141 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1144 #define x86_mov_reg_reg(inst,dreg,reg,size) \
1146 x86_codegen_pre(&(inst), 3); \
1148 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1149 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1150 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1151 default: assert (0); \
1153 x86_reg_emit ((inst), (dreg), (reg)); \
1156 #define x86_mov_reg_mem(inst,reg,mem,size) \
1158 x86_codegen_pre(&(inst), 7); \
1160 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1161 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1162 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1163 default: assert (0); \
1165 x86_mem_emit ((inst), (reg), (mem)); \
1168 #define kMovRegMembasePadding (2 + kMaxMembaseEmitPadding)
1170 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
1172 x86_codegen_pre(&(inst), kMovRegMembasePadding); \
1174 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1175 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1176 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1177 default: assert (0); \
1179 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1182 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
1184 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1186 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1187 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1188 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1189 default: assert (0); \
1191 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1195 * Note: x86_clear_reg () chacnges the condition code!
1197 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
1199 #define x86_mov_reg_imm(inst,reg,imm) \
1201 x86_codegen_pre(&(inst), 5); \
1202 *(inst)++ = (unsigned char)0xb8 + (reg); \
1203 x86_imm_emit32 ((inst), (imm)); \
1206 #define x86_mov_mem_imm(inst,mem,imm,size) \
1208 if ((size) == 1) { \
1209 x86_codegen_pre(&(inst), 7); \
1210 *(inst)++ = (unsigned char)0xc6; \
1211 x86_mem_emit ((inst), 0, (mem)); \
1212 x86_imm_emit8 ((inst), (imm)); \
1213 } else if ((size) == 2) { \
1214 x86_codegen_pre(&(inst), 9); \
1215 x86_prefix((inst), X86_OPERAND_PREFIX); \
1216 *(inst)++ = (unsigned char)0xc7; \
1217 x86_mem_emit ((inst), 0, (mem)); \
1218 x86_imm_emit16 ((inst), (imm)); \
1220 x86_codegen_pre(&(inst), 10); \
1221 *(inst)++ = (unsigned char)0xc7; \
1222 x86_mem_emit ((inst), 0, (mem)); \
1223 x86_imm_emit32 ((inst), (imm)); \
1227 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
1229 if ((size) == 1) { \
1230 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1231 *(inst)++ = (unsigned char)0xc6; \
1232 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1233 x86_imm_emit8 ((inst), (imm)); \
1234 } else if ((size) == 2) { \
1235 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
1236 x86_prefix((inst), X86_OPERAND_PREFIX); \
1237 *(inst)++ = (unsigned char)0xc7; \
1238 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1239 x86_imm_emit16 ((inst), (imm)); \
1241 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1242 *(inst)++ = (unsigned char)0xc7; \
1243 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1244 x86_imm_emit32 ((inst), (imm)); \
1248 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
1250 if ((size) == 1) { \
1251 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1252 *(inst)++ = (unsigned char)0xc6; \
1253 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1254 x86_imm_emit8 ((inst), (imm)); \
1255 } else if ((size) == 2) { \
1256 x86_codegen_pre(&(inst), 4 + kMaxMemindexEmitPadding); \
1257 x86_prefix((inst), X86_OPERAND_PREFIX); \
1258 *(inst)++ = (unsigned char)0xc7; \
1259 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1260 x86_imm_emit16 ((inst), (imm)); \
1262 x86_codegen_pre(&(inst), 5 + kMaxMemindexEmitPadding); \
1263 *(inst)++ = (unsigned char)0xc7; \
1264 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1265 x86_imm_emit32 ((inst), (imm)); \
1269 #define x86_lea_mem(inst,reg,mem) \
1271 x86_codegen_pre(&(inst), 5); \
1272 *(inst)++ = (unsigned char)0x8d; \
1273 x86_mem_emit ((inst), (reg), (mem)); \
1276 #define x86_lea_membase(inst,reg,basereg,disp) \
1278 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1279 *(inst)++ = (unsigned char)0x8d; \
1280 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1283 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
1285 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1286 *(inst)++ = (unsigned char)0x8d; \
1287 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1290 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1292 unsigned char op = 0xb6; \
1293 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1294 x86_codegen_pre(&(inst), 3); \
1295 *(inst)++ = (unsigned char)0x0f; \
1296 if ((is_signed)) op += 0x08; \
1297 if ((is_half)) op += 0x01; \
1299 x86_reg_emit ((inst), (dreg), (reg)); \
1302 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1304 unsigned char op = 0xb6; \
1305 x86_codegen_pre(&(inst), 7); \
1306 *(inst)++ = (unsigned char)0x0f; \
1307 if ((is_signed)) op += 0x08; \
1308 if ((is_half)) op += 0x01; \
1310 x86_mem_emit ((inst), (dreg), (mem)); \
1313 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1315 unsigned char op = 0xb6; \
1316 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1317 *(inst)++ = (unsigned char)0x0f; \
1318 if ((is_signed)) op += 0x08; \
1319 if ((is_half)) op += 0x01; \
1321 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1324 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1326 unsigned char op = 0xb6; \
1327 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1328 *(inst)++ = (unsigned char)0x0f; \
1329 if ((is_signed)) op += 0x08; \
1330 if ((is_half)) op += 0x01; \
1332 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1335 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1336 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1338 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1340 x86_codegen_pre(&(inst), 6); \
1341 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1342 x86_mem_emit ((inst), (opc), (mem)); \
1345 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1347 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1348 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1349 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1352 #define x86_fp_op(inst,opc,index) \
1354 x86_codegen_pre(&(inst), 2); \
1355 *(inst)++ = (unsigned char)0xd8; \
1356 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1359 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1361 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1362 x86_codegen_pre(&(inst), 2); \
1363 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1364 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1368 * @x86_fp_int_op_membase
1369 * Supports FPU operations between ST(0) and integer operand in memory.
1370 * Operation encoded using X86_FP_Opcode enum.
1371 * Operand is addressed by [basereg + disp].
1372 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1374 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1376 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1377 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1378 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1381 #define x86_fstp(inst,index) \
1383 x86_codegen_pre(&(inst), 2); \
1384 *(inst)++ = (unsigned char)0xdd; \
1385 *(inst)++ = (unsigned char)0xd8+(index); \
1388 #define x86_fcompp(inst) \
1390 x86_codegen_pre(&(inst), 2); \
1391 *(inst)++ = (unsigned char)0xde; \
1392 *(inst)++ = (unsigned char)0xd9; \
1395 #define x86_fucompp(inst) \
1397 x86_codegen_pre(&(inst), 2); \
1398 *(inst)++ = (unsigned char)0xda; \
1399 *(inst)++ = (unsigned char)0xe9; \
1402 #define x86_fnstsw(inst) \
1404 x86_codegen_pre(&(inst), 2); \
1405 *(inst)++ = (unsigned char)0xdf; \
1406 *(inst)++ = (unsigned char)0xe0; \
1409 #define x86_fnstcw(inst,mem) \
1411 x86_codegen_pre(&(inst), 6); \
1412 *(inst)++ = (unsigned char)0xd9; \
1413 x86_mem_emit ((inst), 7, (mem)); \
1416 #define x86_fnstcw_membase(inst,basereg,disp) \
1418 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1419 *(inst)++ = (unsigned char)0xd9; \
1420 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1423 #define x86_fldcw(inst,mem) \
1425 x86_codegen_pre(&(inst), 6); \
1426 *(inst)++ = (unsigned char)0xd9; \
1427 x86_mem_emit ((inst), 5, (mem)); \
1430 #define x86_fldcw_membase(inst,basereg,disp) \
1432 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1433 *(inst)++ = (unsigned char)0xd9; \
1434 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1437 #define x86_fchs(inst) \
1439 x86_codegen_pre(&(inst), 2); \
1440 *(inst)++ = (unsigned char)0xd9; \
1441 *(inst)++ = (unsigned char)0xe0; \
1444 #define x86_frem(inst) \
1446 x86_codegen_pre(&(inst), 2); \
1447 *(inst)++ = (unsigned char)0xd9; \
1448 *(inst)++ = (unsigned char)0xf8; \
1451 #define x86_fxch(inst,index) \
1453 x86_codegen_pre(&(inst), 2); \
1454 *(inst)++ = (unsigned char)0xd9; \
1455 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1458 #define x86_fcomi(inst,index) \
1460 x86_codegen_pre(&(inst), 2); \
1461 *(inst)++ = (unsigned char)0xdb; \
1462 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1465 #define x86_fcomip(inst,index) \
1467 x86_codegen_pre(&(inst), 2); \
1468 *(inst)++ = (unsigned char)0xdf; \
1469 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1472 #define x86_fucomi(inst,index) \
1474 x86_codegen_pre(&(inst), 2); \
1475 *(inst)++ = (unsigned char)0xdb; \
1476 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1479 #define x86_fucomip(inst,index) \
1481 x86_codegen_pre(&(inst), 2); \
1482 *(inst)++ = (unsigned char)0xdf; \
1483 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1486 #define x86_fld(inst,mem,is_double) \
1488 x86_codegen_pre(&(inst), 6); \
1489 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1490 x86_mem_emit ((inst), 0, (mem)); \
1493 #define x86_fld_membase(inst,basereg,disp,is_double) \
1495 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1496 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1497 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1500 #define x86_fld80_mem(inst,mem) \
1502 x86_codegen_pre(&(inst), 6); \
1503 *(inst)++ = (unsigned char)0xdb; \
1504 x86_mem_emit ((inst), 5, (mem)); \
1507 #define x86_fld80_membase(inst,basereg,disp) \
1509 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1510 *(inst)++ = (unsigned char)0xdb; \
1511 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1514 #define x86_fild(inst,mem,is_long) \
1516 x86_codegen_pre(&(inst), 6); \
1518 *(inst)++ = (unsigned char)0xdf; \
1519 x86_mem_emit ((inst), 5, (mem)); \
1521 *(inst)++ = (unsigned char)0xdb; \
1522 x86_mem_emit ((inst), 0, (mem)); \
1526 #define x86_fild_membase(inst,basereg,disp,is_long) \
1528 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1530 *(inst)++ = (unsigned char)0xdf; \
1531 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1533 *(inst)++ = (unsigned char)0xdb; \
1534 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1538 #define x86_fld_reg(inst,index) \
1540 x86_codegen_pre(&(inst), 2); \
1541 *(inst)++ = (unsigned char)0xd9; \
1542 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1545 #define x86_fldz(inst) \
1547 x86_codegen_pre(&(inst), 2); \
1548 *(inst)++ = (unsigned char)0xd9; \
1549 *(inst)++ = (unsigned char)0xee; \
1552 #define x86_fld1(inst) \
1554 x86_codegen_pre(&(inst), 2); \
1555 *(inst)++ = (unsigned char)0xd9; \
1556 *(inst)++ = (unsigned char)0xe8; \
1559 #define x86_fldpi(inst) \
1561 x86_codegen_pre(&(inst), 2); \
1562 *(inst)++ = (unsigned char)0xd9; \
1563 *(inst)++ = (unsigned char)0xeb; \
1566 #define x86_fst(inst,mem,is_double,pop_stack) \
1568 x86_codegen_pre(&(inst), 6); \
1569 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1570 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1573 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1575 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1576 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1577 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1580 #define x86_fst80_mem(inst,mem) \
1582 x86_codegen_pre(&(inst), 6); \
1583 *(inst)++ = (unsigned char)0xdb; \
1584 x86_mem_emit ((inst), 7, (mem)); \
1588 #define x86_fst80_membase(inst,basereg,disp) \
1590 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1591 *(inst)++ = (unsigned char)0xdb; \
1592 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1596 #define x86_fist_pop(inst,mem,is_long) \
1598 x86_codegen_pre(&(inst), 6); \
1600 *(inst)++ = (unsigned char)0xdf; \
1601 x86_mem_emit ((inst), 7, (mem)); \
1603 *(inst)++ = (unsigned char)0xdb; \
1604 x86_mem_emit ((inst), 3, (mem)); \
1608 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1610 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1612 *(inst)++ = (unsigned char)0xdf; \
1613 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1615 *(inst)++ = (unsigned char)0xdb; \
1616 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1620 #define x86_fstsw(inst) \
1622 x86_codegen_pre(&(inst), 3); \
1623 *(inst)++ = (unsigned char)0x9b; \
1624 *(inst)++ = (unsigned char)0xdf; \
1625 *(inst)++ = (unsigned char)0xe0; \
1630 * Converts content of ST(0) to integer and stores it at memory location
1631 * addressed by [basereg + disp].
1632 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1634 #define x86_fist_membase(inst,basereg,disp,is_int) \
1636 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1638 *(inst)++ = (unsigned char)0xdb; \
1639 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1641 *(inst)++ = (unsigned char)0xdf; \
1642 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1647 #define x86_push_reg(inst,reg) \
1649 *(inst)++ = (unsigned char)0x50 + (reg); \
1652 #define x86_push_regp(inst,reg) \
1654 x86_codegen_pre(&(inst), 2); \
1655 *(inst)++ = (unsigned char)0xff; \
1656 x86_regp_emit ((inst), 6, (reg)); \
1659 #define x86_push_mem(inst,mem) \
1661 x86_codegen_pre(&(inst), 6); \
1662 *(inst)++ = (unsigned char)0xff; \
1663 x86_mem_emit ((inst), 6, (mem)); \
1666 #define x86_push_membase(inst,basereg,disp) \
1668 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1669 *(inst)++ = (unsigned char)0xff; \
1670 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1673 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1675 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1676 *(inst)++ = (unsigned char)0xff; \
1677 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1680 #define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)
1682 #define x86_push_imm(inst,imm) \
1684 int _imm = (int) (imm); \
1685 if (x86_is_imm8 (_imm)) { \
1686 x86_codegen_pre(&(inst), 2); \
1687 *(inst)++ = (unsigned char)0x6A; \
1688 x86_imm_emit8 ((inst), (_imm)); \
1690 x86_codegen_pre(&(inst), 5); \
1691 *(inst)++ = (unsigned char)0x68; \
1692 x86_imm_emit32 ((inst), (_imm)); \
1696 #define x86_pop_reg(inst,reg) \
1698 *(inst)++ = (unsigned char)0x58 + (reg); \
1701 #define x86_pop_mem(inst,mem) \
1703 x86_codegen_pre(&(inst), 6); \
1704 *(inst)++ = (unsigned char)0x87; \
1705 x86_mem_emit ((inst), 0, (mem)); \
1708 #define x86_pop_membase(inst,basereg,disp) \
1710 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1711 *(inst)++ = (unsigned char)0x87; \
1712 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1715 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1716 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1717 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1718 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1720 #define x86_loop(inst,imm) \
1722 x86_codegen_pre(&(inst), 2); \
1723 *(inst)++ = (unsigned char)0xe2; \
1724 x86_imm_emit8 ((inst), (imm)); \
1727 #define x86_loope(inst,imm) \
1729 x86_codegen_pre(&(inst), 2); \
1730 *(inst)++ = (unsigned char)0xe1; \
1731 x86_imm_emit8 ((inst), (imm)); \
1734 #define x86_loopne(inst,imm) \
1736 x86_codegen_pre(&(inst), 2); \
1737 *(inst)++ = (unsigned char)0xe0; \
1738 x86_imm_emit8 ((inst), (imm)); \
1741 #if defined(TARGET_X86)
1742 #define x86_jump32(inst,imm) \
1744 x86_codegen_pre(&(inst), 5); \
1745 *(inst)++ = (unsigned char)0xe9; \
1746 x86_imm_emit32 ((inst), (imm)); \
1749 #define x86_jump8(inst,imm) \
1751 x86_codegen_pre(&(inst), 2); \
1752 *(inst)++ = (unsigned char)0xeb; \
1753 x86_imm_emit8 ((inst), (imm)); \
1755 #elif defined(TARGET_AMD64)
1756 /* These macros are used directly from mini-amd64.c and other */
1757 /* amd64 specific files, so they need to be instrumented directly. */
1758 #define x86_jump32(inst,imm) \
1760 amd64_codegen_pre(inst); \
1761 *(inst)++ = (unsigned char)0xe9; \
1762 x86_imm_emit32 ((inst), (imm)); \
1763 amd64_codegen_post(inst); \
1766 #define x86_jump8(inst,imm) \
1768 amd64_codegen_pre(inst); \
1769 *(inst)++ = (unsigned char)0xeb; \
1770 x86_imm_emit8 ((inst), (imm)); \
1771 amd64_codegen_post(inst); \
1775 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
1776 #define x86_jump_reg(inst,reg) do { \
1777 x86_codegen_pre(&(inst), 5); \
1778 *(inst)++ = (unsigned char)0x83; /* and */ \
1779 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
1780 *(inst)++ = (unsigned char)nacl_align_byte; \
1781 *(inst)++ = (unsigned char)0xff; \
1782 x86_reg_emit ((inst), 4, (reg)); \
1785 /* Let's hope ECX is available for these... */
1786 #define x86_jump_mem(inst,mem) do { \
1787 x86_mov_reg_mem(inst, (X86_ECX), (mem), 4); \
1788 x86_jump_reg(inst, (X86_ECX)); \
1791 #define x86_jump_membase(inst,basereg,disp) do { \
1792 x86_mov_reg_membase(inst, (X86_ECX), basereg, disp, 4); \
1793 x86_jump_reg(inst, (X86_ECX)); \
1796 /* like x86_jump_membase, but force a 32-bit displacement */
1797 #define x86_jump_membase32(inst,basereg,disp) do { \
1798 x86_codegen_pre(&(inst), 6); \
1799 *(inst)++ = (unsigned char)0x8b; \
1800 x86_address_byte ((inst), 2, X86_ECX, (basereg)); \
1801 x86_imm_emit32 ((inst), (disp)); \
1802 x86_jump_reg(inst, (X86_ECX)); \
1804 #else /* __native_client_codegen__ */
1805 #define x86_jump_reg(inst,reg) \
1807 *(inst)++ = (unsigned char)0xff; \
1808 x86_reg_emit ((inst), 4, (reg)); \
1811 #define x86_jump_mem(inst,mem) \
1813 *(inst)++ = (unsigned char)0xff; \
1814 x86_mem_emit ((inst), 4, (mem)); \
1817 #define x86_jump_membase(inst,basereg,disp) \
1819 *(inst)++ = (unsigned char)0xff; \
1820 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1822 #endif /* __native_client_codegen__ */
1824 * target is a pointer in our buffer.
1826 #define x86_jump_code_body(inst,target) \
1829 x86_codegen_pre(&(inst), 2); \
1830 t = (unsigned char*)(target) - (inst) - 2; \
1831 if (x86_is_imm8(t)) { \
1832 x86_jump8 ((inst), t); \
1834 x86_codegen_pre(&(inst), 5); \
1835 t = (unsigned char*)(target) - (inst) - 5; \
1836 x86_jump32 ((inst), t); \
1840 #if defined(__default_codegen__)
1841 #define x86_jump_code(inst,target) \
1843 x86_jump_code_body((inst),(target)); \
1845 #elif defined(__native_client_codegen__) && defined(TARGET_X86)
1846 #define x86_jump_code(inst,target) \
1848 guint8* jump_start = (inst); \
1849 x86_jump_code_body((inst),(target)); \
1850 x86_patch(jump_start, (target)); \
1852 #elif defined(__native_client_codegen__) && defined(TARGET_AMD64)
1853 #define x86_jump_code(inst,target) \
1855 /* jump_code_body is used twice because there are offsets */ \
1856 /* calculated based on the IP, which can change after the */ \
1857 /* call to amd64_codegen_post */ \
1858 amd64_codegen_pre(inst); \
1859 x86_jump_code_body((inst),(target)); \
1860 inst = amd64_codegen_post(inst); \
1861 x86_jump_code_body((inst),(target)); \
1863 #endif /* __native_client_codegen__ */
1865 #define x86_jump_disp(inst,disp) \
1867 int t = (disp) - 2; \
1868 if (x86_is_imm8(t)) { \
1869 x86_jump8 ((inst), t); \
1872 x86_jump32 ((inst), t); \
1876 #if defined(TARGET_X86)
1877 #define x86_branch8(inst,cond,imm,is_signed) \
1879 x86_codegen_pre(&(inst), 2); \
1881 *(inst)++ = x86_cc_signed_map [(cond)]; \
1883 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1884 x86_imm_emit8 ((inst), (imm)); \
1887 #define x86_branch32(inst,cond,imm,is_signed) \
1889 x86_codegen_pre(&(inst), 6); \
1890 *(inst)++ = (unsigned char)0x0f; \
1892 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1894 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1895 x86_imm_emit32 ((inst), (imm)); \
1897 #elif defined(TARGET_AMD64)
1898 /* These macros are used directly from mini-amd64.c and other */
1899 /* amd64 specific files, so they need to be instrumented directly. */
1900 #define x86_branch8(inst,cond,imm,is_signed) \
1902 amd64_codegen_pre(inst); \
1904 *(inst)++ = x86_cc_signed_map [(cond)]; \
1906 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1907 x86_imm_emit8 ((inst), (imm)); \
1908 amd64_codegen_post(inst); \
1910 #define x86_branch32(inst,cond,imm,is_signed) \
1912 amd64_codegen_pre(inst); \
1913 *(inst)++ = (unsigned char)0x0f; \
1915 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1917 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1918 x86_imm_emit32 ((inst), (imm)); \
1919 amd64_codegen_post(inst); \
1923 #if defined(TARGET_X86)
1924 #define x86_branch(inst,cond,target,is_signed) \
1927 guint8* branch_start; \
1928 x86_codegen_pre(&(inst), 2); \
1929 offset = (target) - (inst) - 2; \
1930 branch_start = (inst); \
1931 if (x86_is_imm8 ((offset))) \
1932 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1934 x86_codegen_pre(&(inst), 6); \
1935 offset = (target) - (inst) - 6; \
1936 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1938 x86_patch(branch_start, (target)); \
1940 #elif defined(TARGET_AMD64)
1941 /* This macro is used directly from mini-amd64.c and other */
1942 /* amd64 specific files, so it needs to be instrumented directly. */
1944 #define x86_branch_body(inst,cond,target,is_signed) \
1946 int offset = (target) - (inst) - 2; \
1947 if (x86_is_imm8 ((offset))) \
1948 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1950 offset = (target) - (inst) - 6; \
1951 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1955 #if defined(__default_codegen__)
1956 #define x86_branch(inst,cond,target,is_signed) \
1958 x86_branch_body((inst),(cond),(target),(is_signed)); \
1960 #elif defined(__native_client_codegen__)
1961 #define x86_branch(inst,cond,target,is_signed) \
1963 /* branch_body is used twice because there are offsets */ \
1964 /* calculated based on the IP, which can change after */ \
1965 /* the call to amd64_codegen_post */ \
1966 amd64_codegen_pre(inst); \
1967 x86_branch_body((inst),(cond),(target),(is_signed)); \
1968 inst = amd64_codegen_post(inst); \
1969 x86_branch_body((inst),(cond),(target),(is_signed)); \
1971 #endif /* __native_client_codegen__ */
1973 #endif /* TARGET_AMD64 */
1975 #define x86_branch_disp(inst,cond,disp,is_signed) \
1977 int offset = (disp) - 2; \
1978 if (x86_is_imm8 ((offset))) \
1979 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1982 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1986 #define x86_set_reg(inst,cond,reg,is_signed) \
1988 g_assert (X86_IS_BYTE_REG (reg)); \
1989 x86_codegen_pre(&(inst), 3); \
1990 *(inst)++ = (unsigned char)0x0f; \
1992 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1994 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1995 x86_reg_emit ((inst), 0, (reg)); \
1998 #define x86_set_mem(inst,cond,mem,is_signed) \
2000 x86_codegen_pre(&(inst), 7); \
2001 *(inst)++ = (unsigned char)0x0f; \
2003 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
2005 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
2006 x86_mem_emit ((inst), 0, (mem)); \
2009 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
2011 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2012 *(inst)++ = (unsigned char)0x0f; \
2014 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
2016 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
2017 x86_membase_emit ((inst), 0, (basereg), (disp)); \
2020 #define x86_call_imm_body(inst,disp) \
2022 *(inst)++ = (unsigned char)0xe8; \
2023 x86_imm_emit32 ((inst), (int)(disp)); \
2026 #define x86_call_imm(inst,disp) \
2028 x86_call_sequence_pre((inst)); \
2029 x86_call_imm_body((inst), (disp)); \
2030 x86_call_sequence_post((inst)); \
2034 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2035 #define x86_call_reg_internal(inst,reg) \
2037 *(inst)++ = (unsigned char)0x83; /* and */ \
2038 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
2039 *(inst)++ = (unsigned char)nacl_align_byte; \
2040 *(inst)++ = (unsigned char)0xff; /* call */ \
2041 x86_reg_emit ((inst), 2, (reg)); /* reg */ \
2044 #define x86_call_reg(inst, reg) do { \
2045 x86_call_sequence_pre((inst)); \
2046 x86_call_reg_internal(inst, reg); \
2047 x86_call_sequence_post((inst)); \
2051 /* It appears that x86_call_mem() is never used, so I'm leaving it out. */
2052 #define x86_call_membase(inst,basereg,disp) do { \
2053 x86_call_sequence_pre((inst)); \
2054 /* x86_mov_reg_membase() inlined so its fixed size */ \
2055 *(inst)++ = (unsigned char)0x8b; \
2056 x86_address_byte ((inst), 2, (X86_ECX), (basereg)); \
2057 x86_imm_emit32 ((inst), (disp)); \
2058 x86_call_reg_internal(inst, X86_ECX); \
2059 x86_call_sequence_post((inst)); \
2061 #else /* __native_client_codegen__ */
2062 #define x86_call_reg(inst,reg) \
2064 *(inst)++ = (unsigned char)0xff; \
2065 x86_reg_emit ((inst), 2, (reg)); \
2068 #define x86_call_mem(inst,mem) \
2070 *(inst)++ = (unsigned char)0xff; \
2071 x86_mem_emit ((inst), 2, (mem)); \
2074 #define x86_call_membase(inst,basereg,disp) \
2076 *(inst)++ = (unsigned char)0xff; \
2077 x86_membase_emit ((inst), 2, (basereg), (disp)); \
2079 #endif /* __native_client_codegen__ */
2082 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2084 #define x86_call_code(inst,target) \
2087 guint8* call_start; \
2088 guint8* _aligned_start; \
2089 x86_call_sequence_pre_val((inst)); \
2090 _x86_offset = (unsigned char*)(target) - (inst); \
2092 x86_call_imm_body ((inst), _x86_offset); \
2093 _aligned_start = x86_call_sequence_post_val((inst)); \
2094 call_start = _aligned_start; \
2095 _x86_offset = (unsigned char*)(target) - (_aligned_start); \
2097 x86_call_imm_body ((_aligned_start), _x86_offset); \
2098 x86_patch(call_start, (target)); \
2101 #define SIZE_OF_RET 6
2102 #define x86_ret(inst) do { \
2103 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2104 x86_codegen_pre(&(inst), 5); \
2105 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2106 *(inst)++ = (unsigned char)0xe1; \
2107 *(inst)++ = (unsigned char)nacl_align_byte; \
2108 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2109 *(inst)++ = (unsigned char)0xe1; \
2112 /* pop return address */
2113 /* pop imm bytes from stack */
2115 #define x86_ret_imm(inst,imm) do { \
2116 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2117 x86_alu_reg_imm ((inst), X86_ADD, X86_ESP, imm); \
2118 x86_codegen_pre(&(inst), 5); \
2119 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2120 *(inst)++ = (unsigned char)0xe1; \
2121 *(inst)++ = (unsigned char)nacl_align_byte; \
2122 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2123 *(inst)++ = (unsigned char)0xe1; \
2125 #else /* __native_client_codegen__ */
2127 #define x86_call_code(inst,target) \
2130 _x86_offset = (unsigned char*)(target) - (inst); \
2132 x86_call_imm_body ((inst), _x86_offset); \
2135 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
2137 #define x86_ret_imm(inst,imm) \
2142 x86_codegen_pre(&(inst), 3); \
2143 *(inst)++ = (unsigned char)0xc2; \
2144 x86_imm_emit16 ((inst), (imm)); \
2147 #endif /* __native_client_codegen__ */
2149 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
2151 x86_codegen_pre(&(inst), 3); \
2152 *(inst)++ = (unsigned char) 0x0f; \
2154 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2156 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2157 x86_reg_emit ((inst), (dreg), (reg)); \
2160 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
2162 x86_codegen_pre(&(inst), 7); \
2163 *(inst)++ = (unsigned char) 0x0f; \
2165 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2167 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2168 x86_mem_emit ((inst), (reg), (mem)); \
2171 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
2173 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2174 *(inst)++ = (unsigned char) 0x0f; \
2176 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2178 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2179 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2182 #define x86_enter(inst,framesize) \
2184 x86_codegen_pre(&(inst), 4); \
2185 *(inst)++ = (unsigned char)0xc8; \
2186 x86_imm_emit16 ((inst), (framesize)); \
2190 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
2191 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
2193 #define x86_fsin(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
2194 #define x86_fcos(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
2195 #define x86_fabs(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
2196 #define x86_ftst(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
2197 #define x86_fxam(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
2198 #define x86_fpatan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
2199 #define x86_fprem(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
2200 #define x86_fprem1(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
2201 #define x86_frndint(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
2202 #define x86_fsqrt(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
2203 #define x86_fptan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
2205 #define x86_padding(inst,size) \
2208 case 1: x86_nop ((inst)); break; \
2209 case 2: *(inst)++ = 0x8b; \
2210 *(inst)++ = 0xc0; break; \
2211 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
2212 *(inst)++ = 0x00; break; \
2213 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2214 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2216 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2217 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2218 x86_nop ((inst)); break; \
2219 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
2220 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2221 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2223 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
2224 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2225 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2226 *(inst)++ = 0x00; break; \
2227 default: assert (0); \
2231 #ifdef __native_client_codegen__
2233 #define kx86NaClLengthOfCallReg 5
2234 #define kx86NaClLengthOfCallImm 5
2235 #define kx86NaClLengthOfCallMembase (kx86NaClLengthOfCallReg + 6)
2237 #endif /* __native_client_codegen__ */
2239 #define x86_prolog(inst,frame_size,reg_mask) \
2241 unsigned i, m = 1; \
2242 x86_enter ((inst), (frame_size)); \
2243 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
2244 if ((reg_mask) & m) \
2245 x86_push_reg ((inst), i); \
2249 #define x86_epilog(inst,reg_mask) \
2251 unsigned i, m = 1 << X86_EDI; \
2252 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
2253 if ((reg_mask) & m) \
2254 x86_pop_reg ((inst), i); \
2256 x86_leave ((inst)); \
2262 X86_SSE_SQRT = 0x51,
2263 X86_SSE_RSQRT = 0x52,
2271 X86_SSE_COMP = 0xC2,
2273 X86_SSE_ANDN = 0x55,
2276 X86_SSE_UNPCKL = 0x14,
2277 X86_SSE_UNPCKH = 0x15,
2279 X86_SSE_ADDSUB = 0xD0,
2280 X86_SSE_HADD = 0x7C,
2281 X86_SSE_HSUB = 0x7D,
2282 X86_SSE_MOVSHDUP = 0x16,
2283 X86_SSE_MOVSLDUP = 0x12,
2284 X86_SSE_MOVDDUP = 0x12,
2286 X86_SSE_PAND = 0xDB,
2288 X86_SSE_PXOR = 0xEF,
2290 X86_SSE_PADDB = 0xFC,
2291 X86_SSE_PADDW = 0xFD,
2292 X86_SSE_PADDD = 0xFE,
2293 X86_SSE_PADDQ = 0xD4,
2295 X86_SSE_PSUBB = 0xF8,
2296 X86_SSE_PSUBW = 0xF9,
2297 X86_SSE_PSUBD = 0xFA,
2298 X86_SSE_PSUBQ = 0xFB,
2300 X86_SSE_PMAXSB = 0x3C, /*sse41*/
2301 X86_SSE_PMAXSW = 0xEE,
2302 X86_SSE_PMAXSD = 0x3D, /*sse41*/
2304 X86_SSE_PMAXUB = 0xDE,
2305 X86_SSE_PMAXUW = 0x3E, /*sse41*/
2306 X86_SSE_PMAXUD = 0x3F, /*sse41*/
2308 X86_SSE_PMINSB = 0x38, /*sse41*/
2309 X86_SSE_PMINSW = 0xEA,
2310 X86_SSE_PMINSD = 0x39,/*sse41*/
2312 X86_SSE_PMINUB = 0xDA,
2313 X86_SSE_PMINUW = 0x3A, /*sse41*/
2314 X86_SSE_PMINUD = 0x3B, /*sse41*/
2316 X86_SSE_PAVGB = 0xE0,
2317 X86_SSE_PAVGW = 0xE3,
2319 X86_SSE_PCMPEQB = 0x74,
2320 X86_SSE_PCMPEQW = 0x75,
2321 X86_SSE_PCMPEQD = 0x76,
2322 X86_SSE_PCMPEQQ = 0x29, /*sse41*/
2324 X86_SSE_PCMPGTB = 0x64,
2325 X86_SSE_PCMPGTW = 0x65,
2326 X86_SSE_PCMPGTD = 0x66,
2327 X86_SSE_PCMPGTQ = 0x37, /*sse42*/
2329 X86_SSE_PSADBW = 0xf6,
2331 X86_SSE_PSHUFD = 0x70,
2333 X86_SSE_PUNPCKLBW = 0x60,
2334 X86_SSE_PUNPCKLWD = 0x61,
2335 X86_SSE_PUNPCKLDQ = 0x62,
2336 X86_SSE_PUNPCKLQDQ = 0x6C,
2338 X86_SSE_PUNPCKHBW = 0x68,
2339 X86_SSE_PUNPCKHWD = 0x69,
2340 X86_SSE_PUNPCKHDQ = 0x6A,
2341 X86_SSE_PUNPCKHQDQ = 0x6D,
2343 X86_SSE_PACKSSWB = 0x63,
2344 X86_SSE_PACKSSDW = 0x6B,
2346 X86_SSE_PACKUSWB = 0x67,
2347 X86_SSE_PACKUSDW = 0x2B,/*sse41*/
2349 X86_SSE_PADDUSB = 0xDC,
2350 X86_SSE_PADDUSW = 0xDD,
2351 X86_SSE_PSUBUSB = 0xD8,
2352 X86_SSE_PSUBUSW = 0xD9,
2354 X86_SSE_PADDSB = 0xEC,
2355 X86_SSE_PADDSW = 0xED,
2356 X86_SSE_PSUBSB = 0xE8,
2357 X86_SSE_PSUBSW = 0xE9,
2359 X86_SSE_PMULLW = 0xD5,
2360 X86_SSE_PMULLD = 0x40,/*sse41*/
2361 X86_SSE_PMULHUW = 0xE4,
2362 X86_SSE_PMULHW = 0xE5,
2363 X86_SSE_PMULUDQ = 0xF4,
2365 X86_SSE_PMOVMSKB = 0xD7,
2367 X86_SSE_PSHIFTW = 0x71,
2368 X86_SSE_PSHIFTD = 0x72,
2369 X86_SSE_PSHIFTQ = 0x73,
2374 X86_SSE_PSRLW_REG = 0xD1,
2375 X86_SSE_PSRAW_REG = 0xE1,
2376 X86_SSE_PSLLW_REG = 0xF1,
2378 X86_SSE_PSRLD_REG = 0xD2,
2379 X86_SSE_PSRAD_REG = 0xE2,
2380 X86_SSE_PSLLD_REG = 0xF2,
2382 X86_SSE_PSRLQ_REG = 0xD3,
2383 X86_SSE_PSLLQ_REG = 0xF3,
2385 X86_SSE_PREFETCH = 0x18,
2386 X86_SSE_MOVNTPS = 0x2B,
2387 X86_SSE_MOVHPD_REG_MEMBASE = 0x16,
2388 X86_SSE_MOVHPD_MEMBASE_REG = 0x17,
2390 X86_SSE_MOVSD_REG_MEMBASE = 0x10,
2391 X86_SSE_MOVSD_MEMBASE_REG = 0x11,
2393 X86_SSE_PINSRB = 0x20,/*sse41*/
2394 X86_SSE_PINSRW = 0xC4,
2395 X86_SSE_PINSRD = 0x22,/*sse41*/
2397 X86_SSE_PEXTRB = 0x14,/*sse41*/
2398 X86_SSE_PEXTRW = 0xC5,
2399 X86_SSE_PEXTRD = 0x16,/*sse41*/
2401 X86_SSE_SHUFP = 0xC6,
2403 X86_SSE_CVTDQ2PD = 0xE6,
2404 X86_SSE_CVTDQ2PS = 0x5B,
2405 X86_SSE_CVTPD2DQ = 0xE6,
2406 X86_SSE_CVTPD2PS = 0x5A,
2407 X86_SSE_CVTPS2DQ = 0x5B,
2408 X86_SSE_CVTPS2PD = 0x5A,
2409 X86_SSE_CVTTPD2DQ = 0xE6,
2410 X86_SSE_CVTTPS2DQ = 0x5B,
2414 /* minimal SSE* support */
2415 #define x86_movsd_reg_membase(inst,dreg,basereg,disp) \
2417 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2418 *(inst)++ = (unsigned char)0xf2; \
2419 *(inst)++ = (unsigned char)0x0f; \
2420 *(inst)++ = (unsigned char)0x10; \
2421 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
2424 #define x86_cvttsd2si(inst,dreg,reg) \
2426 x86_codegen_pre(&(inst), 4); \
2427 *(inst)++ = (unsigned char)0xf2; \
2428 *(inst)++ = (unsigned char)0x0f; \
2429 *(inst)++ = (unsigned char)0x2c; \
2430 x86_reg_emit ((inst), (dreg), (reg)); \
2433 #define x86_sse_alu_reg_reg(inst,opc,dreg,reg) \
2435 x86_codegen_pre(&(inst), 3); \
2436 *(inst)++ = (unsigned char)0x0F; \
2437 *(inst)++ = (unsigned char)(opc); \
2438 x86_reg_emit ((inst), (dreg), (reg)); \
2441 #define x86_sse_alu_reg_membase(inst,opc,sreg,basereg,disp) \
2443 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2444 *(inst)++ = (unsigned char)0x0f; \
2445 *(inst)++ = (unsigned char)(opc); \
2446 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2449 #define x86_sse_alu_membase_reg(inst,opc,basereg,disp,reg) \
2451 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2452 *(inst)++ = (unsigned char)0x0F; \
2453 *(inst)++ = (unsigned char)(opc); \
2454 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2457 #define x86_sse_alu_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2459 x86_codegen_pre(&(inst), 4); \
2460 *(inst)++ = (unsigned char)0x0F; \
2461 *(inst)++ = (unsigned char)(opc); \
2462 x86_reg_emit ((inst), (dreg), (reg)); \
2463 *(inst)++ = (unsigned char)(imm8); \
2466 #define x86_sse_alu_pd_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2468 x86_codegen_pre(&(inst), 5); \
2469 *(inst)++ = (unsigned char)0x66; \
2470 x86_sse_alu_reg_reg_imm8 ((inst), (opc), (dreg), (reg), (imm8)); \
2473 #define x86_sse_alu_pd_reg_reg(inst,opc,dreg,reg) \
2475 x86_codegen_pre(&(inst), 4); \
2476 *(inst)++ = (unsigned char)0x66; \
2477 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2480 #define x86_sse_alu_pd_membase_reg(inst,opc,basereg,disp,reg) \
2482 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2483 *(inst)++ = (unsigned char)0x66; \
2484 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2487 #define x86_sse_alu_pd_reg_membase(inst,opc,dreg,basereg,disp) \
2489 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2490 *(inst)++ = (unsigned char)0x66; \
2491 x86_sse_alu_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2494 #define x86_sse_alu_pd_reg_reg_imm(inst,opc,dreg,reg,imm) \
2496 x86_codegen_pre(&(inst), 5); \
2497 x86_sse_alu_pd_reg_reg ((inst), (opc), (dreg), (reg)); \
2498 *(inst)++ = (unsigned char)(imm); \
2501 #define x86_sse_alu_pd_reg_membase_imm(inst,opc,dreg,basereg,disp,imm) \
2503 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
2504 x86_sse_alu_pd_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2505 *(inst)++ = (unsigned char)(imm); \
2509 #define x86_sse_alu_ps_reg_reg(inst,opc,dreg,reg) \
2511 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2514 #define x86_sse_alu_ps_reg_reg_imm(inst,opc,dreg,reg, imm) \
2516 x86_codegen_pre(&(inst), 4); \
2517 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2518 *(inst)++ = (unsigned char)imm; \
2522 #define x86_sse_alu_sd_reg_reg(inst,opc,dreg,reg) \
2524 x86_codegen_pre(&(inst), 4); \
2525 *(inst)++ = (unsigned char)0xF2; \
2526 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2529 #define x86_sse_alu_sd_membase_reg(inst,opc,basereg,disp,reg) \
2531 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2532 *(inst)++ = (unsigned char)0xF2; \
2533 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2537 #define x86_sse_alu_ss_reg_reg(inst,opc,dreg,reg) \
2539 x86_codegen_pre(&(inst), 4); \
2540 *(inst)++ = (unsigned char)0xF3; \
2541 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2544 #define x86_sse_alu_ss_membase_reg(inst,opc,basereg,disp,reg) \
2546 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2547 *(inst)++ = (unsigned char)0xF3; \
2548 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2553 #define x86_sse_alu_sse41_reg_reg(inst,opc,dreg,reg) \
2555 x86_codegen_pre(&(inst), 5); \
2556 *(inst)++ = (unsigned char)0x66; \
2557 *(inst)++ = (unsigned char)0x0F; \
2558 *(inst)++ = (unsigned char)0x38; \
2559 *(inst)++ = (unsigned char)(opc); \
2560 x86_reg_emit ((inst), (dreg), (reg)); \
2563 #define x86_movups_reg_membase(inst,sreg,basereg,disp) \
2565 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2566 *(inst)++ = (unsigned char)0x0f; \
2567 *(inst)++ = (unsigned char)0x10; \
2568 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2571 #define x86_movups_membase_reg(inst,basereg,disp,reg) \
2573 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2574 *(inst)++ = (unsigned char)0x0f; \
2575 *(inst)++ = (unsigned char)0x11; \
2576 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2579 #define x86_movaps_reg_membase(inst,sreg,basereg,disp) \
2581 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2582 *(inst)++ = (unsigned char)0x0f; \
2583 *(inst)++ = (unsigned char)0x28; \
2584 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2587 #define x86_movaps_membase_reg(inst,basereg,disp,reg) \
2589 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2590 *(inst)++ = (unsigned char)0x0f; \
2591 *(inst)++ = (unsigned char)0x29; \
2592 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2595 #define x86_movaps_reg_reg(inst,dreg,sreg) \
2597 x86_codegen_pre(&(inst), 3); \
2598 *(inst)++ = (unsigned char)0x0f; \
2599 *(inst)++ = (unsigned char)0x28; \
2600 x86_reg_emit ((inst), (dreg), (sreg)); \
2604 #define x86_movd_reg_xreg(inst,dreg,sreg) \
2606 x86_codegen_pre(&(inst), 4); \
2607 *(inst)++ = (unsigned char)0x66; \
2608 *(inst)++ = (unsigned char)0x0f; \
2609 *(inst)++ = (unsigned char)0x7e; \
2610 x86_reg_emit ((inst), (sreg), (dreg)); \
2613 #define x86_movd_xreg_reg(inst,dreg,sreg) \
2615 x86_codegen_pre(&(inst), 4); \
2616 *(inst)++ = (unsigned char)0x66; \
2617 *(inst)++ = (unsigned char)0x0f; \
2618 *(inst)++ = (unsigned char)0x6e; \
2619 x86_reg_emit ((inst), (dreg), (sreg)); \
2622 #define x86_movd_xreg_membase(inst,sreg,basereg,disp) \
2624 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2625 *(inst)++ = (unsigned char)0x66; \
2626 *(inst)++ = (unsigned char)0x0f; \
2627 *(inst)++ = (unsigned char)0x6e; \
2628 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2631 #define x86_pshufw_reg_reg(inst,dreg,sreg,mask,high_words) \
2633 x86_codegen_pre(&(inst), 5); \
2634 *(inst)++ = (unsigned char)(high_words) ? 0xF3 : 0xF2; \
2635 *(inst)++ = (unsigned char)0x0f; \
2636 *(inst)++ = (unsigned char)0x70; \
2637 x86_reg_emit ((inst), (dreg), (sreg)); \
2638 *(inst)++ = (unsigned char)mask; \
2641 #define x86_sse_shift_reg_imm(inst,opc,mode, dreg,imm) \
2643 x86_codegen_pre(&(inst), 5); \
2644 x86_sse_alu_pd_reg_reg (inst, opc, mode, dreg); \
2645 x86_imm_emit8 ((inst), (imm)); \
2648 #define x86_sse_shift_reg_reg(inst,opc,dreg,sreg) \
2650 x86_sse_alu_pd_reg_reg (inst, opc, dreg, sreg); \