2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
20 #ifdef __native_client_codegen__
21 extern gint8 nacl_align_byte;
22 #endif /* __native_client_codegen__ */
25 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
26 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do { mono_nacl_align_inst(inst_ptr_ptr, inst_len); } while (0)
27 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
28 #define x86_call_sequence_post_val(inst) \
29 (mono_nacl_align_call(&_code_start, &(inst)), _code_start);
30 #define x86_call_sequence_pre(inst) x86_call_sequence_pre_val((inst))
31 #define x86_call_sequence_post(inst) x86_call_sequence_post_val((inst))
33 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do {} while (0)
34 /* Two variants are needed to avoid warnings */
35 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
36 #define x86_call_sequence_post_val(inst) _code_start
37 #define x86_call_sequence_pre(inst)
38 #define x86_call_sequence_post(inst)
39 #endif /* __native_client_codegen__ */
43 // x86 register numbers
70 // opcodes for alu instructions
84 // opcodes for shift instructions
99 // opcodes for floating-point instructions
113 // integer conditions codes
116 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
117 X86_CC_NE = 1, X86_CC_NZ = 1,
118 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
119 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
120 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
121 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
122 X86_CC_LZ = 6, X86_CC_S = 6,
123 X86_CC_GEZ = 7, X86_CC_NS = 7,
124 X86_CC_P = 8, X86_CC_PE = 8,
125 X86_CC_NP = 9, X86_CC_PO = 9,
137 X86_FP_CC_MASK = 0x4500
140 /* FP control word */
142 X86_FPCW_INVOPEX_MASK = 0x1,
143 X86_FPCW_DENOPEX_MASK = 0x2,
144 X86_FPCW_ZERODIV_MASK = 0x4,
145 X86_FPCW_OVFEX_MASK = 0x8,
146 X86_FPCW_UNDFEX_MASK = 0x10,
147 X86_FPCW_PRECEX_MASK = 0x20,
148 X86_FPCW_PRECC_MASK = 0x300,
149 X86_FPCW_ROUNDC_MASK = 0xc00,
151 /* values for precision control */
152 X86_FPCW_PREC_SINGLE = 0,
153 X86_FPCW_PREC_DOUBLE = 0x200,
154 X86_FPCW_PREC_EXTENDED = 0x300,
156 /* values for rounding control */
157 X86_FPCW_ROUND_NEAREST = 0,
158 X86_FPCW_ROUND_DOWN = 0x400,
159 X86_FPCW_ROUND_UP = 0x800,
160 X86_FPCW_ROUND_TOZERO = 0xc00
167 X86_LOCK_PREFIX = 0xF0,
168 X86_REPNZ_PREFIX = 0xF2,
169 X86_REPZ_PREFIX = 0xF3,
170 X86_REP_PREFIX = 0xF3,
171 X86_CS_PREFIX = 0x2E,
172 X86_SS_PREFIX = 0x36,
173 X86_DS_PREFIX = 0x3E,
174 X86_ES_PREFIX = 0x26,
175 X86_FS_PREFIX = 0x64,
176 X86_GS_PREFIX = 0x65,
177 X86_UNLIKELY_PREFIX = 0x2E,
178 X86_LIKELY_PREFIX = 0x3E,
179 X86_OPERAND_PREFIX = 0x66,
180 X86_ADDRESS_PREFIX = 0x67
183 static const unsigned char
184 x86_cc_unsigned_map [X86_NCC] = {
199 static const unsigned char
200 x86_cc_signed_map [X86_NCC] = {
220 #define X86_NOBASEREG (-1)
223 // bitvector mask for callee-saved registers
225 #define X86_ESI_MASK (1<<X86_ESI)
226 #define X86_EDI_MASK (1<<X86_EDI)
227 #define X86_EBX_MASK (1<<X86_EBX)
228 #define X86_EBP_MASK (1<<X86_EBP)
230 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
231 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
232 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
234 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
235 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
237 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
242 // +--------------------------------+
243 // | in_arg[0] = var[0] |
244 // | in_arg[1] = var[1] |
246 // | in_arg[n_arg-1] = var[n_arg-1] |
247 // +--------------------------------+
249 // +--------------------------------+
250 // | saved EBP | <-- frame pointer (EBP)
251 // +--------------------------------+
253 // +--------------------------------+
255 // | var[n_arg+1] | local variables area
258 // +--------------------------------+
261 // | spill area | area for spilling mimic stack
263 // +--------------------------------|
265 // | ebp [ESP_Frame only] |
266 // | esi | 0..3 callee-saved regs
267 // | edi | <-- stack pointer (ESP)
268 // +--------------------------------+
270 // | stk1 | operand stack area/
271 // | . . . | out args
273 // +--------------------------------|
280 * useful building blocks
282 #define x86_modrm_mod(modrm) ((modrm) >> 6)
283 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
284 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
286 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
287 #define x86_imm_emit32(inst,imm) \
289 x86_imm_buf imb; imb.val = (int) (imm); \
290 *(inst)++ = imb.b [0]; \
291 *(inst)++ = imb.b [1]; \
292 *(inst)++ = imb.b [2]; \
293 *(inst)++ = imb.b [3]; \
295 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
296 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
297 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
298 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
300 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
301 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
302 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
303 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
305 #define kMaxMembaseEmitPadding 6
307 #define x86_membase_emit_body(inst,r,basereg,disp) do {\
308 if ((basereg) == X86_ESP) { \
310 x86_address_byte ((inst), 0, (r), X86_ESP); \
311 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
312 } else if (x86_is_imm8((disp))) { \
313 x86_address_byte ((inst), 1, (r), X86_ESP); \
314 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
315 x86_imm_emit8 ((inst), (disp)); \
317 x86_address_byte ((inst), 2, (r), X86_ESP); \
318 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
319 x86_imm_emit32 ((inst), (disp)); \
323 if ((disp) == 0 && (basereg) != X86_EBP) { \
324 x86_address_byte ((inst), 0, (r), (basereg)); \
327 if (x86_is_imm8((disp))) { \
328 x86_address_byte ((inst), 1, (r), (basereg)); \
329 x86_imm_emit8 ((inst), (disp)); \
331 x86_address_byte ((inst), 2, (r), (basereg)); \
332 x86_imm_emit32 ((inst), (disp)); \
336 #if defined(__native_client_codegen__) && defined(TARGET_AMD64)
337 #define x86_membase_emit(inst,r,basereg,disp) \
339 amd64_nacl_membase_handler(&(inst), (basereg), (disp), (r)) ; \
341 #else /* __default_codegen__ || 32-bit NaCl codegen */
342 #define x86_membase_emit(inst,r,basereg,disp) \
344 x86_membase_emit_body((inst),(r),(basereg),(disp)); \
348 #define kMaxMemindexEmitPadding 6
350 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
352 if ((basereg) == X86_NOBASEREG) { \
353 x86_address_byte ((inst), 0, (r), 4); \
354 x86_address_byte ((inst), (shift), (indexreg), 5); \
355 x86_imm_emit32 ((inst), (disp)); \
356 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
357 x86_address_byte ((inst), 0, (r), 4); \
358 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
359 } else if (x86_is_imm8((disp))) { \
360 x86_address_byte ((inst), 1, (r), 4); \
361 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
362 x86_imm_emit8 ((inst), (disp)); \
364 x86_address_byte ((inst), 2, (r), 4); \
365 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
366 x86_imm_emit32 ((inst), (disp)); \
371 * target is the position in the code where to jump to:
373 * .. output loop code...
374 * x86_mov_reg_imm (code, X86_EAX, 0);
376 * x86_loop (code, -1);
380 * x86_patch (loop, target);
382 * ins should point at the start of the instruction that encodes a target.
383 * the instruction is inspected for validity and the correct displacement
386 #define x86_do_patch(ins,target) \
388 unsigned char* pos = (ins) + 1; \
389 int disp, size = 0; \
390 switch (*(unsigned char*)(ins)) { \
391 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
392 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
393 ++size; ++pos; break; /* prefix for 32-bit disp */ \
394 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
395 case 0xeb: /* jump8 */ \
396 /* conditional jump opcodes */ \
397 case 0x70: case 0x71: case 0x72: case 0x73: \
398 case 0x74: case 0x75: case 0x76: case 0x77: \
399 case 0x78: case 0x79: case 0x7a: case 0x7b: \
400 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
402 default: assert (0); \
404 disp = (target) - pos; \
405 if (size) x86_imm_emit32 (pos, disp - 4); \
406 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
410 #if defined( __native_client_codegen__ ) && defined(TARGET_X86)
412 #define x86_skip_nops(inst) \
417 if (inst[0] == 0x90) { \
421 if (inst[0] == 0x8b && inst[1] == 0xc0) { \
425 if (inst[0] == 0x8d && inst[1] == 0x6d \
426 && inst[2] == 0x00) { \
430 if (inst[0] == 0x8d && inst[1] == 0x64 \
431 && inst[2] == 0x24 && inst[3] == 0x00) { \
435 /* skip inst+=5 case because it's the 4-byte + 1-byte case */ \
436 if (inst[0] == 0x8d && inst[1] == 0xad \
437 && inst[2] == 0x00 && inst[3] == 0x00 \
438 && inst[4] == 0x00 && inst[5] == 0x00) { \
442 if (inst[0] == 0x8d && inst[1] == 0xa4 \
443 && inst[2] == 0x24 && inst[3] == 0x00 \
444 && inst[4] == 0x00 && inst[5] == 0x00 \
445 && inst[6] == 0x00 ) { \
449 } while ( in_nop ); \
452 #if defined(__native_client__)
453 #define x86_patch(ins,target) \
455 unsigned char* inst = (ins); \
456 guint8* new_target = nacl_modify_patch_target((target)); \
457 x86_skip_nops((inst)); \
458 x86_do_patch((inst), new_target); \
460 #else /* __native_client__ */
461 #define x86_patch(ins,target) \
463 unsigned char* inst = (ins); \
464 guint8* new_target = (target); \
465 x86_skip_nops((inst)); \
466 x86_do_patch((inst), new_target); \
468 #endif /* __native_client__ */
471 #define x86_patch(ins,target) do { x86_do_patch((ins), (target)); } while (0)
472 #endif /* __native_client_codegen__ */
474 #ifdef __native_client_codegen__
475 /* The breakpoint instruction is illegal in Native Client, although the HALT */
476 /* instruction is allowed. The breakpoint is used several places in mini-x86.c */
477 /* and exceptions-x86.c. */
478 #define x86_breakpoint(inst) \
483 #define x86_breakpoint(inst) \
489 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
490 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
491 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
492 #define x86_stosd(inst) x86_stosl((inst))
493 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
494 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
495 #define x86_movsd(inst) x86_movsl((inst))
497 #if defined(__default_codegen__)
498 #define x86_prefix(inst,p) \
500 *(inst)++ =(unsigned char) (p); \
502 #elif defined(__native_client_codegen__)
503 #if defined(TARGET_X86)
504 /* kNaClAlignment - 1 is the max value we can pass into x86_codegen_pre. */
505 /* This keeps us from having to call x86_codegen_pre with specific */
506 /* knowledge of the size of the instruction that follows it, and */
507 /* localizes the alignment requirement to this spot. */
508 #define x86_prefix(inst,p) \
510 x86_codegen_pre(&(inst), kNaClAlignment - 1); \
511 *(inst)++ =(unsigned char) (p); \
513 #elif defined(TARGET_AMD64)
514 /* We need to tag any prefixes so we can perform proper membase sandboxing */
515 /* See: mini-amd64.c:amd64_nacl_membase_handler for verbose details */
516 #define x86_prefix(inst,p) \
518 amd64_nacl_tag_legacy_prefix((inst)); \
519 *(inst)++ =(unsigned char) (p); \
522 #endif /* TARGET_AMD64 */
524 #endif /* __native_client_codegen__ */
526 #define x86_mfence(inst) \
528 x86_codegen_pre(&(inst), 3); \
534 #define x86_rdtsc(inst) \
536 x86_codegen_pre(&(inst), 2); \
541 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
543 x86_codegen_pre(&(inst), 3); \
544 *(inst)++ = (unsigned char)0x0f; \
545 *(inst)++ = (unsigned char)0xb1; \
546 x86_reg_emit ((inst), (reg), (dreg)); \
549 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
551 x86_codegen_pre(&(inst), 7); \
552 *(inst)++ = (unsigned char)0x0f; \
553 *(inst)++ = (unsigned char)0xb1; \
554 x86_mem_emit ((inst), (reg), (mem)); \
557 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
559 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
560 *(inst)++ = (unsigned char)0x0f; \
561 *(inst)++ = (unsigned char)0xb1; \
562 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
565 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
567 x86_codegen_pre(&(inst), 2); \
569 *(inst)++ = (unsigned char)0x86; \
571 *(inst)++ = (unsigned char)0x87; \
572 x86_reg_emit ((inst), (reg), (dreg)); \
575 #define x86_xchg_mem_reg(inst,mem,reg,size) \
577 x86_codegen_pre(&(inst), 6); \
579 *(inst)++ = (unsigned char)0x86; \
581 *(inst)++ = (unsigned char)0x87; \
582 x86_mem_emit ((inst), (reg), (mem)); \
585 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
587 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
589 *(inst)++ = (unsigned char)0x86; \
591 *(inst)++ = (unsigned char)0x87; \
592 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
595 #define x86_xadd_reg_reg(inst,dreg,reg,size) \
597 x86_codegen_pre(&(inst), 3); \
598 *(inst)++ = (unsigned char)0x0F; \
600 *(inst)++ = (unsigned char)0xC0; \
602 *(inst)++ = (unsigned char)0xC1; \
603 x86_reg_emit ((inst), (reg), (dreg)); \
606 #define x86_xadd_mem_reg(inst,mem,reg,size) \
608 x86_codegen_pre(&(inst), 7); \
609 *(inst)++ = (unsigned char)0x0F; \
611 *(inst)++ = (unsigned char)0xC0; \
613 *(inst)++ = (unsigned char)0xC1; \
614 x86_mem_emit ((inst), (reg), (mem)); \
617 #define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \
619 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
620 *(inst)++ = (unsigned char)0x0F; \
622 *(inst)++ = (unsigned char)0xC0; \
624 *(inst)++ = (unsigned char)0xC1; \
625 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
628 #define x86_inc_mem(inst,mem) \
630 x86_codegen_pre(&(inst), 6); \
631 *(inst)++ = (unsigned char)0xff; \
632 x86_mem_emit ((inst), 0, (mem)); \
635 #define x86_inc_membase(inst,basereg,disp) \
637 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
638 *(inst)++ = (unsigned char)0xff; \
639 x86_membase_emit ((inst), 0, (basereg), (disp)); \
642 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
644 #define x86_dec_mem(inst,mem) \
646 x86_codegen_pre(&(inst), 6); \
647 *(inst)++ = (unsigned char)0xff; \
648 x86_mem_emit ((inst), 1, (mem)); \
651 #define x86_dec_membase(inst,basereg,disp) \
653 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
654 *(inst)++ = (unsigned char)0xff; \
655 x86_membase_emit ((inst), 1, (basereg), (disp)); \
658 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
660 #define x86_not_mem(inst,mem) \
662 x86_codegen_pre(&(inst), 6); \
663 *(inst)++ = (unsigned char)0xf7; \
664 x86_mem_emit ((inst), 2, (mem)); \
667 #define x86_not_membase(inst,basereg,disp) \
669 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
670 *(inst)++ = (unsigned char)0xf7; \
671 x86_membase_emit ((inst), 2, (basereg), (disp)); \
674 #define x86_not_reg(inst,reg) \
676 x86_codegen_pre(&(inst), 2); \
677 *(inst)++ = (unsigned char)0xf7; \
678 x86_reg_emit ((inst), 2, (reg)); \
681 #define x86_neg_mem(inst,mem) \
683 x86_codegen_pre(&(inst), 6); \
684 *(inst)++ = (unsigned char)0xf7; \
685 x86_mem_emit ((inst), 3, (mem)); \
688 #define x86_neg_membase(inst,basereg,disp) \
690 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
691 *(inst)++ = (unsigned char)0xf7; \
692 x86_membase_emit ((inst), 3, (basereg), (disp)); \
695 #define x86_neg_reg(inst,reg) \
697 x86_codegen_pre(&(inst), 2); \
698 *(inst)++ = (unsigned char)0xf7; \
699 x86_reg_emit ((inst), 3, (reg)); \
702 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
704 #define x86_alu_reg_imm(inst,opc,reg,imm) \
706 if ((reg) == X86_EAX) { \
707 x86_codegen_pre(&(inst), 5); \
708 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
709 x86_imm_emit32 ((inst), (imm)); \
712 if (x86_is_imm8((imm))) { \
713 x86_codegen_pre(&(inst), 3); \
714 *(inst)++ = (unsigned char)0x83; \
715 x86_reg_emit ((inst), (opc), (reg)); \
716 x86_imm_emit8 ((inst), (imm)); \
718 x86_codegen_pre(&(inst), 6); \
719 *(inst)++ = (unsigned char)0x81; \
720 x86_reg_emit ((inst), (opc), (reg)); \
721 x86_imm_emit32 ((inst), (imm)); \
725 #define x86_alu_mem_imm(inst,opc,mem,imm) \
727 if (x86_is_imm8((imm))) { \
728 x86_codegen_pre(&(inst), 7); \
729 *(inst)++ = (unsigned char)0x83; \
730 x86_mem_emit ((inst), (opc), (mem)); \
731 x86_imm_emit8 ((inst), (imm)); \
733 x86_codegen_pre(&(inst), 10); \
734 *(inst)++ = (unsigned char)0x81; \
735 x86_mem_emit ((inst), (opc), (mem)); \
736 x86_imm_emit32 ((inst), (imm)); \
740 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
742 if (x86_is_imm8((imm))) { \
743 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
744 *(inst)++ = (unsigned char)0x83; \
745 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
746 x86_imm_emit8 ((inst), (imm)); \
748 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
749 *(inst)++ = (unsigned char)0x81; \
750 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
751 x86_imm_emit32 ((inst), (imm)); \
755 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
757 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
758 *(inst)++ = (unsigned char)0x80; \
759 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
760 x86_imm_emit8 ((inst), (imm)); \
763 #define x86_alu_mem_reg(inst,opc,mem,reg) \
765 x86_codegen_pre(&(inst), 6); \
766 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
767 x86_mem_emit ((inst), (reg), (mem)); \
770 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
772 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
773 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
774 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
777 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
779 x86_codegen_pre(&(inst), 2); \
780 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
781 x86_reg_emit ((inst), (dreg), (reg)); \
785 * @x86_alu_reg8_reg8:
786 * Supports ALU operations between two 8-bit registers.
787 * dreg := dreg opc reg
788 * X86_Reg_No enum is used to specify the registers.
789 * Additionally is_*_h flags are used to specify what part
790 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
791 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
793 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
795 x86_codegen_pre(&(inst), 2); \
796 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
797 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
800 #define x86_alu_reg_mem(inst,opc,reg,mem) \
802 x86_codegen_pre(&(inst), 6); \
803 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
804 x86_mem_emit ((inst), (reg), (mem)); \
807 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
809 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
810 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
811 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
814 #define x86_test_reg_imm(inst,reg,imm) \
816 x86_codegen_pre(&(inst), 6); \
817 if ((reg) == X86_EAX) { \
818 *(inst)++ = (unsigned char)0xa9; \
820 *(inst)++ = (unsigned char)0xf7; \
821 x86_reg_emit ((inst), 0, (reg)); \
823 x86_imm_emit32 ((inst), (imm)); \
826 #define x86_test_mem_imm8(inst,mem,imm) \
828 x86_codegen_pre(&(inst), 7); \
829 *(inst)++ = (unsigned char)0xf6; \
830 x86_mem_emit ((inst), 0, (mem)); \
831 x86_imm_emit8 ((inst), (imm)); \
834 #define x86_test_mem_imm(inst,mem,imm) \
836 x86_codegen_pre(&(inst), 10); \
837 *(inst)++ = (unsigned char)0xf7; \
838 x86_mem_emit ((inst), 0, (mem)); \
839 x86_imm_emit32 ((inst), (imm)); \
842 #define x86_test_membase_imm(inst,basereg,disp,imm) \
844 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
845 *(inst)++ = (unsigned char)0xf7; \
846 x86_membase_emit ((inst), 0, (basereg), (disp)); \
847 x86_imm_emit32 ((inst), (imm)); \
850 #define x86_test_reg_reg(inst,dreg,reg) \
852 x86_codegen_pre(&(inst), 2); \
853 *(inst)++ = (unsigned char)0x85; \
854 x86_reg_emit ((inst), (reg), (dreg)); \
857 #define x86_test_mem_reg(inst,mem,reg) \
859 x86_codegen_pre(&(inst), 6); \
860 *(inst)++ = (unsigned char)0x85; \
861 x86_mem_emit ((inst), (reg), (mem)); \
864 #define x86_test_membase_reg(inst,basereg,disp,reg) \
866 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
867 *(inst)++ = (unsigned char)0x85; \
868 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
871 #define x86_shift_reg_imm(inst,opc,reg,imm) \
874 x86_codegen_pre(&(inst), 2); \
875 *(inst)++ = (unsigned char)0xd1; \
876 x86_reg_emit ((inst), (opc), (reg)); \
878 x86_codegen_pre(&(inst), 3); \
879 *(inst)++ = (unsigned char)0xc1; \
880 x86_reg_emit ((inst), (opc), (reg)); \
881 x86_imm_emit8 ((inst), (imm)); \
885 #define x86_shift_mem_imm(inst,opc,mem,imm) \
888 x86_codegen_pre(&(inst), 6); \
889 *(inst)++ = (unsigned char)0xd1; \
890 x86_mem_emit ((inst), (opc), (mem)); \
892 x86_codegen_pre(&(inst), 7); \
893 *(inst)++ = (unsigned char)0xc1; \
894 x86_mem_emit ((inst), (opc), (mem)); \
895 x86_imm_emit8 ((inst), (imm)); \
899 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
902 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
903 *(inst)++ = (unsigned char)0xd1; \
904 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
906 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
907 *(inst)++ = (unsigned char)0xc1; \
908 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
909 x86_imm_emit8 ((inst), (imm)); \
913 #define x86_shift_reg(inst,opc,reg) \
915 x86_codegen_pre(&(inst), 2); \
916 *(inst)++ = (unsigned char)0xd3; \
917 x86_reg_emit ((inst), (opc), (reg)); \
920 #define x86_shift_mem(inst,opc,mem) \
922 x86_codegen_pre(&(inst), 6); \
923 *(inst)++ = (unsigned char)0xd3; \
924 x86_mem_emit ((inst), (opc), (mem)); \
927 #define x86_shift_membase(inst,opc,basereg,disp) \
929 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
930 *(inst)++ = (unsigned char)0xd3; \
931 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
935 * Multi op shift missing.
938 #define x86_shrd_reg(inst,dreg,reg) \
940 x86_codegen_pre(&(inst), 3); \
941 *(inst)++ = (unsigned char)0x0f; \
942 *(inst)++ = (unsigned char)0xad; \
943 x86_reg_emit ((inst), (reg), (dreg)); \
946 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
948 x86_codegen_pre(&(inst), 4); \
949 *(inst)++ = (unsigned char)0x0f; \
950 *(inst)++ = (unsigned char)0xac; \
951 x86_reg_emit ((inst), (reg), (dreg)); \
952 x86_imm_emit8 ((inst), (shamt)); \
955 #define x86_shld_reg(inst,dreg,reg) \
957 x86_codegen_pre(&(inst), 3); \
958 *(inst)++ = (unsigned char)0x0f; \
959 *(inst)++ = (unsigned char)0xa5; \
960 x86_reg_emit ((inst), (reg), (dreg)); \
963 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
965 x86_codegen_pre(&(inst), 4); \
966 *(inst)++ = (unsigned char)0x0f; \
967 *(inst)++ = (unsigned char)0xa4; \
968 x86_reg_emit ((inst), (reg), (dreg)); \
969 x86_imm_emit8 ((inst), (shamt)); \
975 #define x86_mul_reg(inst,reg,is_signed) \
977 x86_codegen_pre(&(inst), 2); \
978 *(inst)++ = (unsigned char)0xf7; \
979 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
982 #define x86_mul_mem(inst,mem,is_signed) \
984 x86_codegen_pre(&(inst), 6); \
985 *(inst)++ = (unsigned char)0xf7; \
986 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
989 #define x86_mul_membase(inst,basereg,disp,is_signed) \
991 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
992 *(inst)++ = (unsigned char)0xf7; \
993 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
999 #define x86_imul_reg_reg(inst,dreg,reg) \
1001 x86_codegen_pre(&(inst), 3); \
1002 *(inst)++ = (unsigned char)0x0f; \
1003 *(inst)++ = (unsigned char)0xaf; \
1004 x86_reg_emit ((inst), (dreg), (reg)); \
1007 #define x86_imul_reg_mem(inst,reg,mem) \
1009 x86_codegen_pre(&(inst), 7); \
1010 *(inst)++ = (unsigned char)0x0f; \
1011 *(inst)++ = (unsigned char)0xaf; \
1012 x86_mem_emit ((inst), (reg), (mem)); \
1015 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
1017 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1018 *(inst)++ = (unsigned char)0x0f; \
1019 *(inst)++ = (unsigned char)0xaf; \
1020 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1026 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
1028 if (x86_is_imm8 ((imm))) { \
1029 x86_codegen_pre(&(inst), 3); \
1030 *(inst)++ = (unsigned char)0x6b; \
1031 x86_reg_emit ((inst), (dreg), (reg)); \
1032 x86_imm_emit8 ((inst), (imm)); \
1034 x86_codegen_pre(&(inst), 6); \
1035 *(inst)++ = (unsigned char)0x69; \
1036 x86_reg_emit ((inst), (dreg), (reg)); \
1037 x86_imm_emit32 ((inst), (imm)); \
1041 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
1043 if (x86_is_imm8 ((imm))) { \
1044 x86_codegen_pre(&(inst), 7); \
1045 *(inst)++ = (unsigned char)0x6b; \
1046 x86_mem_emit ((inst), (reg), (mem)); \
1047 x86_imm_emit8 ((inst), (imm)); \
1049 x86_codegen_pre(&(inst), 6); \
1050 *(inst)++ = (unsigned char)0x69; \
1051 x86_mem_emit ((inst), (reg), (mem)); \
1052 x86_imm_emit32 ((inst), (imm)); \
1056 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
1058 if (x86_is_imm8 ((imm))) { \
1059 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1060 *(inst)++ = (unsigned char)0x6b; \
1061 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1062 x86_imm_emit8 ((inst), (imm)); \
1064 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1065 *(inst)++ = (unsigned char)0x69; \
1066 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1067 x86_imm_emit32 ((inst), (imm)); \
1072 * divide EDX:EAX by rm;
1073 * eax = quotient, edx = remainder
1076 #define x86_div_reg(inst,reg,is_signed) \
1078 x86_codegen_pre(&(inst), 2); \
1079 *(inst)++ = (unsigned char)0xf7; \
1080 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
1083 #define x86_div_mem(inst,mem,is_signed) \
1085 x86_codegen_pre(&(inst), 6); \
1086 *(inst)++ = (unsigned char)0xf7; \
1087 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
1090 #define x86_div_membase(inst,basereg,disp,is_signed) \
1092 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1093 *(inst)++ = (unsigned char)0xf7; \
1094 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
1097 #define x86_mov_mem_reg(inst,mem,reg,size) \
1099 x86_codegen_pre(&(inst), 7); \
1101 case 1: *(inst)++ = (unsigned char)0x88; break; \
1102 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1103 case 4: *(inst)++ = (unsigned char)0x89; break; \
1104 default: assert (0); \
1106 x86_mem_emit ((inst), (reg), (mem)); \
1109 #define x86_mov_regp_reg(inst,regp,reg,size) \
1111 x86_codegen_pre(&(inst), 3); \
1113 case 1: *(inst)++ = (unsigned char)0x88; break; \
1114 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1115 case 4: *(inst)++ = (unsigned char)0x89; break; \
1116 default: assert (0); \
1118 x86_regp_emit ((inst), (reg), (regp)); \
1121 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
1123 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1125 case 1: *(inst)++ = (unsigned char)0x88; break; \
1126 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1127 case 4: *(inst)++ = (unsigned char)0x89; break; \
1128 default: assert (0); \
1130 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1133 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
1135 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1137 case 1: *(inst)++ = (unsigned char)0x88; break; \
1138 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1139 case 4: *(inst)++ = (unsigned char)0x89; break; \
1140 default: assert (0); \
1142 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1145 #define x86_mov_reg_reg(inst,dreg,reg,size) \
1147 x86_codegen_pre(&(inst), 3); \
1149 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1150 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1151 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1152 default: assert (0); \
1154 x86_reg_emit ((inst), (dreg), (reg)); \
1157 #define x86_mov_reg_mem(inst,reg,mem,size) \
1159 x86_codegen_pre(&(inst), 7); \
1161 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1162 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1163 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1164 default: assert (0); \
1166 x86_mem_emit ((inst), (reg), (mem)); \
1169 #define kMovRegMembasePadding (2 + kMaxMembaseEmitPadding)
1171 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
1173 x86_codegen_pre(&(inst), kMovRegMembasePadding); \
1175 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1176 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1177 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1178 default: assert (0); \
1180 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1183 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
1185 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1187 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1188 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1189 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1190 default: assert (0); \
1192 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1196 * Note: x86_clear_reg () chacnges the condition code!
1198 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
1200 #define x86_mov_reg_imm(inst,reg,imm) \
1202 x86_codegen_pre(&(inst), 5); \
1203 *(inst)++ = (unsigned char)0xb8 + (reg); \
1204 x86_imm_emit32 ((inst), (imm)); \
1207 #define x86_mov_mem_imm(inst,mem,imm,size) \
1209 if ((size) == 1) { \
1210 x86_codegen_pre(&(inst), 7); \
1211 *(inst)++ = (unsigned char)0xc6; \
1212 x86_mem_emit ((inst), 0, (mem)); \
1213 x86_imm_emit8 ((inst), (imm)); \
1214 } else if ((size) == 2) { \
1215 x86_codegen_pre(&(inst), 9); \
1216 x86_prefix((inst), X86_OPERAND_PREFIX); \
1217 *(inst)++ = (unsigned char)0xc7; \
1218 x86_mem_emit ((inst), 0, (mem)); \
1219 x86_imm_emit16 ((inst), (imm)); \
1221 x86_codegen_pre(&(inst), 10); \
1222 *(inst)++ = (unsigned char)0xc7; \
1223 x86_mem_emit ((inst), 0, (mem)); \
1224 x86_imm_emit32 ((inst), (imm)); \
1228 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
1230 if ((size) == 1) { \
1231 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1232 *(inst)++ = (unsigned char)0xc6; \
1233 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1234 x86_imm_emit8 ((inst), (imm)); \
1235 } else if ((size) == 2) { \
1236 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
1237 x86_prefix((inst), X86_OPERAND_PREFIX); \
1238 *(inst)++ = (unsigned char)0xc7; \
1239 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1240 x86_imm_emit16 ((inst), (imm)); \
1242 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1243 *(inst)++ = (unsigned char)0xc7; \
1244 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1245 x86_imm_emit32 ((inst), (imm)); \
1249 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
1251 if ((size) == 1) { \
1252 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1253 *(inst)++ = (unsigned char)0xc6; \
1254 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1255 x86_imm_emit8 ((inst), (imm)); \
1256 } else if ((size) == 2) { \
1257 x86_codegen_pre(&(inst), 4 + kMaxMemindexEmitPadding); \
1258 x86_prefix((inst), X86_OPERAND_PREFIX); \
1259 *(inst)++ = (unsigned char)0xc7; \
1260 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1261 x86_imm_emit16 ((inst), (imm)); \
1263 x86_codegen_pre(&(inst), 5 + kMaxMemindexEmitPadding); \
1264 *(inst)++ = (unsigned char)0xc7; \
1265 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1266 x86_imm_emit32 ((inst), (imm)); \
1270 #define x86_lea_mem(inst,reg,mem) \
1272 x86_codegen_pre(&(inst), 5); \
1273 *(inst)++ = (unsigned char)0x8d; \
1274 x86_mem_emit ((inst), (reg), (mem)); \
1277 #define x86_lea_membase(inst,reg,basereg,disp) \
1279 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1280 *(inst)++ = (unsigned char)0x8d; \
1281 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1284 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
1286 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1287 *(inst)++ = (unsigned char)0x8d; \
1288 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1291 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1293 unsigned char op = 0xb6; \
1294 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1295 x86_codegen_pre(&(inst), 3); \
1296 *(inst)++ = (unsigned char)0x0f; \
1297 if ((is_signed)) op += 0x08; \
1298 if ((is_half)) op += 0x01; \
1300 x86_reg_emit ((inst), (dreg), (reg)); \
1303 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1305 unsigned char op = 0xb6; \
1306 x86_codegen_pre(&(inst), 7); \
1307 *(inst)++ = (unsigned char)0x0f; \
1308 if ((is_signed)) op += 0x08; \
1309 if ((is_half)) op += 0x01; \
1311 x86_mem_emit ((inst), (dreg), (mem)); \
1314 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1316 unsigned char op = 0xb6; \
1317 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1318 *(inst)++ = (unsigned char)0x0f; \
1319 if ((is_signed)) op += 0x08; \
1320 if ((is_half)) op += 0x01; \
1322 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1325 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1327 unsigned char op = 0xb6; \
1328 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1329 *(inst)++ = (unsigned char)0x0f; \
1330 if ((is_signed)) op += 0x08; \
1331 if ((is_half)) op += 0x01; \
1333 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1336 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1337 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1339 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1341 x86_codegen_pre(&(inst), 6); \
1342 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1343 x86_mem_emit ((inst), (opc), (mem)); \
1346 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1348 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1349 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1350 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1353 #define x86_fp_op(inst,opc,index) \
1355 x86_codegen_pre(&(inst), 2); \
1356 *(inst)++ = (unsigned char)0xd8; \
1357 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1360 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1362 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1363 x86_codegen_pre(&(inst), 2); \
1364 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1365 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1369 * @x86_fp_int_op_membase
1370 * Supports FPU operations between ST(0) and integer operand in memory.
1371 * Operation encoded using X86_FP_Opcode enum.
1372 * Operand is addressed by [basereg + disp].
1373 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1375 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1377 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1378 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1379 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1382 #define x86_fstp(inst,index) \
1384 x86_codegen_pre(&(inst), 2); \
1385 *(inst)++ = (unsigned char)0xdd; \
1386 *(inst)++ = (unsigned char)0xd8+(index); \
1389 #define x86_fcompp(inst) \
1391 x86_codegen_pre(&(inst), 2); \
1392 *(inst)++ = (unsigned char)0xde; \
1393 *(inst)++ = (unsigned char)0xd9; \
1396 #define x86_fucompp(inst) \
1398 x86_codegen_pre(&(inst), 2); \
1399 *(inst)++ = (unsigned char)0xda; \
1400 *(inst)++ = (unsigned char)0xe9; \
1403 #define x86_fnstsw(inst) \
1405 x86_codegen_pre(&(inst), 2); \
1406 *(inst)++ = (unsigned char)0xdf; \
1407 *(inst)++ = (unsigned char)0xe0; \
1410 #define x86_fnstcw(inst,mem) \
1412 x86_codegen_pre(&(inst), 6); \
1413 *(inst)++ = (unsigned char)0xd9; \
1414 x86_mem_emit ((inst), 7, (mem)); \
1417 #define x86_fnstcw_membase(inst,basereg,disp) \
1419 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1420 *(inst)++ = (unsigned char)0xd9; \
1421 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1424 #define x86_fldcw(inst,mem) \
1426 x86_codegen_pre(&(inst), 6); \
1427 *(inst)++ = (unsigned char)0xd9; \
1428 x86_mem_emit ((inst), 5, (mem)); \
1431 #define x86_fldcw_membase(inst,basereg,disp) \
1433 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1434 *(inst)++ = (unsigned char)0xd9; \
1435 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1438 #define x86_fchs(inst) \
1440 x86_codegen_pre(&(inst), 2); \
1441 *(inst)++ = (unsigned char)0xd9; \
1442 *(inst)++ = (unsigned char)0xe0; \
1445 #define x86_frem(inst) \
1447 x86_codegen_pre(&(inst), 2); \
1448 *(inst)++ = (unsigned char)0xd9; \
1449 *(inst)++ = (unsigned char)0xf8; \
1452 #define x86_fxch(inst,index) \
1454 x86_codegen_pre(&(inst), 2); \
1455 *(inst)++ = (unsigned char)0xd9; \
1456 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1459 #define x86_fcomi(inst,index) \
1461 x86_codegen_pre(&(inst), 2); \
1462 *(inst)++ = (unsigned char)0xdb; \
1463 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1466 #define x86_fcomip(inst,index) \
1468 x86_codegen_pre(&(inst), 2); \
1469 *(inst)++ = (unsigned char)0xdf; \
1470 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1473 #define x86_fucomi(inst,index) \
1475 x86_codegen_pre(&(inst), 2); \
1476 *(inst)++ = (unsigned char)0xdb; \
1477 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1480 #define x86_fucomip(inst,index) \
1482 x86_codegen_pre(&(inst), 2); \
1483 *(inst)++ = (unsigned char)0xdf; \
1484 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1487 #define x86_fld(inst,mem,is_double) \
1489 x86_codegen_pre(&(inst), 6); \
1490 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1491 x86_mem_emit ((inst), 0, (mem)); \
1494 #define x86_fld_membase(inst,basereg,disp,is_double) \
1496 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1497 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1498 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1501 #define x86_fld80_mem(inst,mem) \
1503 x86_codegen_pre(&(inst), 6); \
1504 *(inst)++ = (unsigned char)0xdb; \
1505 x86_mem_emit ((inst), 5, (mem)); \
1508 #define x86_fld80_membase(inst,basereg,disp) \
1510 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1511 *(inst)++ = (unsigned char)0xdb; \
1512 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1515 #define x86_fild(inst,mem,is_long) \
1517 x86_codegen_pre(&(inst), 6); \
1519 *(inst)++ = (unsigned char)0xdf; \
1520 x86_mem_emit ((inst), 5, (mem)); \
1522 *(inst)++ = (unsigned char)0xdb; \
1523 x86_mem_emit ((inst), 0, (mem)); \
1527 #define x86_fild_membase(inst,basereg,disp,is_long) \
1529 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1531 *(inst)++ = (unsigned char)0xdf; \
1532 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1534 *(inst)++ = (unsigned char)0xdb; \
1535 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1539 #define x86_fld_reg(inst,index) \
1541 x86_codegen_pre(&(inst), 2); \
1542 *(inst)++ = (unsigned char)0xd9; \
1543 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1546 #define x86_fldz(inst) \
1548 x86_codegen_pre(&(inst), 2); \
1549 *(inst)++ = (unsigned char)0xd9; \
1550 *(inst)++ = (unsigned char)0xee; \
1553 #define x86_fld1(inst) \
1555 x86_codegen_pre(&(inst), 2); \
1556 *(inst)++ = (unsigned char)0xd9; \
1557 *(inst)++ = (unsigned char)0xe8; \
1560 #define x86_fldpi(inst) \
1562 x86_codegen_pre(&(inst), 2); \
1563 *(inst)++ = (unsigned char)0xd9; \
1564 *(inst)++ = (unsigned char)0xeb; \
1567 #define x86_fst(inst,mem,is_double,pop_stack) \
1569 x86_codegen_pre(&(inst), 6); \
1570 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1571 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1574 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1576 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1577 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1578 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1581 #define x86_fst80_mem(inst,mem) \
1583 x86_codegen_pre(&(inst), 6); \
1584 *(inst)++ = (unsigned char)0xdb; \
1585 x86_mem_emit ((inst), 7, (mem)); \
1589 #define x86_fst80_membase(inst,basereg,disp) \
1591 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1592 *(inst)++ = (unsigned char)0xdb; \
1593 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1597 #define x86_fist_pop(inst,mem,is_long) \
1599 x86_codegen_pre(&(inst), 6); \
1601 *(inst)++ = (unsigned char)0xdf; \
1602 x86_mem_emit ((inst), 7, (mem)); \
1604 *(inst)++ = (unsigned char)0xdb; \
1605 x86_mem_emit ((inst), 3, (mem)); \
1609 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1611 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1613 *(inst)++ = (unsigned char)0xdf; \
1614 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1616 *(inst)++ = (unsigned char)0xdb; \
1617 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1621 #define x86_fstsw(inst) \
1623 x86_codegen_pre(&(inst), 3); \
1624 *(inst)++ = (unsigned char)0x9b; \
1625 *(inst)++ = (unsigned char)0xdf; \
1626 *(inst)++ = (unsigned char)0xe0; \
1631 * Converts content of ST(0) to integer and stores it at memory location
1632 * addressed by [basereg + disp].
1633 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1635 #define x86_fist_membase(inst,basereg,disp,is_int) \
1637 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1639 *(inst)++ = (unsigned char)0xdb; \
1640 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1642 *(inst)++ = (unsigned char)0xdf; \
1643 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1648 #define x86_push_reg(inst,reg) \
1650 *(inst)++ = (unsigned char)0x50 + (reg); \
1653 #define x86_push_regp(inst,reg) \
1655 x86_codegen_pre(&(inst), 2); \
1656 *(inst)++ = (unsigned char)0xff; \
1657 x86_regp_emit ((inst), 6, (reg)); \
1660 #define x86_push_mem(inst,mem) \
1662 x86_codegen_pre(&(inst), 6); \
1663 *(inst)++ = (unsigned char)0xff; \
1664 x86_mem_emit ((inst), 6, (mem)); \
1667 #define x86_push_membase(inst,basereg,disp) \
1669 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1670 *(inst)++ = (unsigned char)0xff; \
1671 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1674 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1676 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1677 *(inst)++ = (unsigned char)0xff; \
1678 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1681 #define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)
1683 #define x86_push_imm(inst,imm) \
1685 int _imm = (int) (imm); \
1686 if (x86_is_imm8 (_imm)) { \
1687 x86_codegen_pre(&(inst), 2); \
1688 *(inst)++ = (unsigned char)0x6A; \
1689 x86_imm_emit8 ((inst), (_imm)); \
1691 x86_codegen_pre(&(inst), 5); \
1692 *(inst)++ = (unsigned char)0x68; \
1693 x86_imm_emit32 ((inst), (_imm)); \
1697 #define x86_pop_reg(inst,reg) \
1699 *(inst)++ = (unsigned char)0x58 + (reg); \
1702 #define x86_pop_mem(inst,mem) \
1704 x86_codegen_pre(&(inst), 6); \
1705 *(inst)++ = (unsigned char)0x87; \
1706 x86_mem_emit ((inst), 0, (mem)); \
1709 #define x86_pop_membase(inst,basereg,disp) \
1711 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1712 *(inst)++ = (unsigned char)0x87; \
1713 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1716 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1717 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1718 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1719 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1721 #define x86_loop(inst,imm) \
1723 x86_codegen_pre(&(inst), 2); \
1724 *(inst)++ = (unsigned char)0xe2; \
1725 x86_imm_emit8 ((inst), (imm)); \
1728 #define x86_loope(inst,imm) \
1730 x86_codegen_pre(&(inst), 2); \
1731 *(inst)++ = (unsigned char)0xe1; \
1732 x86_imm_emit8 ((inst), (imm)); \
1735 #define x86_loopne(inst,imm) \
1737 x86_codegen_pre(&(inst), 2); \
1738 *(inst)++ = (unsigned char)0xe0; \
1739 x86_imm_emit8 ((inst), (imm)); \
1742 #if defined(TARGET_X86)
1743 #define x86_jump32(inst,imm) \
1745 x86_codegen_pre(&(inst), 5); \
1746 *(inst)++ = (unsigned char)0xe9; \
1747 x86_imm_emit32 ((inst), (imm)); \
1750 #define x86_jump8(inst,imm) \
1752 x86_codegen_pre(&(inst), 2); \
1753 *(inst)++ = (unsigned char)0xeb; \
1754 x86_imm_emit8 ((inst), (imm)); \
1756 #elif defined(TARGET_AMD64)
1757 /* These macros are used directly from mini-amd64.c and other */
1758 /* amd64 specific files, so they need to be instrumented directly. */
1759 #define x86_jump32(inst,imm) \
1761 amd64_codegen_pre(inst); \
1762 *(inst)++ = (unsigned char)0xe9; \
1763 x86_imm_emit32 ((inst), (imm)); \
1764 amd64_codegen_post(inst); \
1767 #define x86_jump8(inst,imm) \
1769 amd64_codegen_pre(inst); \
1770 *(inst)++ = (unsigned char)0xeb; \
1771 x86_imm_emit8 ((inst), (imm)); \
1772 amd64_codegen_post(inst); \
1776 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
1777 #define x86_jump_reg(inst,reg) do { \
1778 x86_codegen_pre(&(inst), 5); \
1779 *(inst)++ = (unsigned char)0x83; /* and */ \
1780 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
1781 *(inst)++ = (unsigned char)nacl_align_byte; \
1782 *(inst)++ = (unsigned char)0xff; \
1783 x86_reg_emit ((inst), 4, (reg)); \
1786 /* Let's hope ECX is available for these... */
1787 #define x86_jump_mem(inst,mem) do { \
1788 x86_mov_reg_mem(inst, (X86_ECX), (mem), 4); \
1789 x86_jump_reg(inst, (X86_ECX)); \
1792 #define x86_jump_membase(inst,basereg,disp) do { \
1793 x86_mov_reg_membase(inst, (X86_ECX), basereg, disp, 4); \
1794 x86_jump_reg(inst, (X86_ECX)); \
1797 /* like x86_jump_membase, but force a 32-bit displacement */
1798 #define x86_jump_membase32(inst,basereg,disp) do { \
1799 x86_codegen_pre(&(inst), 6); \
1800 *(inst)++ = (unsigned char)0x8b; \
1801 x86_address_byte ((inst), 2, X86_ECX, (basereg)); \
1802 x86_imm_emit32 ((inst), (disp)); \
1803 x86_jump_reg(inst, (X86_ECX)); \
1805 #else /* __native_client_codegen__ */
1806 #define x86_jump_reg(inst,reg) \
1808 *(inst)++ = (unsigned char)0xff; \
1809 x86_reg_emit ((inst), 4, (reg)); \
1812 #define x86_jump_mem(inst,mem) \
1814 *(inst)++ = (unsigned char)0xff; \
1815 x86_mem_emit ((inst), 4, (mem)); \
1818 #define x86_jump_membase(inst,basereg,disp) \
1820 *(inst)++ = (unsigned char)0xff; \
1821 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1823 #endif /* __native_client_codegen__ */
1825 * target is a pointer in our buffer.
1827 #define x86_jump_code_body(inst,target) \
1830 x86_codegen_pre(&(inst), 2); \
1831 t = (unsigned char*)(target) - (inst) - 2; \
1832 if (x86_is_imm8(t)) { \
1833 x86_jump8 ((inst), t); \
1835 x86_codegen_pre(&(inst), 5); \
1836 t = (unsigned char*)(target) - (inst) - 5; \
1837 x86_jump32 ((inst), t); \
1841 #if defined(__default_codegen__)
1842 #define x86_jump_code(inst,target) \
1844 x86_jump_code_body((inst),(target)); \
1846 #elif defined(__native_client_codegen__) && defined(TARGET_X86)
1847 #define x86_jump_code(inst,target) \
1849 guint8* jump_start = (inst); \
1850 x86_jump_code_body((inst),(target)); \
1851 x86_patch(jump_start, (target)); \
1853 #elif defined(__native_client_codegen__) && defined(TARGET_AMD64)
1854 #define x86_jump_code(inst,target) \
1856 /* jump_code_body is used twice because there are offsets */ \
1857 /* calculated based on the IP, which can change after the */ \
1858 /* call to amd64_codegen_post */ \
1859 amd64_codegen_pre(inst); \
1860 x86_jump_code_body((inst),(target)); \
1861 inst = amd64_codegen_post(inst); \
1862 x86_jump_code_body((inst),(target)); \
1864 #endif /* __native_client_codegen__ */
1866 #define x86_jump_disp(inst,disp) \
1868 int t = (disp) - 2; \
1869 if (x86_is_imm8(t)) { \
1870 x86_jump8 ((inst), t); \
1873 x86_jump32 ((inst), t); \
1877 #if defined(TARGET_X86)
1878 #define x86_branch8(inst,cond,imm,is_signed) \
1880 x86_codegen_pre(&(inst), 2); \
1882 *(inst)++ = x86_cc_signed_map [(cond)]; \
1884 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1885 x86_imm_emit8 ((inst), (imm)); \
1888 #define x86_branch32(inst,cond,imm,is_signed) \
1890 x86_codegen_pre(&(inst), 6); \
1891 *(inst)++ = (unsigned char)0x0f; \
1893 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1895 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1896 x86_imm_emit32 ((inst), (imm)); \
1898 #elif defined(TARGET_AMD64)
1899 /* These macros are used directly from mini-amd64.c and other */
1900 /* amd64 specific files, so they need to be instrumented directly. */
1901 #define x86_branch8(inst,cond,imm,is_signed) \
1903 amd64_codegen_pre(inst); \
1905 *(inst)++ = x86_cc_signed_map [(cond)]; \
1907 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1908 x86_imm_emit8 ((inst), (imm)); \
1909 amd64_codegen_post(inst); \
1911 #define x86_branch32(inst,cond,imm,is_signed) \
1913 amd64_codegen_pre(inst); \
1914 *(inst)++ = (unsigned char)0x0f; \
1916 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1918 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1919 x86_imm_emit32 ((inst), (imm)); \
1920 amd64_codegen_post(inst); \
1924 #if defined(TARGET_X86)
1925 #define x86_branch(inst,cond,target,is_signed) \
1928 guint8* branch_start; \
1929 x86_codegen_pre(&(inst), 2); \
1930 offset = (target) - (inst) - 2; \
1931 branch_start = (inst); \
1932 if (x86_is_imm8 ((offset))) \
1933 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1935 x86_codegen_pre(&(inst), 6); \
1936 offset = (target) - (inst) - 6; \
1937 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1939 x86_patch(branch_start, (target)); \
1941 #elif defined(TARGET_AMD64)
1942 /* This macro is used directly from mini-amd64.c and other */
1943 /* amd64 specific files, so it needs to be instrumented directly. */
1945 #define x86_branch_body(inst,cond,target,is_signed) \
1947 int offset = (target) - (inst) - 2; \
1948 if (x86_is_imm8 ((offset))) \
1949 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1951 offset = (target) - (inst) - 6; \
1952 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1956 #if defined(__default_codegen__)
1957 #define x86_branch(inst,cond,target,is_signed) \
1959 x86_branch_body((inst),(cond),(target),(is_signed)); \
1961 #elif defined(__native_client_codegen__)
1962 #define x86_branch(inst,cond,target,is_signed) \
1964 /* branch_body is used twice because there are offsets */ \
1965 /* calculated based on the IP, which can change after */ \
1966 /* the call to amd64_codegen_post */ \
1967 amd64_codegen_pre(inst); \
1968 x86_branch_body((inst),(cond),(target),(is_signed)); \
1969 inst = amd64_codegen_post(inst); \
1970 x86_branch_body((inst),(cond),(target),(is_signed)); \
1972 #endif /* __native_client_codegen__ */
1974 #endif /* TARGET_AMD64 */
1976 #define x86_branch_disp(inst,cond,disp,is_signed) \
1978 int offset = (disp) - 2; \
1979 if (x86_is_imm8 ((offset))) \
1980 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1983 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1987 #define x86_set_reg(inst,cond,reg,is_signed) \
1989 g_assert (X86_IS_BYTE_REG (reg)); \
1990 x86_codegen_pre(&(inst), 3); \
1991 *(inst)++ = (unsigned char)0x0f; \
1993 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1995 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1996 x86_reg_emit ((inst), 0, (reg)); \
1999 #define x86_set_mem(inst,cond,mem,is_signed) \
2001 x86_codegen_pre(&(inst), 7); \
2002 *(inst)++ = (unsigned char)0x0f; \
2004 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
2006 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
2007 x86_mem_emit ((inst), 0, (mem)); \
2010 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
2012 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2013 *(inst)++ = (unsigned char)0x0f; \
2015 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
2017 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
2018 x86_membase_emit ((inst), 0, (basereg), (disp)); \
2021 #define x86_call_imm_body(inst,disp) \
2023 *(inst)++ = (unsigned char)0xe8; \
2024 x86_imm_emit32 ((inst), (int)(disp)); \
2027 #define x86_call_imm(inst,disp) \
2029 x86_call_sequence_pre((inst)); \
2030 x86_call_imm_body((inst), (disp)); \
2031 x86_call_sequence_post((inst)); \
2035 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2036 #define x86_call_reg_internal(inst,reg) \
2038 *(inst)++ = (unsigned char)0x83; /* and */ \
2039 x86_reg_emit ((inst), 4, (reg)); /* reg */ \
2040 *(inst)++ = (unsigned char)nacl_align_byte; \
2041 *(inst)++ = (unsigned char)0xff; /* call */ \
2042 x86_reg_emit ((inst), 2, (reg)); /* reg */ \
2045 #define x86_call_reg(inst, reg) do { \
2046 x86_call_sequence_pre((inst)); \
2047 x86_call_reg_internal(inst, reg); \
2048 x86_call_sequence_post((inst)); \
2052 /* It appears that x86_call_mem() is never used, so I'm leaving it out. */
2053 #define x86_call_membase(inst,basereg,disp) do { \
2054 x86_call_sequence_pre((inst)); \
2055 /* x86_mov_reg_membase() inlined so its fixed size */ \
2056 *(inst)++ = (unsigned char)0x8b; \
2057 x86_address_byte ((inst), 2, (X86_ECX), (basereg)); \
2058 x86_imm_emit32 ((inst), (disp)); \
2059 x86_call_reg_internal(inst, X86_ECX); \
2060 x86_call_sequence_post((inst)); \
2062 #else /* __native_client_codegen__ */
2063 #define x86_call_reg(inst,reg) \
2065 *(inst)++ = (unsigned char)0xff; \
2066 x86_reg_emit ((inst), 2, (reg)); \
2069 #define x86_call_mem(inst,mem) \
2071 *(inst)++ = (unsigned char)0xff; \
2072 x86_mem_emit ((inst), 2, (mem)); \
2075 #define x86_call_membase(inst,basereg,disp) \
2077 *(inst)++ = (unsigned char)0xff; \
2078 x86_membase_emit ((inst), 2, (basereg), (disp)); \
2080 #endif /* __native_client_codegen__ */
2083 #if defined( __native_client_codegen__ ) && defined( TARGET_X86 )
2085 #define x86_call_code(inst,target) \
2088 guint8* call_start; \
2089 guint8* _aligned_start; \
2090 x86_call_sequence_pre_val((inst)); \
2091 _x86_offset = (unsigned char*)(target) - (inst); \
2093 x86_call_imm_body ((inst), _x86_offset); \
2094 _aligned_start = x86_call_sequence_post_val((inst)); \
2095 call_start = _aligned_start; \
2096 _x86_offset = (unsigned char*)(target) - (_aligned_start); \
2098 x86_call_imm_body ((_aligned_start), _x86_offset); \
2099 x86_patch(call_start, (target)); \
2102 #define SIZE_OF_RET 6
2103 #define x86_ret(inst) do { \
2104 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2105 x86_codegen_pre(&(inst), 5); \
2106 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2107 *(inst)++ = (unsigned char)0xe1; \
2108 *(inst)++ = (unsigned char)nacl_align_byte; \
2109 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2110 *(inst)++ = (unsigned char)0xe1; \
2113 /* pop return address */
2114 /* pop imm bytes from stack */
2116 #define x86_ret_imm(inst,imm) do { \
2117 *(inst)++ = (unsigned char)0x59; /* pop ecx */ \
2118 x86_alu_reg_imm ((inst), X86_ADD, X86_ESP, imm); \
2119 x86_codegen_pre(&(inst), 5); \
2120 *(inst)++ = (unsigned char)0x83; /* and 0xffffffff, ecx */ \
2121 *(inst)++ = (unsigned char)0xe1; \
2122 *(inst)++ = (unsigned char)nacl_align_byte; \
2123 *(inst)++ = (unsigned char)0xff; /* jmp ecx */ \
2124 *(inst)++ = (unsigned char)0xe1; \
2126 #else /* __native_client_codegen__ */
2128 #define x86_call_code(inst,target) \
2131 _x86_offset = (unsigned char*)(target) - (inst); \
2133 x86_call_imm_body ((inst), _x86_offset); \
2136 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
2138 #define x86_ret_imm(inst,imm) \
2143 x86_codegen_pre(&(inst), 3); \
2144 *(inst)++ = (unsigned char)0xc2; \
2145 x86_imm_emit16 ((inst), (imm)); \
2148 #endif /* __native_client_codegen__ */
2150 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
2152 x86_codegen_pre(&(inst), 3); \
2153 *(inst)++ = (unsigned char) 0x0f; \
2155 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2157 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2158 x86_reg_emit ((inst), (dreg), (reg)); \
2161 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
2163 x86_codegen_pre(&(inst), 7); \
2164 *(inst)++ = (unsigned char) 0x0f; \
2166 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2168 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2169 x86_mem_emit ((inst), (reg), (mem)); \
2172 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
2174 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2175 *(inst)++ = (unsigned char) 0x0f; \
2177 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
2179 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
2180 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2183 #define x86_enter(inst,framesize) \
2185 x86_codegen_pre(&(inst), 4); \
2186 *(inst)++ = (unsigned char)0xc8; \
2187 x86_imm_emit16 ((inst), (framesize)); \
2191 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
2192 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
2194 #define x86_fsin(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
2195 #define x86_fcos(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
2196 #define x86_fabs(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
2197 #define x86_ftst(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
2198 #define x86_fxam(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
2199 #define x86_fpatan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
2200 #define x86_fprem(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
2201 #define x86_fprem1(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
2202 #define x86_frndint(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
2203 #define x86_fsqrt(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
2204 #define x86_fptan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
2206 #define x86_padding(inst,size) \
2209 case 1: x86_nop ((inst)); break; \
2210 case 2: *(inst)++ = 0x8b; \
2211 *(inst)++ = 0xc0; break; \
2212 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
2213 *(inst)++ = 0x00; break; \
2214 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2215 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2217 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
2218 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2219 x86_nop ((inst)); break; \
2220 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
2221 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2222 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2224 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
2225 *(inst)++ = 0x24; *(inst)++ = 0x00; \
2226 *(inst)++ = 0x00; *(inst)++ = 0x00; \
2227 *(inst)++ = 0x00; break; \
2228 default: assert (0); \
2232 #ifdef __native_client_codegen__
2234 #define kx86NaClLengthOfCallReg 5
2235 #define kx86NaClLengthOfCallImm 5
2236 #define kx86NaClLengthOfCallMembase (kx86NaClLengthOfCallReg + 6)
2238 #endif /* __native_client_codegen__ */
2240 #define x86_prolog(inst,frame_size,reg_mask) \
2242 unsigned i, m = 1; \
2243 x86_enter ((inst), (frame_size)); \
2244 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
2245 if ((reg_mask) & m) \
2246 x86_push_reg ((inst), i); \
2250 #define x86_epilog(inst,reg_mask) \
2252 unsigned i, m = 1 << X86_EDI; \
2253 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
2254 if ((reg_mask) & m) \
2255 x86_pop_reg ((inst), i); \
2257 x86_leave ((inst)); \
2263 X86_SSE_SQRT = 0x51,
2264 X86_SSE_RSQRT = 0x52,
2272 X86_SSE_COMP = 0xC2,
2274 X86_SSE_ANDN = 0x55,
2277 X86_SSE_UNPCKL = 0x14,
2278 X86_SSE_UNPCKH = 0x15,
2280 X86_SSE_ADDSUB = 0xD0,
2281 X86_SSE_HADD = 0x7C,
2282 X86_SSE_HSUB = 0x7D,
2283 X86_SSE_MOVSHDUP = 0x16,
2284 X86_SSE_MOVSLDUP = 0x12,
2285 X86_SSE_MOVDDUP = 0x12,
2287 X86_SSE_PAND = 0xDB,
2289 X86_SSE_PXOR = 0xEF,
2291 X86_SSE_PADDB = 0xFC,
2292 X86_SSE_PADDW = 0xFD,
2293 X86_SSE_PADDD = 0xFE,
2294 X86_SSE_PADDQ = 0xD4,
2296 X86_SSE_PSUBB = 0xF8,
2297 X86_SSE_PSUBW = 0xF9,
2298 X86_SSE_PSUBD = 0xFA,
2299 X86_SSE_PSUBQ = 0xFB,
2301 X86_SSE_PMAXSB = 0x3C, /*sse41*/
2302 X86_SSE_PMAXSW = 0xEE,
2303 X86_SSE_PMAXSD = 0x3D, /*sse41*/
2305 X86_SSE_PMAXUB = 0xDE,
2306 X86_SSE_PMAXUW = 0x3E, /*sse41*/
2307 X86_SSE_PMAXUD = 0x3F, /*sse41*/
2309 X86_SSE_PMINSB = 0x38, /*sse41*/
2310 X86_SSE_PMINSW = 0xEA,
2311 X86_SSE_PMINSD = 0x39,/*sse41*/
2313 X86_SSE_PMINUB = 0xDA,
2314 X86_SSE_PMINUW = 0x3A, /*sse41*/
2315 X86_SSE_PMINUD = 0x3B, /*sse41*/
2317 X86_SSE_PAVGB = 0xE0,
2318 X86_SSE_PAVGW = 0xE3,
2320 X86_SSE_PCMPEQB = 0x74,
2321 X86_SSE_PCMPEQW = 0x75,
2322 X86_SSE_PCMPEQD = 0x76,
2323 X86_SSE_PCMPEQQ = 0x29, /*sse41*/
2325 X86_SSE_PCMPGTB = 0x64,
2326 X86_SSE_PCMPGTW = 0x65,
2327 X86_SSE_PCMPGTD = 0x66,
2328 X86_SSE_PCMPGTQ = 0x37, /*sse42*/
2330 X86_SSE_PSADBW = 0xf6,
2332 X86_SSE_PSHUFD = 0x70,
2334 X86_SSE_PUNPCKLBW = 0x60,
2335 X86_SSE_PUNPCKLWD = 0x61,
2336 X86_SSE_PUNPCKLDQ = 0x62,
2337 X86_SSE_PUNPCKLQDQ = 0x6C,
2339 X86_SSE_PUNPCKHBW = 0x68,
2340 X86_SSE_PUNPCKHWD = 0x69,
2341 X86_SSE_PUNPCKHDQ = 0x6A,
2342 X86_SSE_PUNPCKHQDQ = 0x6D,
2344 X86_SSE_PACKSSWB = 0x63,
2345 X86_SSE_PACKSSDW = 0x6B,
2347 X86_SSE_PACKUSWB = 0x67,
2348 X86_SSE_PACKUSDW = 0x2B,/*sse41*/
2350 X86_SSE_PADDUSB = 0xDC,
2351 X86_SSE_PADDUSW = 0xDD,
2352 X86_SSE_PSUBUSB = 0xD8,
2353 X86_SSE_PSUBUSW = 0xD9,
2355 X86_SSE_PADDSB = 0xEC,
2356 X86_SSE_PADDSW = 0xED,
2357 X86_SSE_PSUBSB = 0xE8,
2358 X86_SSE_PSUBSW = 0xE9,
2360 X86_SSE_PMULLW = 0xD5,
2361 X86_SSE_PMULLD = 0x40,/*sse41*/
2362 X86_SSE_PMULHUW = 0xE4,
2363 X86_SSE_PMULHW = 0xE5,
2364 X86_SSE_PMULUDQ = 0xF4,
2366 X86_SSE_PMOVMSKB = 0xD7,
2368 X86_SSE_PSHIFTW = 0x71,
2369 X86_SSE_PSHIFTD = 0x72,
2370 X86_SSE_PSHIFTQ = 0x73,
2375 X86_SSE_PSRLW_REG = 0xD1,
2376 X86_SSE_PSRAW_REG = 0xE1,
2377 X86_SSE_PSLLW_REG = 0xF1,
2379 X86_SSE_PSRLD_REG = 0xD2,
2380 X86_SSE_PSRAD_REG = 0xE2,
2381 X86_SSE_PSLLD_REG = 0xF2,
2383 X86_SSE_PSRLQ_REG = 0xD3,
2384 X86_SSE_PSLLQ_REG = 0xF3,
2386 X86_SSE_PREFETCH = 0x18,
2387 X86_SSE_MOVNTPS = 0x2B,
2388 X86_SSE_MOVHPD_REG_MEMBASE = 0x16,
2389 X86_SSE_MOVHPD_MEMBASE_REG = 0x17,
2391 X86_SSE_MOVSD_REG_MEMBASE = 0x10,
2392 X86_SSE_MOVSD_MEMBASE_REG = 0x11,
2394 X86_SSE_PINSRB = 0x20,/*sse41*/
2395 X86_SSE_PINSRW = 0xC4,
2396 X86_SSE_PINSRD = 0x22,/*sse41*/
2398 X86_SSE_PEXTRB = 0x14,/*sse41*/
2399 X86_SSE_PEXTRW = 0xC5,
2400 X86_SSE_PEXTRD = 0x16,/*sse41*/
2402 X86_SSE_SHUFP = 0xC6,
2404 X86_SSE_CVTDQ2PD = 0xE6,
2405 X86_SSE_CVTDQ2PS = 0x5B,
2406 X86_SSE_CVTPD2DQ = 0xE6,
2407 X86_SSE_CVTPD2PS = 0x5A,
2408 X86_SSE_CVTPS2DQ = 0x5B,
2409 X86_SSE_CVTPS2PD = 0x5A,
2410 X86_SSE_CVTTPD2DQ = 0xE6,
2411 X86_SSE_CVTTPS2DQ = 0x5B,
2415 /* minimal SSE* support */
2416 #define x86_movsd_reg_membase(inst,dreg,basereg,disp) \
2418 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2419 *(inst)++ = (unsigned char)0xf2; \
2420 *(inst)++ = (unsigned char)0x0f; \
2421 *(inst)++ = (unsigned char)0x10; \
2422 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
2425 #define x86_cvttsd2si(inst,dreg,reg) \
2427 x86_codegen_pre(&(inst), 4); \
2428 *(inst)++ = (unsigned char)0xf2; \
2429 *(inst)++ = (unsigned char)0x0f; \
2430 *(inst)++ = (unsigned char)0x2c; \
2431 x86_reg_emit ((inst), (dreg), (reg)); \
2434 #define x86_sse_alu_reg_reg(inst,opc,dreg,reg) \
2436 x86_codegen_pre(&(inst), 3); \
2437 *(inst)++ = (unsigned char)0x0F; \
2438 *(inst)++ = (unsigned char)(opc); \
2439 x86_reg_emit ((inst), (dreg), (reg)); \
2442 #define x86_sse_alu_reg_membase(inst,opc,sreg,basereg,disp) \
2444 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2445 *(inst)++ = (unsigned char)0x0f; \
2446 *(inst)++ = (unsigned char)(opc); \
2447 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2450 #define x86_sse_alu_membase_reg(inst,opc,basereg,disp,reg) \
2452 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2453 *(inst)++ = (unsigned char)0x0F; \
2454 *(inst)++ = (unsigned char)(opc); \
2455 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2458 #define x86_sse_alu_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2460 x86_codegen_pre(&(inst), 4); \
2461 *(inst)++ = (unsigned char)0x0F; \
2462 *(inst)++ = (unsigned char)(opc); \
2463 x86_reg_emit ((inst), (dreg), (reg)); \
2464 *(inst)++ = (unsigned char)(imm8); \
2467 #define x86_sse_alu_pd_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2469 x86_codegen_pre(&(inst), 5); \
2470 *(inst)++ = (unsigned char)0x66; \
2471 x86_sse_alu_reg_reg_imm8 ((inst), (opc), (dreg), (reg), (imm8)); \
2474 #define x86_sse_alu_pd_reg_reg(inst,opc,dreg,reg) \
2476 x86_codegen_pre(&(inst), 4); \
2477 *(inst)++ = (unsigned char)0x66; \
2478 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2481 #define x86_sse_alu_pd_membase_reg(inst,opc,basereg,disp,reg) \
2483 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2484 *(inst)++ = (unsigned char)0x66; \
2485 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2488 #define x86_sse_alu_pd_reg_membase(inst,opc,dreg,basereg,disp) \
2490 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2491 *(inst)++ = (unsigned char)0x66; \
2492 x86_sse_alu_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2495 #define x86_sse_alu_pd_reg_reg_imm(inst,opc,dreg,reg,imm) \
2497 x86_codegen_pre(&(inst), 5); \
2498 x86_sse_alu_pd_reg_reg ((inst), (opc), (dreg), (reg)); \
2499 *(inst)++ = (unsigned char)(imm); \
2502 #define x86_sse_alu_pd_reg_membase_imm(inst,opc,dreg,basereg,disp,imm) \
2504 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
2505 x86_sse_alu_pd_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2506 *(inst)++ = (unsigned char)(imm); \
2510 #define x86_sse_alu_ps_reg_reg(inst,opc,dreg,reg) \
2512 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2515 #define x86_sse_alu_ps_reg_reg_imm(inst,opc,dreg,reg, imm) \
2517 x86_codegen_pre(&(inst), 4); \
2518 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2519 *(inst)++ = (unsigned char)imm; \
2523 #define x86_sse_alu_sd_reg_reg(inst,opc,dreg,reg) \
2525 x86_codegen_pre(&(inst), 4); \
2526 *(inst)++ = (unsigned char)0xF2; \
2527 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2530 #define x86_sse_alu_sd_membase_reg(inst,opc,basereg,disp,reg) \
2532 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2533 *(inst)++ = (unsigned char)0xF2; \
2534 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2538 #define x86_sse_alu_ss_reg_reg(inst,opc,dreg,reg) \
2540 x86_codegen_pre(&(inst), 4); \
2541 *(inst)++ = (unsigned char)0xF3; \
2542 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2545 #define x86_sse_alu_ss_membase_reg(inst,opc,basereg,disp,reg) \
2547 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2548 *(inst)++ = (unsigned char)0xF3; \
2549 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2554 #define x86_sse_alu_sse41_reg_reg(inst,opc,dreg,reg) \
2556 x86_codegen_pre(&(inst), 5); \
2557 *(inst)++ = (unsigned char)0x66; \
2558 *(inst)++ = (unsigned char)0x0F; \
2559 *(inst)++ = (unsigned char)0x38; \
2560 *(inst)++ = (unsigned char)(opc); \
2561 x86_reg_emit ((inst), (dreg), (reg)); \
2564 #define x86_movups_reg_membase(inst,sreg,basereg,disp) \
2566 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2567 *(inst)++ = (unsigned char)0x0f; \
2568 *(inst)++ = (unsigned char)0x10; \
2569 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2572 #define x86_movups_membase_reg(inst,basereg,disp,reg) \
2574 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2575 *(inst)++ = (unsigned char)0x0f; \
2576 *(inst)++ = (unsigned char)0x11; \
2577 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2580 #define x86_movaps_reg_membase(inst,sreg,basereg,disp) \
2582 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2583 *(inst)++ = (unsigned char)0x0f; \
2584 *(inst)++ = (unsigned char)0x28; \
2585 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2588 #define x86_movaps_membase_reg(inst,basereg,disp,reg) \
2590 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2591 *(inst)++ = (unsigned char)0x0f; \
2592 *(inst)++ = (unsigned char)0x29; \
2593 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2596 #define x86_movaps_reg_reg(inst,dreg,sreg) \
2598 x86_codegen_pre(&(inst), 3); \
2599 *(inst)++ = (unsigned char)0x0f; \
2600 *(inst)++ = (unsigned char)0x28; \
2601 x86_reg_emit ((inst), (dreg), (sreg)); \
2605 #define x86_movd_reg_xreg(inst,dreg,sreg) \
2607 x86_codegen_pre(&(inst), 4); \
2608 *(inst)++ = (unsigned char)0x66; \
2609 *(inst)++ = (unsigned char)0x0f; \
2610 *(inst)++ = (unsigned char)0x7e; \
2611 x86_reg_emit ((inst), (sreg), (dreg)); \
2614 #define x86_movd_xreg_reg(inst,dreg,sreg) \
2616 x86_codegen_pre(&(inst), 4); \
2617 *(inst)++ = (unsigned char)0x66; \
2618 *(inst)++ = (unsigned char)0x0f; \
2619 *(inst)++ = (unsigned char)0x6e; \
2620 x86_reg_emit ((inst), (dreg), (sreg)); \
2623 #define x86_movd_xreg_membase(inst,sreg,basereg,disp) \
2625 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2626 *(inst)++ = (unsigned char)0x66; \
2627 *(inst)++ = (unsigned char)0x0f; \
2628 *(inst)++ = (unsigned char)0x6e; \
2629 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2632 #define x86_pshufw_reg_reg(inst,dreg,sreg,mask,high_words) \
2634 x86_codegen_pre(&(inst), 5); \
2635 *(inst)++ = (unsigned char)(high_words) ? 0xF3 : 0xF2; \
2636 *(inst)++ = (unsigned char)0x0f; \
2637 *(inst)++ = (unsigned char)0x70; \
2638 x86_reg_emit ((inst), (dreg), (sreg)); \
2639 *(inst)++ = (unsigned char)mask; \
2642 #define x86_sse_shift_reg_imm(inst,opc,mode, dreg,imm) \
2644 x86_codegen_pre(&(inst), 5); \
2645 x86_sse_alu_pd_reg_reg (inst, opc, mode, dreg); \
2646 x86_imm_emit8 ((inst), (imm)); \
2649 #define x86_sse_shift_reg_reg(inst,opc,dreg,sreg) \
2651 x86_sse_alu_pd_reg_reg (inst, opc, dreg, sreg); \