2 * x86-codegen.h: Macros for generating x86 code
5 * Paolo Molaro (lupus@ximian.com)
6 * Intel Corporation (ORP Project)
7 * Sergey Chaban (serge@wildwestsoftware.com)
8 * Dietmar Maurer (dietmar@ximian.com)
11 * Copyright (C) 2000 Intel Corporation. All rights reserved.
12 * Copyright (C) 2001, 2002 Ximian, Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
20 #define x86_codegen_pre(inst_ptr_ptr, inst_len) do {} while (0)
21 /* Two variants are needed to avoid warnings */
22 #define x86_call_sequence_pre_val(inst) guint8* _code_start = (inst);
23 #define x86_call_sequence_post_val(inst) _code_start
24 #define x86_call_sequence_pre(inst)
25 #define x86_call_sequence_post(inst)
28 // x86 register numbers
55 // opcodes for alu instructions
69 // opcodes for shift instructions
84 // opcodes for floating-point instructions
98 // integer conditions codes
101 X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,
102 X86_CC_NE = 1, X86_CC_NZ = 1,
103 X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,
104 X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,
105 X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,
106 X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,
107 X86_CC_LZ = 6, X86_CC_S = 6,
108 X86_CC_GEZ = 7, X86_CC_NS = 7,
109 X86_CC_P = 8, X86_CC_PE = 8,
110 X86_CC_NP = 9, X86_CC_PO = 9,
122 X86_FP_CC_MASK = 0x4500
125 /* FP control word */
127 X86_FPCW_INVOPEX_MASK = 0x1,
128 X86_FPCW_DENOPEX_MASK = 0x2,
129 X86_FPCW_ZERODIV_MASK = 0x4,
130 X86_FPCW_OVFEX_MASK = 0x8,
131 X86_FPCW_UNDFEX_MASK = 0x10,
132 X86_FPCW_PRECEX_MASK = 0x20,
133 X86_FPCW_PRECC_MASK = 0x300,
134 X86_FPCW_ROUNDC_MASK = 0xc00,
136 /* values for precision control */
137 X86_FPCW_PREC_SINGLE = 0,
138 X86_FPCW_PREC_DOUBLE = 0x200,
139 X86_FPCW_PREC_EXTENDED = 0x300,
141 /* values for rounding control */
142 X86_FPCW_ROUND_NEAREST = 0,
143 X86_FPCW_ROUND_DOWN = 0x400,
144 X86_FPCW_ROUND_UP = 0x800,
145 X86_FPCW_ROUND_TOZERO = 0xc00
152 X86_LOCK_PREFIX = 0xF0,
153 X86_REPNZ_PREFIX = 0xF2,
154 X86_REPZ_PREFIX = 0xF3,
155 X86_REP_PREFIX = 0xF3,
156 X86_CS_PREFIX = 0x2E,
157 X86_SS_PREFIX = 0x36,
158 X86_DS_PREFIX = 0x3E,
159 X86_ES_PREFIX = 0x26,
160 X86_FS_PREFIX = 0x64,
161 X86_GS_PREFIX = 0x65,
162 X86_UNLIKELY_PREFIX = 0x2E,
163 X86_LIKELY_PREFIX = 0x3E,
164 X86_OPERAND_PREFIX = 0x66,
165 X86_ADDRESS_PREFIX = 0x67
168 static const unsigned char
169 x86_cc_unsigned_map [X86_NCC] = {
184 static const unsigned char
185 x86_cc_signed_map [X86_NCC] = {
205 #define X86_NOBASEREG (-1)
208 // bitvector mask for callee-saved registers
210 #define X86_ESI_MASK (1<<X86_ESI)
211 #define X86_EDI_MASK (1<<X86_EDI)
212 #define X86_EBX_MASK (1<<X86_EBX)
213 #define X86_EBP_MASK (1<<X86_EBP)
215 #define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))
216 #define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))
217 #define X86_BYTE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))
219 #define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg))) /* X86_EAX, X86_ECX, or X86_EDX */
220 #define X86_IS_CALLEE(reg) (X86_CALLEE_REGS & (1 << (reg))) /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */
222 #define X86_IS_BYTE_REG(reg) ((reg) < 4)
227 // +--------------------------------+
228 // | in_arg[0] = var[0] |
229 // | in_arg[1] = var[1] |
231 // | in_arg[n_arg-1] = var[n_arg-1] |
232 // +--------------------------------+
234 // +--------------------------------+
235 // | saved EBP | <-- frame pointer (EBP)
236 // +--------------------------------+
238 // +--------------------------------+
240 // | var[n_arg+1] | local variables area
243 // +--------------------------------+
246 // | spill area | area for spilling mimic stack
248 // +--------------------------------|
250 // | ebp [ESP_Frame only] |
251 // | esi | 0..3 callee-saved regs
252 // | edi | <-- stack pointer (ESP)
253 // +--------------------------------+
255 // | stk1 | operand stack area/
256 // | . . . | out args
258 // +--------------------------------|
265 * useful building blocks
267 #define x86_modrm_mod(modrm) ((modrm) >> 6)
268 #define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)
269 #define x86_modrm_rm(modrm) ((modrm) & 0x7)
271 #define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)
272 #define x86_imm_emit32(inst,imm) \
274 x86_imm_buf imb; imb.val = (int) (imm); \
275 *(inst)++ = imb.b [0]; \
276 *(inst)++ = imb.b [1]; \
277 *(inst)++ = imb.b [2]; \
278 *(inst)++ = imb.b [3]; \
280 #define x86_imm_emit16(inst,imm) do { *(short*)(inst) = (imm); (inst) += 2; } while (0)
281 #define x86_imm_emit8(inst,imm) do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)
282 #define x86_is_imm8(imm) (((int)(imm) >= -128 && (int)(imm) <= 127))
283 #define x86_is_imm16(imm) (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))
285 #define x86_reg_emit(inst,r,regno) do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)
286 #define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh) do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)
287 #define x86_regp_emit(inst,r,regno) do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)
288 #define x86_mem_emit(inst,r,disp) do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)
290 #define kMaxMembaseEmitPadding 6
292 #define x86_membase_emit_body(inst,r,basereg,disp) do {\
293 if ((basereg) == X86_ESP) { \
295 x86_address_byte ((inst), 0, (r), X86_ESP); \
296 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
297 } else if (x86_is_imm8((disp))) { \
298 x86_address_byte ((inst), 1, (r), X86_ESP); \
299 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
300 x86_imm_emit8 ((inst), (disp)); \
302 x86_address_byte ((inst), 2, (r), X86_ESP); \
303 x86_address_byte ((inst), 0, X86_ESP, X86_ESP); \
304 x86_imm_emit32 ((inst), (disp)); \
308 if ((disp) == 0 && (basereg) != X86_EBP) { \
309 x86_address_byte ((inst), 0, (r), (basereg)); \
312 if (x86_is_imm8((disp))) { \
313 x86_address_byte ((inst), 1, (r), (basereg)); \
314 x86_imm_emit8 ((inst), (disp)); \
316 x86_address_byte ((inst), 2, (r), (basereg)); \
317 x86_imm_emit32 ((inst), (disp)); \
321 #define x86_membase_emit(inst,r,basereg,disp) \
323 x86_membase_emit_body((inst),(r),(basereg),(disp)); \
326 #define kMaxMemindexEmitPadding 6
328 #define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift) \
330 if ((basereg) == X86_NOBASEREG) { \
331 x86_address_byte ((inst), 0, (r), 4); \
332 x86_address_byte ((inst), (shift), (indexreg), 5); \
333 x86_imm_emit32 ((inst), (disp)); \
334 } else if ((disp) == 0 && (basereg) != X86_EBP) { \
335 x86_address_byte ((inst), 0, (r), 4); \
336 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
337 } else if (x86_is_imm8((disp))) { \
338 x86_address_byte ((inst), 1, (r), 4); \
339 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
340 x86_imm_emit8 ((inst), (disp)); \
342 x86_address_byte ((inst), 2, (r), 4); \
343 x86_address_byte ((inst), (shift), (indexreg), (basereg)); \
344 x86_imm_emit32 ((inst), (disp)); \
349 * target is the position in the code where to jump to:
351 * .. output loop code...
352 * x86_mov_reg_imm (code, X86_EAX, 0);
354 * x86_loop (code, -1);
358 * x86_patch (loop, target);
360 * ins should point at the start of the instruction that encodes a target.
361 * the instruction is inspected for validity and the correct displacement
364 #define x86_do_patch(ins,target) \
366 unsigned char* pos = (ins) + 1; \
367 int disp, size = 0; \
368 switch (*(unsigned char*)(ins)) { \
369 case 0xe8: case 0xe9: ++size; break; /* call, jump32 */ \
370 case 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0); \
371 ++size; ++pos; break; /* prefix for 32-bit disp */ \
372 case 0xe0: case 0xe1: case 0xe2: /* loop */ \
373 case 0xeb: /* jump8 */ \
374 /* conditional jump opcodes */ \
375 case 0x70: case 0x71: case 0x72: case 0x73: \
376 case 0x74: case 0x75: case 0x76: case 0x77: \
377 case 0x78: case 0x79: case 0x7a: case 0x7b: \
378 case 0x7c: case 0x7d: case 0x7e: case 0x7f: \
380 default: assert (0); \
382 disp = (target) - pos; \
383 if (size) x86_imm_emit32 (pos, disp - 4); \
384 else if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1); \
388 #define x86_patch(ins,target) do { x86_do_patch((ins), (target)); } while (0)
390 #define x86_breakpoint(inst) \
395 #define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)
396 #define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)
397 #define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)
398 #define x86_stosd(inst) x86_stosl((inst))
399 #define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)
400 #define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)
401 #define x86_movsd(inst) x86_movsl((inst))
403 #define x86_prefix(inst,p) \
405 *(inst)++ =(unsigned char) (p); \
408 #define x86_mfence(inst) \
410 x86_codegen_pre(&(inst), 3); \
416 #define x86_rdtsc(inst) \
418 x86_codegen_pre(&(inst), 2); \
423 #define x86_cmpxchg_reg_reg(inst,dreg,reg) \
425 x86_codegen_pre(&(inst), 3); \
426 *(inst)++ = (unsigned char)0x0f; \
427 *(inst)++ = (unsigned char)0xb1; \
428 x86_reg_emit ((inst), (reg), (dreg)); \
431 #define x86_cmpxchg_mem_reg(inst,mem,reg) \
433 x86_codegen_pre(&(inst), 7); \
434 *(inst)++ = (unsigned char)0x0f; \
435 *(inst)++ = (unsigned char)0xb1; \
436 x86_mem_emit ((inst), (reg), (mem)); \
439 #define x86_cmpxchg_membase_reg(inst,basereg,disp,reg) \
441 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
442 *(inst)++ = (unsigned char)0x0f; \
443 *(inst)++ = (unsigned char)0xb1; \
444 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
447 #define x86_xchg_reg_reg(inst,dreg,reg,size) \
449 x86_codegen_pre(&(inst), 2); \
451 *(inst)++ = (unsigned char)0x86; \
453 *(inst)++ = (unsigned char)0x87; \
454 x86_reg_emit ((inst), (reg), (dreg)); \
457 #define x86_xchg_mem_reg(inst,mem,reg,size) \
459 x86_codegen_pre(&(inst), 6); \
461 *(inst)++ = (unsigned char)0x86; \
463 *(inst)++ = (unsigned char)0x87; \
464 x86_mem_emit ((inst), (reg), (mem)); \
467 #define x86_xchg_membase_reg(inst,basereg,disp,reg,size) \
469 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
471 *(inst)++ = (unsigned char)0x86; \
473 *(inst)++ = (unsigned char)0x87; \
474 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
477 #define x86_xadd_reg_reg(inst,dreg,reg,size) \
479 x86_codegen_pre(&(inst), 3); \
480 *(inst)++ = (unsigned char)0x0F; \
482 *(inst)++ = (unsigned char)0xC0; \
484 *(inst)++ = (unsigned char)0xC1; \
485 x86_reg_emit ((inst), (reg), (dreg)); \
488 #define x86_xadd_mem_reg(inst,mem,reg,size) \
490 x86_codegen_pre(&(inst), 7); \
491 *(inst)++ = (unsigned char)0x0F; \
493 *(inst)++ = (unsigned char)0xC0; \
495 *(inst)++ = (unsigned char)0xC1; \
496 x86_mem_emit ((inst), (reg), (mem)); \
499 #define x86_xadd_membase_reg(inst,basereg,disp,reg,size) \
501 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
502 *(inst)++ = (unsigned char)0x0F; \
504 *(inst)++ = (unsigned char)0xC0; \
506 *(inst)++ = (unsigned char)0xC1; \
507 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
510 #define x86_inc_mem(inst,mem) \
512 x86_codegen_pre(&(inst), 6); \
513 *(inst)++ = (unsigned char)0xff; \
514 x86_mem_emit ((inst), 0, (mem)); \
517 #define x86_inc_membase(inst,basereg,disp) \
519 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
520 *(inst)++ = (unsigned char)0xff; \
521 x86_membase_emit ((inst), 0, (basereg), (disp)); \
524 #define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)
526 #define x86_dec_mem(inst,mem) \
528 x86_codegen_pre(&(inst), 6); \
529 *(inst)++ = (unsigned char)0xff; \
530 x86_mem_emit ((inst), 1, (mem)); \
533 #define x86_dec_membase(inst,basereg,disp) \
535 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
536 *(inst)++ = (unsigned char)0xff; \
537 x86_membase_emit ((inst), 1, (basereg), (disp)); \
540 #define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)
542 #define x86_not_mem(inst,mem) \
544 x86_codegen_pre(&(inst), 6); \
545 *(inst)++ = (unsigned char)0xf7; \
546 x86_mem_emit ((inst), 2, (mem)); \
549 #define x86_not_membase(inst,basereg,disp) \
551 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
552 *(inst)++ = (unsigned char)0xf7; \
553 x86_membase_emit ((inst), 2, (basereg), (disp)); \
556 #define x86_not_reg(inst,reg) \
558 x86_codegen_pre(&(inst), 2); \
559 *(inst)++ = (unsigned char)0xf7; \
560 x86_reg_emit ((inst), 2, (reg)); \
563 #define x86_neg_mem(inst,mem) \
565 x86_codegen_pre(&(inst), 6); \
566 *(inst)++ = (unsigned char)0xf7; \
567 x86_mem_emit ((inst), 3, (mem)); \
570 #define x86_neg_membase(inst,basereg,disp) \
572 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
573 *(inst)++ = (unsigned char)0xf7; \
574 x86_membase_emit ((inst), 3, (basereg), (disp)); \
577 #define x86_neg_reg(inst,reg) \
579 x86_codegen_pre(&(inst), 2); \
580 *(inst)++ = (unsigned char)0xf7; \
581 x86_reg_emit ((inst), 3, (reg)); \
584 #define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)
586 #define x86_alu_reg_imm(inst,opc,reg,imm) \
588 if ((reg) == X86_EAX) { \
589 x86_codegen_pre(&(inst), 5); \
590 *(inst)++ = (((unsigned char)(opc)) << 3) + 5; \
591 x86_imm_emit32 ((inst), (imm)); \
594 if (x86_is_imm8((imm))) { \
595 x86_codegen_pre(&(inst), 3); \
596 *(inst)++ = (unsigned char)0x83; \
597 x86_reg_emit ((inst), (opc), (reg)); \
598 x86_imm_emit8 ((inst), (imm)); \
600 x86_codegen_pre(&(inst), 6); \
601 *(inst)++ = (unsigned char)0x81; \
602 x86_reg_emit ((inst), (opc), (reg)); \
603 x86_imm_emit32 ((inst), (imm)); \
607 #define x86_alu_mem_imm(inst,opc,mem,imm) \
609 if (x86_is_imm8((imm))) { \
610 x86_codegen_pre(&(inst), 7); \
611 *(inst)++ = (unsigned char)0x83; \
612 x86_mem_emit ((inst), (opc), (mem)); \
613 x86_imm_emit8 ((inst), (imm)); \
615 x86_codegen_pre(&(inst), 10); \
616 *(inst)++ = (unsigned char)0x81; \
617 x86_mem_emit ((inst), (opc), (mem)); \
618 x86_imm_emit32 ((inst), (imm)); \
622 #define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \
624 if (x86_is_imm8((imm))) { \
625 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
626 *(inst)++ = (unsigned char)0x83; \
627 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
628 x86_imm_emit8 ((inst), (imm)); \
630 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
631 *(inst)++ = (unsigned char)0x81; \
632 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
633 x86_imm_emit32 ((inst), (imm)); \
637 #define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \
639 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
640 *(inst)++ = (unsigned char)0x80; \
641 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
642 x86_imm_emit8 ((inst), (imm)); \
645 #define x86_alu_mem_reg(inst,opc,mem,reg) \
647 x86_codegen_pre(&(inst), 6); \
648 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
649 x86_mem_emit ((inst), (reg), (mem)); \
652 #define x86_alu_membase_reg(inst,opc,basereg,disp,reg) \
654 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
655 *(inst)++ = (((unsigned char)(opc)) << 3) + 1; \
656 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
659 #define x86_alu_reg_reg(inst,opc,dreg,reg) \
661 x86_codegen_pre(&(inst), 2); \
662 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
663 x86_reg_emit ((inst), (dreg), (reg)); \
667 * @x86_alu_reg8_reg8:
668 * Supports ALU operations between two 8-bit registers.
669 * dreg := dreg opc reg
670 * X86_Reg_No enum is used to specify the registers.
671 * Additionally is_*_h flags are used to specify what part
672 * of a given 32-bit register is used - high (TRUE) or low (FALSE).
673 * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH
675 #define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h) \
677 x86_codegen_pre(&(inst), 2); \
678 *(inst)++ = (((unsigned char)(opc)) << 3) + 2; \
679 x86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h)); \
682 #define x86_alu_reg_mem(inst,opc,reg,mem) \
684 x86_codegen_pre(&(inst), 6); \
685 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
686 x86_mem_emit ((inst), (reg), (mem)); \
689 #define x86_alu_reg_membase(inst,opc,reg,basereg,disp) \
691 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
692 *(inst)++ = (((unsigned char)(opc)) << 3) + 3; \
693 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
696 #define x86_test_reg_imm(inst,reg,imm) \
698 x86_codegen_pre(&(inst), 6); \
699 if ((reg) == X86_EAX) { \
700 *(inst)++ = (unsigned char)0xa9; \
702 *(inst)++ = (unsigned char)0xf7; \
703 x86_reg_emit ((inst), 0, (reg)); \
705 x86_imm_emit32 ((inst), (imm)); \
708 #define x86_test_mem_imm8(inst,mem,imm) \
710 x86_codegen_pre(&(inst), 7); \
711 *(inst)++ = (unsigned char)0xf6; \
712 x86_mem_emit ((inst), 0, (mem)); \
713 x86_imm_emit8 ((inst), (imm)); \
716 #define x86_test_mem_imm(inst,mem,imm) \
718 x86_codegen_pre(&(inst), 10); \
719 *(inst)++ = (unsigned char)0xf7; \
720 x86_mem_emit ((inst), 0, (mem)); \
721 x86_imm_emit32 ((inst), (imm)); \
724 #define x86_test_membase_imm(inst,basereg,disp,imm) \
726 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
727 *(inst)++ = (unsigned char)0xf7; \
728 x86_membase_emit ((inst), 0, (basereg), (disp)); \
729 x86_imm_emit32 ((inst), (imm)); \
732 #define x86_test_reg_reg(inst,dreg,reg) \
734 x86_codegen_pre(&(inst), 2); \
735 *(inst)++ = (unsigned char)0x85; \
736 x86_reg_emit ((inst), (reg), (dreg)); \
739 #define x86_test_mem_reg(inst,mem,reg) \
741 x86_codegen_pre(&(inst), 6); \
742 *(inst)++ = (unsigned char)0x85; \
743 x86_mem_emit ((inst), (reg), (mem)); \
746 #define x86_test_membase_reg(inst,basereg,disp,reg) \
748 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
749 *(inst)++ = (unsigned char)0x85; \
750 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
753 #define x86_shift_reg_imm(inst,opc,reg,imm) \
756 x86_codegen_pre(&(inst), 2); \
757 *(inst)++ = (unsigned char)0xd1; \
758 x86_reg_emit ((inst), (opc), (reg)); \
760 x86_codegen_pre(&(inst), 3); \
761 *(inst)++ = (unsigned char)0xc1; \
762 x86_reg_emit ((inst), (opc), (reg)); \
763 x86_imm_emit8 ((inst), (imm)); \
767 #define x86_shift_mem_imm(inst,opc,mem,imm) \
770 x86_codegen_pre(&(inst), 6); \
771 *(inst)++ = (unsigned char)0xd1; \
772 x86_mem_emit ((inst), (opc), (mem)); \
774 x86_codegen_pre(&(inst), 7); \
775 *(inst)++ = (unsigned char)0xc1; \
776 x86_mem_emit ((inst), (opc), (mem)); \
777 x86_imm_emit8 ((inst), (imm)); \
781 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm) \
784 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
785 *(inst)++ = (unsigned char)0xd1; \
786 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
788 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
789 *(inst)++ = (unsigned char)0xc1; \
790 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
791 x86_imm_emit8 ((inst), (imm)); \
795 #define x86_shift_reg(inst,opc,reg) \
797 x86_codegen_pre(&(inst), 2); \
798 *(inst)++ = (unsigned char)0xd3; \
799 x86_reg_emit ((inst), (opc), (reg)); \
802 #define x86_shift_mem(inst,opc,mem) \
804 x86_codegen_pre(&(inst), 6); \
805 *(inst)++ = (unsigned char)0xd3; \
806 x86_mem_emit ((inst), (opc), (mem)); \
809 #define x86_shift_membase(inst,opc,basereg,disp) \
811 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
812 *(inst)++ = (unsigned char)0xd3; \
813 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
817 * Multi op shift missing.
820 #define x86_shrd_reg(inst,dreg,reg) \
822 x86_codegen_pre(&(inst), 3); \
823 *(inst)++ = (unsigned char)0x0f; \
824 *(inst)++ = (unsigned char)0xad; \
825 x86_reg_emit ((inst), (reg), (dreg)); \
828 #define x86_shrd_reg_imm(inst,dreg,reg,shamt) \
830 x86_codegen_pre(&(inst), 4); \
831 *(inst)++ = (unsigned char)0x0f; \
832 *(inst)++ = (unsigned char)0xac; \
833 x86_reg_emit ((inst), (reg), (dreg)); \
834 x86_imm_emit8 ((inst), (shamt)); \
837 #define x86_shld_reg(inst,dreg,reg) \
839 x86_codegen_pre(&(inst), 3); \
840 *(inst)++ = (unsigned char)0x0f; \
841 *(inst)++ = (unsigned char)0xa5; \
842 x86_reg_emit ((inst), (reg), (dreg)); \
845 #define x86_shld_reg_imm(inst,dreg,reg,shamt) \
847 x86_codegen_pre(&(inst), 4); \
848 *(inst)++ = (unsigned char)0x0f; \
849 *(inst)++ = (unsigned char)0xa4; \
850 x86_reg_emit ((inst), (reg), (dreg)); \
851 x86_imm_emit8 ((inst), (shamt)); \
857 #define x86_mul_reg(inst,reg,is_signed) \
859 x86_codegen_pre(&(inst), 2); \
860 *(inst)++ = (unsigned char)0xf7; \
861 x86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg)); \
864 #define x86_mul_mem(inst,mem,is_signed) \
866 x86_codegen_pre(&(inst), 6); \
867 *(inst)++ = (unsigned char)0xf7; \
868 x86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem)); \
871 #define x86_mul_membase(inst,basereg,disp,is_signed) \
873 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
874 *(inst)++ = (unsigned char)0xf7; \
875 x86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
881 #define x86_imul_reg_reg(inst,dreg,reg) \
883 x86_codegen_pre(&(inst), 3); \
884 *(inst)++ = (unsigned char)0x0f; \
885 *(inst)++ = (unsigned char)0xaf; \
886 x86_reg_emit ((inst), (dreg), (reg)); \
889 #define x86_imul_reg_mem(inst,reg,mem) \
891 x86_codegen_pre(&(inst), 7); \
892 *(inst)++ = (unsigned char)0x0f; \
893 *(inst)++ = (unsigned char)0xaf; \
894 x86_mem_emit ((inst), (reg), (mem)); \
897 #define x86_imul_reg_membase(inst,reg,basereg,disp) \
899 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
900 *(inst)++ = (unsigned char)0x0f; \
901 *(inst)++ = (unsigned char)0xaf; \
902 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
908 #define x86_imul_reg_reg_imm(inst,dreg,reg,imm) \
910 if (x86_is_imm8 ((imm))) { \
911 x86_codegen_pre(&(inst), 3); \
912 *(inst)++ = (unsigned char)0x6b; \
913 x86_reg_emit ((inst), (dreg), (reg)); \
914 x86_imm_emit8 ((inst), (imm)); \
916 x86_codegen_pre(&(inst), 6); \
917 *(inst)++ = (unsigned char)0x69; \
918 x86_reg_emit ((inst), (dreg), (reg)); \
919 x86_imm_emit32 ((inst), (imm)); \
923 #define x86_imul_reg_mem_imm(inst,reg,mem,imm) \
925 if (x86_is_imm8 ((imm))) { \
926 x86_codegen_pre(&(inst), 7); \
927 *(inst)++ = (unsigned char)0x6b; \
928 x86_mem_emit ((inst), (reg), (mem)); \
929 x86_imm_emit8 ((inst), (imm)); \
931 x86_codegen_pre(&(inst), 6); \
932 *(inst)++ = (unsigned char)0x69; \
933 x86_mem_emit ((inst), (reg), (mem)); \
934 x86_imm_emit32 ((inst), (imm)); \
938 #define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm) \
940 if (x86_is_imm8 ((imm))) { \
941 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
942 *(inst)++ = (unsigned char)0x6b; \
943 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
944 x86_imm_emit8 ((inst), (imm)); \
946 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
947 *(inst)++ = (unsigned char)0x69; \
948 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
949 x86_imm_emit32 ((inst), (imm)); \
954 * divide EDX:EAX by rm;
955 * eax = quotient, edx = remainder
958 #define x86_div_reg(inst,reg,is_signed) \
960 x86_codegen_pre(&(inst), 2); \
961 *(inst)++ = (unsigned char)0xf7; \
962 x86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg)); \
965 #define x86_div_mem(inst,mem,is_signed) \
967 x86_codegen_pre(&(inst), 6); \
968 *(inst)++ = (unsigned char)0xf7; \
969 x86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem)); \
972 #define x86_div_membase(inst,basereg,disp,is_signed) \
974 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
975 *(inst)++ = (unsigned char)0xf7; \
976 x86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp)); \
979 #define x86_mov_mem_reg(inst,mem,reg,size) \
981 x86_codegen_pre(&(inst), 7); \
983 case 1: *(inst)++ = (unsigned char)0x88; break; \
984 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
985 case 4: *(inst)++ = (unsigned char)0x89; break; \
986 default: assert (0); \
988 x86_mem_emit ((inst), (reg), (mem)); \
991 #define x86_mov_regp_reg(inst,regp,reg,size) \
993 x86_codegen_pre(&(inst), 3); \
995 case 1: *(inst)++ = (unsigned char)0x88; break; \
996 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
997 case 4: *(inst)++ = (unsigned char)0x89; break; \
998 default: assert (0); \
1000 x86_regp_emit ((inst), (reg), (regp)); \
1003 #define x86_mov_membase_reg(inst,basereg,disp,reg,size) \
1005 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1007 case 1: *(inst)++ = (unsigned char)0x88; break; \
1008 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1009 case 4: *(inst)++ = (unsigned char)0x89; break; \
1010 default: assert (0); \
1012 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1015 #define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size) \
1017 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1019 case 1: *(inst)++ = (unsigned char)0x88; break; \
1020 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1021 case 4: *(inst)++ = (unsigned char)0x89; break; \
1022 default: assert (0); \
1024 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1027 #define x86_mov_reg_reg(inst,dreg,reg,size) \
1029 x86_codegen_pre(&(inst), 3); \
1031 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1032 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1033 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1034 default: assert (0); \
1036 x86_reg_emit ((inst), (dreg), (reg)); \
1039 #define x86_mov_reg_mem(inst,reg,mem,size) \
1041 x86_codegen_pre(&(inst), 7); \
1043 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1044 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1045 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1046 default: assert (0); \
1048 x86_mem_emit ((inst), (reg), (mem)); \
1051 #define kMovRegMembasePadding (2 + kMaxMembaseEmitPadding)
1053 #define x86_mov_reg_membase(inst,reg,basereg,disp,size) \
1055 x86_codegen_pre(&(inst), kMovRegMembasePadding); \
1057 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1058 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1059 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1060 default: assert (0); \
1062 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1065 #define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size) \
1067 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1069 case 1: *(inst)++ = (unsigned char)0x8a; break; \
1070 case 2: x86_prefix((inst), X86_OPERAND_PREFIX); /* fall through */ \
1071 case 4: *(inst)++ = (unsigned char)0x8b; break; \
1072 default: assert (0); \
1074 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1078 * Note: x86_clear_reg () chacnges the condition code!
1080 #define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))
1082 #define x86_mov_reg_imm(inst,reg,imm) \
1084 x86_codegen_pre(&(inst), 5); \
1085 *(inst)++ = (unsigned char)0xb8 + (reg); \
1086 x86_imm_emit32 ((inst), (imm)); \
1089 #define x86_mov_mem_imm(inst,mem,imm,size) \
1091 if ((size) == 1) { \
1092 x86_codegen_pre(&(inst), 7); \
1093 *(inst)++ = (unsigned char)0xc6; \
1094 x86_mem_emit ((inst), 0, (mem)); \
1095 x86_imm_emit8 ((inst), (imm)); \
1096 } else if ((size) == 2) { \
1097 x86_codegen_pre(&(inst), 9); \
1098 x86_prefix((inst), X86_OPERAND_PREFIX); \
1099 *(inst)++ = (unsigned char)0xc7; \
1100 x86_mem_emit ((inst), 0, (mem)); \
1101 x86_imm_emit16 ((inst), (imm)); \
1103 x86_codegen_pre(&(inst), 10); \
1104 *(inst)++ = (unsigned char)0xc7; \
1105 x86_mem_emit ((inst), 0, (mem)); \
1106 x86_imm_emit32 ((inst), (imm)); \
1110 #define x86_mov_membase_imm(inst,basereg,disp,imm,size) \
1112 if ((size) == 1) { \
1113 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1114 *(inst)++ = (unsigned char)0xc6; \
1115 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1116 x86_imm_emit8 ((inst), (imm)); \
1117 } else if ((size) == 2) { \
1118 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
1119 x86_prefix((inst), X86_OPERAND_PREFIX); \
1120 *(inst)++ = (unsigned char)0xc7; \
1121 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1122 x86_imm_emit16 ((inst), (imm)); \
1124 x86_codegen_pre(&(inst), 5 + kMaxMembaseEmitPadding); \
1125 *(inst)++ = (unsigned char)0xc7; \
1126 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1127 x86_imm_emit32 ((inst), (imm)); \
1131 #define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size) \
1133 if ((size) == 1) { \
1134 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1135 *(inst)++ = (unsigned char)0xc6; \
1136 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1137 x86_imm_emit8 ((inst), (imm)); \
1138 } else if ((size) == 2) { \
1139 x86_codegen_pre(&(inst), 4 + kMaxMemindexEmitPadding); \
1140 x86_prefix((inst), X86_OPERAND_PREFIX); \
1141 *(inst)++ = (unsigned char)0xc7; \
1142 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1143 x86_imm_emit16 ((inst), (imm)); \
1145 x86_codegen_pre(&(inst), 5 + kMaxMemindexEmitPadding); \
1146 *(inst)++ = (unsigned char)0xc7; \
1147 x86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift)); \
1148 x86_imm_emit32 ((inst), (imm)); \
1152 #define x86_lea_mem(inst,reg,mem) \
1154 x86_codegen_pre(&(inst), 5); \
1155 *(inst)++ = (unsigned char)0x8d; \
1156 x86_mem_emit ((inst), (reg), (mem)); \
1159 #define x86_lea_membase(inst,reg,basereg,disp) \
1161 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1162 *(inst)++ = (unsigned char)0x8d; \
1163 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1166 #define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift) \
1168 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1169 *(inst)++ = (unsigned char)0x8d; \
1170 x86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift)); \
1173 #define x86_widen_reg(inst,dreg,reg,is_signed,is_half) \
1175 unsigned char op = 0xb6; \
1176 g_assert (is_half || X86_IS_BYTE_REG (reg)); \
1177 x86_codegen_pre(&(inst), 3); \
1178 *(inst)++ = (unsigned char)0x0f; \
1179 if ((is_signed)) op += 0x08; \
1180 if ((is_half)) op += 0x01; \
1182 x86_reg_emit ((inst), (dreg), (reg)); \
1185 #define x86_widen_mem(inst,dreg,mem,is_signed,is_half) \
1187 unsigned char op = 0xb6; \
1188 x86_codegen_pre(&(inst), 7); \
1189 *(inst)++ = (unsigned char)0x0f; \
1190 if ((is_signed)) op += 0x08; \
1191 if ((is_half)) op += 0x01; \
1193 x86_mem_emit ((inst), (dreg), (mem)); \
1196 #define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half) \
1198 unsigned char op = 0xb6; \
1199 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1200 *(inst)++ = (unsigned char)0x0f; \
1201 if ((is_signed)) op += 0x08; \
1202 if ((is_half)) op += 0x01; \
1204 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
1207 #define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half) \
1209 unsigned char op = 0xb6; \
1210 x86_codegen_pre(&(inst), 2 + kMaxMemindexEmitPadding); \
1211 *(inst)++ = (unsigned char)0x0f; \
1212 if ((is_signed)) op += 0x08; \
1213 if ((is_half)) op += 0x01; \
1215 x86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift)); \
1218 #define x86_cdq(inst) do { *(inst)++ = (unsigned char)0x99; } while (0)
1219 #define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)
1221 #define x86_fp_op_mem(inst,opc,mem,is_double) \
1223 x86_codegen_pre(&(inst), 6); \
1224 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1225 x86_mem_emit ((inst), (opc), (mem)); \
1228 #define x86_fp_op_membase(inst,opc,basereg,disp,is_double) \
1230 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1231 *(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8; \
1232 x86_membase_emit ((inst), (opc), (basereg), (disp)); \
1235 #define x86_fp_op(inst,opc,index) \
1237 x86_codegen_pre(&(inst), 2); \
1238 *(inst)++ = (unsigned char)0xd8; \
1239 *(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07); \
1242 #define x86_fp_op_reg(inst,opc,index,pop_stack) \
1244 static const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8}; \
1245 x86_codegen_pre(&(inst), 2); \
1246 *(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc; \
1247 *(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07); \
1251 * @x86_fp_int_op_membase
1252 * Supports FPU operations between ST(0) and integer operand in memory.
1253 * Operation encoded using X86_FP_Opcode enum.
1254 * Operand is addressed by [basereg + disp].
1255 * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).
1257 #define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int) \
1259 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1260 *(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde; \
1261 x86_membase_emit ((inst), opc, (basereg), (disp)); \
1264 #define x86_fstp(inst,index) \
1266 x86_codegen_pre(&(inst), 2); \
1267 *(inst)++ = (unsigned char)0xdd; \
1268 *(inst)++ = (unsigned char)0xd8+(index); \
1271 #define x86_fcompp(inst) \
1273 x86_codegen_pre(&(inst), 2); \
1274 *(inst)++ = (unsigned char)0xde; \
1275 *(inst)++ = (unsigned char)0xd9; \
1278 #define x86_fucompp(inst) \
1280 x86_codegen_pre(&(inst), 2); \
1281 *(inst)++ = (unsigned char)0xda; \
1282 *(inst)++ = (unsigned char)0xe9; \
1285 #define x86_fnstsw(inst) \
1287 x86_codegen_pre(&(inst), 2); \
1288 *(inst)++ = (unsigned char)0xdf; \
1289 *(inst)++ = (unsigned char)0xe0; \
1292 #define x86_fnstcw(inst,mem) \
1294 x86_codegen_pre(&(inst), 6); \
1295 *(inst)++ = (unsigned char)0xd9; \
1296 x86_mem_emit ((inst), 7, (mem)); \
1299 #define x86_fnstcw_membase(inst,basereg,disp) \
1301 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1302 *(inst)++ = (unsigned char)0xd9; \
1303 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1306 #define x86_fldcw(inst,mem) \
1308 x86_codegen_pre(&(inst), 6); \
1309 *(inst)++ = (unsigned char)0xd9; \
1310 x86_mem_emit ((inst), 5, (mem)); \
1313 #define x86_fldcw_membase(inst,basereg,disp) \
1315 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1316 *(inst)++ = (unsigned char)0xd9; \
1317 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1320 #define x86_fchs(inst) \
1322 x86_codegen_pre(&(inst), 2); \
1323 *(inst)++ = (unsigned char)0xd9; \
1324 *(inst)++ = (unsigned char)0xe0; \
1327 #define x86_frem(inst) \
1329 x86_codegen_pre(&(inst), 2); \
1330 *(inst)++ = (unsigned char)0xd9; \
1331 *(inst)++ = (unsigned char)0xf8; \
1334 #define x86_fxch(inst,index) \
1336 x86_codegen_pre(&(inst), 2); \
1337 *(inst)++ = (unsigned char)0xd9; \
1338 *(inst)++ = (unsigned char)0xc8 + ((index) & 0x07); \
1341 #define x86_fcomi(inst,index) \
1343 x86_codegen_pre(&(inst), 2); \
1344 *(inst)++ = (unsigned char)0xdb; \
1345 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1348 #define x86_fcomip(inst,index) \
1350 x86_codegen_pre(&(inst), 2); \
1351 *(inst)++ = (unsigned char)0xdf; \
1352 *(inst)++ = (unsigned char)0xf0 + ((index) & 0x07); \
1355 #define x86_fucomi(inst,index) \
1357 x86_codegen_pre(&(inst), 2); \
1358 *(inst)++ = (unsigned char)0xdb; \
1359 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1362 #define x86_fucomip(inst,index) \
1364 x86_codegen_pre(&(inst), 2); \
1365 *(inst)++ = (unsigned char)0xdf; \
1366 *(inst)++ = (unsigned char)0xe8 + ((index) & 0x07); \
1369 #define x86_fld(inst,mem,is_double) \
1371 x86_codegen_pre(&(inst), 6); \
1372 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1373 x86_mem_emit ((inst), 0, (mem)); \
1376 #define x86_fld_membase(inst,basereg,disp,is_double) \
1378 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1379 *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9; \
1380 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1383 #define x86_fld80_mem(inst,mem) \
1385 x86_codegen_pre(&(inst), 6); \
1386 *(inst)++ = (unsigned char)0xdb; \
1387 x86_mem_emit ((inst), 5, (mem)); \
1390 #define x86_fld80_membase(inst,basereg,disp) \
1392 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1393 *(inst)++ = (unsigned char)0xdb; \
1394 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1397 #define x86_fild(inst,mem,is_long) \
1399 x86_codegen_pre(&(inst), 6); \
1401 *(inst)++ = (unsigned char)0xdf; \
1402 x86_mem_emit ((inst), 5, (mem)); \
1404 *(inst)++ = (unsigned char)0xdb; \
1405 x86_mem_emit ((inst), 0, (mem)); \
1409 #define x86_fild_membase(inst,basereg,disp,is_long) \
1411 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1413 *(inst)++ = (unsigned char)0xdf; \
1414 x86_membase_emit ((inst), 5, (basereg), (disp)); \
1416 *(inst)++ = (unsigned char)0xdb; \
1417 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1421 #define x86_fld_reg(inst,index) \
1423 x86_codegen_pre(&(inst), 2); \
1424 *(inst)++ = (unsigned char)0xd9; \
1425 *(inst)++ = (unsigned char)0xc0 + ((index) & 0x07); \
1428 #define x86_fldz(inst) \
1430 x86_codegen_pre(&(inst), 2); \
1431 *(inst)++ = (unsigned char)0xd9; \
1432 *(inst)++ = (unsigned char)0xee; \
1435 #define x86_fld1(inst) \
1437 x86_codegen_pre(&(inst), 2); \
1438 *(inst)++ = (unsigned char)0xd9; \
1439 *(inst)++ = (unsigned char)0xe8; \
1442 #define x86_fldpi(inst) \
1444 x86_codegen_pre(&(inst), 2); \
1445 *(inst)++ = (unsigned char)0xd9; \
1446 *(inst)++ = (unsigned char)0xeb; \
1449 #define x86_fst(inst,mem,is_double,pop_stack) \
1451 x86_codegen_pre(&(inst), 6); \
1452 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1453 x86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem)); \
1456 #define x86_fst_membase(inst,basereg,disp,is_double,pop_stack) \
1458 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1459 *(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9; \
1460 x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp)); \
1463 #define x86_fst80_mem(inst,mem) \
1465 x86_codegen_pre(&(inst), 6); \
1466 *(inst)++ = (unsigned char)0xdb; \
1467 x86_mem_emit ((inst), 7, (mem)); \
1471 #define x86_fst80_membase(inst,basereg,disp) \
1473 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1474 *(inst)++ = (unsigned char)0xdb; \
1475 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1479 #define x86_fist_pop(inst,mem,is_long) \
1481 x86_codegen_pre(&(inst), 6); \
1483 *(inst)++ = (unsigned char)0xdf; \
1484 x86_mem_emit ((inst), 7, (mem)); \
1486 *(inst)++ = (unsigned char)0xdb; \
1487 x86_mem_emit ((inst), 3, (mem)); \
1491 #define x86_fist_pop_membase(inst,basereg,disp,is_long) \
1493 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1495 *(inst)++ = (unsigned char)0xdf; \
1496 x86_membase_emit ((inst), 7, (basereg), (disp)); \
1498 *(inst)++ = (unsigned char)0xdb; \
1499 x86_membase_emit ((inst), 3, (basereg), (disp)); \
1503 #define x86_fstsw(inst) \
1505 x86_codegen_pre(&(inst), 3); \
1506 *(inst)++ = (unsigned char)0x9b; \
1507 *(inst)++ = (unsigned char)0xdf; \
1508 *(inst)++ = (unsigned char)0xe0; \
1513 * Converts content of ST(0) to integer and stores it at memory location
1514 * addressed by [basereg + disp].
1515 * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).
1517 #define x86_fist_membase(inst,basereg,disp,is_int) \
1519 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1521 *(inst)++ = (unsigned char)0xdb; \
1522 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1524 *(inst)++ = (unsigned char)0xdf; \
1525 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1530 #define x86_push_reg(inst,reg) \
1532 *(inst)++ = (unsigned char)0x50 + (reg); \
1535 #define x86_push_regp(inst,reg) \
1537 x86_codegen_pre(&(inst), 2); \
1538 *(inst)++ = (unsigned char)0xff; \
1539 x86_regp_emit ((inst), 6, (reg)); \
1542 #define x86_push_mem(inst,mem) \
1544 x86_codegen_pre(&(inst), 6); \
1545 *(inst)++ = (unsigned char)0xff; \
1546 x86_mem_emit ((inst), 6, (mem)); \
1549 #define x86_push_membase(inst,basereg,disp) \
1551 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1552 *(inst)++ = (unsigned char)0xff; \
1553 x86_membase_emit ((inst), 6, (basereg), (disp)); \
1556 #define x86_push_memindex(inst,basereg,disp,indexreg,shift) \
1558 x86_codegen_pre(&(inst), 1 + kMaxMemindexEmitPadding); \
1559 *(inst)++ = (unsigned char)0xff; \
1560 x86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift)); \
1563 #define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)
1565 #define x86_push_imm(inst,imm) \
1567 int _imm = (int) (imm); \
1568 if (x86_is_imm8 (_imm)) { \
1569 x86_codegen_pre(&(inst), 2); \
1570 *(inst)++ = (unsigned char)0x6A; \
1571 x86_imm_emit8 ((inst), (_imm)); \
1573 x86_codegen_pre(&(inst), 5); \
1574 *(inst)++ = (unsigned char)0x68; \
1575 x86_imm_emit32 ((inst), (_imm)); \
1579 #define x86_pop_reg(inst,reg) \
1581 *(inst)++ = (unsigned char)0x58 + (reg); \
1584 #define x86_pop_mem(inst,mem) \
1586 x86_codegen_pre(&(inst), 6); \
1587 *(inst)++ = (unsigned char)0x87; \
1588 x86_mem_emit ((inst), 0, (mem)); \
1591 #define x86_pop_membase(inst,basereg,disp) \
1593 x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
1594 *(inst)++ = (unsigned char)0x87; \
1595 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1598 #define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)
1599 #define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)
1600 #define x86_popad(inst) do { *(inst)++ = (unsigned char)0x61; } while (0)
1601 #define x86_popfd(inst) do { *(inst)++ = (unsigned char)0x9d; } while (0)
1603 #define x86_loop(inst,imm) \
1605 x86_codegen_pre(&(inst), 2); \
1606 *(inst)++ = (unsigned char)0xe2; \
1607 x86_imm_emit8 ((inst), (imm)); \
1610 #define x86_loope(inst,imm) \
1612 x86_codegen_pre(&(inst), 2); \
1613 *(inst)++ = (unsigned char)0xe1; \
1614 x86_imm_emit8 ((inst), (imm)); \
1617 #define x86_loopne(inst,imm) \
1619 x86_codegen_pre(&(inst), 2); \
1620 *(inst)++ = (unsigned char)0xe0; \
1621 x86_imm_emit8 ((inst), (imm)); \
1624 #if defined(TARGET_X86)
1625 #define x86_jump32(inst,imm) \
1627 x86_codegen_pre(&(inst), 5); \
1628 *(inst)++ = (unsigned char)0xe9; \
1629 x86_imm_emit32 ((inst), (imm)); \
1632 #define x86_jump8(inst,imm) \
1634 x86_codegen_pre(&(inst), 2); \
1635 *(inst)++ = (unsigned char)0xeb; \
1636 x86_imm_emit8 ((inst), (imm)); \
1638 #elif defined(TARGET_AMD64)
1639 /* These macros are used directly from mini-amd64.c and other */
1640 /* amd64 specific files, so they need to be instrumented directly. */
1641 #define x86_jump32(inst,imm) \
1643 amd64_codegen_pre(inst); \
1644 *(inst)++ = (unsigned char)0xe9; \
1645 x86_imm_emit32 ((inst), (imm)); \
1646 amd64_codegen_post(inst); \
1649 #define x86_jump8(inst,imm) \
1651 amd64_codegen_pre(inst); \
1652 *(inst)++ = (unsigned char)0xeb; \
1653 x86_imm_emit8 ((inst), (imm)); \
1654 amd64_codegen_post(inst); \
1658 #define x86_jump_reg(inst,reg) \
1660 *(inst)++ = (unsigned char)0xff; \
1661 x86_reg_emit ((inst), 4, (reg)); \
1664 #define x86_jump_mem(inst,mem) \
1666 *(inst)++ = (unsigned char)0xff; \
1667 x86_mem_emit ((inst), 4, (mem)); \
1670 #define x86_jump_membase(inst,basereg,disp) \
1672 *(inst)++ = (unsigned char)0xff; \
1673 x86_membase_emit ((inst), 4, (basereg), (disp)); \
1676 * target is a pointer in our buffer.
1678 #define x86_jump_code_body(inst,target) \
1681 x86_codegen_pre(&(inst), 2); \
1682 t = (unsigned char*)(target) - (inst) - 2; \
1683 if (x86_is_imm8(t)) { \
1684 x86_jump8 ((inst), t); \
1686 x86_codegen_pre(&(inst), 5); \
1687 t = (unsigned char*)(target) - (inst) - 5; \
1688 x86_jump32 ((inst), t); \
1692 #define x86_jump_code(inst,target) \
1694 x86_jump_code_body((inst),(target)); \
1697 #define x86_jump_disp(inst,disp) \
1699 int t = (disp) - 2; \
1700 if (x86_is_imm8(t)) { \
1701 x86_jump8 ((inst), t); \
1704 x86_jump32 ((inst), t); \
1708 #if defined(TARGET_X86)
1709 #define x86_branch8(inst,cond,imm,is_signed) \
1711 x86_codegen_pre(&(inst), 2); \
1713 *(inst)++ = x86_cc_signed_map [(cond)]; \
1715 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1716 x86_imm_emit8 ((inst), (imm)); \
1719 #define x86_branch32(inst,cond,imm,is_signed) \
1721 x86_codegen_pre(&(inst), 6); \
1722 *(inst)++ = (unsigned char)0x0f; \
1724 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1726 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1727 x86_imm_emit32 ((inst), (imm)); \
1729 #elif defined(TARGET_AMD64)
1730 /* These macros are used directly from mini-amd64.c and other */
1731 /* amd64 specific files, so they need to be instrumented directly. */
1732 #define x86_branch8(inst,cond,imm,is_signed) \
1734 amd64_codegen_pre(inst); \
1736 *(inst)++ = x86_cc_signed_map [(cond)]; \
1738 *(inst)++ = x86_cc_unsigned_map [(cond)]; \
1739 x86_imm_emit8 ((inst), (imm)); \
1740 amd64_codegen_post(inst); \
1742 #define x86_branch32(inst,cond,imm,is_signed) \
1744 amd64_codegen_pre(inst); \
1745 *(inst)++ = (unsigned char)0x0f; \
1747 *(inst)++ = x86_cc_signed_map [(cond)] + 0x10; \
1749 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10; \
1750 x86_imm_emit32 ((inst), (imm)); \
1751 amd64_codegen_post(inst); \
1755 #if defined(TARGET_X86)
1756 #define x86_branch(inst,cond,target,is_signed) \
1759 guint8* branch_start; \
1760 x86_codegen_pre(&(inst), 2); \
1761 offset = (target) - (inst) - 2; \
1762 branch_start = (inst); \
1763 if (x86_is_imm8 ((offset))) \
1764 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1766 x86_codegen_pre(&(inst), 6); \
1767 offset = (target) - (inst) - 6; \
1768 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1770 x86_patch(branch_start, (target)); \
1772 #elif defined(TARGET_AMD64)
1773 /* This macro is used directly from mini-amd64.c and other */
1774 /* amd64 specific files, so it needs to be instrumented directly. */
1776 #define x86_branch_body(inst,cond,target,is_signed) \
1778 int offset = (target) - (inst) - 2; \
1779 if (x86_is_imm8 ((offset))) \
1780 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1782 offset = (target) - (inst) - 6; \
1783 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1787 #define x86_branch(inst,cond,target,is_signed) \
1789 x86_branch_body((inst),(cond),(target),(is_signed)); \
1792 #endif /* TARGET_AMD64 */
1794 #define x86_branch_disp(inst,cond,disp,is_signed) \
1796 int offset = (disp) - 2; \
1797 if (x86_is_imm8 ((offset))) \
1798 x86_branch8 ((inst), (cond), offset, (is_signed)); \
1801 x86_branch32 ((inst), (cond), offset, (is_signed)); \
1805 #define x86_set_reg(inst,cond,reg,is_signed) \
1807 g_assert (X86_IS_BYTE_REG (reg)); \
1808 x86_codegen_pre(&(inst), 3); \
1809 *(inst)++ = (unsigned char)0x0f; \
1811 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1813 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1814 x86_reg_emit ((inst), 0, (reg)); \
1817 #define x86_set_mem(inst,cond,mem,is_signed) \
1819 x86_codegen_pre(&(inst), 7); \
1820 *(inst)++ = (unsigned char)0x0f; \
1822 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1824 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1825 x86_mem_emit ((inst), 0, (mem)); \
1828 #define x86_set_membase(inst,cond,basereg,disp,is_signed) \
1830 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1831 *(inst)++ = (unsigned char)0x0f; \
1833 *(inst)++ = x86_cc_signed_map [(cond)] + 0x20; \
1835 *(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20; \
1836 x86_membase_emit ((inst), 0, (basereg), (disp)); \
1839 #define x86_call_imm_body(inst,disp) \
1841 *(inst)++ = (unsigned char)0xe8; \
1842 x86_imm_emit32 ((inst), (int)(disp)); \
1845 #define x86_call_imm(inst,disp) \
1847 x86_call_sequence_pre((inst)); \
1848 x86_call_imm_body((inst), (disp)); \
1849 x86_call_sequence_post((inst)); \
1853 #define x86_call_reg(inst,reg) \
1855 *(inst)++ = (unsigned char)0xff; \
1856 x86_reg_emit ((inst), 2, (reg)); \
1859 #define x86_call_mem(inst,mem) \
1861 *(inst)++ = (unsigned char)0xff; \
1862 x86_mem_emit ((inst), 2, (mem)); \
1865 #define x86_call_membase(inst,basereg,disp) \
1867 *(inst)++ = (unsigned char)0xff; \
1868 x86_membase_emit ((inst), 2, (basereg), (disp)); \
1871 #define x86_call_code(inst,target) \
1874 _x86_offset = (unsigned char*)(target) - (inst); \
1876 x86_call_imm_body ((inst), _x86_offset); \
1879 #define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)
1881 #define x86_ret_imm(inst,imm) \
1886 x86_codegen_pre(&(inst), 3); \
1887 *(inst)++ = (unsigned char)0xc2; \
1888 x86_imm_emit16 ((inst), (imm)); \
1892 #define x86_cmov_reg(inst,cond,is_signed,dreg,reg) \
1894 x86_codegen_pre(&(inst), 3); \
1895 *(inst)++ = (unsigned char) 0x0f; \
1897 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1899 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1900 x86_reg_emit ((inst), (dreg), (reg)); \
1903 #define x86_cmov_mem(inst,cond,is_signed,reg,mem) \
1905 x86_codegen_pre(&(inst), 7); \
1906 *(inst)++ = (unsigned char) 0x0f; \
1908 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1910 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1911 x86_mem_emit ((inst), (reg), (mem)); \
1914 #define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp) \
1916 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
1917 *(inst)++ = (unsigned char) 0x0f; \
1919 *(inst)++ = x86_cc_signed_map [(cond)] - 0x30; \
1921 *(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30; \
1922 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
1925 #define x86_enter(inst,framesize) \
1927 x86_codegen_pre(&(inst), 4); \
1928 *(inst)++ = (unsigned char)0xc8; \
1929 x86_imm_emit16 ((inst), (framesize)); \
1933 #define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)
1934 #define x86_sahf(inst) do { *(inst)++ = (unsigned char)0x9e; } while (0)
1936 #define x86_fsin(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)
1937 #define x86_fcos(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)
1938 #define x86_fabs(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)
1939 #define x86_ftst(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)
1940 #define x86_fxam(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)
1941 #define x86_fpatan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)
1942 #define x86_fprem(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)
1943 #define x86_fprem1(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)
1944 #define x86_frndint(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)
1945 #define x86_fsqrt(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)
1946 #define x86_fptan(inst) do { x86_codegen_pre(&(inst), 2); *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)
1948 #define x86_padding(inst,size) \
1951 case 1: x86_nop ((inst)); break; \
1952 case 2: *(inst)++ = 0x8b; \
1953 *(inst)++ = 0xc0; break; \
1954 case 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d; \
1955 *(inst)++ = 0x00; break; \
1956 case 4: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1957 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1959 case 5: *(inst)++ = 0x8d; *(inst)++ = 0x64; \
1960 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1961 x86_nop ((inst)); break; \
1962 case 6: *(inst)++ = 0x8d; *(inst)++ = 0xad; \
1963 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1964 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1966 case 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4; \
1967 *(inst)++ = 0x24; *(inst)++ = 0x00; \
1968 *(inst)++ = 0x00; *(inst)++ = 0x00; \
1969 *(inst)++ = 0x00; break; \
1970 default: assert (0); \
1974 #define x86_prolog(inst,frame_size,reg_mask) \
1976 unsigned i, m = 1; \
1977 x86_enter ((inst), (frame_size)); \
1978 for (i = 0; i < X86_NREG; ++i, m <<= 1) { \
1979 if ((reg_mask) & m) \
1980 x86_push_reg ((inst), i); \
1984 #define x86_epilog(inst,reg_mask) \
1986 unsigned i, m = 1 << X86_EDI; \
1987 for (i = X86_EDI; m != 0; i--, m=m>>1) { \
1988 if ((reg_mask) & m) \
1989 x86_pop_reg ((inst), i); \
1991 x86_leave ((inst)); \
1997 X86_SSE_SQRT = 0x51,
1998 X86_SSE_RSQRT = 0x52,
2006 X86_SSE_COMP = 0xC2,
2008 X86_SSE_ANDN = 0x55,
2011 X86_SSE_UNPCKL = 0x14,
2012 X86_SSE_UNPCKH = 0x15,
2014 X86_SSE_ADDSUB = 0xD0,
2015 X86_SSE_HADD = 0x7C,
2016 X86_SSE_HSUB = 0x7D,
2017 X86_SSE_MOVSHDUP = 0x16,
2018 X86_SSE_MOVSLDUP = 0x12,
2019 X86_SSE_MOVDDUP = 0x12,
2021 X86_SSE_PAND = 0xDB,
2023 X86_SSE_PXOR = 0xEF,
2025 X86_SSE_PADDB = 0xFC,
2026 X86_SSE_PADDW = 0xFD,
2027 X86_SSE_PADDD = 0xFE,
2028 X86_SSE_PADDQ = 0xD4,
2030 X86_SSE_PSUBB = 0xF8,
2031 X86_SSE_PSUBW = 0xF9,
2032 X86_SSE_PSUBD = 0xFA,
2033 X86_SSE_PSUBQ = 0xFB,
2035 X86_SSE_PMAXSB = 0x3C, /*sse41*/
2036 X86_SSE_PMAXSW = 0xEE,
2037 X86_SSE_PMAXSD = 0x3D, /*sse41*/
2039 X86_SSE_PMAXUB = 0xDE,
2040 X86_SSE_PMAXUW = 0x3E, /*sse41*/
2041 X86_SSE_PMAXUD = 0x3F, /*sse41*/
2043 X86_SSE_PMINSB = 0x38, /*sse41*/
2044 X86_SSE_PMINSW = 0xEA,
2045 X86_SSE_PMINSD = 0x39,/*sse41*/
2047 X86_SSE_PMINUB = 0xDA,
2048 X86_SSE_PMINUW = 0x3A, /*sse41*/
2049 X86_SSE_PMINUD = 0x3B, /*sse41*/
2051 X86_SSE_PAVGB = 0xE0,
2052 X86_SSE_PAVGW = 0xE3,
2054 X86_SSE_PCMPEQB = 0x74,
2055 X86_SSE_PCMPEQW = 0x75,
2056 X86_SSE_PCMPEQD = 0x76,
2057 X86_SSE_PCMPEQQ = 0x29, /*sse41*/
2059 X86_SSE_PCMPGTB = 0x64,
2060 X86_SSE_PCMPGTW = 0x65,
2061 X86_SSE_PCMPGTD = 0x66,
2062 X86_SSE_PCMPGTQ = 0x37, /*sse42*/
2064 X86_SSE_PSADBW = 0xf6,
2066 X86_SSE_PSHUFD = 0x70,
2068 X86_SSE_PUNPCKLBW = 0x60,
2069 X86_SSE_PUNPCKLWD = 0x61,
2070 X86_SSE_PUNPCKLDQ = 0x62,
2071 X86_SSE_PUNPCKLQDQ = 0x6C,
2073 X86_SSE_PUNPCKHBW = 0x68,
2074 X86_SSE_PUNPCKHWD = 0x69,
2075 X86_SSE_PUNPCKHDQ = 0x6A,
2076 X86_SSE_PUNPCKHQDQ = 0x6D,
2078 X86_SSE_PACKSSWB = 0x63,
2079 X86_SSE_PACKSSDW = 0x6B,
2081 X86_SSE_PACKUSWB = 0x67,
2082 X86_SSE_PACKUSDW = 0x2B,/*sse41*/
2084 X86_SSE_PADDUSB = 0xDC,
2085 X86_SSE_PADDUSW = 0xDD,
2086 X86_SSE_PSUBUSB = 0xD8,
2087 X86_SSE_PSUBUSW = 0xD9,
2089 X86_SSE_PADDSB = 0xEC,
2090 X86_SSE_PADDSW = 0xED,
2091 X86_SSE_PSUBSB = 0xE8,
2092 X86_SSE_PSUBSW = 0xE9,
2094 X86_SSE_PMULLW = 0xD5,
2095 X86_SSE_PMULLD = 0x40,/*sse41*/
2096 X86_SSE_PMULHUW = 0xE4,
2097 X86_SSE_PMULHW = 0xE5,
2098 X86_SSE_PMULUDQ = 0xF4,
2100 X86_SSE_PMOVMSKB = 0xD7,
2102 X86_SSE_PSHIFTW = 0x71,
2103 X86_SSE_PSHIFTD = 0x72,
2104 X86_SSE_PSHIFTQ = 0x73,
2109 X86_SSE_PSRLW_REG = 0xD1,
2110 X86_SSE_PSRAW_REG = 0xE1,
2111 X86_SSE_PSLLW_REG = 0xF1,
2113 X86_SSE_PSRLD_REG = 0xD2,
2114 X86_SSE_PSRAD_REG = 0xE2,
2115 X86_SSE_PSLLD_REG = 0xF2,
2117 X86_SSE_PSRLQ_REG = 0xD3,
2118 X86_SSE_PSLLQ_REG = 0xF3,
2120 X86_SSE_PREFETCH = 0x18,
2121 X86_SSE_MOVNTPS = 0x2B,
2122 X86_SSE_MOVHPD_REG_MEMBASE = 0x16,
2123 X86_SSE_MOVHPD_MEMBASE_REG = 0x17,
2125 X86_SSE_MOVSD_REG_MEMBASE = 0x10,
2126 X86_SSE_MOVSD_MEMBASE_REG = 0x11,
2128 X86_SSE_PINSRB = 0x20,/*sse41*/
2129 X86_SSE_PINSRW = 0xC4,
2130 X86_SSE_PINSRD = 0x22,/*sse41*/
2132 X86_SSE_PEXTRB = 0x14,/*sse41*/
2133 X86_SSE_PEXTRW = 0xC5,
2134 X86_SSE_PEXTRD = 0x16,/*sse41*/
2136 X86_SSE_SHUFP = 0xC6,
2138 X86_SSE_CVTDQ2PD = 0xE6,
2139 X86_SSE_CVTDQ2PS = 0x5B,
2140 X86_SSE_CVTPD2DQ = 0xE6,
2141 X86_SSE_CVTPD2PS = 0x5A,
2142 X86_SSE_CVTPS2DQ = 0x5B,
2143 X86_SSE_CVTPS2PD = 0x5A,
2144 X86_SSE_CVTTPD2DQ = 0xE6,
2145 X86_SSE_CVTTPS2DQ = 0x5B,
2149 /* minimal SSE* support */
2150 #define x86_movsd_reg_membase(inst,dreg,basereg,disp) \
2152 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2153 *(inst)++ = (unsigned char)0xf2; \
2154 *(inst)++ = (unsigned char)0x0f; \
2155 *(inst)++ = (unsigned char)0x10; \
2156 x86_membase_emit ((inst), (dreg), (basereg), (disp)); \
2159 #define x86_cvttsd2si(inst,dreg,reg) \
2161 x86_codegen_pre(&(inst), 4); \
2162 *(inst)++ = (unsigned char)0xf2; \
2163 *(inst)++ = (unsigned char)0x0f; \
2164 *(inst)++ = (unsigned char)0x2c; \
2165 x86_reg_emit ((inst), (dreg), (reg)); \
2168 #define x86_sse_alu_reg_reg(inst,opc,dreg,reg) \
2170 x86_codegen_pre(&(inst), 3); \
2171 *(inst)++ = (unsigned char)0x0F; \
2172 *(inst)++ = (unsigned char)(opc); \
2173 x86_reg_emit ((inst), (dreg), (reg)); \
2176 #define x86_sse_alu_reg_membase(inst,opc,sreg,basereg,disp) \
2178 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2179 *(inst)++ = (unsigned char)0x0f; \
2180 *(inst)++ = (unsigned char)(opc); \
2181 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2184 #define x86_sse_alu_membase_reg(inst,opc,basereg,disp,reg) \
2186 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2187 *(inst)++ = (unsigned char)0x0F; \
2188 *(inst)++ = (unsigned char)(opc); \
2189 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2192 #define x86_sse_alu_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2194 x86_codegen_pre(&(inst), 4); \
2195 *(inst)++ = (unsigned char)0x0F; \
2196 *(inst)++ = (unsigned char)(opc); \
2197 x86_reg_emit ((inst), (dreg), (reg)); \
2198 *(inst)++ = (unsigned char)(imm8); \
2201 #define x86_sse_alu_pd_reg_reg_imm8(inst,opc,dreg,reg, imm8) \
2203 x86_codegen_pre(&(inst), 5); \
2204 *(inst)++ = (unsigned char)0x66; \
2205 x86_sse_alu_reg_reg_imm8 ((inst), (opc), (dreg), (reg), (imm8)); \
2208 #define x86_sse_alu_pd_reg_reg(inst,opc,dreg,reg) \
2210 x86_codegen_pre(&(inst), 4); \
2211 *(inst)++ = (unsigned char)0x66; \
2212 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2215 #define x86_sse_alu_pd_membase_reg(inst,opc,basereg,disp,reg) \
2217 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2218 *(inst)++ = (unsigned char)0x66; \
2219 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2222 #define x86_sse_alu_pd_reg_membase(inst,opc,dreg,basereg,disp) \
2224 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2225 *(inst)++ = (unsigned char)0x66; \
2226 x86_sse_alu_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2229 #define x86_sse_alu_pd_reg_reg_imm(inst,opc,dreg,reg,imm) \
2231 x86_codegen_pre(&(inst), 5); \
2232 x86_sse_alu_pd_reg_reg ((inst), (opc), (dreg), (reg)); \
2233 *(inst)++ = (unsigned char)(imm); \
2236 #define x86_sse_alu_pd_reg_membase_imm(inst,opc,dreg,basereg,disp,imm) \
2238 x86_codegen_pre(&(inst), 4 + kMaxMembaseEmitPadding); \
2239 x86_sse_alu_pd_reg_membase ((inst), (opc), (dreg),(basereg), (disp)); \
2240 *(inst)++ = (unsigned char)(imm); \
2244 #define x86_sse_alu_ps_reg_reg(inst,opc,dreg,reg) \
2246 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2249 #define x86_sse_alu_ps_reg_reg_imm(inst,opc,dreg,reg, imm) \
2251 x86_codegen_pre(&(inst), 4); \
2252 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2253 *(inst)++ = (unsigned char)imm; \
2257 #define x86_sse_alu_sd_reg_reg(inst,opc,dreg,reg) \
2259 x86_codegen_pre(&(inst), 4); \
2260 *(inst)++ = (unsigned char)0xF2; \
2261 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2264 #define x86_sse_alu_sd_membase_reg(inst,opc,basereg,disp,reg) \
2266 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2267 *(inst)++ = (unsigned char)0xF2; \
2268 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2272 #define x86_sse_alu_ss_reg_reg(inst,opc,dreg,reg) \
2274 x86_codegen_pre(&(inst), 4); \
2275 *(inst)++ = (unsigned char)0xF3; \
2276 x86_sse_alu_reg_reg ((inst), (opc), (dreg), (reg)); \
2279 #define x86_sse_alu_ss_membase_reg(inst,opc,basereg,disp,reg) \
2281 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2282 *(inst)++ = (unsigned char)0xF3; \
2283 x86_sse_alu_membase_reg ((inst), (opc), (basereg), (disp), (reg)); \
2288 #define x86_sse_alu_sse41_reg_reg(inst,opc,dreg,reg) \
2290 x86_codegen_pre(&(inst), 5); \
2291 *(inst)++ = (unsigned char)0x66; \
2292 *(inst)++ = (unsigned char)0x0F; \
2293 *(inst)++ = (unsigned char)0x38; \
2294 *(inst)++ = (unsigned char)(opc); \
2295 x86_reg_emit ((inst), (dreg), (reg)); \
2298 #define x86_movups_reg_membase(inst,sreg,basereg,disp) \
2300 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2301 *(inst)++ = (unsigned char)0x0f; \
2302 *(inst)++ = (unsigned char)0x10; \
2303 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2306 #define x86_movups_membase_reg(inst,basereg,disp,reg) \
2308 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2309 *(inst)++ = (unsigned char)0x0f; \
2310 *(inst)++ = (unsigned char)0x11; \
2311 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2314 #define x86_movaps_reg_membase(inst,sreg,basereg,disp) \
2316 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2317 *(inst)++ = (unsigned char)0x0f; \
2318 *(inst)++ = (unsigned char)0x28; \
2319 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2322 #define x86_movaps_membase_reg(inst,basereg,disp,reg) \
2324 x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
2325 *(inst)++ = (unsigned char)0x0f; \
2326 *(inst)++ = (unsigned char)0x29; \
2327 x86_membase_emit ((inst), (reg), (basereg), (disp)); \
2330 #define x86_movaps_reg_reg(inst,dreg,sreg) \
2332 x86_codegen_pre(&(inst), 3); \
2333 *(inst)++ = (unsigned char)0x0f; \
2334 *(inst)++ = (unsigned char)0x28; \
2335 x86_reg_emit ((inst), (dreg), (sreg)); \
2339 #define x86_movd_reg_xreg(inst,dreg,sreg) \
2341 x86_codegen_pre(&(inst), 4); \
2342 *(inst)++ = (unsigned char)0x66; \
2343 *(inst)++ = (unsigned char)0x0f; \
2344 *(inst)++ = (unsigned char)0x7e; \
2345 x86_reg_emit ((inst), (sreg), (dreg)); \
2348 #define x86_movd_xreg_reg(inst,dreg,sreg) \
2350 x86_codegen_pre(&(inst), 4); \
2351 *(inst)++ = (unsigned char)0x66; \
2352 *(inst)++ = (unsigned char)0x0f; \
2353 *(inst)++ = (unsigned char)0x6e; \
2354 x86_reg_emit ((inst), (dreg), (sreg)); \
2357 #define x86_movd_xreg_membase(inst,sreg,basereg,disp) \
2359 x86_codegen_pre(&(inst), 3 + kMaxMembaseEmitPadding); \
2360 *(inst)++ = (unsigned char)0x66; \
2361 *(inst)++ = (unsigned char)0x0f; \
2362 *(inst)++ = (unsigned char)0x6e; \
2363 x86_membase_emit ((inst), (sreg), (basereg), (disp)); \
2366 #define x86_pshufw_reg_reg(inst,dreg,sreg,mask,high_words) \
2368 x86_codegen_pre(&(inst), 5); \
2369 *(inst)++ = (unsigned char)(high_words) ? 0xF3 : 0xF2; \
2370 *(inst)++ = (unsigned char)0x0f; \
2371 *(inst)++ = (unsigned char)0x70; \
2372 x86_reg_emit ((inst), (dreg), (sreg)); \
2373 *(inst)++ = (unsigned char)mask; \
2376 #define x86_sse_shift_reg_imm(inst,opc,mode, dreg,imm) \
2378 x86_codegen_pre(&(inst), 5); \
2379 x86_sse_alu_pd_reg_reg (inst, opc, mode, dreg); \
2380 x86_imm_emit8 ((inst), (imm)); \
2383 #define x86_sse_shift_reg_reg(inst,opc,dreg,sreg) \
2385 x86_sse_alu_pd_reg_reg (inst, opc, dreg, sreg); \