2 // Copyright 2011 Xamarin Inc
4 // Licensed under the MIT license. See LICENSE file in the project root for full license information.
6 #ifndef __MONO_ARM_VFP_CODEGEN_H__
7 #define __MONO_ARM_VFP_CODEGEN_H__
9 #include "arm-codegen.h"
46 ARM_VFP_D0 = ARM_VFP_F0,
47 ARM_VFP_D1 = ARM_VFP_F2,
48 ARM_VFP_D2 = ARM_VFP_F4,
49 ARM_VFP_D3 = ARM_VFP_F6,
50 ARM_VFP_D4 = ARM_VFP_F8,
51 ARM_VFP_D5 = ARM_VFP_F10,
52 ARM_VFP_D6 = ARM_VFP_F12,
53 ARM_VFP_D7 = ARM_VFP_F14,
54 ARM_VFP_D8 = ARM_VFP_F16,
55 ARM_VFP_D9 = ARM_VFP_F18,
56 ARM_VFP_D10 = ARM_VFP_F20,
57 ARM_VFP_D11 = ARM_VFP_F22,
58 ARM_VFP_D12 = ARM_VFP_F24,
59 ARM_VFP_D13 = ARM_VFP_F26,
60 ARM_VFP_D14 = ARM_VFP_F28,
61 ARM_VFP_D15 = ARM_VFP_F30,
63 ARM_VFP_COPROC_SINGLE = 10,
64 ARM_VFP_COPROC_DOUBLE = 11,
66 #define ARM_VFP_OP(p,q,r,s) (((p) << 23) | ((q) << 21) | ((r) << 20) | ((s) << 6))
67 #define ARM_VFP_OP2(Fn,N) (ARM_VFP_OP (1,1,1,1) | ((Fn) << 16) | ((N) << 7))
69 ARM_VFP_MUL = ARM_VFP_OP (0,1,0,0),
70 ARM_VFP_NMUL = ARM_VFP_OP (0,1,0,1),
71 ARM_VFP_ADD = ARM_VFP_OP (0,1,1,0),
72 ARM_VFP_SUB = ARM_VFP_OP (0,1,1,1),
73 ARM_VFP_DIV = ARM_VFP_OP (1,0,0,0),
75 ARM_VFP_CPY = ARM_VFP_OP2 (0,0),
76 ARM_VFP_ABS = ARM_VFP_OP2 (0,1),
77 ARM_VFP_NEG = ARM_VFP_OP2 (1,0),
78 ARM_VFP_SQRT = ARM_VFP_OP2 (1,1),
79 ARM_VFP_CMP = ARM_VFP_OP2 (4,0),
80 ARM_VFP_CMPE = ARM_VFP_OP2 (4,1),
81 ARM_VFP_CMPZ = ARM_VFP_OP2 (5,0),
82 ARM_VFP_CMPEZ = ARM_VFP_OP2 (5,1),
83 ARM_VFP_CVT = ARM_VFP_OP2 (7,1),
84 ARM_VFP_UITO = ARM_VFP_OP2 (8,0),
85 ARM_VFP_SITO = ARM_VFP_OP2 (8,1),
86 ARM_VFP_TOUI = ARM_VFP_OP2 (12,0),
87 ARM_VFP_TOSI = ARM_VFP_OP2 (13,0),
88 ARM_VFP_TOUIZ = ARM_VFP_OP2 (12,1),
89 ARM_VFP_TOSIZ = ARM_VFP_OP2 (13,1),
96 #define ARM_DEF_VFP_DYADIC(cond,cp,op,Fd,Fn,Fm) \
100 (((Fd) >> 1) << 12) | \
101 (((Fd) & 1) << 22) | \
102 (((Fn) >> 1) << 16) | \
103 (((Fn) & 1) << 7) | \
104 (((Fm) >> 1) << 0) | \
105 (((Fm) & 1) << 5) | \
108 #define ARM_DEF_VFP_MONADIC(cond,cp,op,Fd,Fm) \
112 (((Fd) >> 1) << 12) | \
113 (((Fd) & 1) << 22) | \
114 (((Fm) >> 1) << 0) | \
115 (((Fm) & 1) << 5) | \
118 #define ARM_DEF_VFP_LSF(cond,cp,post,ls,wback,basereg,Fd,offset) \
119 ((offset) >= 0? (offset)>>2: -(offset)>>2) | \
122 (((Fd) >> 1) << 12) | \
123 (((Fd) & 1) << 22) | \
124 ((basereg) << 16) | \
127 (((offset) >= 0) << 23) | \
132 #define ARM_DEF_VFP_CPT(cond,cp,op,L,Fn,Rd) \
139 (((Fn) >> 1) << 16) | \
140 (((Fn) & 1) << 7) | \
143 /* FP load and stores */
144 #define ARM_FLDS_COND(p,freg,base,offset,cond) \
145 ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_SINGLE,1,ARMOP_LDR,0,(base),(freg),(offset)))
146 #define ARM_FLDS(p,freg,base,offset) \
147 ARM_FLDS_COND(p,freg,base,offset,ARMCOND_AL)
149 #define ARM_FLDD_COND(p,freg,base,offset,cond) \
150 ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,1,ARMOP_LDR,0,(base),(freg),(offset)))
151 #define ARM_FLDD(p,freg,base,offset) \
152 ARM_FLDD_COND(p,freg,base,offset,ARMCOND_AL)
154 #define ARM_FSTS_COND(p,freg,base,offset,cond) \
155 ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_SINGLE,1,ARMOP_STR,0,(base),(freg),(offset)))
156 #define ARM_FSTS(p,freg,base,offset) \
157 ARM_FSTS_COND(p,freg,base,offset,ARMCOND_AL)
159 #define ARM_FSTD_COND(p,freg,base,offset,cond) \
160 ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,1,ARMOP_STR,0,(base),(freg),(offset)))
161 #define ARM_FSTD(p,freg,base,offset) \
162 ARM_FSTD_COND(p,freg,base,offset,ARMCOND_AL)
164 #define ARM_FLDMD_COND(p,first_reg,nregs,base,cond) \
165 ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,0,ARMOP_LDR,0,(base),(first_reg),((nregs) * 2) << 2))
167 #define ARM_FLDMD(p,first_reg,nregs,base) \
168 ARM_FLDMD_COND(p,first_reg,nregs,base,ARMCOND_AL)
170 #define ARM_FSTMD_COND(p,first_reg,nregs,base,cond) \
171 ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,0,ARMOP_STR,0,(base),(first_reg),((nregs) * 2) << 2))
173 #define ARM_FSTMD(p,first_reg,nregs,base) \
174 ARM_FSTMD_COND(p,first_reg,nregs,base,ARMCOND_AL)
176 #include <mono/arch/arm/arm_vfpmacros.h>
178 /* coprocessor register transfer */
179 #define ARM_FMSR(p,freg,reg) \
180 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,0,0,(freg),(reg)))
181 #define ARM_FMRS(p,reg,freg) \
182 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,0,1,(freg),(reg)))
184 #define ARM_FMDLR(p,freg,reg) \
185 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,0,0,(freg),(reg)))
186 #define ARM_FMRDL(p,reg,freg) \
187 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,0,1,(freg),(reg)))
188 #define ARM_FMDHR(p,freg,reg) \
189 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,1,0,(freg),(reg)))
190 #define ARM_FMRDH(p,reg,freg) \
191 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,1,1,(freg),(reg)))
193 #define ARM_FMXR(p,freg,reg) \
194 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,7,0,(freg),(reg)))
195 #define ARM_FMRX(p,reg,fcreg) \
196 ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,7,1,(fcreg),(reg)))
198 #define ARM_FMSTAT(p) \
199 ARM_FMRX((p),ARMREG_R15,ARM_VFP_SCR)
201 #define ARM_DEF_MCRR(cond,cp,rn,rd,Fm,M) \
212 #define ARM_FMDRR(p,rd,rn,dm) \
213 ARM_EMIT((p), ARM_DEF_MCRR(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,(rn),(rd),(dm) >> 1, (dm) & 1))
215 #define ARM_DEF_FMRRD(cond,cp,rn,rd,Dm,D) \
224 #define ARM_FMRRD(p,rd,rn,dm) \
225 ARM_EMIT((p), ARM_DEF_FMRRD(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,(rn),(rd),(dm) >> 1, (dm) & 1))
227 #define ARM_DEF_FUITOS(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xa) << 8) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
229 #define ARM_FUITOS(p,dreg,sreg) \
230 ARM_EMIT((p), ARM_DEF_FUITOS (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
232 #define ARM_DEF_FUITOD(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xb) << 8) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
234 #define ARM_FUITOD(p,dreg,sreg) \
235 ARM_EMIT((p), ARM_DEF_FUITOD (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
237 #define ARM_DEF_FSITOS(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xa) << 8) | ((1) << 7) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
239 #define ARM_FSITOS(p,dreg,sreg) \
240 ARM_EMIT((p), ARM_DEF_FSITOS (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
242 #define ARM_DEF_FSITOD(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xb) << 8) | ((1) << 7) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
244 #define ARM_FSITOD(p,dreg,sreg) \
245 ARM_EMIT((p), ARM_DEF_FSITOD (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
247 #endif /* __MONO_ARM_VFP_CODEGEN_H__ */