variable y : boolean;
begin
case x is
- -- nur gueltig wenn davor ein numpad-mod byte gekommen ist
- when SC_KP_DIV => y := last = x"e0";
-
- -- immer gueltig
when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
- SC_KP_MINUS | SC_KP_MUL | SC_SPACE |
+ SC_KP_MINUS | SC_KP_MUL |
+ SC_KP_DIV | SC_SPACE |
SC_BKSP | SC_ENTER =>
y := true;
when others => y := false;
next mainl;
end if;
+ -- jedes mal release
+ new_data <= '1';
+ data <= x"f0";
+ icwait(sys_clk, 1);
+ new_data <= '0';
+ icwait(sys_clk, 1);
new_data <= '1';
+
case input(j) is
when nul => data <= ascii2sc(x"1c"); -- $ (enter)
when '!' => data <= ascii2sc(x"0e"); -- ! (backspace)
- when '.' => data <= x"e0"; -- . (modifier fuer Numpad)
when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8)));
end case;
icwait(sys_clk, 1);
end entity scanner;
architecture beh of scanner is
- type SCANNER_STATE is (SIDLE, SREAD, SMOD, STAKE, SDEL, SENTER);
+ type SCANNER_STATE is (SINIT, SIDLE, SREAD, STAKE, SDEL, SENTER);
signal state_int, state_next : SCANNER_STATE;
signal s_char_int, s_char_next : hbyte;
signal s_take_int, s_take_next : std_logic;
signal s_backspace_int, s_backspace_next : std_logic;
signal do_it_int, do_it_next : std_logic;
+ signal was_f0_int, was_f0_next : std_logic;
begin
s_char <= s_char_int;
s_take <= s_take_int;
begin
if sys_res_n = '0' then
-- internal
- state_int <= SIDLE;
+ state_int <= SINIT;
+ was_f0_int <= '0';
-- out
s_char_int <= (others => '0');
s_take_int <= '0';
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
+ was_f0_int <= was_f0_next;
-- out
s_char_int <= s_char_next;
s_take_int <= s_take_next;
end process;
-- next state
- process(state_int, new_data, data, finished, s_done)
+ process(state_int, new_data, data, finished, s_done, was_f0_int)
begin
state_next <= state_int;
case state_int is
+ when SINIT =>
+ state_next <= SIDLE;
when SIDLE =>
- if new_data = '1' and finished = '0' and s_done = '0' then
+ if new_data = '1' and was_f0_int = '1' then
state_next <= SREAD;
end if;
when SREAD =>
case data is
- when x"e0" => state_next <= SMOD;
when SC_BKSP => state_next <= SDEL;
when SC_ENTER => state_next <= SENTER;
when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
- SC_KP_MINUS | SC_KP_MUL | SC_SPACE =>
- state_next <= STAKE;
+ SC_KP_MINUS | SC_KP_MUL | SC_SPACE |
+ SC_KP_DIV => state_next <= STAKE;
when others => state_next <= SIDLE;
end case;
- when SMOD =>
- if new_data = '1' then
- if data = SC_KP_ENTER then
- state_next <= SENTER;
- elsif data = SC_KP_DIV then
- state_next <= STAKE;
- else
- state_next <= SIDLE;
- end if;
- end if;
when STAKE | SDEL=>
if s_done = '1' then
state_next <= SIDLE;
end process;
-- out
- process(state_int, data)
+ process(state_int, data, s_char_int, new_data, was_f0_int)
function sc2ascii (x : hbyte) return hbyte is
variable y : hbyte;
begin
return y;
end function;
begin
- s_char_next <= (others => '0');
+ s_char_next <= s_char_int;
s_take_next <= '0';
s_backspace_next <= '0';
do_it_next <= '0';
+ was_f0_next <= was_f0_int;
case state_int is
+ when SINIT =>
+ was_f0_next <= '0';
when SIDLE =>
- null;
+ if new_data = '1' and data = x"f0" then
+ was_f0_next <= '1';
+ end if;
when SREAD =>
- null;
- when SMOD =>
- null;
+ was_f0_next <= '0';
when STAKE =>
s_take_next <= '1';
s_char_next <= sc2ascii(hbyte(data));