small bugfixes that resolve signal instabilities where needed

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 4efc777a9f1a4895ee5fa0d328b113ae9e9591bc..854e7eeeb6d61357b0e240b2b4b70c8875c4903e 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -66,29 +66,39 @@ begin
                file f : byte_file_type open read_mode is "../../src/pc_communication.test";
                variable rb : hbyte;
        begin
+               d_done <= '0';
                wait until rising_edge(d_get);
                assert not endfile(f) report "test beendet" severity failure;
                read(f, rb);
                wait for 30 ns;
                d_char <= rb;
                d_done <= '1';
-               wait for 15 ns;
-               d_done <= '0';
+               wait for 30 ns;
        end process stub_history;
 
+
+       stub_uart : process
+       begin
+               tx_done <= '0';
+               wait until rising_edge(tx_new);
+               wait for 90 ns;
+               tx_done <= '1';
+               wait for 90 ns;
+       end process stub_uart;
+
        reset_and_button : process
        begin
                -- init & reset
                -- we only simulate pressing of button a by now!
                sys_res_n <= '0';
                btn_a <= '0';
-               d_done <= '0';
                tx_data <= "00000000";
                rx_data <= "00000000";
                d_zeile <= "0000000";
                d_spalte <= "0000000";
                tx_new <= '0';
                tx_done <= '0';
+               rx_new <= '0';
                
                wait for 90 ns;
                sys_res_n <= '1';

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 53ca2150cf5b2dc3492504455ee9b0a2f8914ad3..3251284a4ca13c926e7bbed69d2220e0d00ccb3c 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -36,6 +36,7 @@ architecture beh of pc_communication is
        signal zeile , zeile_next : hzeile;
        signal spalte_up, spalte_up_next : std_logic;
        signal get, get_next : std_logic;
+       signal new_i, new_i_next : std_logic;
 
        signal char, char_next : hbyte;
        signal char_en : std_logic;
@@ -48,6 +49,8 @@ begin
        d_zeile <= zeile;
        d_spalte <= spalte;
        d_get <= get;
+       char_next <= d_char;
+       tx_new <= new_i;
 
        sync: process (sys_clk, sys_res_n)
        begin
@@ -59,7 +62,7 @@ begin
                        zeile <= "0000000";
                        zeile_next <= "0000000";
                        get <= '0';
-                       tx_new <= '0';
+                       new_i <= '0';
                        tx_data <= "00000000";
                elsif rising_edge(sys_clk) then
                        push_history <= push_history_next;
@@ -67,8 +70,9 @@ begin
                        zeile <= zeile_next;
                        state <= state_next;
                        get <= get_next;
+                       new_i <= new_i_next;
                        if (char_en = '1') then
-                               state <= state_next;
+                               char <= char_next;
                        end if;
                end if;
        end process sync;
@@ -111,9 +115,10 @@ begin
        output_pc : process (state, zeile, spalte, char)
        begin
                get_next <= '0';
+               new_i_next <= '0';
                spalte_next <= "0000000";
                zeile_next <= "0000000";
-               case state is 
+               case state is
                        when IDLE =>
                                null;
                        when FETCH =>
@@ -122,7 +127,7 @@ begin
                        when FORWARD =>
                                char_en <= '0';
                                tx_data <= char;
-                               tx_new <= '1';
+                               new_i_next <= '1';
                        when DONE =>
                                null;
                end case;
@@ -135,7 +140,7 @@ begin
                        when IDLE =>
                                if rx_new = '1' or btn_a = '1' then
                                        state_next <= FETCH;
-                                       char <= d_char; --latch
+                                       
                                end if;
                        when FETCH =>
                                if (d_done = '1') then