scanner: rewrite fuer key-pressed only. TODO: testbench

diff --git a/src/TODO b/src/TODO
index ac3ae5765340da4ba4302c6ad1e5859480735d30..f53db39eb3502dd24a869b6b6f5a06d959e024c6 100644 (file)
--- a/src/TODO
+++ b/src/TODO
@@ -5,11 +5,6 @@
 - rs232/pc-kommunikation: RAM dumpen
 
 
 - rs232/pc-kommunikation: RAM dumpen
 
 

-- scanner rewrite: nicht bei key-release sondern bei key-pressed
-       o vorteil: man kann auf der taste drauf bleiben und man kann
-         keine zahlen mehr mit den coursertasten eingeben
-
-

 - uart rx oversampling, uart rx synchronizen (vlg. debouncing/sync*.vhd)
 
 
 - uart rx oversampling, uart rx synchronizen (vlg. debouncing/sync*.vhd)
 
 

diff --git a/src/beh_scanner_tb.vhd b/src/beh_scanner_tb.vhd
index 379d26b546c837a8fbfbf15cb095f1c3da609191..f5a0a34ad7d023a7f8f37b0c85666f19ec936c8c 100644 (file)
--- a/src/beh_scanner_tb.vhd
+++ b/src/beh_scanner_tb.vhd
@@ -175,12 +175,6 @@ begin
                                        next mainl;
                                end if;
 
                                        next mainl;
                                end if;
 

-                               -- jedes mal release
-                               new_data <= '1';
-                               data <= x"f0";
-                               icwait(sys_clk, 1);
-                               new_data <= '0';
-                               icwait(sys_clk, 1);

                                new_data <= '1';
 
                                case input(j) is
                                new_data <= '1';
 
                                case input(j) is

diff --git a/src/scanner.vhd b/src/scanner.vhd
index 875cddda4a88fa9979823c6bba6e46ceb2ae9f73..78a89fa9f82012bdb82bfa33ddcb49250bb34586 100644 (file)
--- a/src/scanner.vhd
+++ b/src/scanner.vhd
@@ -23,13 +23,12 @@ entity scanner is
 end entity scanner;
 
 architecture beh of scanner is
 end entity scanner;
 
 architecture beh of scanner is

-       type SCANNER_STATE is (SINIT, SIDLE, SREAD, STAKE, SDEL, SENTER);
+       type SCANNER_STATE is (SIDLE, SIGNORE_NEXT, SREAD_NEXT, STAKE, SDEL, SENTER);

        signal state_int, state_next : SCANNER_STATE;
        signal s_char_int, s_char_next : hbyte;
        signal s_take_int, s_take_next : std_logic;
        signal s_backspace_int, s_backspace_next : std_logic;
        signal do_it_int, do_it_next : std_logic;
        signal state_int, state_next : SCANNER_STATE;
        signal s_char_int, s_char_next : hbyte;
        signal s_take_int, s_take_next : std_logic;
        signal s_backspace_int, s_backspace_next : std_logic;
        signal do_it_int, do_it_next : std_logic;

-       signal was_f0_int, was_f0_next : std_logic;

 begin
        s_char <= s_char_int;
        s_take <= s_take_int;
 begin
        s_char <= s_char_int;
        s_take <= s_take_int;


@@ -40,8 +39,7 @@ begin
        begin
                if sys_res_n = '0' then
                        -- internal
        begin
                if sys_res_n = '0' then
                        -- internal

-                       state_int <= SINIT;
-                       was_f0_int <= '0';
+                       state_int <= SIDLE;

                        -- out
                        s_char_int <= (others => '0');
                        s_take_int <= '0';
                        -- out
                        s_char_int <= (others => '0');
                        s_take_int <= '0';


@@ -50,7 +48,6 @@ begin
                elsif rising_edge(sys_clk) then
                        -- internal
                        state_int <= state_next;
                elsif rising_edge(sys_clk) then
                        -- internal
                        state_int <= state_next;

-                       was_f0_int <= was_f0_next;

                        -- out
                        s_char_int <= s_char_next;
                        s_take_int <= s_take_next;
                        -- out
                        s_char_int <= s_char_next;
                        s_take_int <= s_take_next;


@@ -60,28 +57,46 @@ begin
        end process;
 
        -- next state
        end process;
 
        -- next state

-       process(state_int, new_data, data, finished, s_done, was_f0_int)
+       process(state_int, new_data, data, finished, s_done)

        begin
                state_next <= state_int;
 
                case state_int is
        begin
                state_next <= state_int;
 
                case state_int is

-                       when SINIT =>
-                               state_next <= SIDLE;

                        when SIDLE =>
                        when SIDLE =>

-                               if new_data = '1' and was_f0_int = '1' then
-                                       state_next <= SREAD;
+                               if new_data = '1' then
+                                       case data is
+                                               when x"f0" =>
+                                                       state_next <= SIGNORE_NEXT;
+                                               when x"e0" =>
+                                                       state_next <= SREAD_NEXT;
+                                               when SC_BKSP =>
+                                                       state_next <= SDEL;
+                                               when SC_ENTER =>
+                                                       state_next <= SENTER;
+                                               when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
+                                                       SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
+                                                       SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
+                                                       SC_KP_MINUS | SC_KP_MUL | SC_SPACE =>
+                                                               state_next <= STAKE;
+                                               when others => state_next <= SIDLE;
+                                       end case;
+                               end if;
+                       when SIGNORE_NEXT =>
+                               if new_data = '1' then
+                                       state_next <= SIDLE;
+                               end if;
+                       when SREAD_NEXT =>
+                               if new_data = '1' then
+                                       case data is
+                                               when x"f0" =>
+                                                       state_next <= SIGNORE_NEXT;
+                                               when SC_ENTER =>
+                                                       state_next <= SENTER;
+                                               when SC_KP_DIV =>
+                                                       state_next <= STAKE;
+                                               when others => state_next <= SIDLE;
+                                       end case;

                                end if;
                                end if;

-                       when SREAD =>
-                               case data is
-                                       when SC_BKSP => state_next <= SDEL;
-                                       when SC_ENTER => state_next <= SENTER;
-                                       when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
-                                               SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
-                                               SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
-                                               SC_KP_MINUS | SC_KP_MUL | SC_SPACE |
-                                               SC_KP_DIV => state_next <= STAKE;
-                                       when others => state_next <= SIDLE;
-                               end case;

                        when STAKE | SDEL=>
                                if s_done = '1' then
                                        state_next <= SIDLE;
                        when STAKE | SDEL=>
                                if s_done = '1' then
                                        state_next <= SIDLE;


@@ -94,7 +109,7 @@ begin
        end process;
 
        -- out
        end process;
 
        -- out

-       process(state_int, data, s_char_int, new_data, was_f0_int)
+       process(state_int, data, s_char_int, new_data)

                function sc2ascii (x : hbyte) return hbyte is
                        variable y : hbyte;
                begin
                function sc2ascii (x : hbyte) return hbyte is
                        variable y : hbyte;
                begin


@@ -123,17 +138,11 @@ begin
                s_take_next <= '0';
                s_backspace_next <= '0';
                do_it_next <= '0';
                s_take_next <= '0';
                s_backspace_next <= '0';
                do_it_next <= '0';

-               was_f0_next <= was_f0_int;

 
                case state_int is
 
                case state_int is

-                       when SINIT =>
-                               was_f0_next <= '0';
-                       when SIDLE =>
-                               if new_data = '1' and data = x"f0" then
-                                       was_f0_next <= '1';
-                               end if;
-                       when SREAD =>
-                               was_f0_next <= '0';
+                       when SIDLE => null;
+                       when SIGNORE_NEXT => null;
+                       when SREAD_NEXT => null;

                        when STAKE =>
                                s_take_next <= '1';
                                s_char_next <= sc2ascii(hbyte(data));
                        when STAKE =>
                                s_take_next <= '1';
                                s_char_next <= sc2ascii(hbyte(data));