den punkt "- gen_pkg: unsigned fuer hspalte, hzeile" hab ich verworfen weil es zu
viel "breakt"
logic elements atm: 2947
-
- pc-kommunikation: ein wait state fehlt warum es momentan zu komischem
verhalten in der state machine kommt.
- rs232/pc-kommunikation: RAM dumpen
-
-- gen_pkg: unsigned fuer hspalte, hzeile
-
-
== low prio ==
- logic elements eliminieren
i := 1;
f_loop : while not endfile(f) loop
- realresult := (72 => nul, others => ' ');
+ realresult := (HSPALTE_MAX+1 => nul, others => ' ');
f1_loop : while not endfile(f) loop
readline (f, l);
input := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
input(1 to l'length) := l.all;
if (input(1) = '#') then
next f1_loop;
f2_loop : while not endfile(f) loop
readline (f, l);
expectedresult := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
expectedresult(1 to l'length) := l.all;
if (expectedresult(1) = '#') then
next f2_loop;
-- ergebnis string richtig formatieren
hstrtmp := expectedresult;
- expectedresult := (72 => nul, others => ' ');
- for x in 1 to 71 loop
+ expectedresult := (HSPALTE_MAX+1 => nul, others => ' ');
+ for x in 1 to HSPALTE_MAX loop
if hstrtmp(x) /= nul then
- expectedresult((71-y) + x) := hstrtmp(x);
+ expectedresult((HSPALTE_MAX-y) + x) := hstrtmp(x);
end if;
end loop;
icwait(sys_clk, 5);
do_it <= '1';
run_tc := true;
- j := 1; k := 71;
+ j := 1; k := HSPALTE_MAX;
while run_tc loop
wait on p_rget, p_wtake, p_finished, finished;
f1_loop : while not endfile(f) loop
readline (f, l);
input := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
input(1 to l'length) := l.all;
if (input(1) = '#') then
next f1_loop;
f2_loop : while not endfile(f) loop
readline (f, l);
expectedresult := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
expectedresult(1 to l'length) := l.all;
if (expectedresult(1) = '#') then
next f2_loop;
istate_next <= IS_RESULT1_2_RESULT2;
state_next <= S_WAIT;
when S_READ_RESULT_2 =>
- if unsigned(d_spalte_int) /= 70 then
+ if unsigned(d_spalte_int) /= HSPALTE_MAX-1 then
state_next <= S_COUNTUP;
istate_next <= IS_RESULT1_2_RESULT2;
else
d_spalte_next <= (others => '0');
case d_zeile_int is
when
- std_logic_vector(to_unsigned((49*2)+1,d_zeile_int'length)) => d_zeile_next <= (others => '0');
+ std_logic_vector(to_unsigned(HZEILE_MAX-1,d_zeile_int'length)) => d_zeile_next <= (others => '0');
when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
end case;
-- integer ist 32bit (31bit + sign)
subtype cinteger is integer;
- -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes
- constant hspalte_max : integer := 71;
- constant hzeile_max : integer := 100;
- constant H_RAM_SIZE : integer := 7100;
- constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
+
+ constant HSPALTE_MAX : integer := 71;
subtype hspalte is std_logic_vector(6 downto 0);
+
+ constant HZEILE_MAX : integer := 100;
subtype hzeile is std_logic_vector(6 downto 0);
+
+ -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes
+ constant H_RAM_SIZE : integer := HZEILE_MAX * HSPALTE_MAX;
+ constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
+
subtype hbyte is std_logic_vector(7 downto 0);
- subtype hstring is string(1 to 72);
- subtype hstr_int is integer range 0 to 72;
+ subtype hstring is string(1 to HSPALTE_MAX+1);
+ subtype hstr_int is integer range 0 to HSPALTE_MAX+1;
procedure icwait(signal clk_i : IN std_logic; cycles: natural);
p_wdone_int <= '0';
p_read_int <= (others => '0');
p_sp_read_int <= (others => '0');
- p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
+ p_sp_write_int <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_int'length));
pc_char_int <= (others => '0');
pc_done_int <= '0';
when S_S_FIN_POSUP =>
state_next <= S_S_CLEAR_NEXT0;
when S_S_CLEAR_NEXT0 =>
- if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+ if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
state_next <= S_S_CLEAR_NEXT1;
end if;
when S_S_CLEAR_NEXT1 =>
- if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+ if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
state_next <= SIDLE;
end if;
when S_S_DONE =>
when S_S_INIT =>
null;
when S_S_WRITE =>
- -- nur bei < 71 weiter machen
+ -- nur bei < HSPALTE_MAX weiter machen
-- Hint: '/=' billiger als '<'
- if unsigned(s_cnt_int) /= 71 then
+ if unsigned(s_cnt_int) /= HSPALTE_MAX then
wr_next <= '1';
address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
data_in_next <= s_char;
d_new_result_next <= '1';
-- resetten der parser counter
p_sp_read_next <= (others => '0');
- p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
+ p_sp_write_next <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_next'length));
when S_S_FIN_POSUP =>
-- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
wr_next <= '1';
address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
data_in_next <= (others => '0');
- if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+ if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
s_cnt_next <= (0 => '1', others => '0');
else
s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
when S_S_CLEAR_NEXT1 =>
-- die naechsten 142 bytes im speicher resetten
wr_next <= '1';
- address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int));
+ address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(s_cnt_int));
data_in_next <= (others => '0');
- if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+ if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
s_cnt_next <= (0 => '1', others => '0');
else
s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
when S_D_INIT =>
addr_tmp := (others => '0');
addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
- mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
+ mul_tmp := std_logic_vector(unsigned(addr_tmp) *
+ to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
address_next <= addr_tmp;
when S_PC_INIT =>
addr_tmp := (others => '0');
addr_tmp(hzeile'length - 1 downto 0) := pc_zeile;
- mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
+ mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
address_next <= addr_tmp;
data_in_next <= p_write;
spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
p_sp_write_next <= spalte_tmp;
- address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
+ address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(spalte_tmp));
when S_P_WRITE_DONE =>
p_wdone_next <= '1';
when S_P_DONE =>
aktop_int <= ALU_NOP;
opp_int <= ALU_NOP;
err_int <= 0;
- errc_int <= 71;
+ errc_int <= HSPALTE_MAX;
errc_tmp_int <= 0;
firstz_int <= true;
-- out ports
when SDONE =>
err_next <= 0;
- errc_next <= 71;
+ errc_next <= HSPALTE_MAX;
p_finished_next <= '1';
finished_next <= '1';
end entity pc_communication;
architecture beh of pc_communication is
- signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
- signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
+ signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1;
+ signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1;
signal get, get_next : std_logic;
signal new_i, new_i_next : std_logic;
signal tx_done_i, tx_done_i_next : std_logic;
when WAIT_UART =>
new_i_next <= '1';
when UART_DONE =>
- if tx_data_i = x"00" or spalte = hspalte_max then
+ if tx_data_i = x"00" or spalte = HSPALTE_MAX then
tx_data_i_next <= x"0a";
zeile_next <= zeile + 1;
spalte_next <= 1;
- if zeile = hzeile_max then
+ if zeile = HZEILE_MAX then
zeile_next <= 1;
end if;
else
state_next <= UART_DONE;
end if;
when UART_DONE =>
- if (tx_data_i = x"00" or spalte = hspalte_max) and
- zeile = hzeile_max then
+ if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and
+ zeile = HZEILE_MAX then
state_next <= IDLE;
else
state_next <= FETCH;
i := 1;
f_loop : while not endfile(f) loop
- realresult := (72 => nul, others => ' ');
+ realresult := (HSPALTE_MAX+1 => nul, others => ' ');
f1_loop : while not endfile(f) loop
readline (f, l);
input := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
input(1 to l'length) := l.all;
if (input(1) = '#') then
next f1_loop;
f2_loop : while not endfile(f) loop
readline (f, l);
expectedresult := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
expectedresult(1 to l'length) := l.all;
if (expectedresult(1) = '#') then
next f2_loop;
-- ergebnis string richtig formatieren
hstrtmp := expectedresult;
- expectedresult := (72 => nul, others => ' ');
- for x in 1 to 71 loop
+ expectedresult := (HSPALTE_MAX+1 => nul, others => ' ');
+ for x in 1 to HSPALTE_MAX loop
if hstrtmp(x) /= nul then
- expectedresult((71-y) + x) := hstrtmp(x);
+ expectedresult((HSPALTE_MAX-y) + x) := hstrtmp(x);
end if;
end loop;
icwait(sys_clk, 5);
do_it <= '1';
run_tc := true;
- j := 1; k := 71;
+ j := 1; k := HSPALTE_MAX;
while run_tc loop
wait on p_rget, p_wtake, p_finished, finished;
f1_loop : while not endfile(f) loop
readline (f, l);
input := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
input(1 to l'length) := l.all;
if (input(1) = '#') then
next f1_loop;
f2_loop : while not endfile(f) loop
readline (f, l);
expectedresult := (others => nul);
- if (l'length <= 72) then
+ if (l'length <= HSPALTE_MAX+1) then
expectedresult(1 to l'length) := l.all;
if (expectedresult(1) = '#') then
next f2_loop;