MPWD := $(shell pwd)
D_BEHSIM := $(MPWD)/../sim/beh
+D_POSTSIM := $(MPWD)/../sim/post
+POST_VHO := $(MPWD)/../quartus/calc/simulation/modelsim/calc.vho
+POST_SDO := $(MPWD)/../quartus/calc/simulation/modelsim/calc_vhd.sdo
+POST_SDO_INST := inst
WORK := work
-#reihenfolge ist hier wichtig!
-IFILES = gen_pkg alu alu_tb
-IFILES := $(strip $(IFILES))
-#virtuelle targets: weil wir sowas wie ein objectfile von vcom nicht bekommen. bessere ideen sind willkommen
-VTARGETS := $(foreach n, $(IFILES), $(D_BEHSIM)/$(WORK)/$(n)/_primary.dat)
+# o reihenfolge ist wichtig
+# o keine testbechnes hier angeben
+BEH_IFILES = gen_pkg alu
+BEH_IFILES := $(strip $(BEH_IFILES))
+
+# o keine testbenches hier angeben
+# o beachte, dass sich viele files schon in dem VHO file befinden -- es muessen eigentlich nur
+# abhaengigkeiten fuer die testbenches angegeben werden
+POST_IFILES = gen_pkg
+POST_IFILES := $(strip $(POST_IFILES))
+
+#virtuelle targets fuer behsim: weil wir sowas wie ein objectfile von vcom nicht bekommen. bessere ideen sind willkommen
+BEH_VTARGETS := $(foreach n, $(BEH_IFILES), $(D_BEHSIM)/$(WORK)/$(n)/_primary.dat)
+
+#virtuelle targets fuer postsim
+POST_VTARGETS := $(foreach n, $(shell grep ENTITY $(POST_VHO) | awk '{ print $$2 }'), $(D_POSTSIM)/$(WORK)/$(n)/_primary.dbs)
+POST_VTARGETS += $(foreach n, $(POST_IFILES), $(D_POSTSIM)/$(WORK)/$(n)/_primary.dat)
+
all: behsim
-behsim: $(D_BEHSIM)/modelsim.ini $(VTARGETS)
+#behsim
+behsim: $(D_BEHSIM)/modelsim.ini $(BEH_VTARGETS)
$(D_BEHSIM)/modelsim.ini:
@echo " INIT for behavioural simulation"
vlib work > /dev/null ; \
vmap work work > /dev/null ;
-$(D_BEHSIM)/$(WORK)/%/_primary.dat: %.vhd
+$(D_BEHSIM)/$(WORK)/%/_primary.dat: %.vhd $(D_BEHSIM)/modelsim.ini
@echo " CC $<"
@cd $(D_BEHSIM); \
vcom -work $(WORK) $(MPWD)/$<
-modelsim: behsim
- @cd $(D_BEHSIM); \
- vsim "work.alu_tb(sim)" -f /dev/null -do $(MPWD)/alu.do
+beh_%: $(D_BEHSIM)/$(WORK)/beh_%_tb/_primary.dat beh_%_tb.do behsim
+ cd $(D_BEHSIM); \
+ vsim "work.$@_tb(sim)" -f /dev/null -do $(MPWD)/$@_tb.do
+
+#postsim
+postsim: $(POST_VHO) $(D_POSTSIM)/modelsim.ini $(POST_VTARGETS)
+
+$(D_POSTSIM)/modelsim.ini:
+ @echo " INIT for post-layout simulation"
+ @mkdir -p $(D_POSTSIM)
+ @cd $(D_POSTSIM); \
+ vlib work > /dev/null ; \
+ vmap work work > /dev/null ;
+
+$(D_POSTSIM)/$(WORK)/%/_primary.dbs: $(POST_VHO) $(D_POSTSIM)/modelsim.ini
+ @echo " CC $<"
+ @cd $(D_POSTSIM); \
+ vcom -work $(WORK) $(POST_VHO)
+
+$(D_POSTSIM)/$(WORK)/%/_primary.dat: %.vhd $(D_POSTSIM)/modelsim.ini
+ @echo " CC $<"
+ @cd $(D_POSTSIM); \
+ vcom -work $(WORK) $(MPWD)/$<
+
+post_%: $(D_POSTSIM)/$(WORK)/post_%_tb/_primary.dat post_%_tb.do postsim $(POST_SDO)
+ cd $(D_POSTSIM); \
+ vsim "work.$@_tb(sim)" -sdftyp /$(POST_SDO_INST)=$(POST_SDO) -f /dev/null -do $(MPWD)/$@_tb.do
+
+$(POST_VHO) $(POST_SDO):
+ @if [ -f $@ ]; \
+ then echo "vho/sdo: passt"; true ; \
+ else echo "Fehler: $@ muss mit quartus erstellt werden"; false; \
+ fi
quartus:
@echo "Die angebotene (free) Quartus II Version funktioniert leider nicht. (Build endet mit einem Error, auch mit dem debouncing-bsp der LVA)."
.PHONY: clean
clean:
- rm -Rf $(D_BEHSIM)
+ rm -Rf $(D_BEHSIM) $(D_POSTSIM)
+++ /dev/null
-#alias fuer simulation neustarten
-alias rr "restart -f"
-
-#signale hinzufuegen
-add wave sys_clk
-add wave sys_res_n
-add wave op1
-add wave opcode
-add wave op2
-add wave op3
-add wave do_calc
-add wave calc_done
-
-#rauszoomen
-wave zoomout 500.0
-
-#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
-run -all
-
-#ganz nach links scrollen
-wave seetime 0
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.gen_pkg.all;
-
-entity alu_tb is
-end entity alu_tb;
-
-architecture sim of alu_tb is
- component alu is
- port
- (
- sys_clk : in std_logic;
- sys_res_n : in std_logic;
- opcode : in alu_ops;
- op1 : in csigned;
- op2 : in csigned;
- op3 : out csigned;
- do_calc : in std_logic;
- calc_done : out std_logic
- );
- end component alu;
-
- signal sys_clk, sys_res_n, do_calc, calc_done : std_logic;
- signal opcode : alu_ops;
- signal op1, op2, op3 : csigned;
- signal stop : boolean := false;
-begin
- bla : alu
- port map
- (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
- do_calc => do_calc,
- calc_done => calc_done,
- op1 => op1,
- op2 => op2,
- op3 => op3,
- opcode => opcode
- );
-
- process
- begin
- sys_clk <= '0';
- wait for 15 ns;
- sys_clk <= '1';
- wait for 15 ns;
- if stop = true then
- wait;
- end if;
- end process;
-
- process
- type alu_testv is record
- o1 : cinteger;
- o : alu_ops;
- o2 : cinteger;
- expected : cinteger;
- end record alu_testv;
-
- -- ggf. groesse des arrays erhoehen
- type alu_testv_array is array (natural range 0 to 20) of alu_testv;
-
- variable testmatrix : alu_testv_array :=
- ( 0 => (-5, DIV, 3, -1),
- 1 => (7, ADD, 3, 10),
- 2 => (7, SUB, 1, 6),
- 3 => (7, DIV, 1, 7),
- 4 => (7, DIV, 3, 2),
- 5 => (7, ADD, 1, 8),
- 6 => (7, MUL, 3, 21),
- 7 => (-7, MUL, 3, -21),
- 8 => (268435456, MUL, -2, -536870912),
- 9 => (268435456, MUL, 2**5, 0), -- um fuenf nach links shiften
- 10 => (268435456 + 5, MUL, 2**5, 160), -- = 5 * (2^5)
- 11 => (100, DIV, 10, 10),
- 12 => (100, DIV, 51, 1),
- 13 => (100, DIV, 49, 2),
- 14 => (153156, DIV, 3543, 43),
- 15 => (-153156, DIV, 3543, -43),
- 16 => (153156, DIV, -3543, -43),
- 17 => (-153156, DIV, -3543, 43),
- others => (0, ADD, 0, 0)
- );
-
- begin
- sys_res_n <= '0';
- wait for 50 ns;
- sys_res_n <= '1';
-
- for i in testmatrix'range loop
- wait for 100 ns;
- op1 <= to_signed(testmatrix(i).o1,CBITS);
- opcode <= testmatrix(i).o;
- op2 <= to_signed(testmatrix(i).o2,CBITS);
-
- -- berechnung kann los gehen
- do_calc <= '1';
-
- -- warten auf die alu einheit
- wait on calc_done;
-
- assert op3 = to_signed(testmatrix(i).expected,CBITS)
- report "" & cinteger'image(testmatrix(i).o1) &
- " " & alu_ops'image(opcode) &
- " " & cinteger'image(testmatrix(i).o2) &
- "/= " & integer'image(to_integer(op3)) &
- " -- erwartet: " & cinteger'image(testmatrix(i).expected);
-
- wait for 5 ns;
- -- ack it!
- do_calc <= '0';
- end loop;
-
- assert false
- report "alle testfaelle der ALU waren erfolgreich!";
- stop <= true;
- wait;
- end process;
-end architecture sim;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.gen_pkg.all;
-
-entity alu_tb is
-end entity alu_tb;
-
-architecture sim of alu_tb is
- component alu is
- port
- (
- sys_clk : in std_logic;
- sys_res_n : in std_logic;
- \opcode.NOP\ : in std_logic;
- \opcode.SUB\ : in std_logic;
- \opcode.ADD\ : in std_logic;
- \opcode.MUL\ : in std_logic;
- \opcode.DIV\ : in std_logic;
- \opcode.DONE\ : in std_logic;
- op1 : in std_logic_vector(31 downto 0);
- op2 : in std_logic_vector(31 downto 0);
- op3 : out std_logic_vector(31 downto 0);
- do_calc : in std_logic;
- calc_done : out std_logic
- );
- end component alu;
-
- signal sys_clk, sys_res_n, do_calc, calc_done : std_logic;
- signal opcode : alu_ops;
- signal \opcode.NOP\ : std_logic;
- signal \opcode.SUB\ : std_logic;
- signal \opcode.ADD\ : std_logic;
- signal \opcode.MUL\ : std_logic;
- signal \opcode.DIV\ : std_logic;
- signal \opcode.DONE\ : std_logic;
- signal op1, op2, op3 : std_logic_vector(31 downto 0);
- signal stop : boolean := false;
-begin
- bla : alu
- port map
- (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
- do_calc => do_calc,
- calc_done => calc_done,
- op1 => op1,
- op2 => op2,
- op3 => op3,
- \opcode.NOP\ => \opcode.NOP\,
- \opcode.SUB\ => \opcode.SUB\,
- \opcode.ADD\ => \opcode.ADD\,
- \opcode.MUL\ => \opcode.MUL\,
- \opcode.DIV\ => \opcode.DIV\,
- \opcode.DONE\ => \opcode.DONE\
- );
-
- process
- begin
- sys_clk <= '0';
- wait for 15 ns;
- sys_clk <= '1';
- wait for 15 ns;
- if stop = true then
- wait;
- end if;
- end process;
-
- process
- type alu_testv is record
- o1 : cinteger;
- o : alu_ops;
- o2 : cinteger;
- expected : cinteger;
- end record alu_testv;
-
- -- ggf. groesse des arrays erhoehen
- type alu_testv_array is array (natural range 0 to 20) of alu_testv;
-
- variable testmatrix : alu_testv_array :=
- ( 0 => (-5, DIV, 3, -1),
- 1 => (7, ADD, 3, 10),
- 2 => (7, SUB, 1, 6),
- 3 => (7, DIV, 1, 7),
- 4 => (7, DIV, 3, 2),
- 5 => (7, ADD, 1, 8),
- 6 => (7, MUL, 3, 21),
- 7 => (-7, MUL, 3, -21),
- 8 => (268435456, MUL, -2, -536870912),
- 9 => (268435456, MUL, 2**5, 0), -- um fuenf nach links shiften
- 10 => (268435456 + 5, MUL, 2**5, 160), -- = 5 * (2^5)
- 11 => (100, DIV, 10, 10),
- 12 => (100, DIV, 51, 1),
- 13 => (100, DIV, 49, 2),
- 14 => (153156, DIV, 3543, 43),
- 15 => (-153156, DIV, 3543, -43),
- 16 => (153156, DIV, -3543, -43),
- 17 => (-153156, DIV, -3543, 43),
- others => (0, ADD, 0, 0)
- );
-
- begin
- sys_res_n <= '0';
- wait for 50 ns;
- sys_res_n <= '1';
-
- for i in testmatrix'range loop
- wait for 100 ns;
- \opcode.NOP\ <= '0';
- \opcode.SUB\ <= '0';
- \opcode.ADD\ <= '0';
- \opcode.MUL\ <= '0';
- \opcode.DIV\ <= '0';
- \opcode.DONE\ <= '0';
- op1 <= std_logic_vector(to_signed(testmatrix(i).o1,CBITS));
- case testmatrix(i).o is
- when NOP => \opcode.NOP\ <= '1';
- when SUB => \opcode.SUB\ <= '1';
- when ADD => \opcode.ADD\ <= '1';
- when MUL => \opcode.MUL\ <= '1';
- when DIV => \opcode.DIV\ <= '1';
- when DONE => \opcode.DONE\ <= '1';
- end case;
- op2 <= std_logic_vector(to_signed(testmatrix(i).o2,CBITS));
-
- -- berechnung kann los gehen
- do_calc <= '1';
-
- -- warten auf die alu einheit
- wait on calc_done;
-
- assert op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))
- report "" & cinteger'image(testmatrix(i).o1) &
- " " & alu_ops'image(opcode) &
- " " & cinteger'image(testmatrix(i).o2) &
- "/= " & integer'image(to_integer(signed(op3))) &
- " -- erwartet: " & cinteger'image(testmatrix(i).expected);
-
- wait for 5 ns;
- -- ack it!
- do_calc <= '0';
- end loop;
-
- assert false
- report "alle testfaelle der ALU waren erfolgreich!";
- stop <= true;
- wait;
- end process;
-end architecture sim;
--- /dev/null
+#alias fuer simulation neustarten
+alias rr "restart -f"
+
+#signale hinzufuegen
+add wave sys_clk
+add wave sys_res_n
+add wave op1
+add wave opcode
+add wave op2
+add wave op3
+add wave do_calc
+add wave calc_done
+
+#rauszoomen
+wave zoomout 500.0
+
+#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
+run -all
+
+#ganz nach links scrollen
+wave seetime 0
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity beh_alu_tb is
+end entity beh_alu_tb;
+
+architecture sim of beh_alu_tb is
+ component alu is
+ port
+ (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ opcode : in alu_ops;
+ op1 : in csigned;
+ op2 : in csigned;
+ op3 : out csigned;
+ do_calc : in std_logic;
+ calc_done : out std_logic
+ );
+ end component alu;
+
+ signal sys_clk, sys_res_n, do_calc, calc_done : std_logic;
+ signal opcode : alu_ops;
+ signal op1, op2, op3 : csigned;
+ signal stop : boolean := false;
+begin
+ inst : alu
+ port map
+ (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ do_calc => do_calc,
+ calc_done => calc_done,
+ op1 => op1,
+ op2 => op2,
+ op3 => op3,
+ opcode => opcode
+ );
+
+ process
+ begin
+ sys_clk <= '0';
+ wait for 15 ns;
+ sys_clk <= '1';
+ wait for 15 ns;
+ if stop = true then
+ wait;
+ end if;
+ end process;
+
+ process
+ type alu_testv is record
+ o1 : cinteger;
+ o : alu_ops;
+ o2 : cinteger;
+ expected : cinteger;
+ end record alu_testv;
+
+ -- ggf. groesse des arrays erhoehen
+ type alu_testv_array is array (natural range 0 to 20) of alu_testv;
+
+ variable testmatrix : alu_testv_array :=
+ ( 0 => (-5, DIV, 3, -1),
+ 1 => (7, ADD, 3, 10),
+ 2 => (7, SUB, 1, 6),
+ 3 => (7, DIV, 1, 7),
+ 4 => (7, DIV, 3, 2),
+ 5 => (7, ADD, 1, 8),
+ 6 => (7, MUL, 3, 21),
+ 7 => (-7, MUL, 3, -21),
+ 8 => (268435456, MUL, -2, -536870912),
+ 9 => (268435456, MUL, 2**5, 0), -- um fuenf nach links shiften
+ 10 => (268435456 + 5, MUL, 2**5, 160), -- = 5 * (2^5)
+ 11 => (100, DIV, 10, 10),
+ 12 => (100, DIV, 51, 1),
+ 13 => (100, DIV, 49, 2),
+ 14 => (153156, DIV, 3543, 43),
+ 15 => (-153156, DIV, 3543, -43),
+ 16 => (153156, DIV, -3543, -43),
+ 17 => (-153156, DIV, -3543, 43),
+ others => (0, ADD, 0, 0)
+ );
+
+ begin
+ sys_res_n <= '0';
+ wait for 50 ns;
+ sys_res_n <= '1';
+
+ for i in testmatrix'range loop
+ wait for 100 ns;
+ op1 <= to_signed(testmatrix(i).o1,CBITS);
+ opcode <= testmatrix(i).o;
+ op2 <= to_signed(testmatrix(i).o2,CBITS);
+
+ -- berechnung kann los gehen
+ do_calc <= '1';
+
+ -- warten auf die alu einheit
+ wait on calc_done;
+
+ assert op3 = to_signed(testmatrix(i).expected,CBITS)
+ report "" & cinteger'image(testmatrix(i).o1) &
+ " " & alu_ops'image(opcode) &
+ " " & cinteger'image(testmatrix(i).o2) &
+ "/= " & integer'image(to_integer(op3)) &
+ " -- erwartet: " & cinteger'image(testmatrix(i).expected);
+
+ wait for 5 ns;
+ -- ack it!
+ do_calc <= '0';
+ end loop;
+
+ assert false
+ report "alle testfaelle der ALU waren erfolgreich!";
+ stop <= true;
+ wait;
+ end process;
+end architecture sim;
--- /dev/null
+#alias fuer simulation neustarten
+alias rr "restart -f"
+
+#signale hinzufuegen
+add wave sys_clk
+add wave sys_res_n
+add wave op1
+add wave opcode
+add wave op2
+add wave op3
+add wave do_calc
+add wave calc_done
+add wave \\opcode.NOP\\
+add wave \\opcode.SUB\\
+add wave \\opcode.ADD\\
+add wave \\opcode.MUL\\
+add wave \\opcode.DIV\\
+add wave \\opcode.DONE\\
+
+#rauszoomen
+wave zoomout 500.0
+
+#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
+run -all
+
+#ganz nach links scrollen
+wave seetime 0
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity post_alu_tb is
+end entity post_alu_tb;
+
+architecture sim of post_alu_tb is
+ component alu is
+ port
+ (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ \opcode.NOP\ : in std_logic;
+ \opcode.SUB\ : in std_logic;
+ \opcode.ADD\ : in std_logic;
+ \opcode.MUL\ : in std_logic;
+ \opcode.DIV\ : in std_logic;
+ \opcode.DONE\ : in std_logic;
+ op1 : in std_logic_vector(31 downto 0);
+ op2 : in std_logic_vector(31 downto 0);
+ op3 : out std_logic_vector(31 downto 0);
+ do_calc : in std_logic;
+ calc_done : out std_logic
+ );
+ end component alu;
+
+ signal sys_clk, sys_res_n, do_calc, calc_done : std_logic;
+ signal opcode : alu_ops;
+ signal \opcode.NOP\ : std_logic;
+ signal \opcode.SUB\ : std_logic;
+ signal \opcode.ADD\ : std_logic;
+ signal \opcode.MUL\ : std_logic;
+ signal \opcode.DIV\ : std_logic;
+ signal \opcode.DONE\ : std_logic;
+ signal op1, op2, op3 : std_logic_vector(31 downto 0);
+ signal stop : boolean := false;
+begin
+ inst : alu
+ port map
+ (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ do_calc => do_calc,
+ calc_done => calc_done,
+ op1 => op1,
+ op2 => op2,
+ op3 => op3,
+ \opcode.NOP\ => \opcode.NOP\,
+ \opcode.SUB\ => \opcode.SUB\,
+ \opcode.ADD\ => \opcode.ADD\,
+ \opcode.MUL\ => \opcode.MUL\,
+ \opcode.DIV\ => \opcode.DIV\,
+ \opcode.DONE\ => \opcode.DONE\
+ );
+
+ process
+ begin
+ sys_clk <= '0';
+ wait for 15 ns;
+ sys_clk <= '1';
+ wait for 15 ns;
+ if stop = true then
+ wait;
+ end if;
+ end process;
+
+ process
+ type alu_testv is record
+ o1 : cinteger;
+ o : alu_ops;
+ o2 : cinteger;
+ expected : cinteger;
+ end record alu_testv;
+
+ -- ggf. groesse des arrays erhoehen
+ type alu_testv_array is array (natural range 0 to 20) of alu_testv;
+
+ variable testmatrix : alu_testv_array :=
+ ( 0 => (-5, DIV, 3, -1),
+ 1 => (7, ADD, 3, 10),
+ 2 => (7, SUB, 1, 6),
+ 3 => (7, DIV, 1, 7),
+ 4 => (7, DIV, 3, 2),
+ 5 => (7, ADD, 1, 8),
+ 6 => (7, MUL, 3, 21),
+ 7 => (-7, MUL, 3, -21),
+ 8 => (268435456, MUL, -2, -536870912),
+ 9 => (268435456, MUL, 2**5, 0), -- um fuenf nach links shiften
+ 10 => (268435456 + 5, MUL, 2**5, 160), -- = 5 * (2^5)
+ 11 => (100, DIV, 10, 10),
+ 12 => (100, DIV, 51, 1),
+ 13 => (100, DIV, 49, 2),
+ 14 => (153156, DIV, 3543, 43),
+ 15 => (-153156, DIV, 3543, -43),
+ 16 => (153156, DIV, -3543, -43),
+ 17 => (-153156, DIV, -3543, 43),
+ others => (0, ADD, 0, 0)
+ );
+
+ begin
+ sys_res_n <= '0';
+ wait for 50 ns;
+ sys_res_n <= '1';
+
+ for i in testmatrix'range loop
+ wait for 100 ns;
+ \opcode.NOP\ <= '0';
+ \opcode.SUB\ <= '0';
+ \opcode.ADD\ <= '0';
+ \opcode.MUL\ <= '0';
+ \opcode.DIV\ <= '0';
+ \opcode.DONE\ <= '0';
+ op1 <= std_logic_vector(to_signed(testmatrix(i).o1,CBITS));
+ case testmatrix(i).o is
+ when NOP => \opcode.NOP\ <= '1';
+ when SUB => \opcode.SUB\ <= '1';
+ when ADD => \opcode.ADD\ <= '1';
+ when MUL => \opcode.MUL\ <= '1';
+ when DIV => \opcode.DIV\ <= '1';
+ when DONE => \opcode.DONE\ <= '1';
+ end case;
+ op2 <= std_logic_vector(to_signed(testmatrix(i).o2,CBITS));
+
+ -- berechnung kann los gehen
+ do_calc <= '1';
+
+ -- warten auf die alu einheit
+ wait on calc_done;
+
+ assert op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))
+ report "" & cinteger'image(testmatrix(i).o1) &
+ " " & alu_ops'image(opcode) &
+ " " & cinteger'image(testmatrix(i).o2) &
+ "/= " & integer'image(to_integer(signed(op3))) &
+ " -- erwartet: " & cinteger'image(testmatrix(i).expected);
+
+ wait for 5 ns;
+ -- ack it!
+ do_calc <= '0';
+ end loop;
+
+ assert false
+ report "alle testfaelle der ALU waren erfolgreich!";
+ stop <= true;
+ wait;
+ end process;
+end architecture sim;
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