added initial uart_rx files, not exaustively tested though.

diff --git a/src/beh_uart_rx.do b/src/beh_uart_rx.do
deleted file mode 100644 (file)
index 4f70701..0000000
--- a/src/beh_uart_rx.do
+++ /dev/null
@@ -1,56 +0,0 @@
-#alias fuer simulation neustarten
-alias rr "restart -f"
-
-#signale hinzufuegen
-add wave inst/*
-
-delete wave /beh_parser_tb/inst/op1_int
-delete wave /beh_parser_tb/inst/op1
-delete wave /beh_parser_tb/inst/op1_next
-add wave -radix decimal inst/op1_int
-
-delete wave /beh_parser_tb/inst/op2_int
-delete wave /beh_parser_tb/inst/op2
-delete wave /beh_parser_tb/inst/op2_next
-add wave -radix decimal inst/op2_int
-
-delete wave /beh_parser_tb/inst/op3
-add wave -radix decimal inst/op3
-delete wave /beh_parser_tb/inst/opM
-add wave -radix decimal inst/opM
-
-delete wave /beh_parser_tb/inst/z_int
-delete wave /beh_parser_tb/inst/z_next
-add wave -radix decimal inst/z_int
-add wave -radix decimal inst/z_next
-
-delete wave /beh_parser_tb/inst/strich_int
-delete wave /beh_parser_tb/inst/strich_next
-add wave -radix decimal inst/strich_int
-add wave -radix decimal inst/strich_next
-
-delete wave /beh_parser_tb/inst/punkt_int
-delete wave /beh_parser_tb/inst/punkt_next
-add wave -radix decimal inst/punkt_int
-add wave -radix decimal inst/punkt_next
-
-delete wave /beh_parser_tb/inst/wtmp_int
-delete wave /beh_parser_tb/inst/wtmp_next
-add wave -radix decimal inst/wtmp_int
-add wave -radix decimal inst/wtmp_next
-
-delete wave /beh_parser_tb/inst/p_write_int
-delete wave /beh_parser_tb/inst/p_write_next
-delete wave /beh_parser_tb/inst/p_write
-add wave -hex inst/p_write_int
-add wave -hex inst/p_write_next
-
-
-#rauszoomen
-wave zoomout 500.0
-
-#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
-run -all
-
-#ganz nach links scrollen
-wave seetime 0

diff --git a/src/beh_uart_rx.vhd b/src/beh_uart_rx.vhd
deleted file mode 100644 (file)
index c3394ce..0000000
--- a/src/beh_uart_rx.vhd
+++ /dev/null
@@ -1,57 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.gen_pkg.all;
-
-entity beh_uart_rx_tb is
-end entity beh_uart_rx_tb;
-
-architecture sim of beh_uart_rx_tb is
-
-       constant clk_period  : time := 2ns;
-       signal clock : std_logic;
-       signal reset : std_logic;
-       signal done : std_logic;
-       signal newsig : std_logic;
-       signal data : std_logic_vector(7 downto 0);
-       signal serial_out : std_logic;
-begin
-       inst : entity work.uart_tx(beh)
-       port map (
-               sys_clk => clock,
-               sys_res => reset,
-               txd => serial_out,
-               tx_data => data,
-               tx_new => newsig,
-               tx_done => done
-       );
-
-       stimuli : process
-       begin
-               newsig <= '0';
-               wait for 10ns;
-               --send 'Hallo Welt'
-               data <= X"42"; --'B'
-               newsig <= '1';
-               wait for 1000ns;
-
-               assert false report "Test finished" severity failure;
-       end process stimuli;
-
-       res_gen : process
-       begin
-               reset <= '0';
-               wait for 20ns;
-               reset <= '1';
-               wait for 1000ns;
-       end process res_gen;
-
-       clock_gen : process
-       begin
-               clock <= '0';
-               wait for clk_period/2;
-               clock <= '1';
-               wait for clk_period/2;
-       end process clock_gen;
-
-end sim;

diff --git a/src/beh_uart_rx_tb.do b/src/beh_uart_rx_tb.do
new file mode 100644 (file)
index 0000000..4f70701
--- /dev/null
+++ b/src/beh_uart_rx_tb.do
@@ -0,0 +1,56 @@
+#alias fuer simulation neustarten
+alias rr "restart -f"
+
+#signale hinzufuegen
+add wave inst/*
+
+delete wave /beh_parser_tb/inst/op1_int
+delete wave /beh_parser_tb/inst/op1
+delete wave /beh_parser_tb/inst/op1_next
+add wave -radix decimal inst/op1_int
+
+delete wave /beh_parser_tb/inst/op2_int
+delete wave /beh_parser_tb/inst/op2
+delete wave /beh_parser_tb/inst/op2_next
+add wave -radix decimal inst/op2_int
+
+delete wave /beh_parser_tb/inst/op3
+add wave -radix decimal inst/op3
+delete wave /beh_parser_tb/inst/opM
+add wave -radix decimal inst/opM
+
+delete wave /beh_parser_tb/inst/z_int
+delete wave /beh_parser_tb/inst/z_next
+add wave -radix decimal inst/z_int
+add wave -radix decimal inst/z_next
+
+delete wave /beh_parser_tb/inst/strich_int
+delete wave /beh_parser_tb/inst/strich_next
+add wave -radix decimal inst/strich_int
+add wave -radix decimal inst/strich_next
+
+delete wave /beh_parser_tb/inst/punkt_int
+delete wave /beh_parser_tb/inst/punkt_next
+add wave -radix decimal inst/punkt_int
+add wave -radix decimal inst/punkt_next
+
+delete wave /beh_parser_tb/inst/wtmp_int
+delete wave /beh_parser_tb/inst/wtmp_next
+add wave -radix decimal inst/wtmp_int
+add wave -radix decimal inst/wtmp_next
+
+delete wave /beh_parser_tb/inst/p_write_int
+delete wave /beh_parser_tb/inst/p_write_next
+delete wave /beh_parser_tb/inst/p_write
+add wave -hex inst/p_write_int
+add wave -hex inst/p_write_next
+
+
+#rauszoomen
+wave zoomout 500.0
+
+#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
+run -all
+
+#ganz nach links scrollen
+wave seetime 0

diff --git a/src/beh_uart_rx_tb.vhd b/src/beh_uart_rx_tb.vhd
new file mode 100644 (file)
index 0000000..bca920a
--- /dev/null
+++ b/src/beh_uart_rx_tb.vhd
@@ -0,0 +1,57 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity beh_uart_rx_tb is
+end entity beh_uart_rx_tb;
+
+architecture sim of beh_uart_rx_tb is
+
+       constant clk_period : time := 2ns;
+       signal clock : std_logic;
+       signal reset : std_logic;
+       signal done : std_logic;
+       signal newsig : std_logic;
+       signal data : std_logic_vector(7 downto 0);
+       signal serial_in: std_logic;
+begin
+       inst : entity work.uart_rx(beh)
+       port map (
+               sys_clk => clock,
+               sys_res => reset,
+               txd => serial_in,
+               tx_data => data,
+               tx_new => newsig
+       );
+
+       stimuli : process
+       begin
+               serial_in <= '0';
+               wait for 10ns;
+               --send 'Hallo Welt'
+               serial_in <= '1';
+               wait for clk_period;
+               serial_in <= '0';
+               wait for 1000ns;
+
+               assert false report "Test finished" severity failure;
+       end process stimuli;
+
+       res_gen : process
+       begin
+               reset <= '0';
+               wait for 20ns;
+               reset <= '1';
+               wait for 1000ns;
+       end process res_gen;
+
+       clock_gen : process
+       begin
+               clock <= '0';
+               wait for clk_period/2;
+               clock <= '1';
+               wait for clk_period/2;
+       end process clock_gen;
+
+end sim;

diff --git a/src/uart_rx.vhd b/src/uart_rx.vhd
index 90dcedc4a5160bcbf2ff61cf3c54f4be1e20c406..e36b5c583b5b3e76afc6d924cb821a5ab1329ba7 100644 (file)
--- a/src/uart_rx.vhd
+++ b/src/uart_rx.vhd
@@ -1,11 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
---use work.gen_pkg.all;
-
---package int_types is
---     type STATE_UART_RX is (IDLE, BUSY, DONE);
---end package int_types;
+use work.gen_pkg.all;
 
 entity uart_rx is
 port(
@@ -13,30 +9,39 @@ port(
        sys_res : in std_logic;
        txd : in std_logic; -- warning: this is asynchronous input!
        tx_data : out std_logic_vector(7 downto 0); -- map this to a larger register with containing input
-       tx_new : out std_logic;
+       tx_new : out std_logic
 );
 end entity uart_rx;
 
 architecture beh of uart_rx is
        constant timer_max : integer := 35;
 
+       type STATE_UART_RX is (IDLE, BUSY, DONE);
+
        signal timer, timer_next : integer range 0 to 65535;
        signal counter, counter_next : integer range 0 to 15;
        signal state, state_next : STATE_UART_RX;
-       signal tx_data_pref : std_logic_vector(7 downto 0); -- FIXME: this isnt named next so that the interface isn't called tx_data_next ...
+       signal tx_data_prev : std_logic_vector(7 downto 0); -- FIXME: this isnt named next so that the interface isn't called tx_data_next ...
 
+       -- these are internal signals that are actually used as in and output
+       signal tx_data_i : std_logic_vector(7 downto 0);
+       signal tx_new_i : std_logic;
 begin
 --FIXME:
-       process(sys_clk, sys_res_n)
-               begin
-               if sys_res_n = ‘0‘ then
+
+       tx_new <= tx_new_i;
+       tx_data <= tx_data_i;
+
+       process(sys_clk, sys_res)
+       begin
+               if (sys_res = '0') then
                        -- Set reset state
                        state <= IDLE;
-                       tx_data_prev <= X"0";
+                       tx_data_prev <= X"00";
                elsif rising_edge(sys_clk) then
                        -- Store next state
                        state <= state_next;
-                       tx_data_prev <= tx_data;
+                       tx_data_prev <= tx_data_i;
                end if;
        end process;
 
@@ -45,7 +50,7 @@ begin
                state_next <= state;
                case state is
                        when IDLE =>
-                               if (txd = 0) then
+                               if (txd = '0') then
                                        state_next <= BUSY;
                                else
                                        state_next <= IDLE;
@@ -65,21 +70,18 @@ begin
        begin
                -- Set default values
                -- for the outputs
-               tx_new <= ‘0‘;
+               tx_new_i <= '0';
 
                -- Calculate the outputs
                -- based on the current
                -- state
                case state is
                        when IDLE =>
-                               tx_new <= ‘0‘;
+                               tx_new_i <= '0';
                        when BUSY =>
-                               tx_new <= ‘0‘;
-                               case (counter)
-                                       tx_data(counter-2) <= txd;
-                               end case;
+                               tx_new_i <= '0';
                        when DONE =>
-                               tx_new <= '1';
+                               tx_new_i <= '1';
                end case;
        end process;
 -- END FIXME: do fill this out CORRECTLY
@@ -95,7 +97,7 @@ begin
                end if;
        end process;
 
-       process(timer)
+       process (timer)
        begin
                if (timer = timer_max) then
                        timer_next <= 0;
@@ -104,9 +106,9 @@ begin
                end if;
        end process;
 
-       process (timer, counter, tx_new)
+       process (timer, counter, tx_new_i)
        begin
-               if (tx_new = '1') then
+               if (tx_new_i = '1') then
                        if (timer = timer_max) then
                                if (counter > 10) then
                                        counter_next <= 0;
@@ -123,28 +125,28 @@ begin
 
        process (counter, txd)
        begin
-               tx_data <= tx_data_prev;
+               tx_data_i <= tx_data_prev;
                -- TODO: we probably want oversampling and averaging + failure!
                -- FIXME: this is per se not synthesisable
                case (counter) is
                        when 0 => --start bit
                                assert (txd = '0');
                        when 1 =>
-                               tx_data(0) <= txd;
+                               tx_data_i(0) <= txd;
                        when 2 =>
-                               tx_data(1) <= txd;
+                               tx_data_i(1) <= txd;
                        when 3 =>
-                               tx_data(2) <= txd;
+                               tx_data_i(2) <= txd;
                        when 4 =>
-                               tx_data(3) <= txd;
+                               tx_data_i(3) <= txd;
                        when 5 =>
-                               tx_data(4) <= txd;
+                               tx_data_i(4) <= txd;
                        when 6 =>
-                               tx_data(5) <= txd;
+                               tx_data_i(5) <= txd;
                        when 7 =>
-                               tx_data(6) <= txd;
+                               tx_data_i(6) <= txd;
                        when 8 =>
-                               tx_data(7) <= txd;
+                               tx_data_i(7) <= txd;
                        when 9 => -- stop bit
                                assert (txd = '1');
                        when others => -- idle
@@ -152,6 +154,4 @@ begin
                end case;
        end process;
 
-       tx_done <= '0';
-
 end architecture beh;