spartan3e: pinmapping fuer uart

diff --git a/spartan3e/Makefile b/spartan3e/Makefile
index dd3a8acebc277ab3a6f848d3e320a97ee63bb0a6..0ce3e189425e2ffcda5698b44060da105be70659 100644 (file)
--- a/spartan3e/Makefile
+++ b/spartan3e/Makefile
@@ -12,6 +12,8 @@ PROJ_VHDL = alu.vhd \
        parser.vhd \
        scanner.vhd \
        sp_ram.vhd \
+       uart_rx.vhd \
+       uart_tx.vhd \
        textmode_vga/console_sm.vhd \
        textmode_vga/console_sm_beh.vhd \
        textmode_vga/console_sm_sync.vhd \
@@ -36,7 +38,20 @@ PROJ_VHDL = alu.vhd \
        ps2/ps2_keyboard_controller_pkg.vhd \
        ps2/ps2_transceiver.vhd \
        ps2/ps2_transceiver_beh.vhd \
-       ps2/ps2_transceiver_pkg.vhd
+       ps2/ps2_transceiver_pkg.vhd \
+       debouncing/counter.vhd \
+       debouncing/counter_beh.vhd \
+       debouncing/debounce.vhd \
+       debouncing/debounce_fsm.vhd \
+       debouncing/debounce_fsm_beh.vhd \
+       debouncing/debounce_pkg.vhd \
+       debouncing/debounce_struct.vhd \
+       debouncing/event_counter.vhd \
+       debouncing/event_counter_beh.vhd \
+       debouncing/event_counter_pkg.vhd \
+       debouncing/sync.vhd \
+       debouncing/sync_beh.vhd \
+       debouncing/sync_pkg.vhd
 
 PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
 

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
index fc193cd85267cccb69e54683dd34b31b4b4d4f49..5e47e3b741cf984b7705cdf9ef52748e145cb132 100644 (file)
--- a/spartan3e/spartan3e.ucf
+++ b/spartan3e/spartan3e.ucf
@@ -129,8 +129,8 @@ NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %;
 #NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 # ==== Discrete LEDs (LED) ====
 # These are shared connections with the FX2 connector
-NET "LED0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
 #NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
 #NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
 #NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
@@ -145,8 +145,8 @@ NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
 #NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
 #NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
 # ==== RS-232 Serial Ports (RS232) ====
-#NET "RS232_DCE_RXD" LOC = "F8" | IOSTANDARD = LVTTL ;
-#NET "RS232_DCE_TXD" LOC = "E8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+NET "rxd" LOC = "E8" | IOSTANDARD = LVTTL ;
+NET "txd" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
 #NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
 #NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
 # ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)

diff --git a/src/TODO b/src/TODO
index f71752a73b4df4c12b5c35db201e1719f788713a..e1a0f19be6714f0e262b89299f3a9fbc5ced5bbf 100644 (file)
--- a/src/TODO
+++ b/src/TODO
@@ -1,16 +1,9 @@
-- debounce fuer sys_res_n und btnA -- einfach die debounce entity vom example
-  hernehmen
+- debounce fuer btnA -- einfach die debounce entity vom example hernehmen
 
 
 - rs232/pc-kommunikation: RAM dumpen
 
 
-- uart rx oversampling, uart rx synchronizen (vlg. debouncing/sync*.vhd)
-
-
-- postlayout: nochmal testen obs im tilab wirklich ned geht.
-
-
 - gen_pkg: unsigned fuer hspalte, hzeile
 
 == BUGS ==
@@ -27,6 +20,8 @@
 - wie detailiert muessen die screenshots der simulationen sein?
 - warum ist auf seite 14 im foliensatz "VHDL_Architecture" "directly at
   instantation" durchgestrichen? :/ (wird so ziemlich ueberall verwendet hier)
+- postlayout: geht im tilab nicht... reicht screenshot?
+
 
 
 == FAQ =

diff --git a/src/calc.vhd b/src/calc.vhd
index bd4e903f80c51dd859479a9dd96270054c6309a0..2175ee932086b666c40f8f46c77cfa78d855c23e 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -65,7 +65,6 @@ architecture top of calc is
        signal rx_data : std_logic_vector (7 downto 0);
        signal tx_new, tx_done : std_logic;
        signal tx_data : std_logic_vector (7 downto 0);
-       signal txd_out : std_logic;
 begin
        -- vga/ipcore
        textmode_vga_inst : entity work.textmode_vga(struct)
@@ -248,7 +247,7 @@ begin
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
-               txd => txd_out,
+               txd => txd,
                tx_data => tx_data,
                tx_new => tx_new,
                tx_done => tx_done

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index c43749d699d003a3243024e65159bc9dd5d3d3fc..040034ad3ec94bd49496f72f503241d0cd7d12b4 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -6,6 +6,7 @@ use work.textmode_vga_component_pkg.all;
 use work.textmode_vga_pkg.all;
 use work.textmode_vga_platform_dependent_pkg.all;
 use work.ps2_keyboard_controller_pkg.all;
+use work.sync_pkg.all;
 
 entity calc is
        port (
@@ -14,7 +15,8 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               -- TODO: pins
+               rxd : in std_logic;
+               txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
                hsync_n : out std_logic;
@@ -23,10 +25,7 @@ entity calc is
                b : out std_logic_vector(BLUE_BITS - 1 downto 0);
                -- ps/2
                ps2_clk : inout std_logic;
-               ps2_data : inout std_logic;
-               -- debug
-               led0 : out std_logic;
-               led1 : out std_logic
+               ps2_data : inout std_logic
        );
 end entity calc;
 
@@ -60,9 +59,12 @@ architecture top of calc is
        signal p_finished : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
+       -- rs232
+       signal rx_new, rxd_sync : std_logic;
+       signal rx_data : std_logic_vector (7 downto 0);
+       signal tx_new, tx_done : std_logic;
+       signal tx_data : std_logic_vector (7 downto 0);
 begin
-       led0 <= '0';
-       led1 <= '1';
        sys_res_n <= not sys_res;
 
        -- vga/ipcore
@@ -194,4 +196,46 @@ begin
                ps2_clk => ps2_clk,
                ps2_data => ps2_data
        );
+
+       -- synchronizer fuer rxd
+       sync_rxd_inst : entity work.sync(beh)
+       generic map (
+               SYNC_STAGES => 2,
+               RESET_VALUE => '1'
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               data_in => rxd,
+               data_out => rxd_sync
+       );
+
+       -- rs232-rx
+       rs232rx_inst : entity work.uart_rx(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               rxd => rxd_sync,
+               rx_data => rx_data,
+               rx_new => rx_new
+       );
+
+       -- rs232-tx
+       rs232tx_inst : entity work.uart_tx(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
+       );
 end architecture top;