+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity parser is
+ port
+ (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- History
+ p_rw : out std_logic;
+ p_spalte : out hspalte;
+ p_rget : out std_logic;
+ p_rdone : in std_logic;
+ p_read : in hbyte;
+ p_wtake : out std_logic;
+ p_wdone : in std_logic;
+ p_write : out hbyte;
+ p_finished : out std_logic;
+ -- ALU
+ opcode : out alu_ops;
+ op1 : out csigned;
+ op2 : out csigned;
+ op3 : in csigned;
+ do_calc : out std_logic;
+ calc_done : in std_logic;
+ -- TODO: calc_error : in std_logic;
+ -- Scanner
+ do_it : in std_logic;
+ finished : out std_logic
+ );
+end entity parser;
+
+architecture beh of parser is
+ type PARSER_STATE is (SIDLE, SREAD_CHAR1, SREAD_CHAR2, SWRITE_CHAR);
+ signal state_int, state_next : PARSER_STATE;
+ signal z_int, z_next : csigned;
+ signal rbyte_int, rbyte_next : hbyte;
+ signal p_write_int, p_write_next : hbyte;
+ signal p_rget_int, p_rget_next : std_logic;
+ signal p_wtake_int, p_wtake_next : std_logic;
+ signal p_finished_int, p_finished_next : std_logic;
+begin
+ p_write <= p_write_int;
+ p_rget <= p_rget_int;
+ p_wtake <= p_wtake_int;
+ p_finished <= p_finished_int;
+
+ process(sys_clk, sys_res_n)
+ begin
+ if sys_res_n = '0' then
+ state_int <= SIDLE;
+ z_int <= (others => '0');
+ rbyte_int <= (others => '0');
+ -- out ports
+ p_rw <= '0';
+ p_spalte <= (others => '0');
+ p_rget_int <= '0';
+ p_write_int <= (others => '0');
+ p_wtake_int <= '0';
+ p_finished_int <= '0';
+ opcode <= ALU_NOP;
+ op1 <= (others => '0');
+ op2 <= (others => '0');
+ do_calc <= '0';
+ finished <= '0';
+ elsif rising_edge(sys_clk) then
+ -- internal
+ state_int <= state_next;
+ z_int <= z_next;
+ rbyte_int <= rbyte_next;
+ -- out ports
+ p_rget_int <= p_rget_next;
+ p_write_int <= p_write_next;
+ p_wtake_int <= p_wtake_next;
+ p_finished_int <= p_finished_next;
+ end if;
+ end process;
+
+ -- next state
+ process(state_int, do_it, p_rdone, p_wdone, p_read)
+ begin
+ state_next <= state_int;
+
+ case state_int is
+ when SIDLE =>
+ if do_it = '1' then
+ state_next <= SREAD_CHAR1;
+ end if;
+ when SREAD_CHAR1 =>
+ if p_rdone = '1' then
+ state_next <= SREAD_CHAR2;
+ end if;
+ when SREAD_CHAR2 =>
+ if p_wdone = '1' then
+ state_next <= SWRITE_CHAR;
+ end if;
+ when SWRITE_CHAR =>
+ if rbyte_int = hbyte(to_unsigned(character'pos(character'val(0)), 8)) then
+ if do_it = '0' then
+ state_next <= SIDLE;
+ end if;
+ else
+ state_next <= SREAD_CHAR1;
+ end if;
+ end case;
+ end process;
+
+ process(state_int, p_read, p_write_int, z_int, rbyte_int, p_rget_int)
+ begin
+ -- internal
+ z_next <= z_int;
+ rbyte_next <= rbyte_int;
+ -- signals
+ p_rget_next <= '0';
+ p_write_next <= p_write_int;
+ p_wtake_next <= '0';
+ p_finished_next <= '0';
+
+ case state_int is
+ when SIDLE =>
+ z_next <= (others => '0');
+ rbyte_next <= (others => '0');
+ p_write_next <= (others => '0');
+ when SREAD_CHAR1 =>
+ p_rget_next <= '1';
+ p_write_next <= (others => '0');
+ when SREAD_CHAR2 =>
+ rbyte_next <= p_read;
+ p_wtake_next <= '1';
+ p_write_next <= p_read;
+ when SWRITE_CHAR =>
+ if rbyte_int = hbyte(to_unsigned(character'pos(character'val(0)), 8)) then
+ p_finished_next <= '1';
+ end if;
+ end case;
+ end process;
+end architecture beh;