parser: alu als eigene instanz im parser

diff --git a/spec/speck.tex b/spec/speck.tex
index 96cbd6bc072fbfd0d62021a4aa188751d7d51991..c2e715f28bd1cf5702591e0c262abab6d9f5c064 100644 (file)
--- a/spec/speck.tex
+++ b/spec/speck.tex
@@ -619,6 +619,7 @@ jeweils im Modul Parser und History vertauscht.
 behandelt??)
 \item aussagekr\"aftigere Fehlermeldungen.
 \item ALU: signal \emph{opM} fuer restberechnung
+\item Parser: Signale der ALU bleiben intern.
 \end{itemize}
 
 \end{document}

diff --git a/src/beh_parser_tb.vhd b/src/beh_parser_tb.vhd
index 663e1bda455d58e5d1c0c500fa1d5168bb199adb..732f3642bdf5b354c0e9116c3be3a8b1953c9323 100644 (file)
--- a/src/beh_parser_tb.vhd
+++ b/src/beh_parser_tb.vhd
@@ -13,12 +13,6 @@ architecture sim of beh_parser_tb is
        signal p_rw, p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
        signal p_read, p_write : hbyte;
        signal p_spalte : hspalte;
-
-       -- alu
-       signal opcode : alu_ops;
-       signal op1, op2, op3, opM : csigned;
-       signal do_calc, calc_done, calc_error : std_logic;
-
        --scanner
        signal do_it : std_logic;
        signal finished : std_logic;
@@ -39,36 +33,11 @@ begin
                p_wdone => p_wdone,
                p_write => p_write,
                p_finished => p_finished,
-               -- ALU
-               opcode => opcode,
-               op1 => op1,
-               op2 => op2,
-               op3 => op3,
-               opM => opM,
-               do_calc => do_calc,
-               calc_done => calc_done,
-               calc_error => calc_error,
-               -- TODO: calc_error : in std_logic;
                -- Scanner
                do_it => do_it,
                finished => finished
        );
 
-       instalu : entity work.alu(beh)
-       port map
-       (
-               sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
-               do_calc => do_calc,
-               calc_done => calc_done,
-               calc_error => calc_error,
-               op1 => op1,
-               op2 => op2,
-               op3 => op3,
-               opM => opM,
-               opcode => opcode
-       );
-
        process
        begin
                sys_clk <= '0';

diff --git a/src/parser.vhd b/src/parser.vhd
index 1d75398bfc87454dbc5694abba14d4844d40722d..ec03fedc4e407f4c4ef9a98e68562b9422d501ed 100644 (file)
--- a/src/parser.vhd
+++ b/src/parser.vhd
@@ -18,15 +18,6 @@ entity parser is
                p_wdone : in std_logic;
                p_write : out hbyte;
                p_finished : out std_logic;
-               -- ALU
-               opcode : out alu_ops;
-               op1 : out csigned;
-               op2 : out csigned;
-               op3 : in csigned;
-               opM : in csigned;
-               do_calc : out std_logic;
-               calc_done : in std_logic;
-               calc_error : in std_logic;
                -- Scanner
                do_it : in std_logic;
                finished : out std_logic
@@ -59,7 +50,31 @@ architecture beh of parser is
        signal err_next, err_int : hstr_int;
        signal errc_next, errc_int : hstr_int;
        signal errc_tmp_next, errc_tmp_int : hstr_int;
+       -- ALU
+       signal opcode : alu_ops;
+       signal op1 : csigned;
+       signal op2 : csigned;
+       signal op3 : csigned;
+       signal opM : csigned;
+       signal do_calc : std_logic;
+       signal calc_done : std_logic;
+       signal calc_error : std_logic;
 begin
+       instalu : entity work.alu(beh)
+       port map
+       (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               do_calc => do_calc,
+               calc_done => calc_done,
+               calc_error => calc_error,
+               op1 => op1,
+               op2 => op2,
+               op3 => op3,
+               opM => opM,
+               opcode => opcode
+       );
+
        p_write <= p_write_int;
        p_rget <= p_rget_int;
        p_wtake <= p_wtake_int;