architecture sim of beh_pc_communication_tb is
type byte_file_type is file of hbyte;
+ subtype my_string is string(1 to 720);
signal sys_clk : std_logic;
signal sys_res_n : std_logic;
signal btn_a : std_logic;
end process clk;
stub_history : process
- file f : byte_file_type open read_mode is "../../src/pc_communication.test";
- variable rb : hbyte;
+ file f : text open read_mode is "../../src/pc_communication.test";
+ --variable rb : hbyte;
+ variable rb : character;
+ variable good : boolean;
+ variable i : integer;
+ variable buf : my_string;
+ variable l : line;
begin
- d_done <= '0';
- wait until rising_edge(d_get);
+ --take control of the situation.
+ d_char <= (others => '0');
+ wait until sys_res_n = '1';
+
+ while not endfile (f) loop
+ readline(f, l);
+ i := 1;
+ while i < l'length loop
+ wait until rising_edge(d_get);
+ d_done <= '0';
+ d_char <= (others => '0');
+ wait for 90 ns;
+
+ d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+ d_done <= '1';
+ wait for 30 ns;
+
+ end loop;
+ end loop;
+
assert not endfile(f) report "test beendet" severity failure;
- read(f, rb);
- wait for 30 ns;
- d_char <= rb;
- d_done <= '1';
- wait for 30 ns;
end process stub_history;
-
stub_uart : process
begin
tx_done <= '0';
- wait until rising_edge(tx_new);
- wait for 90 ns;
- tx_done <= '1'; -- FIXME: why is this unresolved?
- wait for 30 ns;
+ while true loop
+ wait until sys_res_n = '1';
+
+ wait until rising_edge(tx_new);
+ tx_done <= '0';
+ wait for 300 ns;
+ tx_done <= '1';
+ wait for 30 ns;
+ end loop;
end process stub_uart;
reset_and_button : process
-- we only simulate pressing of button a by now!
sys_res_n <= '0';
btn_a <= '0';
- tx_data <= "00000000";
- rx_data <= "00000000";
- d_zeile <= "0000000";
- d_spalte <= "0000000";
- tx_done <= '0';
+ tx_data <= ( others => '0');
+ rx_data <= ( others => '0');
+ d_zeile <= ( others => '0');
+ d_spalte <= ( others => '0');
rx_new <= '0';
- d_char <= (others => '0');
wait for 90 ns;
sys_res_n <= '1';
btn_a <= '1';
wait for 15 ns;
btn_a <= '0';
- --wait;
- wait for 1000 ns;
- assert false report "test beendet" severity failure;
+ wait;
+ --wait for 1000 ns;
+ --assert false report "test beendet" severity failure;
end process reset_and_button;
end architecture sim;
signal get, get_next : std_logic;
signal new_i, new_i_next : std_logic;
signal tx_done_i, tx_done_i_next : std_logic;
- signal d_done_i, d_done_i_next : std_logic;
+ signal d_done_i : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
char_next <= d_char;
tx_new <= new_i;
d_done_i <= d_done;
- tx_done_i <= tx_done;
+ tx_done_i_next <= tx_done;
sync: process (sys_clk, sys_res_n)
begin
new_i <= '0';
tx_data <= "00000000";
spalte_up <= '0';
+ tx_done_i <= '0';
elsif rising_edge(sys_clk) then
push_history <= push_history_next;
spalte <= spalte_next;
state <= state_next;
get <= get_next;
new_i <= new_i_next;
+ tx_done_i <= tx_done_i_next;
spalte_up <= spalte_up_next;
if (char_en = '1') then
char <= char_next;
end if;
end process async_push_history;
- output_pc : process (state, zeile, spalte, char)
+ output_pc : process (state, zeile, spalte, char, tx_done_i)
begin
get_next <= '0';
new_i_next <= '0';
char_en <= '0';
tx_data <= char;
new_i_next <= '1';
- if (tx_done = '1') then
+ if (tx_done_i = '1') then
spalte_up_next <= '1';
end if;
when DONE =>
end case;
end process output_pc;
- next_state_pc : process (rx_new, btn_a, d_done, tx_done)
+ next_state_pc : process (rx_new, btn_a, d_done, tx_done_i)
begin
case state is
when IDLE =>
state_next <= FORWARD;
end if;
when FORWARD =>
- if (tx_done = '1') then
+ if (tx_done_i = '1') then
state_next <= FETCH;
end if;
when DONE =>