parser.vhd \
scanner.vhd \
sp_ram.vhd \
+ uart_rx.vhd \
+ uart_tx.vhd \
textmode_vga/console_sm.vhd \
textmode_vga/console_sm_beh.vhd \
textmode_vga/console_sm_sync.vhd \
ps2/ps2_keyboard_controller_pkg.vhd \
ps2/ps2_transceiver.vhd \
ps2/ps2_transceiver_beh.vhd \
- ps2/ps2_transceiver_pkg.vhd
+ ps2/ps2_transceiver_pkg.vhd \
+ debouncing/counter.vhd \
+ debouncing/counter_beh.vhd \
+ debouncing/debounce.vhd \
+ debouncing/debounce_fsm.vhd \
+ debouncing/debounce_fsm_beh.vhd \
+ debouncing/debounce_pkg.vhd \
+ debouncing/debounce_struct.vhd \
+ debouncing/event_counter.vhd \
+ debouncing/event_counter_beh.vhd \
+ debouncing/event_counter_pkg.vhd \
+ debouncing/sync.vhd \
+ debouncing/sync_beh.vhd \
+ debouncing/sync_pkg.vhd
PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# ==== Discrete LEDs (LED) ====
# These are shared connections with the FX2 connector
-NET "LED0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
#NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
#NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
# ==== RS-232 Serial Ports (RS232) ====
-#NET "RS232_DCE_RXD" LOC = "F8" | IOSTANDARD = LVTTL ;
-#NET "RS232_DCE_TXD" LOC = "E8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+NET "rxd" LOC = "E8" | IOSTANDARD = LVTTL ;
+NET "txd" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
\item Display $\Rightarrow$ History: die Breite f\"ur \emph{d\_zeile} muss
ebenfalls so breit wie \emph{p\_zeile} sein (zumindest vereinfacht das die
Implementierung)
+\item RS232: \emph{tx\_done} hinzugefuegt.
\end{itemize}
\end{document}
-- debounce fuer sys_res_n und btnA -- einfach die debounce entity vom example
- hernehmen
+- debounce fuer btnA -- einfach die debounce entity vom example hernehmen
- rs232/pc-kommunikation: RAM dumpen
-- uart rx oversampling, uart rx synchronizen (vlg. debouncing/sync*.vhd)
-
-
-- postlayout: nochmal testen obs im tilab wirklich ned geht.
-
-
- gen_pkg: unsigned fuer hspalte, hzeile
-== BUGS ==
-- warum ist in beh_history s_done und finished manchmal 'X'?
-
== low prio ==
- logic elements eliminieren
- wie detailiert muessen die screenshots der simulationen sein?
- warum ist auf seite 14 im foliensatz "VHDL_Architecture" "directly at
instantation" durchgestrichen? :/ (wird so ziemlich ueberall verwendet hier)
+- postlayout: geht im tilab nicht... reicht screenshot?
+
== FAQ =
run_inner := false;
if s_backspace = '1' or s_take = '1' then
icwait(sys_clk, 1);
- s_done <= '1';
wait on s_take; -- = '0'
icwait(sys_clk, 1);
- s_done <= '0';
elsif do_it = '1' then
-- dauert normalweiser noch laenger (parser braucht
-- relativ lange)
icwait(sys_clk, 7);
- finished <= '1';
wait on do_it; -- = '0'
- icwait(sys_clk, 1);
- finished <= '0';
icwait(sys_clk, 850);
run_tc := false;
-- 1. parameter: testfallnummer
-- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
-- 3. parameter: byte das rauskommen soll
- exec_tc(1, b"0000011111", b"00001111");
- exec_tc(2, b"0101010101", b"10101010");
- exec_tc(3, b"0110011001", b"11001100");
- exec_tc(4, b"0001100111", b"00110011");
- exec_tc(5, b"0010101011", b"01010101");
- exec_tc(6, b"0100110111", b"10011011");
+ exec_tc(1, b"0000011111", b"11110000");
+ exec_tc(2, b"0101010101", b"01010101");
+ exec_tc(3, b"0110011001", b"00110011");
+ exec_tc(4, b"0001100111", b"11001100");
+ exec_tc(5, b"0010101011", b"10101010");
+ exec_tc(6, b"0100110111", b"11011001");
stop <= true;
wait;
-- 1. parameter: testfallnummer
-- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
- -- 3. parameter: byte das rauskommen soll
- exec_tc(1, b"0000011111", b"00001111");
- exec_tc(2, b"0101010101", b"10101010");
- exec_tc(3, b"0110011001", b"11001100");
- exec_tc(4, b"0001100111", b"00110011");
- exec_tc(5, b"0010101011", b"01010101");
- exec_tc(6, b"0100110111", b"10011011");
+ -- 3. parameter: byte das rauskommen soll (umgekehrte reihenfolge)
+ exec_tc(1, b"0000011111", b"11110000");
+ exec_tc(2, b"0101010101", b"01010101");
+ exec_tc(3, b"0110011001", b"00110011");
+ exec_tc(4, b"0001100111", b"11001100");
+ exec_tc(5, b"0010101011", b"10101010");
+ exec_tc(6, b"0100110111", b"11011001");
stop <= true;
wait;
signal rx_data : std_logic_vector (7 downto 0);
signal tx_new, tx_done : std_logic;
signal tx_data : std_logic_vector (7 downto 0);
- signal txd_out : std_logic;
begin
-- vga/ipcore
textmode_vga_inst : entity work.textmode_vga(struct)
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
- txd => txd_out,
+ txd => txd,
tx_data => tx_data,
tx_new => tx_new,
tx_done => tx_done
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;
use work.ps2_keyboard_controller_pkg.all;
+use work.sync_pkg.all;
entity calc is
port (
-- btnA
-- TODO: pins
-- rs232
- -- TODO: pins
+ rxd : in std_logic;
+ txd : out std_logic;
-- vga
vsync_n : out std_logic;
hsync_n : out std_logic;
b : out std_logic_vector(BLUE_BITS - 1 downto 0);
-- ps/2
ps2_clk : inout std_logic;
- ps2_data : inout std_logic;
- -- debug
- led0 : out std_logic;
- led1 : out std_logic
+ ps2_data : inout std_logic
);
end entity calc;
signal p_finished : std_logic;
-- parser/scanner
signal do_it, finished : std_logic;
+ -- rs232
+ signal rx_new, rxd_sync : std_logic;
+ signal rx_data : std_logic_vector (7 downto 0);
+ signal tx_new, tx_done : std_logic;
+ signal tx_data : std_logic_vector (7 downto 0);
begin
- led0 <= '0';
- led1 <= '1';
sys_res_n <= not sys_res;
-- vga/ipcore
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
+
+ -- synchronizer fuer rxd
+ sync_rxd_inst : entity work.sync(beh)
+ generic map (
+ SYNC_STAGES => 2,
+ RESET_VALUE => '1'
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ data_in => rxd,
+ data_out => rxd_sync
+ );
+
+ -- rs232-rx
+ rs232rx_inst : entity work.uart_rx(beh)
+ generic map (
+ CLK_FREQ => 50000000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ rxd => rxd_sync,
+ rx_data => rx_data,
+ rx_new => rx_new
+ );
+
+ -- rs232-tx
+ rs232tx_inst : entity work.uart_tx(beh)
+ generic map (
+ CLK_FREQ => 50000000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ txd => txd,
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done
+ );
end architecture top;
-- starbit (= '0')? dann kommen daten
state_next <= DBITS;
bitcnt_next <= 0;
+ baudcnt_next <= 0;
else
-- sonst war das nix...
state_next <= IDLE;
baudcnt_next <= baudcnt_int + 1;
else
baudcnt_next <= 0;
- rx_data_next <= rx_data_int(6 downto 0) & rxd;
+ -- bitorder beachten
+ rx_data_next <= rxd & rx_data_int(7 downto 1);
if bitcnt_int = 7 then
state_next <= STOPBIT;
projects / hwmod.git / commitdiff