postlayoutsim: alu gefixt und parser hinzugefuegt, inkl. screenshots

diff --git a/.gitignore b/.gitignore
index d4daef8cff14d99e263b5999a830ab6b8e451376..2bec035a1b9de12d02acc4565d72b61a7e652014 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -13,7 +13,8 @@ spec/*.png
 *.ppk
 
 #sim
 *.ppk
 
 #sim

-sim/
+sim/post
+sim/beh

 
 #modelsim
 src/transcript
 
 #modelsim
 src/transcript

diff --git a/quartus/linux_tilab.sh b/quartus/linux_tilab.sh
index dcfd9b471814de5873552c65e0b7266f9ad04a45..f0b8f53320589a06509657144ecdf0c02fca8204 100755 (executable)
--- a/quartus/linux_tilab.sh
+++ b/quartus/linux_tilab.sh
@@ -1,6 +1,12 @@
 #!/bin/sh
 unset LS_COLORS
 #!/bin/sh
 unset LS_COLORS

-sed -e 's/%DEVICE%/EP1S25F672C6/g' project_gen.tcl > project_tilab.tcl
+if [ "$1" = "" ]; then
+       echo "kein param"
+       sed -e 's/%DEVICE%/EP1S25F672C6/g' project_gen.tcl > project_tilab.tcl
+else
+       echo "param $1"
+       sed -e 's/%DEVICE%/EP1S25F672C6/g' $1 > project_tilab.tcl
+fi

 mkdir -p calc
 cd calc
 quartus_sh -t ../project_tilab.tcl
 mkdir -p calc
 cd calc
 quartus_sh -t ../project_tilab.tcl

diff --git a/quartus/linux_web.sh b/quartus/linux_web.sh
index a6d0b4a8c61487f6e052931c704a3ec7d5fe9bb4..3799776239728d8084ebce5a250a2ca2dbb4ec50 100755 (executable)
--- a/quartus/linux_web.sh
+++ b/quartus/linux_web.sh
@@ -1,6 +1,12 @@
 #!/bin/sh
 unset LS_COLORS
 #!/bin/sh
 unset LS_COLORS

-sed -e 's/%DEVICE%/EP1S10F672C6/g' project_gen.tcl > project_web.tcl
+if [ "$1" = "" ]; then
+       echo "kein param"
+       sed -e 's/%DEVICE%/EP1S10F672C6/g' project_gen.tcl > project_web.tcl
+else
+       echo "param $1"
+       sed -e 's/%DEVICE%/EP1S10F672C6/g' $1 > project_web.tcl
+fi

 mkdir -p calc
 cd calc
 quartus_sh -t ../project_web.tcl
 mkdir -p calc
 cd calc
 quartus_sh -t ../project_web.tcl

diff --git a/quartus/project_alu.tcl b/quartus/project_alu.tcl
new file mode 100644 (file)
index 0000000..8433ebe
--- /dev/null
+++ b/quartus/project_alu.tcl
@@ -0,0 +1,50 @@
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+       if {[string compare $quartus(project) "calc"]} {
+               puts "Project calc is not open"
+               set make_assignments 0
+       }
+} else {
+       # Only open if not already open
+       if {[project_exists calc]} {
+               project_open -revision calc calc
+       } else {
+               project_new -revision calc calc
+       }
+       set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+       set_global_assignment -name FAMILY Stratix
+       set_global_assignment -name DEVICE %DEVICE%
+       set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+       set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+       set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+       set_global_assignment -name MISC_FILE "calc.dpf"
+       set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+       set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+       set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+       set_global_assignment -name TOP_LEVEL_ENTITY alu
+       set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/alu.vhd
+
+       #pin mapping/system
+       set_location_assignment PIN_N3 -to sys_clk
+       set_location_assignment PIN_AF17 -to sys_res_n
+
+       # Commit assignments
+       export_assignments
+
+       # Close project
+       if {$need_to_close_project} {
+               project_close
+       }
+}

diff --git a/quartus/project_parser.tcl b/quartus/project_parser.tcl
new file mode 100644 (file)
index 0000000..75bd3fe
--- /dev/null
+++ b/quartus/project_parser.tcl
@@ -0,0 +1,51 @@
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+       if {[string compare $quartus(project) "calc"]} {
+               puts "Project calc is not open"
+               set make_assignments 0
+       }
+} else {
+       # Only open if not already open
+       if {[project_exists calc]} {
+               project_open -revision calc calc
+       } else {
+               project_new -revision calc calc
+       }
+       set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+       set_global_assignment -name FAMILY Stratix
+       set_global_assignment -name DEVICE %DEVICE%
+       set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+       set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+       set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+       set_global_assignment -name MISC_FILE "calc.dpf"
+       set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+       set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+       set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+       set_global_assignment -name TOP_LEVEL_ENTITY parser
+       set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/alu.vhd
+       set_global_assignment -name VHDL_FILE ../../src/parser.vhd
+
+       #pin mapping/system
+       set_location_assignment PIN_N3 -to sys_clk
+       set_location_assignment PIN_AF17 -to sys_res_n
+
+       # Commit assignments
+       export_assignments
+
+       # Close project
+       if {$need_to_close_project} {
+               project_close
+       }
+}

diff --git a/sim/screenshots/post_alu_0.png b/sim/screenshots/post_alu_0.png
new file mode 100644 (file)
index 0000000..4b4f581
Binary files /dev/null and b/sim/screenshots/post_alu_0.png differ

diff --git a/sim/screenshots/post_alu_1.png b/sim/screenshots/post_alu_1.png
new file mode 100644 (file)
index 0000000..0771f1c
Binary files /dev/null and b/sim/screenshots/post_alu_1.png differ

diff --git a/sim/screenshots/post_parser.png b/sim/screenshots/post_parser.png
new file mode 100644 (file)
index 0000000..63d31ab
Binary files /dev/null and b/sim/screenshots/post_parser.png differ

diff --git a/src/Makefile b/src/Makefile
index f8694b97bb678c31ad57d9ecfdb42d7f4f5d11b7..2dfd9f534c427803b7d49452f931f5a132fd7498 100644 (file)
--- a/src/Makefile
+++ b/src/Makefile
@@ -85,7 +85,7 @@ beh_%: $(D_BEHSIM)/$(WORK)/beh_%_tb/_primary.dat beh_%_tb.do behsim
        vsim $(COVERVSIM) "work.$@_tb(sim)" -f /dev/null -do $(MPWD)/$@_tb.do
 
 #postsim
        vsim $(COVERVSIM) "work.$@_tb(sim)" -f /dev/null -do $(MPWD)/$@_tb.do
 
 #postsim

-postsim: $(POST_VHO) $(POST_SDO)
+postsim: post_alu

 
 $(D_POSTSIM)/modelsim.ini:
        @echo " INIT for post-layout simulation"
 
 $(D_POSTSIM)/modelsim.ini:
        @echo " INIT for post-layout simulation"


@@ -99,42 +99,34 @@ $(D_POSTSIM)/$(WORK)/%/_primary.dat: %.vhd
        @cd $(D_POSTSIM); \
        vcom -work $(WORK) $(MPWD)/$<
 
        @cd $(D_POSTSIM); \
        vcom -work $(WORK) $(MPWD)/$<
 

-post_%: postsim $(D_POSTSIM)/$(WORK)/post_%_tb/_primary.dat post_%_tb.do
+post_%: quartus_gen_% post_%_tb.do $(D_POSTSIM)/$(WORK)/post_%_tb/_primary.dat

        cd $(D_POSTSIM); \
        vsim "work.$@_tb(sim)" -sdftyp /$(POST_SDO_INST)=$(POST_SDO) -f /dev/null -do $(MPWD)/$@_tb.do
 
        cd $(D_POSTSIM); \
        vsim "work.$@_tb(sim)" -sdftyp /$(POST_SDO_INST)=$(POST_SDO) -f /dev/null -do $(MPWD)/$@_tb.do
 

-$(QUARTUS): $(D_POSTSIM)/modelsim.ini
+quartus_gen_%: ../quartus/project_%.tcl $(D_POSTSIM)/modelsim.ini $(POST_VTARGETS) $(POST_SRC_VTARGETS)

        @echo -n " Quartus  generate project"
 ifeq ($(findstring $(HN), $(TILABHOSTS)),$(HN))
        @echo -n " Quartus  generate project"
 ifeq ($(findstring $(HN), $(TILABHOSTS)),$(HN))

-       @echo "(@tilab)"
-       @cd ../quartus; ./linux_tilab.sh
+       @echo "(@tilab): $<"
+       @cd ../quartus; rm -Rf calc; ./linux_tilab.sh $<

 else
 else

-       @echo "(not @ tilab)"
-       @cd ../quartus; ./linux_web.sh
+       @echo "(not @ tilab): $<"
+       @cd ../quartus; rm -Rf calc; ./linux_web.sh $<

 endif
 endif

-
-#TODO: more targets plz...
-$(POST_VHO) $(POST_SDO): $(QUARTUS) $(POST_VTARGETS) $(POST_SRC_VTARGETS)

        @echo " Quartus  analysis & synthesis"
        @echo " Quartus  analysis & synthesis"

-       @$(QUMACRO) quartus_map $(QUOPT) | tee $(MPWD)/quartusmap.tmp
+       @$(QUMACRO) quartus_map $(QUOPT)

        @echo " Quartus  fitter"
        @$(QUMACRO) quartus_fit $(QUOPT)
        @echo " Quartus  assembler"
        @$(QUMACRO) quartus_asm $(QUOPT)
        @echo " Quartus  timing analyzer"
        @echo " Quartus  fitter"
        @$(QUMACRO) quartus_fit $(QUOPT)
        @echo " Quartus  assembler"
        @$(QUMACRO) quartus_asm $(QUOPT)
        @echo " Quartus  timing analyzer"

-       @$(QUMACRO) quartus_tan $(QUOPT) --timing_analysis_only | tee $(MPWD)/quartustan.tmp
+       @$(QUMACRO) quartus_tan $(QUOPT) --timing_analysis_only

        @echo " Quartus  EDA netlist writer"
        @$(QUMACRO) quartus_eda $(QUOPT)
        @echo " Quartus  EDA netlist writer"
        @$(QUMACRO) quartus_eda $(QUOPT)

-       #not nice atm :/

        @echo " CC    $(POST_VHO)"
        @cd $(D_POSTSIM); \
        vcom -work $(WORK) $(POST_VHO)
        @echo " CC    $(POST_VHO)"
        @cd $(D_POSTSIM); \
        vcom -work $(WORK) $(POST_VHO)

-       @echo -n "  INFO  logic cells: "
-       @grep 'logic cells' quartusmap.tmp | awk ' { print $$3 } '
-       @grep 'Fmax ' quartustan.tmp | sed -e 's/  / /g' -e 's/Info/INFO/g' -e 's/:/ /g'
-       @rm quartus*.tmp

 
 .PHONY: clean
 clean:
 
 .PHONY: clean
 clean:

-       rm -Rf $(D_BEHSIM) $(D_POSTSIM) $(QUARTUS)
+       rm -Rf $(D_BEHSIM) $(D_POSTSIM)

 
 

diff --git a/src/TODO b/src/TODO
index 08541c6eff6f5192015417762e3488f8ba27afc7..ac3ae5765340da4ba4302c6ad1e5859480735d30 100644 (file)
--- a/src/TODO
+++ b/src/TODO
@@ -5,16 +5,17 @@
 - rs232/pc-kommunikation: RAM dumpen
 
 
 - rs232/pc-kommunikation: RAM dumpen
 
 

-- alu postlayout noch an die neue alu anpassen (... wenn das projekt final is),
-  dass ma eine postlayoutsim bei der abgabe zum herzeigen haben
-
-

 - scanner rewrite: nicht bei key-release sondern bei key-pressed
        o vorteil: man kann auf der taste drauf bleiben und man kann
          keine zahlen mehr mit den coursertasten eingeben
 
 - scanner rewrite: nicht bei key-release sondern bei key-pressed
        o vorteil: man kann auf der taste drauf bleiben und man kann
          keine zahlen mehr mit den coursertasten eingeben
 

+

 - uart rx oversampling, uart rx synchronizen (vlg. debouncing/sync*.vhd)
 
 - uart rx oversampling, uart rx synchronizen (vlg. debouncing/sync*.vhd)
 

+
+- postlayout: nochmal testen obs im tilab wirklich ned geht.
+
+

 == low prio ==
 - mehr testfaelle fuer alu/scanner/parser
 - parser refactor
 == low prio ==
 - mehr testfaelle fuer alu/scanner/parser
 - parser refactor

diff --git a/src/post_alu_tb.do b/src/post_alu_tb.do
index 27a93631bd731e6a3e73c5034bed4b0e6b373547..c02a35c0fe49acbdd4887a6f016092cacd88cb96 100644 (file)
--- a/src/post_alu_tb.do
+++ b/src/post_alu_tb.do
@@ -8,6 +8,7 @@ add wave -radix decimal op1
 add wave opcode
 add wave -radix decimal op2
 add wave -radix decimal op3
 add wave opcode
 add wave -radix decimal op2
 add wave -radix decimal op3

+add wave -radix decimal opM

 add wave do_calc
 add wave calc_done
 
 add wave do_calc
 add wave calc_done
 

diff --git a/src/post_alu_tb.vhd b/src/post_alu_tb.vhd
index d113dcaa893060980dac8b1617bf22eb7eb9459d..b6f9db1899ae1bd6ab88121d18a3d8bb2ea06299 100644 (file)
--- a/src/post_alu_tb.vhd
+++ b/src/post_alu_tb.vhd
@@ -17,6 +17,7 @@ architecture sim of post_alu_tb is
                        op1 : in std_logic_vector(31 downto 0);
                        op2 : in std_logic_vector(31 downto 0);
                        op3 : out std_logic_vector(31 downto 0);
                        op1 : in std_logic_vector(31 downto 0);
                        op2 : in std_logic_vector(31 downto 0);
                        op3 : out std_logic_vector(31 downto 0);

+                       opM : out std_logic_vector(31 downto 0);

                        do_calc : in std_logic;
                        calc_done : out std_logic;
                        calc_error : out std_logic
                        do_calc : in std_logic;
                        calc_done : out std_logic;
                        calc_error : out std_logic


@@ -25,7 +26,7 @@ architecture sim of post_alu_tb is
 
        signal sys_clk, sys_res_n, do_calc, calc_done, calc_error : std_logic;
        signal opcode : alu_ops;
 
        signal sys_clk, sys_res_n, do_calc, calc_done, calc_error : std_logic;
        signal opcode : alu_ops;

-       signal op1, op2, op3 : std_logic_vector((CBITS-1) downto 0);
+       signal op1, op2, op3, opM : std_logic_vector((CBITS-1) downto 0);

        signal stop : boolean := false;
 begin
        inst : alu
        signal stop : boolean := false;
 begin
        inst : alu


@@ -38,6 +39,7 @@ begin
                op1 => op1,
                op2 => op2,
                op3 => op3,
                op1 => op1,
                op2 => op2,
                op3 => op3,

+               opM => opM,

                opcode => opcode,
                calc_error => calc_error
        );
                opcode => opcode,
                calc_error => calc_error
        );


@@ -58,62 +60,83 @@ begin
                        o1 : cinteger;
                        o : alu_ops;
                        o2 : cinteger;
                        o1 : cinteger;
                        o : alu_ops;
                        o2 : cinteger;

+                       om : cinteger;

                        expected : cinteger;
                        errcase : boolean;
                end record alu_testv;
 
                -- ggf. groesse des arrays erhoehen
                        expected : cinteger;
                        errcase : boolean;
                end record alu_testv;
 
                -- ggf. groesse des arrays erhoehen

-               type alu_testv_array is array (natural range 0 to 44) of alu_testv;
+               type alu_testv_array is array (natural range 0 to 65) of alu_testv;

 
                variable testmatrix : alu_testv_array :=
 
                variable testmatrix : alu_testv_array :=

-                       ( 0 => (-5, ALU_DIV, 3, -1, false),
-                         1 => (7, ALU_ADD, 3, 10, false),
-                         2 => (7, ALU_SUB, 1, 6, false),
-                         3 => (7, ALU_DIV, 1, 7, false),
-                         4 => (7, ALU_DIV, 3, 2, false),
-                         5 => (7, ALU_ADD, 1, 8, false),
-                         6 => (7, ALU_MUL, 3, 21, false),
-                         7 => (-7, ALU_MUL, 3, -21, false),
-                         8 => (268435456, ALU_MUL, -2, -536870912, false),
-                         9 => (268435456, ALU_MUL, 2**5, 0, false), -- um fuenf nach links shiften
-                         10 => (268435456 + 5, ALU_MUL, 2**5, 160, false), -- = 5 * (2^5)
-                         11 => (100, ALU_DIV, 10, 10, false),
-                         12 => (100, ALU_DIV, 51, 1, false),
-                         13 => (100, ALU_DIV, 49, 2, false),
-                         14 => (153156, ALU_DIV, 3543, 43, false),
-                         15 => (-153156, ALU_DIV, 3543, -43, false),
-                         16 => (153156, ALU_DIV, -3543, -43, false),
-                         17 => (-153156, ALU_DIV, -3543, 43, false),
+                       ( 0 => (-5, ALU_DIV, 3, 2, -1, false),
+                         1 => (7, ALU_ADD, 3, 0, 10, false),
+                         2 => (7, ALU_SUB, 1, 0, 6, false),
+                         3 => (7, ALU_DIV, 1, 0, 7, false),
+                         4 => (7, ALU_DIV, 3, 1, 2, false),
+                         5 => (7, ALU_ADD, 1, 0, 8, false),
+                         6 => (7, ALU_MUL, 3, 0, 21, false),
+                         7 => (-7, ALU_MUL, 3, 0, -21, false),
+                         8 => (268435456, ALU_MUL, -2, 0, -536870912, false),
+                         9 => (268435456, ALU_MUL, 2**5, 0, 0, false), -- um fuenf nach links shiften
+                         10 => (268435456 + 5, ALU_MUL, 2**5, 0, 160, false), -- = 5 * (2^5)
+                         11 => (100, ALU_DIV, 10, 0, 10, false),
+                         12 => (100, ALU_DIV, 51, 49, 1, false),
+                         13 => (100, ALU_DIV, 49, 2, 2, false),
+                         14 => (153156, ALU_DIV, 3543, 807, 43, false),
+                         15 => (-153156, ALU_DIV, 3543, 807, -43, false),
+                         16 => (153156, ALU_DIV, -3543, 807, -43, false),
+                         17 => (-153156, ALU_DIV, -3543, 807, 43, false),

                          -- add: sign and under-/overflow check
                          -- add: sign and under-/overflow check

-                         18 => (2147483647, ALU_ADD, -1, 2147483646, false),
-                         19 => (2147483647, ALU_ADD, 1, 0, true),
-                         20 => (-2147483645, ALU_ADD, -100, 0, true),
-                         21 => (7, ALU_ADD, 1, 8, false),
-                         22 => (7, ALU_ADD, -1, 6, false),
-                         23 => (-7, ALU_ADD, 1, -6, false),
-                         24 => (-7, ALU_ADD, -1, -8, false),
+                         18 => (2147483647, ALU_ADD, -1, 0, 2147483646, false),
+                         19 => (2147483647, ALU_ADD, 1, 0, 0, true),
+                         20 => (-2147483645, ALU_ADD, -100, 0, 0, true),
+                         21 => (7, ALU_ADD, 1, 0, 8, false),
+                         22 => (7, ALU_ADD, -1, 0, 6, false),
+                         23 => (-7, ALU_ADD, 1, 0, -6, false),
+                         24 => (-7, ALU_ADD, -1, 0, -8, false),

                          -- sub: sign and under-/overflow check
                          -- sub: sign and under-/overflow check

-                         25 => (-7, ALU_SUB, 1, -8, false),
-                         26 => (-7, ALU_SUB, -1, -6, false),
-                         27 => (7, ALU_SUB, 1, 6, false),
-                         28 => (7, ALU_SUB, -1, 8, false),
-                         29 => (-2147483645, ALU_SUB, 1000, 0, true),
-                         30 => (2147483645, ALU_SUB, -1000, 0, true),
-                         31 => (-1000, ALU_SUB, 2147483645, 0, true),
-                         32 => (1000, ALU_SUB, -2147483645, 0, true),
+                         25 => (-7, ALU_SUB, 1, 0, -8, false),
+                         26 => (-7, ALU_SUB, -1, 0, -6, false),
+                         27 => (7, ALU_SUB, 1, 0, 6, false),
+                         28 => (7, ALU_SUB, -1, 0, 8, false),
+                         29 => (-2147483645, ALU_SUB, 1000, 0, 0, true),
+                         30 => (2147483645, ALU_SUB, -1000, 0, 0, true),
+                         31 => (-1000, ALU_SUB, 2147483645, 0, 0, true),
+                         32 => (1000, ALU_SUB, -2147483645, 0, 0, true),

                          -- mul: sign and under-/overflow check
                          -- mul: sign and under-/overflow check

-                         33 => (3, ALU_MUL, 2, 6, false),
-                         34 => (3, ALU_MUL, -2, -6, false),
-                         35 => (-3, ALU_MUL, 2, -6, false),
-                         36 => (-3, ALU_MUL, -2, 6, false),
-                         37 => (90000, ALU_MUL, 100000, 0, true),
-                         38 => (90000, ALU_MUL, -100000, 0, true),
-                         39 => (-90000, ALU_MUL, 100000, 0, true),
-                         40 => (-90000, ALU_MUL, -100000, 0, true),
-                         -- mul: overflow check und division durch null
-                         41 => (-2147483648, ALU_DIV, -1, 0, true),
-                         42 => (-2147483648, ALU_DIV, 0, 0, true),
-                         others => (0, ALU_ADD, 0, 0, false)
+                         33 => (3, ALU_MUL, 2, 0, 6, false),
+                         34 => (3, ALU_MUL, -2, 0, -6, false),
+                         35 => (-3, ALU_MUL, 2, 0, -6, false),
+                         36 => (-3, ALU_MUL, -2, 0, 6, false),
+                         37 => (90000, ALU_MUL, 100000, 0, 0, true),
+                         38 => (90000, ALU_MUL, -100000, 0, 0, true),
+                         39 => (-90000, ALU_MUL, 100000, 0, 0, true),
+                         40 => (-90000, ALU_MUL, -100000, 0, 0, true),
+                         -- div: overflow check und division durch null
+                         41 => (-2147483648, ALU_DIV, -1, 0, 0, true),
+                         42 => (-2147483648, ALU_DIV, 0, 0, 0, true),
+                         43 => (-4, ALU_DIV, 2, 0, -2, false),
+                         -- div/mod:
+                         44 => (1234, ALU_DIV, 3, 1, 411, false),
+                         45 => (1, ALU_DIV, 10, 1, 0, false),
+                         46 => (2, ALU_DIV, 10, 2, 0, false),
+                         47 => (3, ALU_DIV, 10, 3, 0, false),
+                         48 => (4, ALU_DIV, 10, 4, 0, false),
+                         49 => (5, ALU_DIV, 10, 5, 0, false),
+                         50 => (6, ALU_DIV, 10, 6, 0, false),
+                         51 => (7, ALU_DIV, 10, 7, 0, false),
+                         52 => (8, ALU_DIV, 10, 8, 0, false),
+                         53 => (9, ALU_DIV, 10, 9, 0, false),
+                         54 => (0, ALU_DIV, 10, 0, 0, false),
+                         55 => (10, ALU_DIV, 10, 0, 1, false),
+                         56 => (5134123, ALU_DIV, 358015, 121913, 14, false),
+                         -- extra
+                         60 => (5, ALU_SUB, -2147483648, 0, 0, true),
+                         61 => (-2147483647, ALU_SUB, 1, 0, -2147483648, false),
+                         62 => (-2147483647, ALU_ADD, -1, 0, -2147483648, false),
+                         63 => (-2147483648, ALU_DIV, 10, 8, -214748364, false),
+                         others => (0, ALU_ADD, 0, 0, 0, false)

                        );
                variable checkall : boolean := true;
        begin
                        );
                variable checkall : boolean := true;
        begin


@@ -161,7 +184,7 @@ begin
                                        "/= " & integer'image(to_integer(signed(op3))) &
                                        " -- erwartet: " & cinteger'image(testmatrix(i).expected);
 
                                        "/= " & integer'image(to_integer(signed(op3))) &
                                        " -- erwartet: " & cinteger'image(testmatrix(i).expected);
 

-                               if op3 /= std_logic_vector(to_signed(testmatrix(i).expected,CBITS)) then
+                               if not((op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))) and (opM = std_logic_vector(to_signed(testmatrix(i).om,CBITS)))) then

                                        checkall := false;
                                end if;
                        end if;
                                        checkall := false;
                                end if;
                        end if;

diff --git a/src/post_parser_tb.do b/src/post_parser_tb.do
new file mode 100644 (file)
index 0000000..c90d9c9
--- /dev/null
+++ b/src/post_parser_tb.do
@@ -0,0 +1,24 @@
+#alias fuer simulation neustarten
+alias rr "restart -f"
+
+#signale hinzufuegen
+add wave sys_clk
+add wave sys_res_n
+add wave p_rget
+add wave p_rdone
+add wave p_read
+add wave p_wtake
+add wave p_wdone
+add wave p_write
+add wave p_finished
+add wave do_it
+add wave finished
+
+#rauszoomen
+wave zoomout 500.0
+
+#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
+run -all
+
+#ganz nach links scrollen
+wave seetime 0

diff --git a/src/post_parser_tb.vhd b/src/post_parser_tb.vhd
new file mode 100644 (file)
index 0000000..8ba3dd5
--- /dev/null
+++ b/src/post_parser_tb.vhd
@@ -0,0 +1,191 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity post_parser_tb is
+end entity post_parser_tb;
+
+architecture sim of post_parser_tb is
+       component parser is
+               port (
+                       sys_clk : in std_logic;
+                       sys_res_n : in std_logic;
+                       -- History
+                       p_rget : out std_logic;
+                       p_rdone : in std_logic;
+                       p_read : in hbyte;
+                       p_wtake : out std_logic;
+                       p_wdone : in std_logic;
+                       p_write : out hbyte;
+                       p_finished : out std_logic;
+                       -- Scanner
+                       do_it : in std_logic;
+                       finished : out std_logic
+               );
+       end component parser;
+       -- system
+       signal sys_clk, sys_res_n : std_logic;
+       -- history
+       signal p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
+       signal p_read, p_write : hbyte;
+       --scanner
+       signal do_it : std_logic;
+       signal finished : std_logic;
+
+       signal stop : boolean := false;
+begin
+       inst : parser
+       port map
+       (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               -- history
+               p_rget => p_rget,
+               p_rdone => p_rdone,
+               p_read => p_read,
+               p_wtake => p_wtake,
+               p_wdone => p_wdone,
+               p_write => p_write,
+               p_finished => p_finished,
+               -- Scanner
+               do_it => do_it,
+               finished => finished
+       );
+
+       process
+       begin
+               sys_clk <= '0';
+               wait for 15 ns;
+               sys_clk <= '1';
+               wait for 15 ns;
+               if stop = true then
+                       wait;
+               end if;
+       end process;
+
+       process
+               -- textio stuff
+               use std.textio.all;
+               file f : text open read_mode is "../../src/parser.test";
+               variable l : line;
+
+               variable input : hstring;
+               variable expectedresult : hstring;
+               variable realresult : hstring;
+               variable hstrtmp : hstring;
+
+               variable checkall : boolean := true;
+               variable run_tc : boolean := true;
+               variable i, j, k, y : natural;
+       begin
+               -- init & reset
+               sys_res_n <= '0';
+               p_rdone <= '0';
+               p_wdone <= '0';
+               p_read <= (others => '0');
+               do_it <= '0';
+
+               icwait(sys_clk, 5);
+               sys_res_n <= '1';
+
+               i := 1;
+               f_loop : while not endfile(f) loop
+                       realresult := (72 => nul, others => ' ');
+
+                       f1_loop : while not endfile(f) loop
+                               readline (f, l);
+                               input := (others => nul);
+                               if (l'length <= 72) then
+                                       input(1 to l'length) := l.all;
+                                       if (input(1) = '#') then
+                                               next f1_loop;
+                                       else
+                                               exit f1_loop;
+                                       end if;
+                               else
+                                       report "fehler in parser.test: eingabe zu lange in testfall " & natural'image(i);
+                                       next f_loop;
+                               end if;
+                       end loop f1_loop;
+
+                       f2_loop : while not endfile(f) loop
+                               readline (f, l);
+                               expectedresult := (others => nul);
+                               if (l'length <= 72) then
+                                       expectedresult(1 to l'length) := l.all;
+                                       if (expectedresult(1) = '#') then
+                                               next f2_loop;
+                                       else
+                                               y := l'length;
+                                               exit f2_loop;
+                                       end if;
+                               else
+                                       report "fehler in parser.test: eingabe zu lange in testfall " & natural'image(i);
+                                       next f_loop;
+                               end if;
+                       end loop f2_loop;
+
+                       -- ergebnis string richtig formatieren
+                       hstrtmp := expectedresult;
+                       expectedresult := (72 => nul, others => ' ');
+                       for x in 1 to 71 loop
+                               if hstrtmp(x) /= nul then
+                                       expectedresult((71-y) + x) := hstrtmp(x);
+                               end if;
+                       end loop;
+
+
+                       report "testcase(" & natural'image(i) & ").input: " & input;
+                       report "testcase(" & natural'image(i) & ").expectedresult: " & expectedresult;
+                       i := i + 1;
+
+                       icwait(sys_clk, 5);
+                       do_it <= '1';
+                       run_tc := true;
+                       j := 1; k := 71;
+
+                       while run_tc loop
+                               wait on p_rget, p_wtake, p_finished, finished;
+                               icwait(sys_clk, 2);
+
+                               if p_rget = '1' then
+                                       p_read <= hbyte( to_unsigned(character'pos(input(j)),8) );
+                                       p_rdone <= '1';
+                                       j := j + 1;
+                               end if;
+                               if p_rget = '0' then
+                                       p_rdone <= '0';
+                               end if;
+
+                               if p_wtake = '1' then
+                                       realresult(k) := character'val(to_integer(unsigned(p_write)));
+                                       p_wdone <= '1';
+                                       k := k - 1;
+                               end if;
+                               if p_wtake = '0' then
+                                       p_wdone <= '0';
+                               end if;
+
+                               if p_finished = '1' or finished = '1' then
+                                       run_tc := false;
+                               end if;
+                       end loop;
+                       
+                       do_it <= '0';
+                       report "realresult                : " & realresult;
+                       if realresult /= expectedresult then
+                               checkall := false;
+                       end if;
+                       report "==================";
+               end loop f_loop;
+
+               if checkall then
+                       report "alle testfaelle des Parser waren erfolgreich!";
+               else
+                       report "nicht alle testfaelle des Parsers waren erfolgreich!";
+               end if;
+               stop <= true;
+               wait;
+       end process;
+end architecture sim;