initial counter working

diff --git a/src/Makefile b/src/Makefile
index f0382f1541ef3adae20ce1ef27907abd566d3d39..461f4a8142750703d9920c9deafa1497e17f3021 100644 (file)
--- a/src/Makefile
+++ b/src/Makefile
@@ -24,7 +24,7 @@ WORK := work
 # o source files der module
 # o reihenfolge ist wichtig
 # o keine testbechnes hier angeben
-SRCFILES := alu parser scanner display sp_ram history
+SRCFILES := alu parser scanner display sp_ram history uart_tx
 
 # o files der packages
 # o keine testbechnes hier angeben

diff --git a/src/beh_uart_tx_tb.do b/src/beh_uart_tx_tb.do
new file mode 100644 (file)
index 0000000..4f70701
--- /dev/null
+++ b/src/beh_uart_tx_tb.do
@@ -0,0 +1,56 @@
+#alias fuer simulation neustarten
+alias rr "restart -f"
+
+#signale hinzufuegen
+add wave inst/*
+
+delete wave /beh_parser_tb/inst/op1_int
+delete wave /beh_parser_tb/inst/op1
+delete wave /beh_parser_tb/inst/op1_next
+add wave -radix decimal inst/op1_int
+
+delete wave /beh_parser_tb/inst/op2_int
+delete wave /beh_parser_tb/inst/op2
+delete wave /beh_parser_tb/inst/op2_next
+add wave -radix decimal inst/op2_int
+
+delete wave /beh_parser_tb/inst/op3
+add wave -radix decimal inst/op3
+delete wave /beh_parser_tb/inst/opM
+add wave -radix decimal inst/opM
+
+delete wave /beh_parser_tb/inst/z_int
+delete wave /beh_parser_tb/inst/z_next
+add wave -radix decimal inst/z_int
+add wave -radix decimal inst/z_next
+
+delete wave /beh_parser_tb/inst/strich_int
+delete wave /beh_parser_tb/inst/strich_next
+add wave -radix decimal inst/strich_int
+add wave -radix decimal inst/strich_next
+
+delete wave /beh_parser_tb/inst/punkt_int
+delete wave /beh_parser_tb/inst/punkt_next
+add wave -radix decimal inst/punkt_int
+add wave -radix decimal inst/punkt_next
+
+delete wave /beh_parser_tb/inst/wtmp_int
+delete wave /beh_parser_tb/inst/wtmp_next
+add wave -radix decimal inst/wtmp_int
+add wave -radix decimal inst/wtmp_next
+
+delete wave /beh_parser_tb/inst/p_write_int
+delete wave /beh_parser_tb/inst/p_write_next
+delete wave /beh_parser_tb/inst/p_write
+add wave -hex inst/p_write_int
+add wave -hex inst/p_write_next
+
+
+#rauszoomen
+wave zoomout 500.0
+
+#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
+run -all
+
+#ganz nach links scrollen
+wave seetime 0

diff --git a/src/beh_uart_tx_tb.vhd b/src/beh_uart_tx_tb.vhd
new file mode 100644 (file)
index 0000000..a02ac72
--- /dev/null
+++ b/src/beh_uart_tx_tb.vhd
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity beh_uart_tx_tb is
+end entity beh_uart_tx_tb;
+
+architecture sim of beh_uart_tx_tb is
+
+       constant clk_period  : time := 10ns;
+       signal clock : std_logic;
+       signal reset : std_logic;
+       signal done : std_logic;
+       signal newsig : std_logic;
+begin
+       inst : entity work.uart_tx(beh)
+       port map (
+                sys_clk => clock,
+                sys_res => reset,
+                --=> txd,
+                --=> tx_data,
+                tx_new => newsig,
+                tx_done => done
+       );
+
+       stimuli : process
+       begin
+               newsig <= '0';
+               wait for 10ns;
+               --send 'Hallo Welt'
+               newsig <= '1';
+               wait for 1000ns;
+
+               assert false report "Test finished" severity failure;
+       end process stimuli;
+
+       res_gen : process
+       begin
+               reset <= '0';
+               wait for 20ns;
+               reset <= '1';
+               wait for 1000ns;
+       end process res_gen;
+
+       clock_gen : process
+       begin
+               clock <= '0';
+               wait for clk_period/2;
+               clock <= '1';
+               wait for clk_period/2;
+       end process clock_gen;
+
+end sim;

diff --git a/src/uart_tx.vhd b/src/uart_tx.vhd
new file mode 100644 (file)
index 0000000..7d06e4c
--- /dev/null
+++ b/src/uart_tx.vhd
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--use work.gen_pkg.all;
+
+--package int_types is
+--     type STATE_UART_TX is (IDLE, STARTBITS, PAYLOAD, PARITY, STOP, DONE);
+--     type PARITY_TYPE is (ODD, EVEN, NONE);
+--end package int_types;
+
+entity uart_tx is
+port(
+       sys_clk : in std_logic;
+       sys_res : in std_logic;
+       --txd : out std_logic;
+       --tx_data : in std_logic;
+       tx_new : in std_logic;
+       tx_done : out std_logic
+);
+end entity uart_tx;
+
+architecture beh of uart_tx is
+       signal timer : integer range 0 to 65535;
+       signal timer_next : integer range 0 to 65535;
+       constant timer_max : integer := 35;
+       signal counter : integer;
+       signal counter_next : integer;
+begin
+       process (sys_clk, sys_res)
+       begin
+               if sys_res = '0' then
+                       counter <= 0;
+                       timer <= 0;
+               elsif rising_edge(sys_clk) then
+                       counter <= counter_next;
+                       timer <= timer_next;
+               end if;
+       end process;
+
+
+       process (timer, counter)
+       begin
+               if (timer = timer_max) then
+                       timer_next <= 0;
+                       counter_next <= counter + 1;
+               else
+                       timer_next <= timer + 1;
+                       counter_next <= counter;
+               end if;
+       end process;
+
+       tx_done <= '0';
+
+end architecture beh;