uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / sp_ram.vhd

diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd
index a2a2371aaf901c9d7debab4fef0020766d7db8bd..66b23d289507da736ed0975d84071e791a4e8d18 100644 (file)
--- a/src/sp_ram.vhd
+++ b/src/sp_ram.vhd
@@ -10,7 +10,6 @@ entity sp_ram is
        );
        port (
                sys_clk : in std_logic;
-               sys_res_n : in std_logic;
                address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
                data_out : out hbyte;
                wr : in std_logic;
@@ -20,14 +19,12 @@ end entity sp_ram;
 
 architecture beh of sp_ram is
        subtype RAM_ENTRY_TYPE is hbyte;
-       type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH) - 1) of RAM_ENTRY_TYPE;
+       type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        signal ram : RAM_TYPE := (others => x"00");
 begin
-       process(sys_clk, sys_res_n)
+       process(sys_clk)
        begin
-               if sys_res_n = '0' then
-                       ram <= (others => x"00");
-               elsif rising_edge(sys_clk) then
+               if rising_edge(sys_clk) then
                        data_out <= ram(to_integer(unsigned(address)));
                        if wr = '1' then
                                ram(to_integer(unsigned(address))) <= data_in;