signal tx_done_i, tx_done_i_next : std_logic;
signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
- type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CALC_VAL);
+ type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, NL, NL_WAIT);
signal state, state_next : STATE_PC ;
begin
pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
end if;
end process sync;
- output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
+ process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
+ pc_done)
begin
get_next <= '0';
new_i_next <= '0';
-
spalte_next <= spalte;
zeile_next <= zeile;
tx_data_i_next <= tx_data_i;
- case state is
- when IDLE =>
- null;
- when FETCH =>
- get_next <= '1';
- when FORWARD =>
- tx_data_i_next <= pc_char;
- new_i_next <= '1';
- -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
- get_next <= '1';
- when WAIT_UART =>
- new_i_next <= '1';
- get_next <= '1';
- when UART_DONE => null;
- -- get_next <= '0';
- -- new_i_next <= '0';
- when CALC_VAL =>
- spalte_next <= spalte + 1;
- if spalte = HSPALTE_MAX + 1 then
- tx_data_i_next <= x"0a";
- new_i_next <= '1';
-
- spalte_next <= 1;
- zeile_next <= zeile + 1;
- if zeile = HZEILE_MAX-1 then
- zeile_next <= 0;
- end if;
- end if;
- end case;
- end process output_pc;
-
- next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
- tx_data_i ,tx_done_i, zeile, pc_char)
- begin
state_next <= state;
case state is
when IDLE =>
state_next <= FETCH;
end if;
when FETCH =>
+ get_next <= '1';
if pc_done = '1' and tx_done_i = '0' then
if pc_char = x"00" then
state_next <= UART_DONE;
end if;
end if;
when FORWARD =>
+ tx_data_i_next <= pc_char;
+ new_i_next <= '1';
+ -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+ get_next <= '1';
state_next <= WAIT_UART;
when WAIT_UART =>
- if (tx_done_i = '1') then
+ new_i_next <= '1';
+ get_next <= '1';
+ if tx_done_i = '1' then
state_next <= UART_DONE;
end if;
- when UART_DONE =>
- state_next <= CALC_VAL;
- when CALC_VAL =>
- if spalte = HSPALTE_MAX + 1 and zeile = HZEILE_MAX - 1 then
+ when UART_DONE => null;
+ state_next <= FETCH;
+ spalte_next <= spalte + 1;
+ if spalte = HSPALTE_MAX + 1 then
+ state_next <= NL;
+ spalte_next <= 1;
+ zeile_next <= zeile + 1;
+ end if;
+ when NL =>
+ tx_data_i_next <= x"0a";
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= NL_WAIT;
+ end if;
+ when NL_WAIT =>
+ state_next <= CR;
+ when CR =>
+ tx_data_i_next <= x"0d";
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= CR_WAIT;
+ end if;
+ when CR_WAIT =>
+ state_next <= FETCH;
+ if zeile = HZEILE_MAX then
state_next <= IDLE;
- else
- state_next <= FETCH;
+ zeile_next <= 0;
+ spalte_next <= 1;
end if;
end case;
- end process next_state_pc;
+ end process;
end architecture beh;