end entity pc_communication;
architecture beh of pc_communication is
- signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
- signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
+ signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1;
+ signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1;
signal get, get_next : std_logic;
signal new_i, new_i_next : std_logic;
signal tx_done_i, tx_done_i_next : std_logic;
when WAIT_UART =>
new_i_next <= '1';
when UART_DONE =>
- if tx_data_i = x"00" or spalte = hspalte_max then
+ if tx_data_i = x"00" or spalte = HSPALTE_MAX then
tx_data_i_next <= x"0a";
zeile_next <= zeile + 1;
spalte_next <= 1;
- if zeile = hzeile_max then
+ if zeile = HZEILE_MAX then
zeile_next <= 1;
end if;
else
state_next <= UART_DONE;
end if;
when UART_DONE =>
- if (tx_data_i = x"00" or spalte = hspalte_max) and
- zeile = hzeile_max then
+ if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and
+ zeile = HZEILE_MAX then
state_next <= IDLE;
else
state_next <= FETCH;