tx_done : in std_logic;
--uart_rx
- rx_data : in std_logic_vector(7 downto 0); --not really required
+ rx_data : in std_logic_vector(7 downto 0);
rx_new : in std_logic;
-- History
- d_zeile : out hzeile;
- d_spalte : out hspalte;
- d_get : out std_logic;
- d_done : in std_logic;
- d_char : in hbyte
+ pc_zeile : out hzeile;
+ pc_spalte : out hspalte;
+ pc_get : out std_logic;
+ pc_busy : in std_logic; --signals if the history module actually grants our request.
+ pc_done : in std_logic;
+ pc_char : in hbyte
);
end entity pc_communication;
architecture beh of pc_communication is
- signal push_history, push_history_next : std_logic;
+ signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1;
+ signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1;
+ signal get, get_next : std_logic;
+ signal new_i, new_i_next : std_logic;
+ signal tx_done_i, tx_done_i_next : std_logic;
+ signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
- signal spalte, spalte_next : hspalte;
- signal zeile , zeile_next : hzeile;
- signal spalte_up, spalte_up_next : std_logic;
-
- signal char, char_next : hbyte;
- signal char_en : std_logic;
- type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
+ type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
signal state, state_next : STATE_PC ;
begin
+
+ pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+ pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+ pc_get <= get;
+ tx_new <= new_i;
+ tx_done_i_next <= tx_done;
+ tx_data <= tx_data_i;
+
sync: process (sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
state <= IDLE;
- push_history <= '0';
- spalte <= "0000000";
- zeile <= "0000000";
+ spalte <= 1;
+ zeile <= 1;
+ get <= '0';
+ new_i <= '0';
+ tx_data_i <= "00000000";
+ tx_done_i <= '0';
elsif rising_edge(sys_clk) then
- push_history <= push_history_next;
spalte <= spalte_next;
zeile <= zeile_next;
state <= state_next;
- if (char_en = '1') then
- state <= state_next;
- end if;
+ get <= get_next;
+ new_i <= new_i_next;
+ tx_done_i <= tx_done_i_next;
+ tx_data_i <= tx_data_i_next;
end if;
end process sync;
- process (spalte_up)
- variable spalte_tmp, zeile_tmp : integer;
+ output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
begin
- if (spalte_up = '1') then
- if (spalte > X"45") then
- spalte_next <= "0000000";
- zeile_tmp := to_integer(unsigned(zeile));
- zeile_tmp := zeile_tmp + 1;
- zeile_next <= hbyte(to_unsigned(zeile_tmp,8));
- else
- spalte_tmp := to_integer(unsigned(spalte));
- spalte_tmp := spalte_tmp + 1;
- spalte_next <= hbyte(to_unsigned(spalte_tmp,8));
- zeile_next <= zeile;
- end if;
- spalte_up <= '0';
- end if;
- end process;
+ get_next <= '0';
+ new_i_next <= '0';
- async_push_history : process (rx_new, rx_data, btn_a)
- begin
- if rx_new = '1' then
- if rx_data = X"41" then
- push_history_next <= '1';
- else
- push_history_next <= '0';
- end if;
- elsif btn_a = '1' then
- push_history_next <= '1';
- else
- push_history_next <= '0';
- end if;
- end process async_push_history;
+ spalte_next <= spalte;
+ zeile_next <= zeile;
+ tx_data_i_next <= tx_data_i;
- output_pc : process (zeile, spalte)
- begin
- case state is
+ case state is
when IDLE =>
- spalte_next <= "0000000";
- zeile_next <= "0000000";
+ null;
when FETCH =>
- d_zeile <= zeile;
- d_spalte <= spalte;
- d_get <= '1';
- char_en <= '1';
- -- wait for timer overflow
- -- increment counter
+ get_next <= '1';
+ when WAIT_HIST =>
+ tx_data_i_next <= pc_char;
when FORWARD =>
- char_en <= '0';
- tx_data <= char;
- tx_new <= '1';
- when DONE =>
- null;
- -- be there for a single cycle and then
+ new_i_next <= '1';
+ when WAIT_UART =>
+ new_i_next <= '1';
+ when UART_DONE =>
+ if tx_data_i = x"00" or spalte = HSPALTE_MAX then
+ tx_data_i_next <= x"0a";
+ zeile_next <= zeile + 1;
+ spalte_next <= 1;
+ if zeile = HZEILE_MAX then
+ zeile_next <= 1;
+ end if;
+ else
+ spalte_next <= spalte + 1;
+ end if;
end case;
end process output_pc;
- next_state_pc : process (rx_new, btn_a)
+ next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte,
+ state, tx_data_i ,tx_done_i, zeile)
begin
+ state_next <= state;
case state is
when IDLE =>
- if rx_new= '1' or btn_a = '1' then
+-- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+ if (rx_new = '1') or btn_a = '0' then
state_next <= FETCH;
- char <= d_char; --latch
end if;
when FETCH =>
- if (d_done = '1') then
+ if pc_busy = '1' then
+ state_next <= WAIT_HIST;
+ else
+ state_next <= FETCH;
+ end if;
+ when WAIT_HIST =>
+ if (pc_done = '1') then
state_next <= FORWARD;
end if;
when FORWARD =>
- if (tx_done = '1') then
+ state_next <= WAIT_UART;
+ when WAIT_UART =>
+ if (tx_done_i = '1') then
+ state_next <= UART_DONE;
+ end if;
+ when UART_DONE =>
+ if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and
+ zeile = HZEILE_MAX then
+ state_next <= IDLE;
+ else
state_next <= FETCH;
end if;
- when DONE =>
- -- be there for a single cycle and then
- state_next <= IDLE;
end case;
end process next_state_pc;
projects / hwmod.git / blobdiff