rx_new : in std_logic;
-- History
- d_zeile : out hzeile;
- d_spalte : out hspalte;
- d_get : out std_logic;
- d_done : in std_logic;
- d_char : in hbyte
+ pc_zeile : out hzeile;
+ pc_spalte : out hspalte;
+ pc_get : out std_logic;
+ pc_busy : in std_logic; --signals if the history module actually grants our request.
+ pc_done : in std_logic;
+ pc_char : in hbyte
);
end entity pc_communication;
architecture beh of pc_communication is
- signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
- signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
+ signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1;
+ signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1;
signal get, get_next : std_logic;
signal new_i, new_i_next : std_logic;
signal tx_done_i, tx_done_i_next : std_logic;
signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
- signal s_done, s_done_next : std_logic;
- type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
+ type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
signal state, state_next : STATE_PC ;
begin
- d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
- d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
- d_get <= get;
+ pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+ pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+ pc_get <= get;
tx_new <= new_i;
tx_done_i_next <= tx_done;
tx_data <= tx_data_i;
new_i <= '0';
tx_data_i <= "00000000";
tx_done_i <= '0';
- s_done <= '0';
elsif rising_edge(sys_clk) then
spalte <= spalte_next;
zeile <= zeile_next;
new_i <= new_i_next;
tx_done_i <= tx_done_i_next;
tx_data_i <= tx_data_i_next;
- s_done <= s_done_next;
end if;
end process sync;
- output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i)
- variable spalte_up : std_logic;
+ output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
begin
get_next <= '0';
new_i_next <= '0';
- s_done_next <= '0';
spalte_next <= spalte;
zeile_next <= zeile;
tx_data_i_next <= tx_data_i;
- spalte_up := '0';
case state is
when IDLE =>
null;
when FETCH =>
get_next <= '1';
- tx_data_i_next <= d_char;
+ when WAIT_HIST =>
+ tx_data_i_next <= pc_char;
when FORWARD =>
new_i_next <= '1';
- if (tx_done_i = '1') then
- spalte_up := '1';
- end if;
-
- when DONE =>
- null;
- end case;
-
- if spalte_up = '1' then
- if spalte = hspalte_max then
- if zeile = hzeile_max then
+ when WAIT_UART =>
+ new_i_next <= '1';
+ when UART_DONE =>
+ if tx_data_i = x"00" or spalte = HSPALTE_MAX then
+ tx_data_i_next <= x"0a";
+ zeile_next <= zeile + 1;
spalte_next <= 1;
- zeile_next <= 1;
- s_done_next <= '1';
+ if zeile = HZEILE_MAX then
+ zeile_next <= 1;
+ end if;
else
- spalte_next <= 1;
- zeile_next <= zeile + 1;
+ spalte_next <= spalte + 1;
end if;
- else
- spalte_next <= spalte + 1; --overflow here!
- zeile_next <= zeile;
- end if;
- end if;
-
+ end case;
end process output_pc;
- next_state_pc : process (state, rx_new, rx_data, btn_a, d_done, tx_done_i, s_done)
+ next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte,
+ state, tx_data_i ,tx_done_i, zeile)
begin
state_next <= state;
case state is
when IDLE =>
- if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
+-- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+ if (rx_new = '1') or btn_a = '0' then
state_next <= FETCH;
end if;
when FETCH =>
- if (d_done = '1') then
+ if pc_busy = '1' then
+ state_next <= WAIT_HIST;
+ else
+ state_next <= FETCH;
+ end if;
+ when WAIT_HIST =>
+ if (pc_done = '1') then
state_next <= FORWARD;
- elsif (s_done = '1') then
- state_next <= IDLE;
end if;
when FORWARD =>
+ state_next <= WAIT_UART;
+ when WAIT_UART =>
if (tx_done_i = '1') then
+ state_next <= UART_DONE;
+ end if;
+ when UART_DONE =>
+ if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and
+ zeile = HZEILE_MAX then
+ state_next <= IDLE;
+ else
state_next <= FETCH;
end if;
- when DONE =>
- state_next <= IDLE;
end case;
end process next_state_pc;
projects / hwmod.git / blobdiff