use ieee.numeric_std.all;
use work.gen_pkg.all;
-
entity pc_communication is
port (
sys_clk : in std_logic;
tx_done : in std_logic;
--uart_rx
- rx_data : in std_logic_vector(7 downt 0); --not really required
- rx_new : in std_logic_vector;
+ rx_data : in std_logic_vector(7 downto 0);
+ rx_new : in std_logic;
-- History
- d_zeile : out hzeile;
- d_spalte : out hspalte;
- d_get : out std_logic;
- d_done : in std_logic;
- d_char : in hbyte --;
+ pc_zeile : out hzeile;
+ pc_spalte : out hspalte;
+ pc_get : out std_logic;
+ pc_done : in std_logic;
+ pc_char : in hbyte
);
end entity pc_communication;
+architecture beh of pc_communication is
+ signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
+ signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
+ signal get, get_next : std_logic;
+ signal new_i, new_i_next : std_logic;
+ signal tx_done_i, tx_done_i_next : std_logic;
+ signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
-
-architecture beh of display is
- signal push_history, push_history_next : std_logic;
+ type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT,
+ NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
+ PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
+ PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT);
+ signal state, state_next : STATE_PC ;
begin
+ pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+ pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+ pc_get <= get;
+ tx_new <= new_i;
+ tx_done_i_next <= tx_done;
+ tx_data <= tx_data_i;
- sync_push_history : process (sys_clk, sys_res_n)
+ sync: process (sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
- push_history <= '0';
+ state <= IDLE;
+ spalte <= 1;
+ zeile <= 0;
+ get <= '0';
+ new_i <= '0';
+ tx_data_i <= x"00";
+ tx_done_i <= '0';
elsif rising_edge(sys_clk) then
- push_history <= push_history_next;
+ spalte <= spalte_next;
+ zeile <= zeile_next;
+ state <= state_next;
+ get <= get_next;
+ new_i <= new_i_next;
+ tx_done_i <= tx_done_i_next;
+ tx_data_i <= tx_data_i_next;
end if;
- end process sync_push_history;
+ end process sync;
- push_history : process(rx_new, rx_data, btn_a)
+ process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
+ pc_done)
+ variable tmp : std_logic_vector(6 downto 0);
begin
- if ( (rx_new = '1' and rx_data = X"41") or btn_a '1') then
- push_history_next <= '1';
- else
- push_history_next <= '0';
- end if;
- end process push_history;
+ get_next <= '0';
+ new_i_next <= '0';
+ spalte_next <= spalte;
+ zeile_next <= zeile;
+ tx_data_i_next <= tx_data_i;
+
+ state_next <= state;
+ case state is
+ when IDLE =>
+-- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+ if (rx_new = '1') or btn_a = '0' then
+ state_next <= PRINT_NO0_WAIT;
+ end if;
+
+ when PRINT_NO0_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO1;
+ end if;
+ when PRINT_NO1 =>
+ tx_data_i_next <= x"28"; -- '('
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO1_WAIT;
+ end if;
+ when PRINT_NO1_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO2;
+ end if;
+ when PRINT_NO2 =>
+ tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO2_WAIT;
+ end if;
+ when PRINT_NO2_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO3;
+ end if;
+ when PRINT_NO3 =>
+ tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO3_WAIT;
+ end if;
+ when PRINT_NO3_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO4;
+ end if;
+ when PRINT_NO4 =>
+ tx_data_i_next <= x"29"; -- ')'
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO4_WAIT;
+ end if;
+ when PRINT_NO4_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO5;
+ end if;
+ when PRINT_NO5 =>
+ tx_data_i_next <= x"24"; -- '$'
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO5_WAIT;
+ end if;
+ when PRINT_NO5_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO6;
+ end if;
+ when PRINT_NO6 =>
+ tx_data_i_next <= x"20"; -- ' '
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= FETCH;
+ end if;
--- sync_pc : process ()
--- begin
--- end process sync_pc;
---
--- next_state_pc : process ()
--- begin
--- end process next_state_pc;
---
--- output_pc : process ()
--- begin
--- end process output_pc;
+ when FETCH =>
+ get_next <= '1';
+ if pc_done = '1' and tx_done_i = '0' then
+ state_next <= FORWARD;
+ if pc_char = x"00" then
+ state_next <= UART_DONE;
+ end if;
+ end if;
+ when FORWARD =>
+ tx_data_i_next <= pc_char;
+ new_i_next <= '1';
+ -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+ get_next <= '1';
+ state_next <= WAIT_UART;
+ when WAIT_UART =>
+ new_i_next <= '1';
+ get_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= UART_DONE;
+ end if;
+ when UART_DONE =>
+ state_next <= FETCH;
+ spalte_next <= spalte + 1;
+ if spalte = HSPALTE_MAX + 1 then
+ state_next <= NL;
+ spalte_next <= 1;
+ zeile_next <= zeile + 1;
+ end if;
+ when NL =>
+ tx_data_i_next <= x"0a";
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= NL_WAIT;
+ end if;
+ when NL_WAIT =>
+ state_next <= CR;
+ when CR =>
+ tx_data_i_next <= x"0d";
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= CR_WAIT;
+ end if;
+ when CR_WAIT =>
+ tmp := std_logic_vector(to_unsigned(zeile,7));
+ if tmp(0) = '0' then
+ -- es handelt sich um eingabe
+ -- => print zeilennummer
+ state_next <= PRINT_NO0_WAIT;
+ else
+ state_next <= FETCH;
+ end if;
+ if zeile = HZEILE_MAX then
+ state_next <= IDLE;
+ zeile_next <= 0;
+ spalte_next <= 1;
+ end if;
+ end case;
+ end process;
end architecture beh;
projects / hwmod.git / blobdiff