signal get, get_next : std_logic;
signal new_i, new_i_next : std_logic;
signal tx_done_i, tx_done_i_next : std_logic;
- signal d_done_i, d_done_i_next : std_logic;
+ signal d_done_i : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
char_next <= d_char;
tx_new <= new_i;
d_done_i <= d_done;
- tx_done_i <= tx_done;
+ tx_done_i_next <= tx_done;
sync: process (sys_clk, sys_res_n)
begin
new_i <= '0';
tx_data <= "00000000";
spalte_up <= '0';
+ tx_done_i <= '0';
elsif rising_edge(sys_clk) then
push_history <= push_history_next;
spalte <= spalte_next;
state <= state_next;
get <= get_next;
new_i <= new_i_next;
+ tx_done_i <= tx_done_i_next;
spalte_up <= spalte_up_next;
if (char_en = '1') then
char <= char_next;
end if;
end process async_push_history;
- output_pc : process (state, zeile, spalte, char)
+ output_pc : process (state, zeile, spalte, char, tx_done_i)
begin
get_next <= '0';
new_i_next <= '0';
char_en <= '0';
tx_data <= char;
new_i_next <= '1';
- if (tx_done = '1') then
+ if (tx_done_i = '1') then
spalte_up_next <= '1';
end if;
when DONE =>
end case;
end process output_pc;
- next_state_pc : process (rx_new, btn_a, d_done, tx_done)
+ next_state_pc : process (rx_new, btn_a, d_done, tx_done_i)
begin
case state is
when IDLE =>
state_next <= FORWARD;
end if;
when FORWARD =>
- if (tx_done = '1') then
+ if (tx_done_i = '1') then
state_next <= FETCH;
end if;
when DONE =>