library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity pc_communication is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;

		--button
		btn_a : in std_logic;

		--uart_tx
		tx_data : out std_logic_vector(7 downto 0);
		tx_new : out std_logic;
		tx_done : in std_logic;

		--uart_rx
		rx_data : in std_logic_vector(7 downto 0); --not really required
		rx_new : in std_logic;

		-- History
		d_zeile : out hzeile;
		d_spalte : out hspalte;
		d_get :  out std_logic;
		d_done : in std_logic;
		d_char : in hbyte
	);
end entity pc_communication;

architecture beh of pc_communication is
	signal push_history, push_history_next : std_logic;

	signal spalte, spalte_next : integer range 0 to 71;
	signal zeile , zeile_next : integer range 0 to 71;
	signal spalte_up, spalte_up_next : std_logic;
	signal get, get_next : std_logic;
	signal new_i, new_i_next : std_logic;
	signal tx_done_i, tx_done_i_next : std_logic;
	signal d_done_i : std_logic;

	signal char, char_next : hbyte;
	signal char_en : std_logic;
	type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
	signal state, state_next : STATE_PC ;

begin


	d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
	d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
	d_get <= get;
	char_next <= d_char;
	tx_new <= new_i;
	d_done_i <= d_done;
	tx_done_i_next <= tx_done;

	sync: process (sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			state <= IDLE;
			push_history <= '0';
			spalte <= 0;
			zeile <= 0;
			get <= '0';
			new_i <= '0';
			tx_data <= "00000000";
			spalte_up <= '0';
			tx_done_i <= '0';
		elsif rising_edge(sys_clk) then
			push_history <= push_history_next;
			spalte <= spalte_next;
			zeile <= zeile_next;
			state <= state_next;
			get <= get_next;
			new_i <= new_i_next;
			tx_done_i <= tx_done_i_next;
			spalte_up <= spalte_up_next;
			if (char_en = '1') then
				char <= char_next;
			end if;
		end if;
	end process sync;

	process (spalte_up, spalte, zeile)
	begin
		if (spalte_up = '1') then
			if (spalte > 71) then
				spalte_next <= 0;
				zeile_next <= zeile + 1;
			else
				spalte_next <= spalte + 1;
				zeile_next <= zeile;
			end if;
		else
			spalte_next <= spalte;
			zeile_next <= zeile;
		end if;
	end process;

	async_push_history : process (rx_new, rx_data, btn_a)
	begin
		if rx_new = '1' then
			if rx_data = X"41" then
				push_history_next <= '1';
			else
				push_history_next <= '0';
			end if;
		elsif btn_a = '1' then
				push_history_next <= '1';
		else
			push_history_next <= '0';
		end if;
	end process async_push_history;

	output_pc : process (state, zeile, spalte, char, tx_done_i)
	begin
		get_next <= '0';
		new_i_next <= '0';
		spalte_up_next <= '0';
		case state is
			when IDLE =>
				null;
			when FETCH =>
				get_next <= '1';
				char_en <= '1';
			when FORWARD =>
				char_en <= '0';
				tx_data <= char;
				new_i_next <= '1';
				if (tx_done_i = '1') then
					spalte_up_next <= '1';
				end if;
			when DONE =>
				null;
		end case;
	end process output_pc;

	next_state_pc : process (rx_new, btn_a, d_done, tx_done_i)
	begin
		case state is
			when IDLE =>
				if rx_new = '1' or btn_a = '1' then
					state_next <= FETCH;
					
				end if;
			when FETCH =>
				if (d_done = '1') then
					state_next <= FORWARD;
				end if;
			when FORWARD =>
				if (tx_done_i = '1') then
					state_next <= FETCH;
				end if;
			when DONE =>
				state_next <= IDLE;
		end case;
	end process next_state_pc;

end architecture beh;