sys_clk : in std_logic;
sys_res_n : in std_logic;
-- History
- p_rw : out std_logic;
- p_spalte : out hspalte;
p_rget : out std_logic;
p_rdone : in std_logic;
p_read : in hbyte;
signal p_rget_int, p_rget_next : std_logic;
signal p_wtake_int, p_wtake_next : std_logic;
signal p_finished_int, p_finished_next : std_logic;
+ signal finished_int, finished_next : std_logic;
signal aktop_int, aktop_next : alu_ops;
signal opp_int, opp_next : alu_ops;
signal opcode_int, opcode_next : alu_ops;
p_rget <= p_rget_int;
p_wtake <= p_wtake_int;
p_finished <= p_finished_int;
+ finished <= finished_int;
opcode <= opcode_int;
op1 <= op1_int;
errc_tmp_int <= 0;
firstz_int <= true;
-- out ports
- p_rw <= '0';
- p_spalte <= (others => '0');
p_rget_int <= '0';
p_write_int <= (others => '0');
p_wtake_int <= '0';
p_finished_int <= '0';
+ finished_int <= '0';
opcode_int <= ALU_NOP;
op1_int <= (others => '0');
op2_int <= (others => '0');
do_calc_int <= '0';
- finished <= '0';
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
p_write_int <= p_write_next;
p_wtake_int <= p_wtake_next;
p_finished_int <= p_finished_next;
+ finished_int <= finished_next;
opcode_int <= opcode_next;
op1_int <= op1_next;
op2_int <= op2_next;
type errstrings is array (natural range 1 to 3) of hstring;
constant error_str : errstrings := (
- 1 => " Division durch Null" & nul,
- 2 => " Syntax" & nul,
- 3 => " Over- bzw. Underflow" & nul
+ 1 => " > Fehler: Division durch Null " & nul,
+ 2 => " > Fehler: Syntax " & nul,
+ 3 => " > Fehler: Over- bzw. Underflow " & nul
);
begin
-- internal
p_write_next <= p_write_int;
p_wtake_next <= '0';
p_finished_next <= '0';
+ finished_next <= '0';
opcode_next <= opcode_int;
op1_next <= op1_int;
op2_next <= op2_int;
err_next <= 0;
errc_next <= 71;
p_finished_next <= '1';
+ finished_next <= '1';
end case;
-- fehlerbehandlung