pc_zeile : in hzeile;
pc_char : out hbyte;
pc_done : out std_logic;
+ pc_busy : out std_logic;
-- Scanner
s_char : in hbyte;
s_take : in std_logic;
signal p_sp_write_int, p_sp_write_next : hspalte;
signal pc_char_next ,pc_char_int : hbyte;
signal pc_done_next, pc_done_int : std_logic;
+ signal pc_busy_next, pc_busy_int : std_logic;
-- ram
signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
p_wdone <= p_wdone_int;
p_read <= p_read_int;
pc_done <= pc_done_int;
+ pc_busy <= pc_busy_int;
pc_char <= pc_char_int;
process(sys_clk, sys_res_n)
process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
- p_write, p_sp_read_int, p_sp_write_int)
+ p_write, p_sp_read_int, p_sp_write_int, pc_char_int, pc_zeile, pc_spalte)
variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
variable spalte_tmp : hspalte;
variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);