d_done : out std_logic;
d_char : out hbyte;
-- Parser
- -- TODO: pins
-
- -- TODO: tmp only!
- do_it : in std_logic;
- finished : out std_logic
+ p_rget : in std_logic;
+ p_rdone : out std_logic;
+ p_read : out hbyte;
+ p_wtake : in std_logic;
+ p_wdone : out std_logic;
+ p_write : in hbyte;
+ p_finished : in std_logic
);
end entity history;
architecture beh of history is
type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
- S_D_INIT, S_D_READ, S_S_FIN_POSUP);
+ S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
+ S_P_WRITE_DONE, S_P_DONE);
signal state_int, state_next : HISTORY_STATE;
signal was_bs_int, was_bs_next : std_logic;
signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
signal d_new_bs_int, d_new_bs_next: std_logic;
signal d_done_int, d_done_next : std_logic;
signal d_char_int, d_char_next : hbyte;
-
- signal finished_int, finished_next : std_logic;
+ signal p_rdone_int, p_rdone_next : std_logic;
+ signal p_wdone_int, p_wdone_next : std_logic;
+ signal p_read_int, p_read_next : hbyte;
+ signal p_sp_read_int, p_sp_read_next : hspalte;
+ signal p_sp_write_int, p_sp_write_next : hspalte;
-- ram
signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
d_new_bs <= d_new_bs_int;
d_done <= d_done_int;
d_char <= d_char_int;
-
- finished <= finished_int;
+ p_rdone <= p_rdone_int;
+ p_wdone <= p_wdone_int;
+ p_read <= p_read_int;
process(sys_clk, sys_res_n)
begin
d_new_bs_int <= '0';
d_done_int <= '0';
d_char_int <= (others => '0');
-
- finished_int <= '0';
+ p_rdone_int <= '0';
+ p_wdone_int <= '0';
+ p_read_int <= (others => '0');
+ p_sp_read_int <= (others => '0');
+ p_sp_write_int <= (others => '0');
address_int <= (0 => '1', others => '0');
data_in_int <= x"00";
d_new_bs_int <= d_new_bs_next;
d_done_int <= d_done_next;
d_char_int <= d_char_next;
-
- finished_int <= finished_next;
+ p_rdone_int <= p_rdone_next;
+ p_wdone_int <= p_wdone_next;
+ p_read_int <= p_read_next;
+ p_sp_read_int <= p_sp_read_next;
+ p_sp_write_int <= p_sp_write_next;
address_int <= address_next;
data_in_int <= data_in_next;
end process;
-- next state
- process(state_int, d_get, do_it, s_take, s_backspace, was_bs_int)
+ process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int,
+ p_rget, p_wtake)
begin
state_next <= state_int;
-- S_S_FIN: tmp..
if s_take = '1' then
state_next <= S_S_INIT;
- elsif do_it = '1' then
+ elsif p_rget = '1' then
+ state_next <= S_P_READ;
+ elsif p_wtake = '1' then
+ state_next <= S_P_WRITE;
+ elsif p_finished = '1' then
state_next <= S_S_FIN;
elsif d_get = '1' then
state_next <= S_D_INIT;
when S_S_BS =>
state_next <= S_S_DONE;
when S_S_FIN =>
- if do_it = '0' then
+ if p_finished = '0' then
state_next <= S_S_FIN_POSUP;
end if;
when S_S_FIN_POSUP =>
if d_get = '0' then
state_next <= SIDLE;
end if;
+
+ when S_P_READ =>
+ state_next <= S_P_READ_DONE;
+ when S_P_READ_DONE =>
+ if p_rget = '0' then
+ state_next <= S_P_DONE;
+ end if;
+ when S_P_WRITE =>
+ state_next <= S_P_WRITE_DONE;
+ when S_P_WRITE_DONE =>
+ if p_wtake = '0' then
+ state_next <= S_P_DONE;
+ end if;
+ when S_P_DONE =>
+ state_next <= SIDLE;
end case;
end process;
-- out
process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
- data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
- was_bs_int, s_take, pos_int)
+ data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
+ was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
+ p_write, p_sp_read_int, p_sp_write_int)
variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
+ variable spalte_tmp : hspalte;
variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
begin
s_done_next <= '0';
d_new_bs_next <= '0';
d_done_next <= '0';
d_char_next <= (others => '0');
- finished_next <= '0';
wr_next <= '0';
address_next <= address_int;
data_in_next <= data_in_int;
+ p_rdone_next <= p_rdone_int;
+ p_wdone_next <= p_wdone_int;
+ p_read_next <= p_read_int;
+ p_sp_read_next <= p_sp_read_int;
+ p_sp_write_next <= p_sp_write_int;
case state_int is
when SIDLE =>
data_in_next <= (others => '0');
was_bs_next <= '1';
when S_S_FIN =>
- finished_next <= '1';
s_cnt_next <= (0 => '1', others => '0');
d_new_result_next <= '1';
when S_S_FIN_POSUP =>
if s_take = '0' then
was_bs_next <= '0';
end if;
+ -- TODO: bessere stelle fuers reseten der parser signale?
+ p_sp_read_next <= (others => '0');
+ p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
when S_D_INIT =>
addr_tmp := (others => '0');
when S_D_READ =>
d_char_next <= data_out;
d_done_next <= '1';
+
+ when S_P_READ =>
+ wr_next <= '0';
+ spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
+ p_sp_read_next <= spalte_tmp;
+ address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp));
+ when S_P_READ_DONE =>
+ p_rdone_next <= '1';
+ p_read_next <= data_out;
+
+ when S_P_WRITE =>
+ wr_next <= '1';
+ data_in_next <= p_write;
+ spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
+ p_sp_write_next <= spalte_tmp;
+ address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
+ when S_P_WRITE_DONE =>
+ p_wdone_next <= '1';
+ when S_P_DONE =>
+ p_rdone_next <= '0';
+ p_wdone_next <= '0';
end case;
end process;
projects / hwmod.git / blobdiff