d_spalte : in hspalte;
d_get : in std_logic;
d_done : out std_logic;
- d_char : out hbyte
+ d_char : out hbyte;
-- Parser
-- TODO: pins
+
+ -- TODO: tmp only!
+ do_it : in std_logic;
+ finished : out std_logic
);
end entity history;
architecture beh of history is
- type HISTORY_STATE is (SIDLE);
+ type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
+ S_D_INIT, S_D_WRITE);
signal state_int, state_next : HISTORY_STATE;
signal s_done_int, s_done_next : std_logic;
+ signal s_cnt_int, s_cnt_next : hspalte;
signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
signal d_new_result_int, d_new_result_next : std_logic;
signal d_done_int, d_done_next : std_logic;
signal d_char_int, d_char_next : hbyte;
+
+ signal finished_int, finished_next : std_logic;
+
+ -- ram
+ signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
+ signal data_out, data_in_next, data_in_int : hbyte;
+ signal wr_next, wr_int : std_logic;
begin
s_done <= s_done_int;
d_new_eingabe <= d_new_eingabe_int;
d_done <= d_done_int;
d_char <= d_char_int;
+ finished <= finished_int;
+
process(sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
state_int <= SIDLE;
-- out
s_done_int <= '0';
+ s_cnt_int <= (0 => '1', others => '0');
d_new_result_int <= '0';
d_new_eingabe_int <= '0';
d_done_int <= '0';
d_char_int <= (others => '0');
+
+ finished_int <= '0';
+
+ address_int <= (0 => '1', others => '0');
+ data_in_int <= x"00";
+ wr_int <= '0';
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
-- out
s_done_int <= s_done_next;
+ s_cnt_int <= s_cnt_next;
d_new_result_int <= d_new_result_next;
d_new_eingabe_int <= d_new_eingabe_next;
d_done_int <= d_done_next;
d_char_int <= d_char_next;
+
+ finished_int <= finished_next;
+
+ address_int <= address_next;
+ data_in_int <= data_in_next;
+ wr_int <= wr_next;
end if;
end process;
-- next state
- process(state_int)
+ process(state_int, d_get, do_it, s_take, s_backspace)
begin
state_next <= state_int;
case state_int is
when SIDLE =>
- null;
+ -- S_S_FIN: tmp..
+ if s_take = '1' then
+ state_next <= S_S_INIT;
+ elsif do_it = '1' then
+ state_next <= S_S_FIN;
+ elsif d_get = '1' then
+ state_next <= S_D_INIT;
+ end if;
+ when S_S_INIT =>
+ if s_backspace = '1' then
+ state_next <= S_S_BS;
+ else
+ state_next <= S_S_WRITE;
+ end if;
+ when S_S_WRITE | S_S_BS =>
+ state_next <= S_S_DONE;
+ when S_S_FIN =>
+ if do_it = '0' then
+ state_next <= SIDLE;
+ end if;
+ when S_S_DONE =>
+ if s_take = '0' then
+ state_next <= SIDLE;
+ end if;
+
+ when S_D_INIT =>
+ state_next <= S_D_WRITE;
+ when S_D_WRITE =>
+ if d_get = '0' then
+ state_next <= SIDLE;
+ end if;
end case;
end process;
-- out
- process(state_int)
+ process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int,
+ data_in_int, d_new_result_int, d_new_eingabe_int)
begin
+ s_done_next <= '0';
+ s_cnt_next <= s_cnt_int;
+ d_new_result_next <= d_new_result_int;
+ d_new_eingabe_next <= d_new_eingabe_int;
+ d_done_next <= '0';
+ d_char_next <= (others => '0');
+ finished_next <= '0';
+ wr_next <= '0';
+ address_next <= address_int;
+ data_in_next <= data_in_int;
+
case state_int is
- when SIDLE =>
+ when S_S_INIT =>
null;
+ when SIDLE =>
+ -- TODO: tmp fix
+ d_new_result_next <= '0';
+ when S_S_WRITE =>
+ wr_next <= '1';
+ address_next <= s_cnt_int;
+ data_in_next <= s_char;
+ s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
+ when S_S_BS =>
+ wr_next <= '1';
+ address_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
+ data_in_next <= (others => '0');
+ if unsigned(s_cnt_int) /= 0 then
+ s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
+ end if;
+ when S_S_FIN =>
+ finished_next <= '1';
+ s_cnt_next <= (0 => '1', others => '0');
+ d_new_result_next <= '1';
+ when S_S_DONE =>
+ s_done_next <= '1';
+ d_new_eingabe_next <= '1';
+
+ when S_D_INIT =>
+ address_next <= d_spalte;
+ d_new_eingabe_next <= '0';
+ d_new_result_next <= '0';
+ when S_D_WRITE =>
+ d_char_next <= data_out;
+ d_done_next <= '1';
end case;
end process;
+
+ sp_ram_inst : entity work.sp_ram(beh)
+ generic map (
+ ADDR_WIDTH => H_RAM_WIDTH
+ )
+ port map (
+ sys_clk => sys_clk,
+ address => address_int,
+ data_out => data_out,
+ wr => wr_int,
+ data_in => data_in_int
+ );
end architecture beh;
projects / hwmod.git / blobdiff