end entity display;
architecture beh of display is
- type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT);
+ type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
+ S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, S_WAIT, S_NOP1);
signal state_int, state_next : DISPLAY_STATE;
signal d_zeile_int, d_zeile_next : hzeile;
signal d_spalte_int, d_spalte_next : hspalte;
signal d_get_int, d_get_next : std_logic;
signal command_int, command_next : std_logic_vector(7 downto 0);
signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
+ signal istate_next, istate_int : signed(2 downto 0);
begin
d_zeile <= d_zeile_int;
d_spalte <= d_spalte_int;
if sys_res_n = '0' then
-- internal
state_int <= SIDLE;
+ istate_int <= (others => '0');
-- out
d_zeile_int <= (others => '0');
d_spalte_int <= (others => '0');
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
+ istate_int <= istate_next;
-- out
d_zeile_int <= d_zeile_next;
d_spalte_int <= d_spalte_next;
end process;
-- next state
- process(state_int, d_new_result, d_new_eingabe, d_done, free)
+ process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
+ d_char, istate_int)
begin
state_next <= state_int;
+ istate_next <= istate_int;
case state_int is
when SIDLE =>
- if free = '1' then
- if d_new_eingabe = '1' then
- state_next <= S_NEW_INPUT;
- end if;
- if d_new_result = '1' then
- state_next <= S_NEW_RESULT;
- end if;
+ istate_next <= b"111"; -- default: immer wieder ins SIDLE;
+ if d_new_eingabe = '1' then
+ state_next <= S_NEW_INPUT;
+ end if;
+ if d_new_result = '1' then
+ state_next <= S_NEW_RESULT;
+ end if;
+ when S_NEW_RESULT =>
+ state_next <= S_CR1;
+ when S_NEW_INPUT =>
+ state_next <= S_COUNTUP;
+ when S_CR1 =>
+ if free = '0' then
+ state_next <= S_WAIT;
+ istate_next <= b"000"; -- => danach S_NL1
end if;
- when S_NEW_RESULT | S_NEW_INPUT =>
+ when S_NL1 =>
if free = '0' then
- state_next <= SIDLE;
+ state_next <= S_WAIT;
+ istate_next <= b"111"; -- => wieder nach SIDLE
+ end if;
+ when S_COUNTUP =>
+ state_next <= S_GETCH;
+ when S_GETCH =>
+ if free = '1' and d_done = '1' and d_new_result = '0' and d_new_eingabe = '0' then
+ state_next <= S_PUTCH1;
+ end if;
+ when S_PUTCH1 =>
+ state_next <= S_PUTCH2;
+ when S_PUTCH2 =>
+ if free = '0' or (free = '1' and d_char = x"00") then
+ state_next <= S_WAIT;
+ end if;
+ when S_WAIT =>
+ if free = '1' and d_done = '0' then
+ state_next <= S_NOP1;
+ end if;
+ when S_NOP1 =>
+ if free = '1' then
+ case istate_int is
+ when b"000" => state_next <= S_NL1;
+ when others => state_next <= SIDLE;
+ end case;
end if;
end case;
end process;
-- out
process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
- command_data_int)
+ command_data_int, d_char)
begin
d_zeile_next <= d_zeile_int;
d_spalte_next <= d_spalte_int;
- d_get_next <= d_get_int;
+ d_get_next <= '0';
command_next <= command_int;
command_data_next <= command_data_int;
case state_int is
- when SIDLE | S_NEW_INPUT | S_NEW_RESULT =>
+ when SIDLE =>
+ null;
+ when S_NEW_INPUT =>
null;
+ when S_NEW_RESULT =>
+ d_spalte_next <= (others => '0');
+ case d_zeile_int is
+ when "11111" => d_zeile_next <= "00000";
+ when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
+ end case;
+ when S_CR1 =>
+ command_next <= COMMAND_SET_CHAR;
+ command_data_next <= x"ffffff" & x"0d"; -- carrige return
+ when S_NL1 =>
+ command_next <= COMMAND_SET_CHAR;
+ command_data_next <= x"ffffff" & x"0a"; -- newline
+ when S_COUNTUP =>
+ d_get_next <= '1';
+ d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
+ when S_GETCH =>
+ d_get_next <= '1';
+ when S_PUTCH1 =>
+ if d_char /= x"00" then
+ command_next <= COMMAND_SET_CHAR;
+ command_data_next <= x"ffffff" & std_logic_vector(d_char);
+ end if;
+ when S_PUTCH2 => null;
+ when S_WAIT | S_NOP1 =>
+ command_next <= COMMAND_NOP;
+ command_data_next <= x"00000000";
end case;
end process;
end architecture beh;