signal d_get_int, d_get_next : std_logic;
signal command_int, command_next : std_logic_vector(7 downto 0);
signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
+ signal istate_next, istate_int : signed(2 downto 0);
begin
d_zeile <= d_zeile_int;
d_spalte <= d_spalte_int;
if sys_res_n = '0' then
-- internal
state_int <= SIDLE;
+ istate_int <= (others => '0');
-- out
d_zeile_int <= (others => '0');
d_spalte_int <= (others => '0');
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
+ istate_int <= istate_next;
-- out
d_zeile_int <= d_zeile_next;
d_spalte_int <= d_spalte_next;
-- next state
process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
- d_char)
+ d_char, istate_int)
begin
state_next <= state_int;
+ istate_next <= istate_int;
case state_int is
when SIDLE =>
+ istate_next <= b"111"; -- default: immer wieder ins SIDLE;
if d_new_eingabe = '1' then
state_next <= S_NEW_INPUT;
end if;
state_next <= S_COUNTUP;
when S_CR1 =>
if free = '0' then
- state_next <= S_NL1;
+ state_next <= S_WAIT;
+ istate_next <= b"000"; -- => danach S_NL1
end if;
when S_NL1 =>
if free = '0' then
- state_next <= S_COUNTUP;
+ state_next <= S_WAIT;
+ istate_next <= b"111"; -- => wieder nach SIDLE
end if;
when S_COUNTUP =>
state_next <= S_GETCH;
when S_GETCH =>
- if free = '1' and d_done = '1' then
+ if free = '1' and d_done = '1' and d_new_result = '0' and d_new_eingabe = '0' then
state_next <= S_PUTCH1;
end if;
when S_PUTCH1 =>
end if;
when S_NOP1 =>
if free = '1' then
- state_next <= SIDLE;
- --if unsigned(d_spalte_int) = 71 then
- -- state_next <= SIDLE;
- --else
- -- state_next <= S_COUNTUP;
- --end if;
+ case istate_int is
+ when b"000" => state_next <= S_NL1;
+ when others => state_next <= SIDLE;
+ end case;
end if;
end case;
end process;