-- History
d_new_eingabe : in std_logic;
d_new_result : in std_logic;
+ d_new_bs : in std_logic;
d_zeile : out hzeile;
d_spalte : out hspalte;
d_get : out std_logic;
end entity display;
architecture beh of display is
- type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
- S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, S_WAIT, S_NOP1);
+ type DISPLAY_STATE is (SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT,
+ S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1, S_PUTCH2,
+ S_WAIT, S_NOP1);
signal state_int, state_next : DISPLAY_STATE;
signal d_zeile_int, d_zeile_next : hzeile;
signal d_spalte_int, d_spalte_next : hspalte;
end process;
-- next state
- process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
- d_char, istate_int)
+ process(state_int, d_new_result, d_new_eingabe, d_new_bs, d_done, free,
+ d_spalte_int, d_char, istate_int)
begin
state_next <= state_int;
istate_next <= istate_int;
case state_int is
when SIDLE =>
istate_next <= b"111"; -- default: immer wieder ins SIDLE;
- if d_new_eingabe = '1' then
+ if d_new_bs = '1' then
+ state_next <= S_NEW_BS;
+ elsif d_new_eingabe = '1' then
state_next <= S_NEW_INPUT;
end if;
if d_new_result = '1' then
state_next <= S_NEW_RESULT;
end if;
+
when S_NEW_RESULT =>
state_next <= S_CR1;
when S_NEW_INPUT =>
state_next <= S_COUNTUP;
+
+ when S_NEW_BS =>
+ state_next <= S_BACK;
+ when S_BACK =>
+ if free = '0' then
+ state_next <= S_WAIT;
+ case istate_int is
+ when b"111" => istate_next <= b"001"; -- => danach S_BLANK und wieder hierher
+ when others => istate_next <= b"111"; -- => danach SIDLE
+ end case;
+ end if;
+ when S_BLANK =>
+ if free = '0' then
+ state_next <= S_WAIT;
+ istate_next <= b"010"; -- => danach S_BACK
+ end if;
+
when S_CR1 =>
if free = '0' then
state_next <= S_WAIT;
state_next <= S_WAIT;
istate_next <= b"111"; -- => wieder nach SIDLE
end if;
+
when S_COUNTUP =>
state_next <= S_GETCH;
when S_GETCH =>
if free = '1' then
case istate_int is
when b"000" => state_next <= S_NL1;
+ when b"001" => state_next <= S_BLANK;
+ when b"010" => state_next <= S_BACK;
when others => state_next <= SIDLE;
end case;
end if;
case state_int is
when SIDLE =>
null;
- when S_NEW_INPUT =>
- null;
when S_NEW_RESULT =>
d_spalte_next <= (others => '0');
case d_zeile_int is
when "11111" => d_zeile_next <= "00000";
when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
end case;
+ when S_NEW_INPUT =>
+ null;
+
+ when S_NEW_BS =>
+ -- underflow check schon im history modul
+ d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) - 1);
+ when S_BACK =>
+ -- einen schritt zurueck
+ command_next <= COMMAND_SET_CURSOR_COLUMN;
+ command_data_next <= x"ffffff" & '0' & std_logic_vector(unsigned(d_spalte_int));
+ when S_BLANK =>
+ command_next <= COMMAND_SET_CHAR;
+ command_data_next <= x"ffffff" & x"20"; -- white space
+
when S_CR1 =>
command_next <= COMMAND_SET_CHAR;
command_data_next <= x"ffffff" & x"0d"; -- carrige return
when S_NL1 =>
command_next <= COMMAND_SET_CHAR;
command_data_next <= x"ffffff" & x"0a"; -- newline
+
when S_COUNTUP =>
d_get_next <= '1';
d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);