\item Scanner: fehler in der state-maschine: ein extriger uebergang von
\emph{read} auf \emph{\"ubernehmen} ist n\"otig um leerzeichen \"ubernehmen zu
k\"oennen.
+\item History $\Rightarrow$ Display: ein zus\"atzliches Signal \emph{d\_new\_bs}.
\end{itemize}
\end{document}
signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
-- history/display
- signal d_new_eingabe, d_new_result : std_logic;
+ signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
signal d_zeile : hzeile;
signal d_spalte : hspalte;
signal d_get, d_done : std_logic;
-- history
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
#signale hinzufuegen
add wave *
+delete wave d_spalte
+add wave inst/d_spalte
+add wave inst/s_cnt_int
+
+add wave inst/state_int
+add wave inst/was_bs_int
+
+add wave inst_disp/state_int
+add wave inst_disp/istate_int
+
#rauszoomen
wave zoomout 500.0
-- system
signal sys_clk, sys_res_n : std_logic;
-- history/display
- signal d_new_eingabe, d_new_result : std_logic;
+ signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
signal d_zeile : hzeile;
signal d_spalte : hspalte;
signal d_get, d_done : std_logic;
-- display
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
-- history
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
process
begin
free <= '0';
- icwait(sys_clk, 2);
+ wait for 15 ns;
free <= '1';
- icwait(sys_clk, 2);
+ wait for 30 ns;
if stop = true then
wait;
end if;
return y;
end function;
- function valid_char (x : std_logic_vector(7 downto 0); last : std_logic_vector(7 downto 0)) return boolean is
+ function valid_char (x : std_logic_vector(7 downto 0)) return boolean is
variable y : boolean;
begin
case x is
variable run_tc, run_inner : boolean := true;
variable i, j, y : natural;
- variable last : std_logic_vector(7 downto 0);
begin
-- init & reset
sys_res_n <= '0';
s_done <= '0';
finished <= '0';
- icwait(sys_clk, 5);
+ icwait(sys_clk, 20);
sys_res_n <= '1';
i := 1;
j := 0;
mainl : while run_tc loop
- last := data;
- icwait(sys_clk, 1);
+ icwait(sys_clk, 10);
j := j + 1;
if j = 73 then
-- ack'en skippen, falls es ein "spezielles" zeichen ist (steht
-- in abhaengigkeit zum vorherigen zeichen)
- if(not valid_char(data, last)) then
+ if(not valid_char(data)) then
next mainl;
end if;
signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
-- history/display
- signal d_new_eingabe, d_new_result : std_logic;
+ signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
signal d_zeile : hzeile;
signal d_spalte : hspalte;
signal d_get, d_done : std_logic;
-- history
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
-- display
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
-- history/display
- signal d_new_eingabe, d_new_result : std_logic;
+ signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
signal d_zeile : hzeile;
signal d_spalte : hspalte;
signal d_get, d_done : std_logic;
-- history
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
-- display
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
-- History
d_new_eingabe : in std_logic;
d_new_result : in std_logic;
+ d_new_bs : in std_logic;
d_zeile : out hzeile;
d_spalte : out hspalte;
d_get : out std_logic;
end entity display;
architecture beh of display is
- type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
- S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, S_WAIT, S_NOP1);
+ type DISPLAY_STATE is (SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT,
+ S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1, S_PUTCH2,
+ S_WAIT, S_NOP1);
signal state_int, state_next : DISPLAY_STATE;
signal d_zeile_int, d_zeile_next : hzeile;
signal d_spalte_int, d_spalte_next : hspalte;
end process;
-- next state
- process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
- d_char, istate_int)
+ process(state_int, d_new_result, d_new_eingabe, d_new_bs, d_done, free,
+ d_spalte_int, d_char, istate_int)
begin
state_next <= state_int;
istate_next <= istate_int;
case state_int is
when SIDLE =>
istate_next <= b"111"; -- default: immer wieder ins SIDLE;
- if d_new_eingabe = '1' then
+ if d_new_bs = '1' then
+ state_next <= S_NEW_BS;
+ elsif d_new_eingabe = '1' then
state_next <= S_NEW_INPUT;
end if;
if d_new_result = '1' then
state_next <= S_NEW_RESULT;
end if;
+
when S_NEW_RESULT =>
state_next <= S_CR1;
when S_NEW_INPUT =>
state_next <= S_COUNTUP;
+
+ when S_NEW_BS =>
+ state_next <= S_BACK;
+ when S_BACK =>
+ if free = '0' then
+ state_next <= S_WAIT;
+ case istate_int is
+ when b"111" => istate_next <= b"001"; -- => danach S_BLANK und wieder hierher
+ when others => istate_next <= b"111"; -- => danach SIDLE
+ end case;
+ end if;
+ when S_BLANK =>
+ if free = '0' then
+ state_next <= S_WAIT;
+ istate_next <= b"010"; -- => danach S_BACK
+ end if;
+
when S_CR1 =>
if free = '0' then
state_next <= S_WAIT;
state_next <= S_WAIT;
istate_next <= b"111"; -- => wieder nach SIDLE
end if;
+
when S_COUNTUP =>
state_next <= S_GETCH;
when S_GETCH =>
if free = '1' then
case istate_int is
when b"000" => state_next <= S_NL1;
+ when b"001" => state_next <= S_BLANK;
+ when b"010" => state_next <= S_BACK;
when others => state_next <= SIDLE;
end case;
end if;
case state_int is
when SIDLE =>
null;
- when S_NEW_INPUT =>
- null;
when S_NEW_RESULT =>
d_spalte_next <= (others => '0');
case d_zeile_int is
when "11111" => d_zeile_next <= "00000";
when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
end case;
+ when S_NEW_INPUT =>
+ null;
+
+ when S_NEW_BS =>
+ -- underflow check schon im history modul
+ d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) - 1);
+ when S_BACK =>
+ -- einen schritt zurueck
+ command_next <= COMMAND_SET_CURSOR_COLUMN;
+ command_data_next <= x"ffffff" & '0' & std_logic_vector(unsigned(d_spalte_int));
+ when S_BLANK =>
+ command_next <= COMMAND_SET_CHAR;
+ command_data_next <= x"ffffff" & x"20"; -- white space
+
when S_CR1 =>
command_next <= COMMAND_SET_CHAR;
command_data_next <= x"ffffff" & x"0d"; -- carrige return
when S_NL1 =>
command_next <= COMMAND_SET_CHAR;
command_data_next <= x"ffffff" & x"0a"; -- newline
+
when S_COUNTUP =>
d_get_next <= '1';
d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
-- integer ist 32bit (31bit + sign)
subtype cinteger is integer;
- -- vorerst: 1 * 71
+ -- TODO: 50 * 71 * 2 = 7100
constant H_RAM_SIZE : integer := 71;
- -- danach: 50 * 71 * 2 = 7100
- -- constant H_RAM_SIZE : integer := 7100;
constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
subtype hspalte is std_logic_vector(6 downto 0);
subtype hzeile is std_logic_vector(4 downto 0);
asdf213
# testfall 2:
12 + 4
+# testfall 3:
+123!!5
+# testfall 4:
+123!!!!5
-- Display
d_new_eingabe : out std_logic;
d_new_result : out std_logic;
+ d_new_bs : out std_logic;
d_zeile : in hzeile;
d_spalte : in hspalte;
d_get : in std_logic;
type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
S_D_INIT, S_D_WRITE);
signal state_int, state_next : HISTORY_STATE;
+ signal was_bs_int, was_bs_next : std_logic;
signal s_done_int, s_done_next : std_logic;
signal s_cnt_int, s_cnt_next : hspalte;
signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
signal d_new_result_int, d_new_result_next : std_logic;
+ signal d_new_bs_int, d_new_bs_next: std_logic;
signal d_done_int, d_done_next : std_logic;
signal d_char_int, d_char_next : hbyte;
s_done <= s_done_int;
d_new_eingabe <= d_new_eingabe_int;
d_new_result <= d_new_result_int;
+ d_new_bs <= d_new_bs_int;
d_done <= d_done_int;
d_char <= d_char_int;
if sys_res_n = '0' then
-- internal
state_int <= SIDLE;
+ was_bs_int <= '0';
-- out
s_done_int <= '0';
s_cnt_int <= (0 => '1', others => '0');
d_new_result_int <= '0';
d_new_eingabe_int <= '0';
+ d_new_bs_int <= '0';
d_done_int <= '0';
d_char_int <= (others => '0');
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
+ was_bs_int <= was_bs_next;
-- out
s_done_int <= s_done_next;
s_cnt_int <= s_cnt_next;
d_new_result_int <= d_new_result_next;
d_new_eingabe_int <= d_new_eingabe_next;
+ d_new_bs_int <= d_new_bs_next;
d_done_int <= d_done_next;
d_char_int <= d_char_next;
end process;
-- next state
- process(state_int, d_get, do_it, s_take, s_backspace)
+ process(state_int, d_get, do_it, s_take, s_backspace, was_bs_int)
begin
state_next <= state_int;
+ was_bs_next <= was_bs_int;
case state_int is
when SIDLE =>
else
state_next <= S_S_WRITE;
end if;
- when S_S_WRITE | S_S_BS =>
+ when S_S_WRITE =>
+ state_next <= S_S_DONE;
+ when S_S_BS =>
state_next <= S_S_DONE;
+ was_bs_next <= '1';
when S_S_FIN =>
if do_it = '0' then
state_next <= SIDLE;
when S_S_DONE =>
if s_take = '0' then
state_next <= SIDLE;
+ was_bs_next <= '0';
end if;
when S_D_INIT =>
-- out
process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int,
- data_in_int, d_new_result_int, d_new_eingabe_int)
+ data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
+ was_bs_int)
+ variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
begin
s_done_next <= '0';
s_cnt_next <= s_cnt_int;
d_new_result_next <= d_new_result_int;
d_new_eingabe_next <= d_new_eingabe_int;
+ d_new_bs_next <= '0';
d_done_next <= '0';
d_char_next <= (others => '0');
finished_next <= '0';
data_in_next <= data_in_int;
case state_int is
- when S_S_INIT =>
- null;
when SIDLE =>
-- TODO: tmp fix
d_new_result_next <= '0';
+ when S_S_INIT =>
+ null;
when S_S_WRITE =>
wr_next <= '1';
address_next <= s_cnt_int;
data_in_next <= s_char;
s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
when S_S_BS =>
+ -- ab 1 darf nicht mehr dekrementiert werden
+ if unsigned(s_cnt_int) /= 1 then
+ addr_tmp := std_logic_vector(unsigned(s_cnt_int) - 1);
+ d_new_bs_next <= '1';
+ else
+ addr_tmp := s_cnt_int;
+ end if;
+ s_cnt_next <= addr_tmp;
+
wr_next <= '1';
- address_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
+ address_next <= addr_tmp;
data_in_next <= (others => '0');
- if unsigned(s_cnt_int) /= 0 then
- s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
- end if;
when S_S_FIN =>
finished_next <= '1';
s_cnt_next <= (0 => '1', others => '0');
d_new_result_next <= '1';
when S_S_DONE =>
s_done_next <= '1';
- d_new_eingabe_next <= '1';
+ if was_bs_int = '0' then
+ d_new_eingabe_next <= '1';
+ end if;
when S_D_INIT =>
address_next <= d_spalte;
projects / hwmod.git / commitdiff