uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / display.vhd

diff --git a/src/display.vhd b/src/display.vhd
index ad5ac66c2a2d8d43988a32b599a50453dde14f36..0f5afef2e6d8e7d32b9166dea604e077d1229ad2 100644 (file)
--- a/src/display.vhd
+++ b/src/display.vhd
@@ -27,10 +27,10 @@ entity display is
 end entity display;
 
 architecture beh of display is
-       type DISPLAY_STATE is (SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT,
+       type DISPLAY_STATE is (S_INIT, SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT,
                S_ZEILEUP, S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1,
                S_PUTCH2, S_WAIT, S_NOP1, S_READ_RESULT_0, S_READ_RESULT_1,
-               S_READ_RESULT_2, S_INIT, S_PS1_0, S_PS1_1, S_PS1_2, S_PS1_3, S_PS1_4,
+               S_READ_RESULT_2, S_PS1_0, S_PS1_1, S_PS1_2, S_PS1_3, S_PS1_4,
                S_PS1_5);
        type DISPLAY_ISTATE is (IS_BACK_2_BLANK, IS_BLANK_2_BACK,
                IS_NL1_2_ZEILEUP, IS_RESULT2_2_CR1, IS_CR1_2_NL1, IS_NL1_2_RESULT0,