library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
use work.textmode_vga_component_pkg.all;
use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;

entity display is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;
		-- History
		d_new_eingabe : in std_logic;
		d_new_result : in std_logic;
		d_new_bs : in std_logic;
		d_zeile : out hzeile;
		d_spalte : out hspalte;
		d_get : out std_logic;
		d_done : in std_logic;
		d_char : in hbyte;
		-- VGA
		command : out std_logic_vector(7 downto 0);
		command_data : out std_logic_vector(31 downto 0);
		free : in std_logic
	);
end entity display;

architecture beh of display is
	type DISPLAY_STATE is (S_INIT, SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT,
		S_ZEILEUP, S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1,
		S_PUTCH2, S_WAIT, S_NOP1, S_READ_RESULT_0, S_READ_RESULT_1,
		S_READ_RESULT_2, S_PS1_0, S_PS1_1, S_PS1_2, S_PS1_3, S_PS1_4,
		S_PS1_5);
	type DISPLAY_ISTATE is (IS_BACK_2_BLANK, IS_BLANK_2_BACK,
		IS_NL1_2_ZEILEUP, IS_RESULT2_2_CR1, IS_CR1_2_NL1, IS_NL1_2_RESULT0,
		IS_RESULT0_2_RESULT1, IS_RESULT1_2_RESULT2, IS_ZEILEUP_2_PS10,
		IS_PS10_2_PS11, IS_PS11_2_PS12, IS_PS12_2_PS13, IS_PS13_2_PS14,
		IS_PS14_2_PS15, IS_RANDOM_2_IDLE, IS_OTHER_2_NL1);

	signal state_int, state_next : DISPLAY_STATE;
	signal istate_next, istate_int : DISPLAY_ISTATE;
	signal d_zeile_int, d_zeile_next : hzeile;
	signal d_spalte_int, d_spalte_next : hspalte;
	signal d_get_int, d_get_next : std_logic;
	signal command_int, command_next : std_logic_vector(7 downto 0);
	signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
begin
	d_zeile <= d_zeile_int;
	d_spalte <= d_spalte_int;
	d_get <= d_get_int;
	command <= command_int;
	command_data <= command_data_int;

	process(sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			-- internal
			state_int <= S_INIT;
			istate_int <= IS_RANDOM_2_IDLE;
			-- out
			d_zeile_int <= (others => '0');
			d_spalte_int <= (others => '0');
			d_get_int <= '0';
			command_int <= COMMAND_NOP;
			command_data_int <= (others => '0');
		elsif rising_edge(sys_clk) then
			-- internal
			state_int <= state_next;
			istate_int <= istate_next;
			-- out
			d_zeile_int <= d_zeile_next;
			d_spalte_int <= d_spalte_next;
			d_get_int <= d_get_next;
			command_int <= command_next;
			command_data_int <= command_data_next;
		end if;
	end process;

	-- next state
	process(state_int, d_new_result, d_new_eingabe, d_new_bs, d_done, free,
		d_spalte_int, d_char, istate_int)
	begin
		state_next <= state_int;
		istate_next <= istate_int;

		case state_int is
			when S_INIT =>
				state_next <= S_PS1_0;

			when S_PS1_0 =>
				istate_next <= IS_PS10_2_PS11;
				state_next <= S_WAIT;
			when S_PS1_1 =>
				istate_next <= IS_PS11_2_PS12;
				state_next <= S_WAIT;
			when S_PS1_2 =>
				istate_next <= IS_PS12_2_PS13;
				state_next <= S_WAIT;
			when S_PS1_3 =>
				istate_next <= IS_PS13_2_PS14;
				state_next <= S_WAIT;
			when S_PS1_4 =>
				istate_next <= IS_PS14_2_PS15;
				state_next <= S_WAIT;
			when S_PS1_5 =>
				istate_next <= IS_RANDOM_2_IDLE;
				state_next <= S_WAIT;

			when SIDLE =>
				istate_next <= IS_RANDOM_2_IDLE;
				if d_new_bs = '1' then
					state_next <= S_NEW_BS;
				elsif d_new_eingabe = '1' then
					state_next <= S_NEW_INPUT;
				end if;
				if d_new_result = '1' then
					state_next <= S_NEW_RESULT;
				end if;

			when S_NEW_RESULT =>
				state_next <= S_ZEILEUP;
			when S_NEW_INPUT =>
				state_next <= S_COUNTUP;

			when S_NEW_BS =>
				state_next <= S_BACK;
			when S_BACK =>
				if free = '0' then
					state_next <= S_WAIT;
					case istate_int is
						when IS_RANDOM_2_IDLE => istate_next <= IS_BACK_2_BLANK;
						when others => istate_next <= IS_RANDOM_2_IDLE;
					end case;
				end if;
			when S_BLANK =>
				if free = '0' then
					state_next <= S_WAIT;
					istate_next <= IS_BLANK_2_BACK;
				end if;

			when S_ZEILEUP =>
				case istate_int is
					when IS_NL1_2_ZEILEUP =>
						state_next <= S_WAIT;
						istate_next <= IS_ZEILEUP_2_PS10;
					when others => state_next <= S_CR1;
				end case;

			when S_CR1 =>
				if free = '0' then
					state_next <= S_WAIT;
					case istate_int is
						when IS_RESULT2_2_CR1 => istate_next <= IS_OTHER_2_NL1;
						when others => istate_next <= IS_CR1_2_NL1;
					end case;
				end if;
			when S_NL1 =>
				if free = '0' then
					state_next <= S_WAIT;
					case istate_int is
						when IS_OTHER_2_NL1 => istate_next <= IS_NL1_2_ZEILEUP;
						when others => istate_next <= IS_NL1_2_RESULT0;
					end case;
				end if;

			when S_READ_RESULT_0 =>
				istate_next <= IS_RESULT0_2_RESULT1;
				state_next <= S_WAIT;
			when S_READ_RESULT_1 =>
				istate_next <= IS_RESULT1_2_RESULT2;
				state_next <= S_WAIT;
			when S_READ_RESULT_2 =>
				if unsigned(d_spalte_int) /= HSPALTE_MAX-1 then
					state_next <= S_COUNTUP;
					istate_next <= IS_RESULT1_2_RESULT2;
				else
					state_next <= S_WAIT;
					istate_next <= IS_RESULT2_2_CR1;
				end if;

			when S_COUNTUP =>
				state_next <= S_GETCH;
			when S_GETCH =>
				if free = '1' and d_done = '1' and d_new_result = '0' and d_new_eingabe = '0' then
					state_next <= S_PUTCH1;
				end if;
			when S_PUTCH1 =>
				state_next <= S_PUTCH2;
			when S_PUTCH2 =>
				if free = '0' then
					state_next <= S_WAIT;
				end if;
			when S_WAIT =>
				if free = '1' and d_done = '0' then
					state_next <= S_NOP1;
				end if;
			when S_NOP1 =>
				if free = '1' then
					case istate_int is
						when IS_CR1_2_NL1 => state_next <= S_NL1;
						when IS_BACK_2_BLANK => state_next <= S_BLANK;
						when IS_BLANK_2_BACK => state_next <= S_BACK;
						when IS_NL1_2_ZEILEUP => state_next <= S_ZEILEUP;
						when IS_RESULT2_2_CR1 => state_next <= S_CR1;
						when IS_OTHER_2_NL1 => state_next <= S_NL1;

						when IS_NL1_2_RESULT0 => state_next <= S_READ_RESULT_0;
						when IS_RESULT0_2_RESULT1 => state_next <= S_READ_RESULT_1;
						when IS_RESULT1_2_RESULT2 => state_next <= S_READ_RESULT_2;

						when IS_ZEILEUP_2_PS10 => state_next <= S_PS1_0;
						when IS_PS10_2_PS11 => state_next <= S_PS1_1;
						when IS_PS11_2_PS12 => state_next <= S_PS1_2;
						when IS_PS12_2_PS13 => state_next <= S_PS1_3;
						when IS_PS13_2_PS14 => state_next <= S_PS1_4;
						when IS_PS14_2_PS15 => state_next <= S_PS1_5;
						when IS_RANDOM_2_IDLE => state_next <= SIDLE;
					end case;
				end if;
		end case;
	end process;

	-- out
	process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
		command_data_int, d_char)
	begin
		d_zeile_next <= d_zeile_int;
		d_spalte_next <= d_spalte_int;
		d_get_next <= '0';
		command_next <= command_int;
		command_data_next <= command_data_int;

		case state_int is
			when S_INIT => null;

			when S_PS1_0 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"0000ff" & x"28"; -- '('
			when S_PS1_1 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"00ff00" & zeile2char(d_zeile_int,1); -- 'x'
			when S_PS1_2 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"00ff00" & zeile2char(d_zeile_int,2); -- 'y'
			when S_PS1_3 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"0000ff" & x"29"; -- ')'
			when S_PS1_4 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"00ffff" & x"24"; -- '$'
			when S_PS1_5 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"20"; -- ' '

			when SIDLE => null;
			when S_NEW_RESULT => null;
			when S_NEW_INPUT => null;

			when S_NEW_BS =>
				-- underflow check schon im history modul
				d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) - 1);
			when S_BACK =>
				-- einen schritt zurueck, +6 wegen $PS1
				command_next <= COMMAND_SET_CURSOR_COLUMN;
				command_data_next <= x"ffffff" & '0' & std_logic_vector(unsigned(d_spalte_int) + 6);
			when S_BLANK =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"20"; -- white space

			when S_ZEILEUP =>
				d_spalte_next <= (others => '0');
				case d_zeile_int is
					when
					std_logic_vector(to_unsigned(HZEILE_MAX-1,d_zeile_int'length)) => d_zeile_next <= (others => '0');
					when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
				end case;

			when S_CR1 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"0d"; -- carrige return
			when S_NL1 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"0a"; -- newline

			when S_READ_RESULT_0 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ff0000" & x"3e"; -- '>'
			when S_READ_RESULT_1 =>
				command_next <= COMMAND_SET_CHAR;
				command_data_next <= x"ffffff" & x"20"; -- ' '
			when S_READ_RESULT_2 => null;

			when S_COUNTUP =>
				d_get_next <= '1';
				d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1);
			when S_GETCH =>
				d_get_next <= '1';
			when S_PUTCH1 =>
				command_next <= COMMAND_SET_CHAR;
				if d_char = x"00" then
					command_data_next <= x"ffffff" & x"20";
				else
					command_data_next <= x"ffffff" & std_logic_vector(d_char);
				end if;
			when S_PUTCH2 => null;
			when S_WAIT | S_NOP1 =>
				command_next <= COMMAND_NOP;
				command_data_next <= x"00000000";
		end case;
	end process;
end architecture beh;